85xx: Using proper I2C source clock divider for MPC8544

Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the
MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
correct. There seems to be an error in the 8544 RM.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 485ba20..70dfad0 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -102,9 +102,9 @@
 	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 	 */
 	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-		gd->i2c1_clk = sys_info.freqSystemBus / 3;
-	else
 		gd->i2c1_clk = sys_info.freqSystemBus / 2;
+	else
+		gd->i2c1_clk = sys_info.freqSystemBus / 3;
 #else
 	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 	gd->i2c1_clk = sys_info.freqSystemBus / 2;