imx8mp: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts
index ecb117a..101d311 100644
--- a/arch/arm/dts/imx8mp-venice-gw74xx.dts
+++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2022 Gateworks Corporation
+ * Copyright 2021 Gateworks Corporation
*/
/dts-v1/;
@@ -485,40 +485,30 @@
reg = <0>;
label = "lan1";
local-mac-address = [00 00 00 00 00 00];
- phy-handle = <&sw_phy0>;
- phy-mode = "internal";
};
lan2: port@1 {
reg = <1>;
label = "lan2";
local-mac-address = [00 00 00 00 00 00];
- phy-handle = <&sw_phy1>;
- phy-mode = "internal";
};
lan3: port@2 {
reg = <2>;
label = "lan3";
local-mac-address = [00 00 00 00 00 00];
- phy-handle = <&sw_phy2>;
- phy-mode = "internal";
};
lan4: port@3 {
reg = <3>;
label = "lan4";
local-mac-address = [00 00 00 00 00 00];
- phy-handle = <&sw_phy3>;
- phy-mode = "internal";
};
lan5: port@4 {
reg = <4>;
label = "lan5";
local-mac-address = [00 00 00 00 00 00];
- phy-handle = <&sw_phy4>;
- phy-mode = "internal";
};
port@6 {
@@ -533,38 +523,6 @@
};
};
};
-
- mdios {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0>;
- compatible = "microchip,ksz-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sw_phy0: ethernet-phy@0 {
- reg = <0x0>;
- };
-
- sw_phy1: ethernet-phy@1 {
- reg = <0x1>;
- };
-
- sw_phy2: ethernet-phy@2 {
- reg = <0x2>;
- };
-
- sw_phy3: ethernet-phy@3 {
- reg = <0x3>;
- };
-
- sw_phy4: ethernet-phy@4 {
- reg = <0x4>;
- };
- };
- };
};
};
@@ -842,6 +800,21 @@
>;
};
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
+ MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
+ >;
+ };
+
+ pinctrl_uart3_gpio: uart3gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119
+ >;
+ };
+
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140