| commit | e2842496ac64c19a0c40cb4cbe301d9d91cf0f56 | [log] [tgz] |
|---|---|---|
| author | Anup Patel <anup@brainfault.org> | Sat Dec 15 11:35:15 2018 +0530 |
| committer | Andes <uboot@andestech.com> | Tue Dec 18 09:56:54 2018 +0800 |
| tree | 327ef0a22123e963b4f7e0a2bfe3695a49ff2187 | |
| parent | dcad9b8d66d68e9258ce4be89fb0ac9ab95083b0 [diff] |
drivers: serial: Add SiFive UART driver This patch adds SiFive UART driver. The driver is 100% DM driver and it determines input clock using clk framework. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>