arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
diff --git a/board/phytium/durian/Kconfig b/board/phytium/durian/Kconfig
new file mode 100644
index 0000000..dc07109
--- /dev/null
+++ b/board/phytium/durian/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DURIAN
+
+config SYS_BOARD
+ default "durian"
+
+config SYS_VENDOR
+ default "phytium"
+
+config SYS_CONFIG_NAME
+ default "durian"
+
+endif
diff --git a/board/phytium/durian/MAINTAINERS b/board/phytium/durian/MAINTAINERS
new file mode 100644
index 0000000..895b762
--- /dev/null
+++ b/board/phytium/durian/MAINTAINERS
@@ -0,0 +1,8 @@
+DURIAN BOARD
+M: liuhao <liuhao@phytium.com.cn>
+M: shuyiqi <shuyiqi@phytium.com.cn>
+S: Maintained
+F: board/phytium/durian/*
+F: include/configs/durian.h
+F: configs/durian_defconfig
+
diff --git a/board/phytium/durian/Makefile b/board/phytium/durian/Makefile
new file mode 100644
index 0000000..c2fbf19
--- /dev/null
+++ b/board/phytium/durian/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# shuyiqi <shuyiqi@phytium.com.cn>
+# liuhao <liuhao@phytium.com.cn>
+#
+
+obj-y += durian.o
+
diff --git a/board/phytium/durian/README b/board/phytium/durian/README
new file mode 100644
index 0000000..4443133
--- /dev/null
+++ b/board/phytium/durian/README
@@ -0,0 +1,59 @@
+Here is the step-by-step to boot U-Boot on phytium durian board.
+
+Compile U-Boot
+==============
+ > make durian_defconfig
+ > make
+
+Get the prebuild binary about BPF
+=================================
+ > cd ../
+ > git clone https://github.com/phytium-durian/bpf.git
+
+Package the image
+=================
+ > cd bpf
+ > cp ../u-boot/u-boot.bin ./
+ > ./dopack
+
+ The fip-all.bin is the final image.
+
+Flash the image into the spi nor-flash
+======================================
+ Any spi nor-flash and appropriate tool can be used to flash.
+ For example, we choose the S25FL256 chip that produced from
+ SPANSION company and EZP_XPro V1.2.
+
+Reset the board, you can get U-Boot log message from boot console:
+
+Power on...
+Start pcie setup!
+End pcie setup!
+Start ddr setup!
+End ddr setup!
+Jump to entrypoint: 0x500000
+
+U-Boot 2019.10-00594-g9ccc1b17ea-dirty (Oct 18 2019 - 00:17:09 +0800)
+
+DRAM: 1.9 GiB
+In: uart@28001000
+Out: uart@28001000
+Err: uart@28001000
+scanning bus for devices...
+Target spinup took 0 ms.
+SATA link 1 timeout.
+SATA link 2 timeout.
+SATA link 3 timeout.
+AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
+flags: 64bit ncq led only pmp fbss pio slum part sxs
+ Device 0: (0:0) Vendor: ATA Prod.: ST1000DM010-2EP1 Rev: CC43
+ Type: Hard Disk
+ Capacity: 953869.7 MB = 931.5 GB (1953525168 x 512)
+SATA link 0 timeout.
+SATA link 1 timeout.
+SATA link 2 timeout.
+SATA link 3 timeout.
+AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
+flags: 64bit ncq led only pmp fbss pio slum part sxs
+Hit any key to stop autoboot: 0
+durian#
diff --git a/board/phytium/durian/cpu.h b/board/phytium/durian/cpu.h
new file mode 100644
index 0000000..a5a213d
--- /dev/null
+++ b/board/phytium/durian/cpu.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019
+ * Phytium Technology Ltd <www.phytium.com>
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ */
+
+#ifndef _FT_DURIAN_H
+#define _FT_DURIAN_H
+
+/* FLUSH L3 CASHE */
+#define HNF_COUNT 0x8
+#define HNF_PSTATE_REQ (HNF_BASE + 0x10)
+#define HNF_PSTATE_STAT (HNF_BASE + 0x18)
+#define HNF_PSTATE_OFF 0x0
+#define HNF_PSTATE_SFONLY 0x1
+#define HNF_PSTATE_HALF 0x2
+#define HNF_PSTATE_FULL 0x3
+#define HNF_STRIDE 0x10000
+#define HNF_BASE (unsigned long)(0x3A200000)
+
+#endif /* _FT_DURIAN_H */
+
diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c
new file mode 100644
index 0000000..59f307d
--- /dev/null
+++ b/board/phytium/durian/durian.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ * liuhao <liuhao@phytium.com.cn>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <linux/kernel.h>
+#include <scsi.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->mem_clk = 0;
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
+ debug("reset cpu error, %lx\n", res.a0);
+}
+
+static struct mm_region durian_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN |
+ PTE_BLOCK_UXN
+ },
+ {
+ .virt = (u64)PHYS_SDRAM_1,
+ .phys = (u64)PHYS_SDRAM_1,
+ .size = (u64)PHYS_SDRAM_1_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_NS |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = durian_mem_map;
+
+int print_cpuinfo(void)
+{
+ printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
+ return 0;
+}
+
+int __asm_flush_l3_dcache(void)
+{
+ int i, pstate;
+
+ for (i = 0; i < HNF_COUNT; i++)
+ writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
+ for (i = 0; i < HNF_COUNT; i++) {
+ do {
+ pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
+ } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
+ }
+
+ for (i = 0; i < HNF_COUNT; i++)
+ writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ int ret;
+
+ /* pci e */
+ pci_init();
+ /* scsi scan */
+ ret = scsi_scan(true);
+ if (ret) {
+ printf("scsi scan failed\n");
+ return CMD_RET_FAILURE;
+ }
+ return ret;
+}
+