commit e809e747996b00acd0ffc833999e97a3a21ddfac
author Priyanka Jain <priyanka.jain@nxp.com> Thu Apr 27 15:08:06 2017 +0530
committer York Sun <york.sun@nxp.com> Tue May 23 09:40:23 2017 -0700
tree e62a9b5249c07df67dba198d2bdf6943a93fae14
parent 89a168f776cbc15a2ff1f25a0f4e54f9bbaffdec

armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

drivers/pci/pcie_layerscape.c

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 1c5a33a..7565e2f 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -170,7 +171,8 @@
 	/* Fix the pcie memory map for LS2088A series SoCs */
 	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
 		if (io)
 			io->phys_start = (io->phys_start &
 					 (PCIE_PHYS_SIZE - 1)) +
@@ -531,7 +533,8 @@
 	svr = get_svr();
 	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
 		pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie->ctrl = pcie->lut + 0x40000;