mtd: nand: denali: fix unaligned cache operations on ARMv7 SoCs
If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still prints "Misaligned operation at range".
=> nand info
Device 0: nand0, sector size 256 KiB
Page size 4096 b
OOB size 224 b
Erase size 262144 b
subpagesize 4096 b
options 0x00104200
bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
...
The cache flushing operations won't happen in this case to cover all of
the range to fix this by making sure we have things aligned.
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Reword the commit message to be clear this is a direct problem
rather than just a warning]
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 7302c37..d1cac06 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -21,6 +21,8 @@
{
unsigned long addr = (unsigned long)ptr;
+ size = ALIGN(size, ARCH_DMA_MINALIGN);
+
if (dir == DMA_FROM_DEVICE)
invalidate_dcache_range(addr, addr + size);
else
@@ -32,6 +34,8 @@
static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
enum dma_data_direction dir)
{
+ size = ALIGN(size, ARCH_DMA_MINALIGN);
+
if (dir != DMA_TO_DEVICE)
invalidate_dcache_range(addr, addr + size);
}