commit e9284066958e906118b3fd71d7e81e9916b2c58a
author Michal Simek <michal.simek@xilinx.com> Mon Oct 05 15:43:44 2020 +0200
committer Michal Simek <michal.simek@xilinx.com> Tue Oct 27 08:13:31 2020 +0100
tree 9e3d5223fc098f91a3c5563f06e7887ca11844d8
parent 0d76b71d93f6d7740b973dbb50010dc8f7b347f0

arm64: zynqmp: Enable FPGA loading from SPL

fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

configs/xilinx_zynqmp_virt_defconfig

diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 264b662..5b4fe53 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -19,6 +19,7 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_FPGA=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y