| commit | eae4e0f3c10967386382b848ef80d9f8852d67a1 | [log] [tgz] |
|---|---|---|
| author | Ye Li <ye.li@nxp.com> | Mon Jul 22 01:25:03 2019 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Tue Oct 08 16:35:16 2019 +0200 |
| tree | c66f5df45fa1f1cd87ce256a4ae160cb1486b145 | |
| parent | eb6d2e5920fa518fc924025e1e7987cd0dde73ad [diff] |
i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem. The correct fix should let GPU handle the clock rate in kernel. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>