Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/.gitignore b/.gitignore
index 29757aa..f1b8015 100644
--- a/.gitignore
+++ b/.gitignore
@@ -85,3 +85,7 @@
*.orig
*~
\#*#
+
+# gcc code coverage files
+*.gcda
+*.gcno
diff --git a/.travis.yml b/.travis.yml
index 7b53b3d..d83a5e6 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -27,6 +27,7 @@
- rpm2cpio
- wget
- device-tree-compiler
+ - lzop
install:
# Clone uboot-test-hooks
@@ -37,7 +38,7 @@
- echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- echo -e "aarch64 = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu" >> ~/.buildman
- echo -e "arm = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf" >> ~/.buildman
- - echo -e "arc = /tmp/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+ - echo -e "arc = /tmp/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
- cat ~/.buildman
- virtualenv /tmp/venv
@@ -69,8 +70,8 @@
echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
fi
- if [[ "${TOOLCHAIN}" == arc ]]; then
- wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2016.09-release/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
- tar -C /tmp -xf arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
+ wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2017.09-release/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
+ tar -C /tmp -xf arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
fi
- if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
diff --git a/Kconfig b/Kconfig
index 4354061..7accdad 100644
--- a/Kconfig
+++ b/Kconfig
@@ -59,6 +59,13 @@
This option is enabled by default for U-Boot.
+config CC_COVERAGE
+ bool "Enable code coverage analysis"
+ depends on SANDBOX
+ help
+ Enabling this option will pass "--coverage" to gcc to compile
+ and link code instrumented for coverage analysis.
+
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
default y if ARCH_SUNXI || TEGRA
@@ -69,22 +76,16 @@
imply USE_BOOTCOMMAND
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
- select CMD_DHCP if NET && CMD_NET
- select CMD_PXE if NET && CMD_NET
+ select CMD_DHCP if CMD_NET
+ select CMD_PING if CMD_NET
+ select CMD_PXE if NET
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
select CMD_FS_GENERIC
imply CMD_MII if NET
- select CMD_PING if NET
select CMD_PART if PARTITIONS
select HUSH_PARSER
- select BOOTP_BOOTPATH if NET && CMD_NET
- select BOOTP_DNS if NET && CMD_NET
- select BOOTP_GATEWAY if NET && CMD_NET
- select BOOTP_HOSTNAME if NET && CMD_NET
- select BOOTP_PXE if NET && CMD_NET
- select BOOTP_SUBNETMASK if NET && CMD_NET
select CMDLINE_EDITING
select AUTO_COMPLETE
select SYS_LONGHELP
@@ -405,6 +406,9 @@
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
default 0x80800000 if ARCH_OMAP2PLUS
+ default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
+ default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
+ default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
hex "Text Base"
help
The address in memory that U-Boot will be running from, initially.
diff --git a/MAINTAINERS b/MAINTAINERS
index d5059f6..44eeefa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -111,7 +111,6 @@
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
-F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
@@ -124,7 +123,7 @@
M: Peter Griffin <peter.griffin@linaro.org>
S: Maintained
F: arch/arm/cpu/armv8/hisilicon
-F: arm/include/asm/arch-hi6220/
+F: arch/arm/include/asm/arch-hi6220/
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
M: Prafulla Wadaskar <prafulla@marvell.com>
@@ -160,6 +159,8 @@
F: drivers/clk/rockchip/
F: drivers/gpio/rk_gpio.c
F: drivers/misc/rockchip-efuse.c
+F: drivers/mmc/rockchip_sdhci.c
+F: drivers/mmc/rockchip_dw_mmc.c
F: drivers/pinctrl/rockchip/
F: drivers/ram/rockchip/
F: drivers/sysreset/sysreset_rockchip.c
@@ -174,11 +175,9 @@
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-samsung.git
-F: arch/arm/cpu/arm920t/s3c24x0/
F: arch/arm/mach-exynos/
F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
-F: arch/arm/include/asm/arch-s3c24x0/
ARM SNAPDRAGON
M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
@@ -198,6 +197,13 @@
F: arch/arm/cpu/arm926ejs/spear/
F: arch/arm/include/asm/arch-spear/
+ARM STM STM32MP
+M: Patrick Delaunay <patrick.delaunay@st.com>
+S: Maintained
+F: arch/arm/mach-stm32mp
+F: drivers/clk/clk_stm32mp1.c
+F: drivers/ram/stm32mp1/
+
ARM STM STV0991
M: Vikas Manocha <vikas.manocha@st.com>
S: Maintained
@@ -227,8 +233,6 @@
T: git git://git.denx.de/u-boot-ti.git
F: arch/arm/mach-davinci/
F: arch/arm/mach-keystone/
-F: arch/arm/cpu/arm926ejs/omap/
-F: arch/arm/cpu/armv7/omap*/
F: arch/arm/include/asm/arch-omap*/
F: arch/arm/include/asm/ti-common/
@@ -243,14 +247,50 @@
ARM ZYNQ
M: Michal Simek <monstr@monstr.eu>
S: Maintained
-F: arch/arm/cpu/armv7/zynq/
-F: arch/arm/include/asm/arch-zynq/
+T: git git://git.denx.de/u-boot-microblaze.git
+F: arch/arm/mach-zynq/
+F: drivers/clk/clk_zynq.c
+F: drivers/fpga/zynqpl.c
+F: drivers/gpio/zynq_gpio.c
+F: drivers/i2c/i2c-cdns.c
+F: drivers/i2c/muxes/pca954x.c
+F: drivers/i2c/zynq_i2c.c
+F: drivers/mmc/zynq_sdhci.c
+F: drivers/mtd/nand/zynq_nand.c
+F: drivers/net/phy/xilinx_phy.c
+F: drivers/net/zynq_gem.c
+F: drivers/serial/serial_zynq.c
+F: drivers/spi/zynq_qspi.c
+F: drivers/spi/zynq_spi.c
+F: drivers/usb/host/ehci-zynq.c
+F: drivers/watchdog/cdns_wdt.c
+F: include/zynqpl.h
+F: tools/zynqimage.c
+N: zynq
ARM ZYNQMP
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-F: arch/arm/cpu/armv8/zynqmp/
-F: arch/arm/include/asm/arch-zynqmp/
+T: git git://git.denx.de/u-boot-microblaze.git
+F: arch/arm/mach-zynq/
+F: drivers/clk/clk_zynqmp.c
+F: drivers/fpga/zynqpl.c
+F: drivers/gpio/zynq_gpio.c
+F: drivers/i2c/i2c-cdns.c
+F: drivers/i2c/muxes/pca954x.c
+F: drivers/i2c/zynq_i2c.c
+F: drivers/mmc/zynq_sdhci.c
+F: drivers/mtd/nand/zynq_nand.c
+F: drivers/net/phy/xilinx_phy.c
+F: drivers/net/zynq_gem.c
+F: drivers/serial/serial_zynq.c
+F: drivers/spi/zynq_qspi.c
+F: drivers/spi/zynq_spi.c
+F: drivers/usb/host/ehci-zynq.c
+F: drivers/watchdog/cdns_wdt.c
+F: include/zynqmppl.h
+F: tools/zynqimage.c
+N: zynqmp
BUILDMAN
M: Simon Glass <sjg@chromium.org>
@@ -290,7 +330,7 @@
M: Alexander Graf <agraf@suse.de>
S: Maintained
T: git git://github.com/agraf/u-boot.git
-F: doc/README.efi
+F: doc/README.uefi
F: doc/README.iscsi
F: include/efi*
F: include/pe.h
@@ -307,7 +347,7 @@
F: lib/fdtdec*
F: lib/libfdt/
F: include/fdt*
-F: include/libfdt*
+F: include/linux/libfdt*
F: cmd/fdt.c
F: common/fdt_support.c
@@ -341,6 +381,14 @@
S: Maintained
T: git git://git.denx.de/u-boot-microblaze.git
F: arch/microblaze/
+F: cmd/mfsl.c
+F: drivers/gpio/xilinx_gpio.c
+F: drivers/net/xilinx_axi_emac.c
+F: drivers/net/xilinx_emaclite.c
+F: drivers/serial/serial_xuartlite.c
+F: drivers/spi/xilinx_spi.c
+F: drivers/watchdog/xilinx_tb_wdt.c
+N: xilinx
MIPS
M: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
@@ -426,12 +474,6 @@
T: git git://git.denx.de/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
-POWERPC PPC4XX
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-ppc4xx.git
-F: arch/powerpc/cpu/ppc4xx/
-
RISC-V
M: Rick Chen <rick@andestech.com>
S: Maintained
@@ -475,7 +517,6 @@
M: Andrew F. Davis <afd@ti.com>
S: Supported
F: arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
-F: arch/arm/mach-omap2/omap5/sec-fxns.c
F: arch/arm/mach-omap2/sec-common.c
F: arch/arm/mach-omap2/config_secure.mk
F: configs/am335x_hs_evm_defconfig
@@ -486,6 +527,7 @@
F: configs/k2hk_hs_evm_defconfig
F: configs/k2e_hs_evm_defconfig
F: configs/k2g_hs_evm_defconfig
+F: configs/k2l_hs_evm_defconfig
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>
diff --git a/Makefile b/Makefile
index f67ad69..5cfe43f 100644
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
#
VERSION = 2018
-PATCHLEVEL = 03
+PATCHLEVEL = 05
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@@ -423,6 +423,7 @@
version_h := include/generated/version_autogenerated.h
timestamp_h := include/generated/timestamp_autogenerated.h
+defaultenv_h := include/generated/defaultenv_autogenerated.h
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
@@ -600,9 +601,13 @@
KBUILD_AFLAGS += -g
# Report stack usage if supported
+# ARC tools based on GCC 7.1 has an issue with stack usage
+# with naked functions, see commit message for more details
+ifndef CONFIG_ARC
ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y)
KBUILD_CFLAGS += -fstack-usage
endif
+endif
KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
@@ -720,6 +725,12 @@
PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
endif
PLATFORM_LIBS += $(PLATFORM_LIBGCC)
+
+ifdef CONFIG_CC_COVERAGE
+KBUILD_CFLAGS += --coverage
+PLATFORM_LIBGCC += -lgcov
+endif
+
export PLATFORM_LIBS
export PLATFORM_LIBGCC
@@ -804,6 +815,11 @@
ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
endif
+# Build a combined spl + u-boot image for sunxi
+ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
+ALL-y += u-boot-sunxi-with-spl.bin
+endif
+
# enable combined SPL/u-boot/dtb rules for tegra
ifeq ($(CONFIG_TEGRA)$(CONFIG_SPL),yy)
ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
@@ -1190,8 +1206,13 @@
endif
ifneq ($(CONFIG_ARCH_SUNXI),)
+ifeq ($(CONFIG_ARM64),)
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
$(call if_changed,binman)
+else
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
+ $(call if_changed,cat)
+endif
endif
ifneq ($(CONFIG_TEGRA),)
@@ -1381,6 +1402,10 @@
@/bin/false
endif
+ifeq ($(CONFIG_USE_DEFAULT_ENV_FILE),y)
+prepare1: $(defaultenv_h)
+endif
+
archprepare: prepare1 scripts_basic
prepare0: archprepare FORCE
@@ -1428,12 +1453,23 @@
fi)
endef
+define filechk_defaultenv.h
+ (grep -v '^#' | \
+ grep -v '^$$' | \
+ tr '\n' '\0' | \
+ sed -e 's/\\\x0/\n/' | \
+ xxd -i ; echo ", 0x00" ; )
+endef
+
$(version_h): include/config/uboot.release FORCE
$(call filechk,version.h)
$(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
+$(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE
+ $(call filechk,defaultenv.h)
+
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@
cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) \
diff --git a/README b/README
index 5cf90a4..6f98e09 100644
--- a/README
+++ b/README
@@ -812,14 +812,6 @@
CONFIG_AT91_HW_WDT_TIMEOUT
specify the timeout in seconds. default 2 seconds.
-- U-Boot Version:
- CONFIG_VERSION_VARIABLE
- If this variable is defined, an environment variable
- named "ver" is created by U-Boot showing the U-Boot
- version as printed by the "version" command.
- Any change to this variable will be reverted at the
- next reset.
-
- Real-Time Clock:
When CONFIG_CMD_DATE is selected, the type of the RTC
@@ -1420,10 +1412,6 @@
be at least 4MB.
- MII/PHY support:
- CONFIG_PHY_ADDR
-
- The address of PHY on MII bus.
-
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
The clock frequency of the MII bus
@@ -2217,12 +2205,6 @@
the environment like the "source" command or the
boot command first.
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
- Define this in order to add variables describing certain
- run-time determined information about the hardware to the
- environment. These will be named board_name, board_rev.
-
CONFIG_DELAY_ENVIRONMENT
Normally the environment is loaded when the board is
@@ -2486,12 +2468,6 @@
kernel. Needed for UBI support.
- UBI support
- CONFIG_UBI_SILENCE_MSG
-
- Make the verbose messages from UBI stop printing. This leaves
- warnings and errors enabled.
-
-
CONFIG_MTD_UBI_WL_THRESHOLD
This parameter defines the maximum difference between the highest
erase counter value and the lowest erase counter value of eraseblocks
@@ -2553,12 +2529,6 @@
Enable UBI fastmap debug
default: 0
-- UBIFS support
- CONFIG_UBIFS_SILENCE_MSG
-
- Make the verbose messages from UBIFS stop printing. This leaves
- warnings and errors enabled.
-
- SPL framework
CONFIG_SPL
Enable building of SPL globally.
@@ -2818,9 +2788,6 @@
Begin and End addresses of the area used by the
simple memory test.
-- CONFIG_SYS_ALT_MEMTEST:
- Enable an alternate, more extensive memory test.
-
- CONFIG_SYS_MEMTEST_SCRATCH:
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
@@ -3446,9 +3413,6 @@
If defined, the x86 reset vector code is included. This is not
needed when U-Boot is running from Coreboot.
-- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
- Enables the RTC32K OSC on AM33xx based plattforms
-
- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Option to disable subpage write in NAND driver
driver that uses this:
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 9e9bc63..aae7dde 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -30,7 +30,7 @@
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index e3f9db7..aee15d5 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -116,6 +116,24 @@
bool "Do not use Data Cache"
default n
+menuconfig ARC_DBG
+ bool "ARC debugging"
+ default n
+
+if ARC_DBG
+
+config ARC_DBG_IOC_ENABLE
+ bool "Enable IO coherency unit"
+ depends on CPU_ARCHS38
+ default n
+ help
+ Enable IO coherency unit to debug problems with caches and
+ DMA peripherals.
+ NOTE: as of today linux will not work properly if this option
+ is enabled in u-boot!
+
+endif
+
choice
prompt "Target select"
default TARGET_AXS103
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index 3ed0c28..d040454 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -51,9 +51,10 @@
endif
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
# Needed for relocation
-LDFLAGS_FINAL += -pie
+LDFLAGS_FINAL += -pie --gc-sections
# Load address for standalone apps
CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index b74d3c8..17ef656 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -31,11 +31,8 @@
};
ethernet@18000 {
- #interrupt-cells = <1>;
compatible = "altr,socfpga-stmmac";
reg = < 0x18000 0x2000 >;
- interrupts = < 25 >;
- interrupt-names = "macirq";
phy-mode = "gmii";
snps,pbl = < 32 >;
clocks = <&apbclk>;
@@ -46,13 +43,11 @@
ehci@0x40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
- interrupts = < 8 >;
};
ohci@0x60000 {
compatible = "generic-ohci";
reg = < 0x60000 0x100 >;
- interrupts = < 8 >;
};
uart0: serial0@22000 {
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 67dfb93..80b864a 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
/ {
#address-cells = <1>;
@@ -13,6 +14,7 @@
aliases {
console = &uart0;
+ spi0 = &spi0;
};
cpu_card {
@@ -24,6 +26,35 @@
};
};
+ clk-fmeas {
+ clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
+ <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
+ <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
+ <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
+ <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
+ <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
+ <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
+ <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
+ <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
+ <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
+ <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
+ <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
+ <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
+ clock-names = "cpu-pll", "sys-pll",
+ "tun-pll", "ddr-clk",
+ "cpu-clk", "hdmi-pll",
+ "tun-clk", "hdmi-clk",
+ "apb-clk", "axi-clk",
+ "eth-clk", "usb-clk",
+ "sdio-clk", "hdmi-sys-clk",
+ "gfx-core-clk", "gfx-dma-clk",
+ "gfx-cfg-clk", "dmac-core-clk",
+ "dmac-cfg-clk", "sdio-ref-clk",
+ "spi-clk", "i2c-clk",
+ "uart-clk", "ebi-clk",
+ "rom-clk", "pwm-clk";
+ };
+
cgu_clk: cgu-clk@f0000000 {
compatible = "snps,hsdk-cgu-clock";
reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
@@ -53,4 +84,29 @@
compatible = "generic-ohci";
reg = <0xf0060000 0x100>;
};
+
+ spi0: spi@f0020000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xf0020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&cgu_clk CLK_SYS_SPI_REF>;
+ clock-names = "spi_clk";
+ cs-gpio = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@f00014b0 {
+ compatible = "snps,hsdk-creg-gpio";
+ reg = <0xf00014b0 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "hsdk-spi-cs";
+ gpio-count = <1>;
+ };
};
diff --git a/arch/arc/include/asm/arc-bcr.h b/arch/arc/include/asm/arc-bcr.h
new file mode 100644
index 0000000..823906d
--- /dev/null
+++ b/arch/arc/include/asm/arc-bcr.h
@@ -0,0 +1,77 @@
+/*
+ * ARC Build Configuration Registers, with encoded hardware config
+ *
+ * Copyright (C) 2018 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARC_BCR_H
+#define __ARC_BCR_H
+#ifndef __ASSEMBLY__
+
+#include <config.h>
+
+union bcr_di_cache {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
+#else
+ unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_slc_cfg {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:24, way:2, lsz:2, sz:4;
+#else
+ unsigned int sz:4, lsz:2, way:2, pad:24;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_generic {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:24, ver:8;
+#else
+ unsigned int ver:8, pad:24;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_clust_cfg {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
+#else
+ unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_mmu_4 {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
+ n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
+#else
+ /* DTLB ITLB JES JE JA */
+ unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
+ pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARC_BCR_H */
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 67f4163..3a51314 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -8,6 +8,7 @@
#define _ASM_ARC_ARCREGS_H
#include <asm/cache.h>
+#include <config.h>
/*
* ARC architecture has additional address space - auxiliary registers.
@@ -88,6 +89,16 @@
/* ARCNUM [15:8] - field to identify each core in a multi-core system */
#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
+
+static const inline int is_isa_arcv2(void)
+{
+ return IS_ENABLED(CONFIG_ISA_ARCV2);
+}
+
+static const inline int is_isa_arcompact(void)
+{
+ return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
+}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index d26d9fb..2269183 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -30,6 +30,13 @@
#ifndef __ASSEMBLY__
void cache_init(void);
+void flush_n_invalidate_dcache_all(void);
+void sync_n_cleanup_cache_all(void);
+
+static const inline int is_ioc_enabled(void)
+{
+ return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
+}
#endif /* __ASSEMBLY__ */
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
index f0242f1..43e1343 100644
--- a/arch/arc/include/asm/global_data.h
+++ b/arch/arc/include/asm/global_data.h
@@ -7,9 +7,15 @@
#ifndef __ASM_ARC_GLOBAL_DATA_H
#define __ASM_ARC_GLOBAL_DATA_H
+#include <config.h>
+
#ifndef __ASSEMBLY__
/* Architecture-specific global data */
struct arch_global_data {
+ int l1_line_sz;
+#if defined(CONFIG_ISA_ARCV2)
+ int slc_line_sz;
+#endif
};
#endif /* __ASSEMBLY__ */
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index a12303b..060cdf6 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -10,7 +10,7 @@
#include <linux/types.h>
#include <asm/byteorder.h>
-#ifdef CONFIG_ISA_ARCV2
+#ifdef __ARCHS__
/*
* ARCv2 based HS38 cores are in-order issue, but still weakly ordered
@@ -42,12 +42,12 @@
#define mb() asm volatile("sync\n" : : : "memory")
#endif
-#ifdef CONFIG_ISA_ARCV2
+#ifdef __ARCHS__
#define __iormb() rmb()
#define __iowmb() wmb()
#else
-#define __iormb() do { } while (0)
-#define __iowmb() do { } while (0)
+#define __iormb() asm volatile("" : : : "memory")
+#define __iowmb() asm volatile("" : : : "memory")
#endif
static inline void sync(void)
diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
index 909129c..8b13789 100644
--- a/arch/arc/include/asm/string.h
+++ b/arch/arc/include/asm/string.h
@@ -1,27 +1 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARC_STRING_H
-#define __ASM_ARC_STRING_H
-
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_STRCHR
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRLEN
-
-extern void *memset(void *ptr, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-extern void memzero(void *ptr, __kernel_size_t n);
-extern int memcmp(const void *, const void *, __kernel_size_t);
-extern char *strchr(const char *s, int c);
-extern char *strcpy(char *dest, const char *src);
-extern int strcmp(const char *cs, const char *ct);
-extern __kernel_size_t strlen(const char *);
-
-#endif /* __ASM_ARC_STRING_H */
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index 12097bf..6b7fb0f 100644
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -10,13 +10,6 @@
obj-y += cpu.o
obj-y += interrupts.o
obj-y += relocate.o
-obj-y += strchr-700.o
-obj-y += strcmp.o
-obj-y += strcpy-700.o
-obj-y += strlen.o
-obj-y += memcmp.o
-obj-y += memcpy-700.o
-obj-y += memset.o
obj-y += reset.o
obj-y += ints_low.o
obj-y += init_helpers.o
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index 4d4acff..4f04aad 100644
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm/cache.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,41 +41,52 @@
static int cleanup_before_linux(void)
{
disable_interrupts();
- flush_dcache_all();
- invalidate_icache_all();
+ sync_n_cleanup_cache_all();
return 0;
}
+__weak int board_prep_linux(bootm_headers_t *images) { return 0; }
+
/* Subcommand: PREP */
-static void boot_prep_linux(bootm_headers_t *images)
+static int boot_prep_linux(bootm_headers_t *images)
{
- if (image_setup_linux(images))
- hang();
+ int ret;
+
+ ret = image_setup_linux(images);
+ if (ret)
+ return ret;
+
+ return board_prep_linux(images);
}
-__weak void smp_set_core_boot_addr(unsigned long addr, int corenr) {}
-__weak void smp_kick_all_cpus(void) {}
+/* Generic implementation for single core CPU */
+__weak void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+ kernel_entry = (void (*)(int, int, uint))entry;
+
+ kernel_entry(zero, arch, params);
+}
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
- void (*kernel_entry)(int zero, int arch, uint params);
+ ulong kernel_entry;
unsigned int r0, r2;
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
- kernel_entry = (void (*)(int, int, uint))images->ep;
+ kernel_entry = images->ep;
debug("## Transferring control to Linux (at address %08lx)...\n",
- (ulong) kernel_entry);
+ kernel_entry);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
printf("\nStarting kernel ...%s\n\n", fake ?
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- cleanup_before_linux();
-
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
r0 = 2;
r2 = (unsigned int)images->ft_addr;
@@ -83,11 +95,10 @@
r2 = (unsigned int)env_get("bootargs");
}
- if (!fake) {
- smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
- smp_kick_all_cpus();
- kernel_entry(r0, 0, r2);
- }
+ cleanup_before_linux();
+
+ if (!fake)
+ board_jump_and_run(kernel_entry, r0, 0, r2);
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
@@ -96,17 +107,13 @@
if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
return -1;
- if (flag & BOOTM_STATE_OS_PREP) {
- boot_prep_linux(images);
- return 0;
- }
+ if (flag & BOOTM_STATE_OS_PREP)
+ return boot_prep_linux(images);
if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
boot_jump_linux(images, flag);
return 0;
}
- boot_prep_linux(images);
- boot_jump_linux(images, flag);
- return 0;
+ return -1;
}
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 04f1d9d..8203fae 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -10,8 +10,145 @@
#include <linux/kernel.h>
#include <linux/log2.h>
#include <asm/arcregs.h>
+#include <asm/arc-bcr.h>
#include <asm/cache.h>
+/*
+ * [ NOTE 1 ]:
+ * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
+ * operation may result in unexpected behavior and data loss even if we flush
+ * data cache right before invalidation. That may happens if we store any context
+ * on stack (like we store BLINK register on stack before function call).
+ * BLINK register is the register where return address is automatically saved
+ * when we do function call with instructions like 'bl'.
+ *
+ * There is the real example:
+ * We may hang in the next code as we store any BLINK register on stack in
+ * invalidate_dcache_all() function.
+ *
+ * void flush_dcache_all() {
+ * __dc_entire_op(OP_FLUSH);
+ * // Other code //
+ * }
+ *
+ * void invalidate_dcache_all() {
+ * __dc_entire_op(OP_INV);
+ * // Other code //
+ * }
+ *
+ * void foo(void) {
+ * flush_dcache_all();
+ * invalidate_dcache_all();
+ * }
+ *
+ * Now let's see what really happens during that code execution:
+ *
+ * foo()
+ * |->> call flush_dcache_all
+ * [return address is saved to BLINK register]
+ * [push BLINK] (save to stack) ![point 1]
+ * |->> call __dc_entire_op(OP_FLUSH)
+ * [return address is saved to BLINK register]
+ * [flush L1 D$]
+ * return [jump to BLINK]
+ * <<------
+ * [other flush_dcache_all code]
+ * [pop BLINK] (get from stack)
+ * return [jump to BLINK]
+ * <<------
+ * |->> call invalidate_dcache_all
+ * [return address is saved to BLINK register]
+ * [push BLINK] (save to stack) ![point 2]
+ * |->> call __dc_entire_op(OP_FLUSH)
+ * [return address is saved to BLINK register]
+ * [invalidate L1 D$] ![point 3]
+ * // Oops!!!
+ * // We lose return address from invalidate_dcache_all function:
+ * // we save it to stack and invalidate L1 D$ after that!
+ * return [jump to BLINK]
+ * <<------
+ * [other invalidate_dcache_all code]
+ * [pop BLINK] (get from stack)
+ * // we don't have this data in L1 dcache as we invalidated it in [point 3]
+ * // so we get it from next memory level (for example DDR memory)
+ * // but in the memory we have value which we save in [point 1], which
+ * // is return address from flush_dcache_all function (instead of
+ * // address from current invalidate_dcache_all function which we
+ * // saved in [point 2] !)
+ * return [jump to BLINK]
+ * <<------
+ * // As BLINK points to invalidate_dcache_all, we call it again and
+ * // loop forever.
+ *
+ * Fortunately we may fix that by using flush & invalidation of D$ with a single
+ * one instruction (instead of flush and invalidation instructions pair) and
+ * enabling force function inline with '__attribute__((always_inline))' gcc
+ * attribute to avoid any function call (and BLINK store) between cache flush
+ * and disable.
+ *
+ *
+ * [ NOTE 2 ]:
+ * As of today we only support the following cache configurations on ARC.
+ * Other configurations may exist in HW (for example, since version 3.0 HS
+ * supports SL$ (L2 system level cache) disable) but we don't support it in SW.
+ * Configuration 1:
+ * ______________________
+ * | |
+ * | ARC CPU |
+ * |______________________|
+ * ___|___ ___|___
+ * | | | |
+ * | L1 I$ | | L1 D$ |
+ * |_______| |_______|
+ * on/off on/off
+ * ___|______________|____
+ * | |
+ * | main memory |
+ * |______________________|
+ *
+ * Configuration 2:
+ * ______________________
+ * | |
+ * | ARC CPU |
+ * |______________________|
+ * ___|___ ___|___
+ * | | | |
+ * | L1 I$ | | L1 D$ |
+ * |_______| |_______|
+ * on/off on/off
+ * ___|______________|____
+ * | |
+ * | L2 (SL$) |
+ * |______________________|
+ * always must be on
+ * ___|______________|____
+ * | |
+ * | main memory |
+ * |______________________|
+ *
+ * Configuration 3:
+ * ______________________
+ * | |
+ * | ARC CPU |
+ * |______________________|
+ * ___|___ ___|___
+ * | | | |
+ * | L1 I$ | | L1 D$ |
+ * |_______| |_______|
+ * on/off must be on
+ * ___|______________|____ _______
+ * | | | |
+ * | L2 (SL$) |-----| IOC |
+ * |______________________| |_______|
+ * always must be on on/off
+ * ___|______________|____
+ * | |
+ * | main memory |
+ * |______________________|
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
/* Bit values in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE BIT(0)
@@ -19,11 +156,10 @@
#define DC_CTRL_CACHE_DISABLE BIT(0)
#define DC_CTRL_INV_MODE_FLUSH BIT(6)
#define DC_CTRL_FLUSH_STATUS BIT(8)
-#define CACHE_VER_NUM_MASK 0xF
-#define OP_INV 0x1
-#define OP_FLUSH 0x2
-#define OP_INV_IC 0x3
+#define OP_INV BIT(0)
+#define OP_FLUSH BIT(1)
+#define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
/* Bit val in SLC_CONTROL */
#define SLC_CTRL_DIS 0x001
@@ -31,55 +167,117 @@
#define SLC_CTRL_BUSY 0x100
#define SLC_CTRL_RGN_OP_INV 0x200
+#define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
+
/*
- * By default that variable will fall into .bss section.
- * But .bss section is not relocated and so it will be initilized before
- * relocation but will be used after being zeroed.
+ * We don't want to use '__always_inline' macro here as it can be redefined
+ * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more
+ * details about the reasons we need to use always_inline functions.
*/
-int l1_line_sz __section(".data");
-bool dcache_exists __section(".data") = false;
-bool icache_exists __section(".data") = false;
+#define inlined_cachefunc inline __attribute__((always_inline))
-#define CACHE_LINE_MASK (~(l1_line_sz - 1))
+static inlined_cachefunc void __ic_entire_invalidate(void);
+static inlined_cachefunc void __dc_entire_op(const int cacheop);
-#ifdef CONFIG_ISA_ARCV2
-int slc_line_sz __section(".data");
-bool slc_exists __section(".data") = false;
-bool ioc_exists __section(".data") = false;
-bool pae_exists __section(".data") = false;
-
-/* To force enable IOC set ioc_enable to 'true' */
-bool ioc_enable __section(".data") = false;
-
-void read_decode_mmu_bcr(void)
+static inline bool pae_exists(void)
{
/* TODO: should we compare mmu version from BCR and from CONFIG? */
#if (CONFIG_ARC_MMU_VER >= 4)
- u32 tmp;
+ union bcr_mmu_4 mmu4;
- tmp = read_aux_reg(ARC_AUX_MMU_BCR);
+ mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
- struct bcr_mmu_4 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
- unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
- n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
-#else
- /* DTLB ITLB JES JE JA */
- unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
- pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
-#endif /* CONFIG_CPU_BIG_ENDIAN */
- } *mmu4;
-
- mmu4 = (struct bcr_mmu_4 *)&tmp;
-
- pae_exists = !!mmu4->pae;
+ if (mmu4.fields.pae)
+ return true;
#endif /* (CONFIG_ARC_MMU_VER >= 4) */
+
+ return false;
}
-static void __slc_entire_op(const int op)
+static inlined_cachefunc bool icache_exists(void)
+{
+ union bcr_di_cache ibcr;
+
+ ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
+ return !!ibcr.fields.ver;
+}
+
+static inlined_cachefunc bool icache_enabled(void)
+{
+ if (!icache_exists())
+ return false;
+
+ return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
+}
+
+static inlined_cachefunc bool dcache_exists(void)
+{
+ union bcr_di_cache dbcr;
+
+ dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
+ return !!dbcr.fields.ver;
+}
+
+static inlined_cachefunc bool dcache_enabled(void)
+{
+ if (!dcache_exists())
+ return false;
+
+ return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
+}
+
+static inlined_cachefunc bool slc_exists(void)
+{
+ if (is_isa_arcv2()) {
+ union bcr_generic sbcr;
+
+ sbcr.word = read_aux_reg(ARC_BCR_SLC);
+ return !!sbcr.fields.ver;
+ }
+
+ return false;
+}
+
+static inlined_cachefunc bool slc_data_bypass(void)
+{
+ /*
+ * If L1 data cache is disabled SL$ is bypassed and all load/store
+ * requests are sent directly to main memory.
+ */
+ return !dcache_enabled();
+}
+
+static inline bool ioc_exists(void)
+{
+ if (is_isa_arcv2()) {
+ union bcr_clust_cfg cbcr;
+
+ cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
+ return cbcr.fields.c;
+ }
+
+ return false;
+}
+
+static inline bool ioc_enabled(void)
+{
+ /*
+ * We check only CONFIG option instead of IOC HW state check as IOC
+ * must be disabled by default.
+ */
+ if (is_ioc_enabled())
+ return ioc_exists();
+
+ return false;
+}
+
+static inlined_cachefunc void __slc_entire_op(const int op)
{
unsigned int ctrl;
+ if (!slc_exists())
+ return;
+
ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
if (!(op & OP_FLUSH)) /* i.e. OP_INV */
@@ -104,6 +302,14 @@
static void slc_upper_region_init(void)
{
/*
+ * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
+ * only if PAE exists in current HW. So we had to check pae_exist
+ * before using them.
+ */
+ if (!pae_exists())
+ return;
+
+ /*
* ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
* as we don't use PAE40.
*/
@@ -113,9 +319,14 @@
static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
{
+#ifdef CONFIG_ISA_ARCV2
+
unsigned int ctrl;
unsigned long end;
+ if (!slc_exists())
+ return;
+
/*
* The Region Flush operation is specified by CTRL.RGN_OP[11..9]
* - b'000 (default) is Flush,
@@ -142,7 +353,7 @@
* END needs to be setup before START (latter triggers the operation)
* END can't be same as START, so add (l2_line_sz - 1) to sz
*/
- end = paddr + sz + slc_line_sz - 1;
+ end = paddr + sz + gd->arch.slc_line_sz - 1;
/*
* Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
@@ -156,85 +367,82 @@
read_aux_reg(ARC_AUX_SLC_CTRL);
while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
-}
-#endif /* CONFIG_ISA_ARCV2 */
-#ifdef CONFIG_ISA_ARCV2
+#endif /* CONFIG_ISA_ARCV2 */
+}
+
+static void arc_ioc_setup(void)
+{
+ /* IOC Aperture start is equal to DDR start */
+ unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+ /* IOC Aperture size is equal to DDR size */
+ long ap_size = CONFIG_SYS_SDRAM_SIZE;
+
+ /* Unsupported configuration. See [ NOTE 2 ] for more details. */
+ if (!slc_exists())
+ panic("Try to enable IOC but SLC is not present");
+
+ /* Unsupported configuration. See [ NOTE 2 ] for more details. */
+ if (!dcache_enabled())
+ panic("Try to enable IOC but L1 D$ is disabled");
+
+ if (!is_power_of_2(ap_size) || ap_size < 4096)
+ panic("IOC Aperture size must be power of 2 and bigger 4Kib");
+
+ /* IOC Aperture start must be aligned to the size of the aperture */
+ if (ap_base % ap_size != 0)
+ panic("IOC Aperture start must be aligned to the size of the aperture");
+
+ flush_n_invalidate_dcache_all();
+
+ /*
+ * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
+ * so setting 0x11 implies 512M, 0x12 implies 1G...
+ */
+ write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
+ order_base_2(ap_size / 1024) - 2);
+
+ write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
+ write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
+ write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
+}
+
static void read_decode_cache_bcr_arcv2(void)
{
- union {
- struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
- unsigned int pad:24, way:2, lsz:2, sz:4;
-#else
- unsigned int sz:4, lsz:2, way:2, pad:24;
-#endif
- } fields;
- unsigned int word;
- } slc_cfg;
+#ifdef CONFIG_ISA_ARCV2
- union {
- struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
- unsigned int pad:24, ver:8;
-#else
- unsigned int ver:8, pad:24;
-#endif
- } fields;
- unsigned int word;
- } sbcr;
+ union bcr_slc_cfg slc_cfg;
- sbcr.word = read_aux_reg(ARC_BCR_SLC);
- if (sbcr.fields.ver) {
+ if (slc_exists()) {
slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
- slc_exists = true;
- slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
+ gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
+
+ /*
+ * We don't support configuration where L1 I$ or L1 D$ is
+ * absent but SL$ exists. See [ NOTE 2 ] for more details.
+ */
+ if (!icache_exists() || !dcache_exists())
+ panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent");
}
- union {
- struct bcr_clust_cfg {
-#ifdef CONFIG_CPU_BIG_ENDIAN
- unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
-#else
- unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
-#endif
- } fields;
- unsigned int word;
- } cbcr;
-
- cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
- if (cbcr.fields.c && ioc_enable)
- ioc_exists = true;
+#endif /* CONFIG_ISA_ARCV2 */
}
-#endif
void read_decode_cache_bcr(void)
{
int dc_line_sz = 0, ic_line_sz = 0;
-
- union {
- struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
- unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
-#else
- unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
-#endif
- } fields;
- unsigned int word;
- } ibcr, dbcr;
+ union bcr_di_cache ibcr, dbcr;
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
if (ibcr.fields.ver) {
- icache_exists = true;
- l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
+ gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
if (!ic_line_sz)
panic("Instruction exists but line length is 0\n");
}
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
if (dbcr.fields.ver) {
- dcache_exists = true;
- l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
+ gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
if (!dc_line_sz)
panic("Data cache exists but line length is 0\n");
}
@@ -247,109 +455,79 @@
{
read_decode_cache_bcr();
-#ifdef CONFIG_ISA_ARCV2
- read_decode_cache_bcr_arcv2();
+ if (is_isa_arcv2())
+ read_decode_cache_bcr_arcv2();
- if (ioc_exists) {
- /* IOC Aperture start is equal to DDR start */
- unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
- /* IOC Aperture size is equal to DDR size */
- long ap_size = CONFIG_SYS_SDRAM_SIZE;
+ if (is_isa_arcv2() && ioc_enabled())
+ arc_ioc_setup();
- flush_dcache_all();
- invalidate_dcache_all();
-
- if (!is_power_of_2(ap_size) || ap_size < 4096)
- panic("IOC Aperture size must be power of 2 and bigger 4Kib");
-
- /*
- * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
- * so setting 0x11 implies 512M, 0x12 implies 1G...
- */
- write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
- order_base_2(ap_size / 1024) - 2);
-
- /* IOC Aperture start must be aligned to the size of the aperture */
- if (ap_base % ap_size != 0)
- panic("IOC Aperture start must be aligned to the size of the aperture");
-
- write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
- write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
- write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
- }
-
- read_decode_mmu_bcr();
-
- /*
- * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
- * only if PAE exists in current HW. So we had to check pae_exist
- * before using them.
- */
- if (slc_exists && pae_exists)
+ if (is_isa_arcv2() && slc_exists())
slc_upper_region_init();
-#endif /* CONFIG_ISA_ARCV2 */
}
int icache_status(void)
{
- if (!icache_exists)
- return 0;
-
- if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
- return 0;
- else
- return 1;
+ return icache_enabled();
}
void icache_enable(void)
{
- if (icache_exists)
+ if (icache_exists())
write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
~IC_CTRL_CACHE_DISABLE);
}
void icache_disable(void)
{
- if (icache_exists)
- write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
- IC_CTRL_CACHE_DISABLE);
+ if (!icache_exists())
+ return;
+
+ __ic_entire_invalidate();
+
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+ IC_CTRL_CACHE_DISABLE);
+}
+
+/* IC supports only invalidation */
+static inlined_cachefunc void __ic_entire_invalidate(void)
+{
+ if (!icache_enabled())
+ return;
+
+ /* Any write to IC_IVIC register triggers invalidation of entire I$ */
+ write_aux_reg(ARC_AUX_IC_IVIC, 1);
+ /*
+ * As per ARC HS databook (see chapter 5.3.3.2)
+ * it is required to add 3 NOPs after each write to IC_IVIC.
+ */
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
}
void invalidate_icache_all(void)
{
- /* Any write to IC_IVIC register triggers invalidation of entire I$ */
- if (icache_status()) {
- write_aux_reg(ARC_AUX_IC_IVIC, 1);
- /*
- * As per ARC HS databook (see chapter 5.3.3.2)
- * it is required to add 3 NOPs after each write to IC_IVIC.
- */
- __builtin_arc_nop();
- __builtin_arc_nop();
- __builtin_arc_nop();
- read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
- }
+ __ic_entire_invalidate();
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists)
+ /*
+ * If SL$ is bypassed for data it is used only for instructions,
+ * so we need to invalidate it too.
+ * TODO: HS 3.0 supports SLC disable so we need to check slc
+ * enable/disable status here.
+ */
+ if (is_isa_arcv2() && slc_data_bypass())
__slc_entire_op(OP_INV);
-#endif
}
int dcache_status(void)
{
- if (!dcache_exists)
- return 0;
-
- if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
- return 0;
- else
- return 1;
+ return dcache_enabled();
}
void dcache_enable(void)
{
- if (!dcache_exists)
+ if (!dcache_exists())
return;
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
@@ -358,83 +536,77 @@
void dcache_disable(void)
{
- if (!dcache_exists)
+ if (!dcache_exists())
return;
+ __dc_entire_op(OP_FLUSH_N_INV);
+
+ /*
+ * As SLC will be bypassed for data after L1 D$ disable we need to
+ * flush it first before L1 D$ disable. Also we invalidate SLC to
+ * avoid any inconsistent data problems after enabling L1 D$ again with
+ * dcache_enable function.
+ */
+ if (is_isa_arcv2())
+ __slc_entire_op(OP_FLUSH_N_INV);
+
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
DC_CTRL_CACHE_DISABLE);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
-/*
- * Common Helper for Line Operations on {I,D}-Cache
- */
-static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
- const int cacheop)
+/* Common Helper for Line Operations on D-cache */
+static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
+ const int cacheop)
{
unsigned int aux_cmd;
-#if (CONFIG_ARC_MMU_VER == 3)
- unsigned int aux_tag;
-#endif
int num_lines;
- if (cacheop == OP_INV_IC) {
- aux_cmd = ARC_AUX_IC_IVIL;
-#if (CONFIG_ARC_MMU_VER == 3)
- aux_tag = ARC_AUX_IC_PTAG;
-#endif
- } else {
- /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
- aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
-#if (CONFIG_ARC_MMU_VER == 3)
- aux_tag = ARC_AUX_DC_PTAG;
-#endif
- }
+ /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
+ aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
sz += paddr & ~CACHE_LINE_MASK;
paddr &= CACHE_LINE_MASK;
- num_lines = DIV_ROUND_UP(sz, l1_line_sz);
+ num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
while (num_lines-- > 0) {
#if (CONFIG_ARC_MMU_VER == 3)
- write_aux_reg(aux_tag, paddr);
+ write_aux_reg(ARC_AUX_DC_PTAG, paddr);
#endif
write_aux_reg(aux_cmd, paddr);
- paddr += l1_line_sz;
+ paddr += gd->arch.l1_line_sz;
}
}
-static unsigned int __before_dc_op(const int op)
+static inlined_cachefunc void __before_dc_op(const int op)
{
- unsigned int reg;
+ unsigned int ctrl;
- if (op == OP_INV) {
- /*
- * IM is set by default and implies Flush-n-inv
- * Clear it here for vanilla inv
- */
- reg = read_aux_reg(ARC_AUX_DC_CTRL);
- write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
- }
+ ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
- return reg;
+ /* IM bit implies flush-n-inv, instead of vanilla inv */
+ if (op == OP_INV)
+ ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
+ else
+ ctrl |= DC_CTRL_INV_MODE_FLUSH;
+
+ write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
}
-static void __after_dc_op(const int op, unsigned int reg)
+static inlined_cachefunc void __after_dc_op(const int op)
{
if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
-
- /* Switch back to default Invalidate mode */
- if (op == OP_INV)
- write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
}
-static inline void __dc_entire_op(const int cacheop)
+static inlined_cachefunc void __dc_entire_op(const int cacheop)
{
int aux;
- unsigned int ctrl_reg = __before_dc_op(cacheop);
+
+ if (!dcache_enabled())
+ return;
+
+ __before_dc_op(cacheop);
if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
aux = ARC_AUX_DC_IVDC;
@@ -443,36 +615,36 @@
write_aux_reg(aux, 0x1);
- __after_dc_op(cacheop, ctrl_reg);
+ __after_dc_op(cacheop);
}
static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
const int cacheop)
{
- unsigned int ctrl_reg = __before_dc_op(cacheop);
+ if (!dcache_enabled())
+ return;
- __cache_line_loop(paddr, sz, cacheop);
- __after_dc_op(cacheop, ctrl_reg);
+ __before_dc_op(cacheop);
+ __dcache_line_loop(paddr, sz, cacheop);
+ __after_dc_op(cacheop);
}
-#else
-#define __dc_entire_op(cacheop)
-#define __dc_line_op(paddr, sz, cacheop)
-#endif /* !CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
if (start >= end)
return;
-#ifdef CONFIG_ISA_ARCV2
- if (!ioc_exists)
-#endif
+ /*
+ * ARCv1 -> call __dc_line_op
+ * ARCv2 && L1 D$ disabled -> nothing
+ * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
+ * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
+ */
+ if (!is_isa_arcv2() || !ioc_enabled())
__dc_line_op(start, end - start, OP_INV);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists && !ioc_exists)
+ if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
__slc_rgn_op(start, end - start, OP_INV);
-#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
@@ -480,15 +652,17 @@
if (start >= end)
return;
-#ifdef CONFIG_ISA_ARCV2
- if (!ioc_exists)
-#endif
+ /*
+ * ARCv1 -> call __dc_line_op
+ * ARCv2 && L1 D$ disabled -> nothing
+ * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
+ * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
+ */
+ if (!is_isa_arcv2() || !ioc_enabled())
__dc_line_op(start, end - start, OP_FLUSH);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists && !ioc_exists)
+ if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
__slc_rgn_op(start, end - start, OP_FLUSH);
-#endif
}
void flush_cache(unsigned long start, unsigned long size)
@@ -496,22 +670,47 @@
flush_dcache_range(start, start + size);
}
-void invalidate_dcache_all(void)
+/*
+ * As invalidate_dcache_all() is not used in generic U-Boot code and as we
+ * don't need it in arch/arc code alone (invalidate without flush) we implement
+ * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
+ * it's much safer. See [ NOTE 1 ] for more details.
+ */
+void flush_n_invalidate_dcache_all(void)
{
- __dc_entire_op(OP_INV);
+ __dc_entire_op(OP_FLUSH_N_INV);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists)
- __slc_entire_op(OP_INV);
-#endif
+ if (is_isa_arcv2() && !slc_data_bypass())
+ __slc_entire_op(OP_FLUSH_N_INV);
}
void flush_dcache_all(void)
{
__dc_entire_op(OP_FLUSH);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists)
+ if (is_isa_arcv2() && !slc_data_bypass())
__slc_entire_op(OP_FLUSH);
-#endif
+}
+
+/*
+ * This is function to cleanup all caches (and therefore sync I/D caches) which
+ * can be used for cleanup before linux launch or to sync caches during
+ * relocation.
+ */
+void sync_n_cleanup_cache_all(void)
+{
+ __dc_entire_op(OP_FLUSH_N_INV);
+
+ /*
+ * If SL$ is bypassed for data it is used only for instructions,
+ * and we shouldn't flush it. So invalidate it instead of flush_n_inv.
+ */
+ if (is_isa_arcv2()) {
+ if (slc_data_bypass())
+ __slc_entire_op(OP_INV);
+ else
+ __slc_entire_op(OP_FLUSH_N_INV);
+ }
+
+ __ic_entire_invalidate();
}
diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c
index dbc8d68..435fe96 100644
--- a/arch/arc/lib/init_helpers.c
+++ b/arch/arc/lib/init_helpers.c
@@ -4,14 +4,14 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm/cache.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int init_cache_f_r(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
- flush_dcache_all();
-#endif
+ sync_n_cleanup_cache_all();
+
return 0;
}
diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
deleted file mode 100644
index 87bccab..0000000
--- a/arch/arc/lib/memcmp.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef __LITTLE_ENDIAN__
-#define WORD2 r2
-#define SHIFT r3
-#else /* __BIG_ENDIAN__ */
-#define WORD2 r3
-#define SHIFT r2
-#endif /* _ENDIAN__ */
-
-.global memcmp
-.align 4
-memcmp:
- or %r12, %r0, %r1
- asl_s %r12, %r12, 30
- sub %r3, %r2, 1
- brls %r2, %r12, .Lbytewise
- ld %r4, [%r0, 0]
- ld %r5, [%r1, 0]
- lsr.f %lp_count, %r3, 3
- lpne .Loop_end
- ld_s WORD2, [%r0, 4]
- ld_s %r12, [%r1, 4]
- brne %r4, %r5, .Leven
- ld.a %r4, [%r0, 8]
- ld.a %r5, [%r1, 8]
- brne WORD2, %r12, .Lodd
- nop
-.Loop_end:
- asl_s SHIFT, SHIFT, 3
- bhs_s .Last_cmp
- brne %r4, %r5, .Leven
- ld %r4, [%r0, 4]
- ld %r5, [%r1, 4]
-#ifdef __LITTLE_ENDIAN__
- nop_s
- /* one more load latency cycle */
-.Last_cmp:
- xor %r0, %r4, %r5
- bset %r0, %r0, SHIFT
- sub_s %r1, %r0, 1
- bic_s %r1, %r1, %r0
- norm %r1, %r1
- b.d .Leven_cmp
- and %r1, %r1, 24
-.Leven:
- xor %r0, %r4, %r5
- sub_s %r1, %r0, 1
- bic_s %r1, %r1, %r0
- norm %r1, %r1
- /* slow track insn */
- and %r1, %r1, 24
-.Leven_cmp:
- asl %r2, %r4, %r1
- asl %r12, %r5, %r1
- lsr_s %r2, %r2, 1
- lsr_s %r12, %r12, 1
- j_s.d [%blink]
- sub %r0, %r2, %r12
- .balign 4
-.Lodd:
- xor %r0, WORD2, %r12
- sub_s %r1, %r0, 1
- bic_s %r1, %r1, %r0
- norm %r1, %r1
- /* slow track insn */
- and %r1, %r1, 24
- asl_s %r2, %r2, %r1
- asl_s %r12, %r12, %r1
- lsr_s %r2, %r2, 1
- lsr_s %r12, %r12, 1
- j_s.d [%blink]
- sub %r0, %r2, %r12
-#else /* __BIG_ENDIAN__ */
-.Last_cmp:
- neg_s SHIFT, SHIFT
- lsr %r4, %r4, SHIFT
- lsr %r5, %r5, SHIFT
- /* slow track insn */
-.Leven:
- sub.f %r0, %r4, %r5
- mov.ne %r0, 1
- j_s.d [%blink]
- bset.cs %r0, %r0, 31
-.Lodd:
- cmp_s WORD2, %r12
-
- mov_s %r0, 1
- j_s.d [%blink]
- bset.cs %r0, %r0, 31
-#endif /* _ENDIAN__ */
- .balign 4
-.Lbytewise:
- breq %r2, 0, .Lnil
- ldb %r4, [%r0, 0]
- ldb %r5, [%r1, 0]
- lsr.f %lp_count, %r3
- lpne .Lbyte_end
- ldb_s %r3, [%r0, 1]
- ldb %r12, [%r1, 1]
- brne %r4, %r5, .Lbyte_even
- ldb.a %r4, [%r0, 2]
- ldb.a %r5, [%r1, 2]
- brne %r3, %r12, .Lbyte_odd
- nop
-.Lbyte_end:
- bcc .Lbyte_even
- brne %r4, %r5, .Lbyte_even
- ldb_s %r3, [%r0, 1]
- ldb_s %r12, [%r1, 1]
-.Lbyte_odd:
- j_s.d [%blink]
- sub %r0, %r3, %r12
-.Lbyte_even:
- j_s.d [%blink]
- sub %r0, %r4, %r5
-.Lnil:
- j_s.d [%blink]
- mov %r0, 0
diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S
deleted file mode 100644
index 51dd73a..0000000
--- a/arch/arc/lib/memcpy-700.S
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global memcpy
-.align 4
-memcpy:
- or %r3, %r0, %r1
- asl_s %r3, %r3, 30
- mov_s %r5, %r0
- brls.d %r2, %r3, .Lcopy_bytewise
- sub.f %r3, %r2, 1
- ld_s %r12, [%r1, 0]
- asr.f %lp_count, %r3, 3
- bbit0.d %r3, 2, .Lnox4
- bmsk_s %r2, %r2, 1
- st.ab %r12, [%r5, 4]
- ld.a %r12, [%r1, 4]
-.Lnox4:
- lppnz .Lendloop
- ld_s %r3, [%r1, 4]
- st.ab %r12, [%r5, 4]
- ld.a %r12, [%r1, 8]
- st.ab %r3, [%r5, 4]
-.Lendloop:
- breq %r2, 0, .Last_store
- ld %r3, [%r5, 0]
-#ifdef __LITTLE_ENDIAN__
- add3 %r2, -1, %r2
- /* uses long immediate */
- xor_s %r12, %r12, %r3
- bmsk %r12, %r12, %r2
- xor_s %r12, %r12, %r3
-#else /* __BIG_ENDIAN__ */
- sub3 %r2, 31, %r2
- /* uses long immediate */
- xor_s %r3, %r3, %r12
- bmsk %r3, %r3, %r2
- xor_s %r12, %r12, %r3
-#endif /* _ENDIAN__ */
-.Last_store:
- j_s.d [%blink]
- st %r12, [%r5, 0]
-
- .balign 4
-.Lcopy_bytewise:
- jcs [%blink]
- ldb_s %r12, [%r1, 0]
- lsr.f %lp_count, %r3
- bhs_s .Lnox1
- stb.ab %r12, [%r5, 1]
- ldb.a %r12, [%r1, 1]
-.Lnox1:
- lppnz .Lendbloop
- ldb_s %r3, [%r1, 1]
- stb.ab %r12, [%r5, 1]
- ldb.a %r12, [%r1, 2]
- stb.ab %r3, [%r5, 1]
-.Lendbloop:
- j_s.d [%blink]
- stb %r12, [%r5, 0]
diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S
deleted file mode 100644
index 017e8af..0000000
--- a/arch/arc/lib/memset.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */
-
-.global memset
-.align 4
-memset:
- mov_s %r4, %r0
- or %r12, %r0, %r2
- bmsk.f %r12, %r12, 1
- extb_s %r1, %r1
- asl %r3, %r1, 8
- beq.d .Laligned
- or_s %r1, %r1, %r3
- brls %r2, SMALL, .Ltiny
- add %r3, %r2, %r0
- stb %r1, [%r3, -1]
- bclr_s %r3, %r3, 0
- stw %r1, [%r3, -2]
- bmsk.f %r12, %r0, 1
- add_s %r2, %r2, %r12
- sub.ne %r2, %r2, 4
- stb.ab %r1, [%r4, 1]
- and %r4, %r4, -2
- stw.ab %r1, [%r4, 2]
- and %r4, %r4, -4
-
- .balign 4
-.Laligned:
- asl %r3, %r1, 16
- lsr.f %lp_count, %r2, 2
- or_s %r1, %r1, %r3
- lpne .Loop_end
- st.ab %r1, [%r4, 4]
-.Loop_end:
- j_s [%blink]
-
- .balign 4
-.Ltiny:
- mov.f %lp_count, %r2
- lpne .Ltiny_end
- stb.ab %r1, [%r4, 1]
-.Ltiny_end:
- j_s [%blink]
-
-/*
- * memzero: @r0 = mem, @r1 = size_t
- * memset: @r0 = mem, @r1 = char, @r2 = size_t
- */
-
-.global memzero
-.align 4
-memzero:
- /* adjust bzero args to memset args */
- mov %r2, %r1
- mov %r1, 0
- /* tail call so need to tinker with blink */
- b memset
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
index 7802f40..96b4bd3 100644
--- a/arch/arc/lib/relocate.c
+++ b/arch/arc/lib/relocate.c
@@ -17,6 +17,9 @@
{
size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ return 0;
+
memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
return 0;
@@ -40,6 +43,9 @@
Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ return 0;
+
debug("Section .rela.dyn is located at %08x-%08x\n",
(unsigned int)re_src, (unsigned int)re_end);
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 0d72fe7..c78dd00 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -10,26 +10,6 @@
#include <asm/arcregs.h>
ENTRY(_start)
-; ARCompact devices are not supposed to be SMP so master/slave check
-; makes no sense.
-#ifdef CONFIG_ISA_ARCV2
- ; Non-masters will be halted immediately, they might be kicked later
- ; by platform code right before passing control to the Linux kernel
- ; in bootm.c:boot_jump_linux().
- lr r5, [identity]
- lsr r5, r5, 8
- bmsk r5, r5, 7
- cmp r5, 0
- mov.nz r0, r5
- bz .Lmaster_proceed
- flag 1
- nop
- nop
- nop
-
-.Lmaster_proceed:
-#endif
-
/* Setup interrupt vector base that matches "__text_start" */
sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
@@ -98,7 +78,13 @@
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
- j board_init_f
+ bl board_init_f
+
+ /* We only get here if relocation is disabled by GD_FLG_SKIP_RELOC */
+ /* Make sure we don't lose GD overwritten by zero new GD */
+ mov %r0, %r25
+ mov %r1, 0
+ bl board_init_r
ENDPROC(_start)
/*
diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S
deleted file mode 100644
index 55fcc9f..0000000
--- a/arch/arc/lib/strchr-700.S
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * ARC700 has a relatively long pipeline and branch prediction, so we want
- * to avoid branches that are hard to predict. On the other hand, the
- * presence of the norm instruction makes it easier to operate on whole
- * words branch-free.
- */
-
-.global strchr
-.align 4
-strchr:
- extb_s %r1, %r1
- asl %r5, %r1, 8
- bmsk %r2, %r0, 1
- or %r5, %r5, %r1
- mov_s %r3, 0x01010101
- breq.d %r2, %r0, .Laligned
- asl %r4, %r5, 16
- sub_s %r0, %r0, %r2
- asl %r7, %r2, 3
- ld_s %r2, [%r0]
-#ifdef __LITTLE_ENDIAN__
- asl %r7, %r3, %r7
-#else /* __BIG_ENDIAN__ */
- lsr %r7, %r3, %r7
-#endif /* _ENDIAN__ */
- or %r5, %r5, %r4
- ror %r4, %r3
- sub %r12, %r2, %r7
- bic_s %r12, %r12, %r2
- and %r12, %r12, %r4
- brne.d %r12, 0, .Lfound0_ua
- xor %r6, %r2, %r5
- ld.a %r2, [%r0, 4]
- sub %r12, %r6, %r7
- bic %r12, %r12, %r6
-#ifdef __LITTLE_ENDIAN__
- and %r7, %r12, %r4
- /* For speed, we want this branch to be unaligned. */
- breq %r7, 0, .Loop
- /* Likewise this one */
- b .Lfound_char
-#else /* __BIG_ENDIAN__ */
- and %r12, %r12, %r4
- /* For speed, we want this branch to be unaligned. */
- breq %r12, 0, .Loop
- lsr_s %r12, %r12, 7
- bic %r2, %r7, %r6
- b.d .Lfound_char_b
- and_s %r2, %r2, %r12
-#endif /* _ENDIAN__ */
- /* We require this code address to be unaligned for speed... */
-.Laligned:
- ld_s %r2, [%r0]
- or %r5, %r5, %r4
- ror %r4, %r3
- /* ... so that this code address is aligned, for itself and ... */
-.Loop:
- sub %r12, %r2, %r3
- bic_s %r12, %r12, %r2
- and %r12, %r12, %r4
- brne.d %r12, 0, .Lfound0
- xor %r6, %r2, %r5
- ld.a %r2, [%r0, 4]
- sub %r12, %r6, %r3
- bic %r12, %r12, %r6
- and %r7, %r12, %r4
- breq %r7, 0, .Loop
- /*
- *... so that this branch is unaligned.
- * Found searched-for character.
- * r0 has already advanced to next word.
- */
-#ifdef __LITTLE_ENDIAN__
- /*
- * We only need the information about the first matching byte
- * (i.e. the least significant matching byte) to be exact,
- * hence there is no problem with carry effects.
- */
-.Lfound_char:
- sub %r3, %r7, 1
- bic %r3, %r3, %r7
- norm %r2, %r3
- sub_s %r0, %r0, 1
- asr_s %r2, %r2, 3
- j.d [%blink]
- sub_s %r0, %r0, %r2
-
- .balign 4
-.Lfound0_ua:
- mov %r3, %r7
-.Lfound0:
- sub %r3, %r6, %r3
- bic %r3, %r3, %r6
- and %r2, %r3, %r4
- or_s %r12, %r12, %r2
- sub_s %r3, %r12, 1
- bic_s %r3, %r3, %r12
- norm %r3, %r3
- add_s %r0, %r0, 3
- asr_s %r12, %r3, 3
- asl.f 0, %r2, %r3
- sub_s %r0, %r0, %r12
- j_s.d [%blink]
- mov.pl %r0, 0
-#else /* __BIG_ENDIAN__ */
-.Lfound_char:
- lsr %r7, %r7, 7
-
- bic %r2, %r7, %r6
-.Lfound_char_b:
- norm %r2, %r2
- sub_s %r0, %r0, 4
- asr_s %r2, %r2, 3
- j.d [%blink]
- add_s %r0, %r0, %r2
-
-.Lfound0_ua:
- mov_s %r3, %r7
-.Lfound0:
- asl_s %r2, %r2, 7
- or %r7, %r6, %r4
- bic_s %r12, %r12, %r2
- sub %r2, %r7, %r3
- or %r2, %r2, %r6
- bic %r12, %r2, %r12
- bic.f %r3, %r4, %r12
- norm %r3, %r3
-
- add.pl %r3, %r3, 1
- asr_s %r12, %r3, 3
- asl.f 0, %r2, %r3
- add_s %r0, %r0, %r12
- j_s.d [%blink]
- mov.mi %r0, 0
-#endif /* _ENDIAN__ */
diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S
deleted file mode 100644
index 8cb7d2f..0000000
--- a/arch/arc/lib/strcmp.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This is optimized primarily for the ARC700.
- * It would be possible to speed up the loops by one cycle / word
- * respective one cycle / byte by forcing double source 1 alignment, unrolling
- * by a factor of two, and speculatively loading the second word / byte of
- * source 1; however, that would increase the overhead for loop setup / finish,
- * and strcmp might often terminate early.
- */
-
-.global strcmp
-.align 4
-strcmp:
- or %r2, %r0, %r1
- bmsk_s %r2, %r2, 1
- brne %r2, 0, .Lcharloop
- mov_s %r12, 0x01010101
- ror %r5, %r12
-.Lwordloop:
- ld.ab %r2, [%r0, 4]
- ld.ab %r3, [%r1, 4]
- nop_s
- sub %r4, %r2, %r12
- bic %r4, %r4, %r2
- and %r4, %r4, %r5
- brne %r4, 0, .Lfound0
- breq %r2 ,%r3, .Lwordloop
-#ifdef __LITTLE_ENDIAN__
- xor %r0, %r2, %r3 /* mask for difference */
- sub_s %r1, %r0, 1
- bic_s %r0, %r0, %r1 /* mask for least significant difference bit */
- sub %r1, %r5, %r0
- xor %r0, %r5, %r1 /* mask for least significant difference byte */
- and_s %r2, %r2, %r0
- and_s %r3, %r3, %r0
-#endif /* _ENDIAN__ */
- cmp_s %r2, %r3
- mov_s %r0, 1
- j_s.d [%blink]
- bset.lo %r0, %r0, 31
-
- .balign 4
-#ifdef __LITTLE_ENDIAN__
-.Lfound0:
- xor %r0, %r2, %r3 /* mask for difference */
- or %r0, %r0, %r4 /* or in zero indicator */
- sub_s %r1, %r0, 1
- bic_s %r0, %r0, %r1 /* mask for least significant difference bit */
- sub %r1, %r5, %r0
- xor %r0, %r5, %r1 /* mask for least significant difference byte */
- and_s %r2, %r2, %r0
- and_s %r3, %r3, %r0
- sub.f %r0, %r2, %r3
- mov.hi %r0, 1
- j_s.d [%blink]
- bset.lo %r0, %r0, 31
-#else /* __BIG_ENDIAN__ */
- /*
- * The zero-detection above can mis-detect 0x01 bytes as zeroes
- * because of carry-propagateion from a lower significant zero byte.
- * We can compensate for this by checking that bit0 is zero.
- * This compensation is not necessary in the step where we
- * get a low estimate for r2, because in any affected bytes
- * we already have 0x00 or 0x01, which will remain unchanged
- * when bit 7 is cleared.
- */
- .balign 4
-.Lfound0:
- lsr %r0, %r4, 8
- lsr_s %r1, %r2
- bic_s %r2, %r2, %r0 /* get low estimate for r2 and get ... */
- bic_s %r0, %r0, %r1 /* <this is the adjusted mask for zeros> */
- or_s %r3, %r3, %r0 /* ... high estimate r3 so that r2 > r3 will */
- cmp_s %r3, %r2 /* ... be independent of trailing garbage */
- or_s %r2, %r2, %r0 /* likewise for r3 > r2 */
- bic_s %r3, %r3, %r0
- rlc %r0, 0 /* r0 := r2 > r3 ? 1 : 0 */
- cmp_s %r2, %r3
- j_s.d [%blink]
- bset.lo %r0, %r0, 31
-#endif /* _ENDIAN__ */
-
- .balign 4
-.Lcharloop:
- ldb.ab %r2,[%r0,1]
- ldb.ab %r3,[%r1,1]
- nop_s
- breq %r2, 0, .Lcmpend
- breq %r2, %r3, .Lcharloop
-.Lcmpend:
- j_s.d [%blink]
- sub %r0, %r2, %r3
diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S
deleted file mode 100644
index 41bb53e..0000000
--- a/arch/arc/lib/strcpy-700.S
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * If dst and src are 4 byte aligned, copy 8 bytes at a time.
- * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
- * it 8 byte aligned. Thus, we can do a little read-ahead, without
- * dereferencing a cache line that we should not touch.
- * Note that short and long instructions have been scheduled to avoid
- * branch stalls.
- * The beq_s to r3z could be made unaligned & long to avoid a stall
- * there, but it is not likely to be taken often, and it would also be likely
- * to cost an unaligned mispredict at the next call.
- */
-
-.global strcpy
-.align 4
-strcpy:
- or %r2, %r0, %r1
- bmsk_s %r2, %r2, 1
- brne.d %r2, 0, charloop
- mov_s %r10, %r0
- ld_s %r3, [%r1, 0]
- mov %r8, 0x01010101
- bbit0.d %r1, 2, loop_start
- ror %r12, %r8
- sub %r2, %r3, %r8
- bic_s %r2, %r2, %r3
- tst_s %r2,%r12
- bne r3z
- mov_s %r4,%r3
- .balign 4
-loop:
- ld.a %r3, [%r1, 4]
- st.ab %r4, [%r10, 4]
-loop_start:
- ld.a %r4, [%r1, 4]
- sub %r2, %r3, %r8
- bic_s %r2, %r2, %r3
- tst_s %r2, %r12
- bne_s r3z
- st.ab %r3, [%r10, 4]
- sub %r2, %r4, %r8
- bic %r2, %r2, %r4
- tst %r2, %r12
- beq loop
- mov_s %r3, %r4
-#ifdef __LITTLE_ENDIAN__
-r3z: bmsk.f %r1, %r3, 7
- lsr_s %r3, %r3, 8
-#else /* __BIG_ENDIAN__ */
-r3z: lsr.f %r1, %r3, 24
- asl_s %r3, %r3, 8
-#endif /* _ENDIAN__ */
- bne.d r3z
- stb.ab %r1, [%r10, 1]
- j_s [%blink]
-
- .balign 4
-charloop:
- ldb.ab %r3, [%r1, 1]
- brne.d %r3, 0, charloop
- stb.ab %r3, [%r10, 1]
- j [%blink]
diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S
deleted file mode 100644
index 666e22c..0000000
--- a/arch/arc/lib/strlen.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global strlen
-.align 4
-strlen:
- or %r3, %r0, 7
- ld %r2, [%r3, -7]
- ld.a %r6, [%r3, -3]
- mov %r4, 0x01010101
- /* uses long immediate */
-#ifdef __LITTLE_ENDIAN__
- asl_s %r1, %r0, 3
- btst_s %r0, 2
- asl %r7, %r4, %r1
- ror %r5, %r4
- sub %r1, %r2, %r7
- bic_s %r1, %r1, %r2
- mov.eq %r7, %r4
- sub %r12, %r6, %r7
- bic %r12, %r12, %r6
- or.eq %r12, %r12, %r1
- and %r12, %r12, %r5
- brne %r12, 0, .Learly_end
-#else /* __BIG_ENDIAN__ */
- ror %r5, %r4
- btst_s %r0, 2
- mov_s %r1, 31
- sub3 %r7, %r1, %r0
- sub %r1, %r2, %r4
- bic_s %r1, %r1, %r2
- bmsk %r1, %r1, %r7
- sub %r12, %r6, %r4
- bic %r12, %r12, %r6
- bmsk.ne %r12, %r12, %r7
- or.eq %r12, %r12, %r1
- and %r12, %r12, %r5
- brne %r12, 0, .Learly_end
-#endif /* _ENDIAN__ */
-
-.Loop:
- ld_s %r2, [%r3, 4]
- ld.a %r6, [%r3, 8]
- /* stall for load result */
- sub %r1, %r2, %r4
- bic_s %r1, %r1, %r2
- sub %r12, %r6, %r4
- bic %r12, %r12, %r6
- or %r12, %r12, %r1
- and %r12, %r12, %r5
- breq %r12, 0, .Loop
-.Lend:
- and.f %r1, %r1, %r5
- sub.ne %r3, %r3, 4
- mov.eq %r1, %r12
-#ifdef __LITTLE_ENDIAN__
- sub_s %r2, %r1, 1
- bic_s %r2, %r2, %r1
- norm %r1, %r2
- sub_s %r0, %r0, 3
- lsr_s %r1, %r1, 3
- sub %r0, %r3, %r0
- j_s.d [%blink]
- sub %r0, %r0, %r1
-#else /* __BIG_ENDIAN__ */
- lsr_s %r1, %r1, 7
- mov.eq %r2, %r6
- bic_s %r1, %r1, %r2
- norm %r1, %r1
- sub %r0, %r3, %r0
- lsr_s %r1, %r1, 3
- j_s.d [%blink]
- add %r0, %r0, %r1
-#endif /* _ENDIAN */
-.Learly_end:
- b.d .Lend
- sub_s.ne %r1, %r1, %r1
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49bcf99..7212fc5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -709,6 +709,7 @@
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
+ select SPECIFY_CONSOLE_INDEX
select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
select SYS_NS16550
@@ -745,6 +746,7 @@
select SUPPORT_SPL
select OF_CONTROL
select SPL_BOARD_INIT if SPL
+ select BOARD_EARLY_INIT_F if WDT
select SPL_OF_CONTROL if SPL
select DM
select DM_ETH if NET
@@ -898,6 +900,7 @@
select DM_SERIAL
select OF_CONTROL
select PL01X_SERIAL
+ select SPECIFY_CONSOLE_INDEX
help
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
@@ -1114,7 +1117,7 @@
(formerly, System LSI Business Division of Panasonic Corporation)
config STM32
- bool "Support STM32"
+ bool "Support STMicroelectronics STM32 MCU with cortex M"
select CPU_V7M
select DM
select DM_SERIAL
@@ -1132,6 +1135,29 @@
Support for STMicroelectronics STiH407/10 SoC family.
This SoC is used on Linaro 96Board STiH410-B2260
+config ARCH_STM32MP
+ bool "Support STMicroelectronics STM32MP Socs with cortex A"
+ select ARCH_MISC_INIT
+ select BOARD_LATE_INIT
+ select CLK
+ select DM
+ select DM_GPIO
+ select DM_RESET
+ select DM_SERIAL
+ select OF_CONTROL
+ select OF_LIBFDT
+ select PINCTRL
+ select REGMAP
+ select SUPPORT_SPL
+ select SYSCON
+ select SYSRESET
+ select SYS_THUMB_BUILD
+ help
+ Support for STM32MP SoC family developed by STMicroelectronics,
+ MPUs based on ARM cortex A core
+ U-BOOT is running in DDR and SPL support is the unsecure First Stage
+ BootLoader (FSBL)
+
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select OF_CONTROL
@@ -1244,6 +1270,8 @@
source "arch/arm/mach-stm32/Kconfig"
+source "arch/arm/mach-stm32mp/Kconfig"
+
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
@@ -1316,6 +1344,7 @@
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5881fdc..4fa8b38 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -72,6 +72,7 @@
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_STM32) += stm32
+machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
index a02304f..f072f2e 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr_misc.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <command.h>
+#include <environment.h>
#include <i2c.h>
#include <net.h>
#include <linux/mtd/st_smi.h>
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 30915d2..3bcb944 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -12,12 +12,26 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_HZ_CLOCK
+static inline u32 read_cntfrq(void)
+{
+ u32 frq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
+ return frq;
+}
+#endif
+
int timer_init(void)
{
gd->arch.tbl = 0;
gd->arch.tbu = 0;
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+#ifdef CONFIG_SYS_HZ_CLOCK
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#else
+ gd->arch.timer_rate_hz = read_cntfrq();
+#endif
return 0;
}
@@ -34,27 +48,9 @@
}
-ulong get_timer(ulong base)
-{
- return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
-}
-
ulong timer_get_boot_us(void)
{
- return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long endtime;
-
- endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
- 1000UL);
-
- endtime += get_ticks();
-
- while (get_ticks() < endtime)
- ;
+ return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000);
}
ulong get_tbclk(void)
diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk
deleted file mode 100644
index 76ffec9..0000000
--- a/arch/arm/cpu/armv7/sunxi/config.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-# Build a combined spl + u-boot image
-ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot-sunxi-with-spl.bin
-endif
-endif
diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c
index a424bab..2959775 100644
--- a/arch/arm/cpu/armv7m/cpu.c
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -37,6 +37,9 @@
* dcache flushing and disabling dcache */
invalidate_dcache_all();
+ icache_disable();
+ invalidate_icache_all();
+
return 0;
}
diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c
index 8e92a33..e4d090e 100644
--- a/arch/arm/cpu/armv7m/mpu.c
+++ b/arch/arm/cpu/armv7m/mpu.c
@@ -10,12 +10,13 @@
#include <asm/armv7m_mpu.h>
#include <asm/io.h>
-#define V7M_MPU_CTRL_ENABLE (1 << 0)
+#define V7M_MPU_CTRL_ENABLE BIT(0)
#define V7M_MPU_CTRL_DISABLE (0 << 0)
-#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
-#define VALID_REGION (1 << 4)
+#define V7M_MPU_CTRL_HFNMIENA BIT(1)
+#define V7M_MPU_CTRL_PRIVDEFENA BIT(2)
+#define VALID_REGION BIT(4)
-#define ENABLE_REGION (1 << 0)
+#define ENABLE_REGION BIT(0)
#define AP_SHIFT 24
#define XN_SHIFT 28
@@ -36,7 +37,7 @@
void enable_mpu(void)
{
- writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
+ writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_PRIVDEFENA, &V7M_MPU->ctrl);
/* Make sure new mpu config is effective for next memory access */
dsb();
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 70a6070..45cbd91 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -644,6 +644,7 @@
switch (reset_type) {
case EFI_RESET_COLD:
case EFI_RESET_WARM:
+ case EFI_RESET_PLATFORM_SPECIFIC:
reset_cpu(0);
break;
case EFI_RESET_SHUTDOWN:
@@ -654,9 +655,9 @@
while (1) { }
}
-void efi_reset_system_init(void)
+efi_status_t efi_reset_system_init(void)
{
- efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
+ return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
}
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9f837d..18fb937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -612,6 +612,29 @@
return 0;
}
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 ecccr2;
+
+ out_be32(&scfg->pfeasbcr,
+ in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+ out_be32(&scfg->pfebsbcr,
+ in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+ /* CCI-400 QoS settings for PFE */
+ out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+ | SCFG_WR_QOS1_PFE2_QOS));
+ out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+ | SCFG_RD_QOS1_PFE2_QOS));
+
+ ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+ out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+ ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index c220267..ff0712b 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -146,6 +146,7 @@
switch (reset_type) {
case EFI_RESET_COLD:
case EFI_RESET_WARM:
+ case EFI_RESET_PLATFORM_SPECIFIC:
psci_system_reset();
break;
case EFI_RESET_SHUTDOWN:
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index bc77dd0..14e7d40 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -185,7 +185,7 @@
pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
- if (pm_api_version != ZYNQMP_PM_VERSION)
+ if (pm_api_version < ZYNQMP_PM_VERSION)
panic("PMUFW version error. Expected: v%d.%d\n",
ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20a4c37..62fbf32 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -143,17 +143,25 @@
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
- zynq-zturn-myir.dtb \
+ zynq-zturn.dtb \
zynq-zybo.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
- zynqmp-ep108.dtb \
zynqmp-mini-emmc.dtb \
zynqmp-mini-nand.dtb \
+ zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zcu102-rev1.0.dtb \
+ zynqmp-zcu104-revA.dtb \
+ zynqmp-zcu104-revC.dtb \
+ zynqmp-zcu106-revA.dtb \
+ zynqmp-zcu111-revA.dtb \
+ zynqmp-zc1232-revA.dtb \
+ zynqmp-zc1254-revA.dtb \
+ zynqmp-zc1275-revA.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
+ zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
@@ -167,7 +175,8 @@
am335x-pdu001.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am43x-epos-evm.dtb \
- am437x-idk-evm.dtb
+ am437x-idk-evm.dtb \
+ am4372-generic.dtb
dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
@@ -225,7 +234,8 @@
stm32f469-disco.dtb
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
- stm32f769-disco.dtb
+ stm32f769-disco.dtb \
+ stm32746g-eval.dtb
dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h743i-eval.dtb
@@ -304,6 +314,8 @@
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+ sun7i-a20-olimex-som204-evb.dtb \
+ sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
@@ -478,12 +490,18 @@
dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
at91-sama5d3_xplained.dtb
+dtb-$(CONFIG_TARGET_MA5D4EK) += \
+ at91-sama5d4_ma5d4evk.dts.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
at91-sama5d4ek.dtb
dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
at91-sama5d4_xplained.dtb
+dtb-$(CONFIG_TARGET_VINCO) += \
+ at91-vinco.dtb
+
dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-a.dtb \
@@ -497,6 +515,9 @@
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+dtb-$(CONFIG_TARGET_STM32MP1) += \
+ stm32mp157c-ed1.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/am4372-generic-u-boot.dtsi b/arch/arm/dts/am4372-generic-u-boot.dtsi
new file mode 100644
index 0000000..03a8a8d
--- /dev/null
+++ b/arch/arm/dts/am4372-generic-u-boot.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/{
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/am4372-generic.dts b/arch/arm/dts/am4372-generic.dts
new file mode 100644
index 0000000..0c48439
--- /dev/null
+++ b/arch/arm/dts/am4372-generic.dts
@@ -0,0 +1,24 @@
+/*
+ * Device Tree Source for Generic AM4372 EVM
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+
+/ {
+ compatible = "ti,am4372", "ti,am43";
+ model = "Texas Instruments AM4372 Generic";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
new file mode 100644
index 0000000..2f68d7a
--- /dev/null
+++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/{
+ ocp {
+ u-boot,dm-spl;
+ };
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&i2c0 {
+ u-boot,dm-spl;
+};
+
+&mmc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
new file mode 100644
index 0000000..2f68d7a
--- /dev/null
+++ b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/{
+ ocp {
+ u-boot,dm-spl;
+ };
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&i2c0 {
+ u-boot,dm-spl;
+};
+
+&mmc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 5f06252..770c08a 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -82,7 +82,7 @@
ð0 {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
+ pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
status = "okay";
phy-mode = "rgmii";
};
@@ -100,6 +100,8 @@
&sdhci0 {
bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_pins>;
status = "okay";
};
@@ -109,6 +111,8 @@
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc_pins>;
status = "okay";
#address-cells = <1>;
@@ -150,3 +154,11 @@
&usb3 {
status = "okay";
};
+
+/* CON17 */
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index aa6587a..7bfccb0 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -89,6 +89,8 @@
ð0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii";
phy_addr = <0x1>;
fixed-link {
@@ -98,6 +100,8 @@
};
&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
@@ -108,6 +112,8 @@
&spi0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_quad_pins>;
spi-flash@0 {
#address-cells = <1>;
@@ -121,6 +127,8 @@
/* Exported on the micro USB connector CON32 through an FTDI */
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
status = "okay";
};
@@ -133,3 +141,10 @@
&usb3 {
status = "okay";
};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 6902342..5400742 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -46,6 +46,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/comphy/comphy_data.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 37xx SoC";
@@ -154,6 +155,11 @@
groups = "uart2";
function = "uart";
};
+
+ mmc_pins: mmc-pins {
+ groups = "emmc_nb";
+ function = "emmc";
+ };
};
pinctrl_sb: pinctrl-sb@18800 {
@@ -162,7 +168,7 @@
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpiosb: gpiosb {
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl_sb 0 0 29>;
+ gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
@@ -177,6 +183,20 @@
function = "mii";
};
+ smi_pins: smi-pins {
+ groups = "smi";
+ function = "smi";
+ };
+
+ sdio_pins: sdio-pins {
+ groups = "sdio_sb";
+ function = "sdio";
+ };
+
+ pcie_pins: pcie-pins {
+ groups = "pcie1";
+ function = "gpio";
+ };
};
usb3: usb@58000 {
@@ -266,20 +286,6 @@
status = "disabled";
};
- pinctl0: pinctl@13830 { /* north bridge */
- compatible = "marvell,armada-3700-pinctl";
- bank-name = "armada-3700-nb";
- reg = <0x13830 0x4>;
- pin-count = <36>;
- };
-
- pinctl1: pinctl@18830 { /* south bridge */
- compatible = "marvell,armada-3700-pinctl";
- bank-name = "armada-3700-sb";
- reg = <0x18830 0x4>;
- pin-count = <30>;
- };
-
comphy: comphy@18300 {
compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
reg = <0x18300 0x28>,
@@ -288,5 +294,21 @@
max-lanes = <2>;
};
};
+
+ pcie0: pcie@d0070000 {
+ compatible = "marvell,armada-37xx-pcie";
+ reg = <0 0xd0070000 0 0x20000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <1>;
+ status = "disabled";
+
+ bus-range = <0 0xff>;
+ ranges = <0x82000000 0 0xe8000000
+ 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
+ 0x81000000 0 0xe9000000
+ 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
+ };
};
};
diff --git a/arch/arm/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/dts/at91-sama5d4_ma5d4.dtsi
new file mode 100644
index 0000000..d3e79fb
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d4_ma5d4.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "sama5d4.dtsi"
+
+/ {
+ model = "Aries/DENX MA5D4";
+ compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
+
+ memory {
+ reg = <0x20000000 0x10000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+
+ clk20m: clk20m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ clock-output-names = "clk20m";
+ };
+ };
+
+ ahb {
+ apb {
+ mmc0: mmc@f8000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
+ vmmc-supply = <&vcc_mmc0_reg>;
+ vqmmc-supply = <&vcc_3v3_reg>;
+ status = "okay";
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ broken-cd;
+ };
+ };
+
+ spi0: spi@f8010000 {
+ cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
+
+ i2c0: i2c@f8014000 {
+ status = "okay";
+ };
+
+ spi1: spi@fc018000 {
+ cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&clk20m>;
+ interrupt-parent = <&pioE>;
+ interrupts = <6 IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <10000000>;
+ };
+
+ can1: can@1 {
+ compatible = "microchip,mcp2515";
+ reg = <1>;
+ clocks = <&clk20m>;
+ interrupt-parent = <&pioE>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <10000000>;
+ };
+ };
+
+ tcb2: timer@fc024000 {
+ timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+ };
+
+ adc0: adc@fc034000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* external trigger conflicts with USBA_VBUS */
+ &pinctrl_adc0_ad0
+ &pinctrl_adc0_ad1
+ &pinctrl_adc0_ad2
+ &pinctrl_adc0_ad3
+ &pinctrl_adc0_ad4
+ >;
+ atmel,adc-vref = <3300>;
+ status = "okay";
+ };
+
+ watchdog@fc068640 {
+ status = "okay";
+ };
+ };
+ };
+
+ vcc_3v3_reg: fixedregulator_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC 3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_mmc0_reg: fixedregulator_mmc0 {
+ compatible = "regulator-fixed";
+ gpio = <&pioE 15 GPIO_ACTIVE_HIGH>;
+ regulator-name = "RST_n MCI0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_reg>;
+ regulator-boot-on;
+ };
+};
diff --git a/arch/arm/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/dts/at91-sama5d4_ma5d4evk.dts
new file mode 100644
index 0000000..f65a67b
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d4_ma5d4evk.dts
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "at91-sama5d4_ma5d4.dtsi"
+
+/ {
+ model = "Aries/DENX MA5D4EVK";
+ compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ ahb {
+ apb {
+ hlcdc: hlcdc@f0000000 {
+ status = "okay";
+
+ hlcdc-display-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
+
+ port@0 {
+ hlcdc_panel_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+
+ };
+
+ macb0: ethernet@f8020000 {
+ phy-mode = "rmii";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ usart0: serial@f802c000 {
+ status = "okay";
+ };
+
+ usart1: serial@f8030000 {
+ status = "okay";
+ };
+
+ mmc1: mmc@fc000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+ vmmc-supply = <&vcc_mmc1_reg>;
+ vqmmc-supply = <&vcc_3v3_reg>;
+ status = "okay";
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ cd-gpios = <&pioE 5 0>;
+ };
+ };
+
+ adc0: adc@fc034000 {
+ atmel,adc-ts-wires = <4>;
+ atmel,adc-ts-pressure-threshold = <10000>;
+ };
+
+
+ pinctrl@fc06a000 {
+ board {
+ pinctrl_mmc1_cd: mmc1_cd {
+ atmel,pins = <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+ pinctrl_usba_vbus: usba_vbus {
+ atmel,pins =
+ <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+ };
+ };
+ };
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ user1 {
+ label = "user1";
+ gpios = <&pioD 28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user2 {
+ label = "user2";
+ gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user3 {
+ label = "user3";
+ gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ panel: panel {
+ /* Actually Ampire 800480R2 */
+ compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
+ backlight = <&backlight>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel_input: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hlcdc_panel_output>;
+ };
+ };
+ };
+
+ vcc_mmc1_reg: fixedregulator_mmc1 {
+ compatible = "regulator-fixed";
+ gpio = <&pioE 17 GPIO_ACTIVE_LOW>;
+ regulator-name = "VDD MCI1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_reg>;
+ };
+};
diff --git a/arch/arm/dts/at91-vinco.dts b/arch/arm/dts/at91-vinco.dts
new file mode 100644
index 0000000..ff6d2e3
--- /dev/null
+++ b/arch/arm/dts/at91-vinco.dts
@@ -0,0 +1,246 @@
+/*
+ * Device Tree file for VInCo platform
+ *
+ * Copyright (C) 2014 Atmel,
+ * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ * 2015 Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+ model = "L+G VInCo platform";
+ compatible = "l+g,vinco", "atmel,sama5d4", "atmel,sama5";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x20000000 0x4000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ ahb {
+ apb {
+
+ adc0: adc@fc034000 {
+ status = "okay"; /* Enable ADC IIO support */
+ };
+
+ mmc0: mmc@f8000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0
+ &pinctrl_mmc0_dat1_3
+ &pinctrl_mmc0_dat4_7>;
+ vqmmc-supply = <&vcc_3v3_reg>;
+ vmmc-supply = <&vcc_3v3_reg>;
+ no-1-8-v;
+ status = "okay";
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ non-removable;
+ broken-cd;
+ status = "okay";
+ };
+ };
+
+ spi0: spi@f8010000 {
+ cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
+ status = "okay";
+ m25p80@0 {
+ compatible = "n25q32b", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
+
+ i2c0: i2c@f8014000 {
+ status = "okay";
+ };
+
+ i2c1: i2c@f8018000 {
+ status = "okay";
+ /* kerkey security module */
+ };
+
+ macb0: ethernet@f8020000 {
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&pioB>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ };
+
+ i2c2: i2c@f8024000 {
+ status = "okay";
+
+ rtc1: rtc@64 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+ };
+
+ usart2: serial@fc008000 {
+ /* MBUS */
+ status = "okay";
+ };
+
+ usart3: serial@fc00c000 {
+ /* debug */
+ status = "okay";
+ };
+
+ usart4: serial@fc010000 {
+ /* LMN */
+ pinctrl-0 = <&pinctrl_usart4 &pinctrl_usart4_rts>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+ };
+
+ tcb2: timer@fc024000 {
+ timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+ };
+
+ macb1: ethernet@fc028000 {
+ phy-mode = "rmii";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ interrupt-parent = <&pioB>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ watchdog@fc068640 {
+ status = "okay";
+ };
+
+ pinctrl@fc06a000 {
+ board {
+ pinctrl_usba_vbus: usba_vbus {
+ atmel,pins =
+ <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+ };
+ };
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ led_err {
+ label = "err";
+ gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led_rssi {
+ label = "rssi";
+ gpios = <&pioA 9 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led_tls {
+ label = "tls";
+ gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led_lmc {
+ label = "lmc";
+ gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led_wmt {
+ label = "wmt";
+ gpios = <&pioA 29 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led_pwr {
+ label = "pwr";
+ gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ };
+
+ vcc_3v3_reg: fixedregulator_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC 3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi
new file mode 100644
index 0000000..c67c3dd
--- /dev/null
+++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi
@@ -0,0 +1,13 @@
+/*
+ * da850-lcdk U-Boot Additions
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ aliases {
+ i2c0 = &i2c0;
+ };
+};
diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts
new file mode 100644
index 0000000..a1f4d6d
--- /dev/null
+++ b/arch/arm/dts/da850-lcdk.dts
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "da850.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "DA850/AM1808/OMAP-L138 LCDK";
+ compatible = "ti,da850-lcdk", "ti,da850";
+
+ aliases {
+ serial2 = &serial2;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0xc0000000 0x08000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dsp_memory_region: dsp-memory@c3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0xc3000000 0x1000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DA850/OMAP-L138 LCDK";
+ simple-audio-card,widgets =
+ "Line", "Line In",
+ "Line", "Line Out";
+ simple-audio-card,routing =
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp0>;
+ system-clock-frequency = <24576000>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <24576000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ user1 {
+ label = "GPIO Key USER1";
+ linux,code = <BTN_0>;
+ gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
+ };
+
+ user2 {
+ label = "GPIO Key USER2";
+ linux,code = <BTN_1>;
+ gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ vga-bridge {
+ compatible = "ti,ths8135";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&lcdc_out_vga>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ ddc-i2c-bus = <&i2c0>;
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+};
+
+&pmx_core {
+ status = "okay";
+
+ mcasp0_pins: pinmux_mcasp0_pins {
+ pinctrl-single,bits = <
+ /* AHCLKX AFSX ACLKX */
+ 0x00 0x00101010 0x00f0f0f0
+ /* ARX13 ARX14 */
+ 0x04 0x00000110 0x00000ff0
+ >;
+ };
+
+ nand_pins: nand_pins {
+ pinctrl-single,bits = <
+ /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
+ 0x1c 0x10110010 0xf0ff00f0
+ /*
+ * EMA_D[0], EMA_D[1], EMA_D[2],
+ * EMA_D[3], EMA_D[4], EMA_D[5],
+ * EMA_D[6], EMA_D[7]
+ */
+ 0x24 0x11111111 0xffffffff
+ /*
+ * EMA_D[8], EMA_D[9], EMA_D[10],
+ * EMA_D[11], EMA_D[12], EMA_D[13],
+ * EMA_D[14], EMA_D[15]
+ */
+ 0x20 0x11111111 0xffffffff
+ /* EMA_A[1], EMA_A[2] */
+ 0x30 0x01100000 0x0ff00000
+ >;
+ };
+};
+
+&serial2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial2_rxtx_pins>;
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ bus_freq = <2200000>;
+ status = "okay";
+};
+
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mii_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ tlv320aic3106: tlv320aic3106@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x18>;
+ status = "okay";
+ };
+};
+
+&mcasp0 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcasp0_pins>;
+ status = "okay";
+
+ op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 1 2 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&aemif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins>;
+ status = "okay";
+ cs3 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-ranges;
+ ranges;
+
+ ti,cs-chipselect = <3>;
+
+ nand@2000000,0 {
+ compatible = "ti,davinci-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x02000000 0x02000000
+ 1 0x00000000 0x00008000>;
+
+ ti,davinci-chipselect = <1>;
+ ti,davinci-mask-ale = <0>;
+ ti,davinci-mask-cle = <0>;
+ ti,davinci-mask-chipsel = <0>;
+
+ ti,davinci-nand-buswidth = <16>;
+ ti,davinci-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ ti,davinci-nand-use-bbt;
+
+ /*
+ * The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
+ * "To boot from NAND Flash, the AIS should be written
+ * to NAND block 1 (NAND block 0 is not used by default)".
+ * The same doc mentions that for ROM "Silicon Revision 2.1",
+ * "Updated NAND boot mode to offer boot from block 0 or block 1".
+ * However the limitaion is left here by default for compatibility
+ * with older silicon and because it needs new boot pin settings
+ * not possible in stock LCDK.
+ */
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot env";
+ reg = <0 0x020000>;
+ };
+ partition@20000 {
+ /* The LCDK defaults to booting from this partition */
+ label = "u-boot";
+ reg = <0x020000 0x080000>;
+ };
+ partition@a0000 {
+ label = "free space";
+ reg = <0x0a0000 0>;
+ };
+ };
+ };
+ };
+};
+
+&prictrl {
+ status = "okay";
+};
+
+&memctrl {
+ status = "okay";
+};
+
+&lcdc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins>;
+
+ port {
+ lcdc_out_vga: endpoint {
+ remote-endpoint = <&vga_bridge_in>;
+ };
+ };
+};
+
+&vpif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vpif_capture_pins>;
+ status = "okay";
+};
+
+&dsp {
+ memory-region = <&dsp_memory_region>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi
index 02e2f8f..c66cf78 100644
--- a/arch/arm/dts/da850.dtsi
+++ b/arch/arm/dts/da850.dtsi
@@ -23,11 +23,18 @@
reg = <0xfffee000 0x2000>;
};
};
-
- aliases {
- spi0 = &spi0;
+ dsp: dsp@11800000 {
+ compatible = "ti,da850-dsp";
+ reg = <0x11800000 0x40000>,
+ <0x11e00000 0x8000>,
+ <0x11f00000 0x8000>,
+ <0x01c14044 0x4>,
+ <0x01c14174 0x8>;
+ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ status = "disabled";
};
-
soc@1c00000 {
compatible = "simple-bus";
model = "da850";
diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi
index 62ef830..3e7da7c 100644
--- a/arch/arm/dts/dra7-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra7-evm-u-boot.dtsi
@@ -13,3 +13,23 @@
&pcf_hdmi{
u-boot,i2c-offset-len = <0>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_ddr_rev20 {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_rev20_conf {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi
index 8ae64c0..e2ab0bb 100644
--- a/arch/arm/dts/dra71-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra71-evm-u-boot.dtsi
@@ -21,3 +21,27 @@
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_ddr_rev20 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_ddr_conf {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_rev20_conf {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
index 8ae64c0..e2ab0bb 100644
--- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
@@ -21,3 +21,27 @@
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_ddr_rev20 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_ddr_conf {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_rev20_conf {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi
index b007f78..a5a0694 100644
--- a/arch/arm/dts/dra76-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra76-evm-u-boot.dtsi
@@ -13,3 +13,15 @@
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_conf {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
index b024a65..a1f289f 100644
--- a/arch/arm/dts/dra76-evm.dts
+++ b/arch/arm/dts/dra76-evm.dts
@@ -9,6 +9,7 @@
#include "dra76x.dtsi"
#include "dra7-evm-common.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -100,46 +101,6 @@
};
};
-&dra7_pmx_core {
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-};
-
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -345,23 +306,27 @@
&mmc1 {
status = "okay";
vmmc-supply = <&vio_3v3_sd>;
- vmmc_aux-supply = <&ldo4_reg>;
+ vqmmc-supply = <&ldo4_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&vio_1v8>;
bus-width = <8>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_default>;
+ pinctrl-2 = <&mmc2_pins_default>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
};
/* No RTC on this device */
diff --git a/arch/arm/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 0000000..baba7b0
--- /dev/null
+++ b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Texas Instruments
+// MMC IOdelay values for TI's DRA76x and AM576x SoCs.
+// Author: Sekhar Nori <nsekhar@ti.com>
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ *
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50: mmc1_pins_ddr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc3_pins_default: mmc3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc4_pins_hs: mmc4_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
+ 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL2 in datamanual */
+ mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_default_conf: mmc4_iodelay_default_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts
index 225c7c5..02000fc 100644
--- a/arch/arm/dts/fsl-ls1088a-qds.dts
+++ b/arch/arm/dts/fsl-ls1088a-qds.dts
@@ -19,6 +19,43 @@
};
};
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0 0 0x5 0x80000000 0x08000000
+ 2 0 0x5 0x30000000 0x00010000
+ 3 0 0x5 0x20000000 0x00010000>;
+ status = "okay";
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ fpga: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus", "fsl,ls1088aqds-fpga",
+ "fsl,fpga-qixis";
+ reg = <0x2 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 2 0 0x100>;
+ };
+};
+
&dspi {
bus-num = <0>;
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f8f8654..b4a42cf 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -75,6 +75,11 @@
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x2240000 0x0 0x20000>;
+ interrupts = <0 21 0x4>; /* Level high type */
+ };
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dts b/arch/arm/dts/r8a7790-stout-u-boot.dts
index 12092fc..d2b7d37 100644
--- a/arch/arm/dts/r8a7790-stout-u-boot.dts
+++ b/arch/arm/dts/r8a7790-stout-u-boot.dts
@@ -8,3 +8,7 @@
#include "r8a7790-stout.dts"
#include "r8a7790-u-boot.dtsi"
+
+&scifa0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-vyasa-u-boot.dtsi b/arch/arm/dts/rk3288-vyasa-u-boot.dtsi
new file mode 100644
index 0000000..6017ca2
--- /dev/null
+++ b/arch/arm/dts/rk3288-vyasa-u-boot.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ /* Add a dummy value to cause of-platdata think this is bytes */
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-vyasa.dts b/arch/arm/dts/rk3288-vyasa.dts
index 93a9c5e..850aa25 100644
--- a/arch/arm/dts/rk3288-vyasa.dts
+++ b/arch/arm/dts/rk3288-vyasa.dts
@@ -52,48 +52,146 @@
};
memory {
+ reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
- reg = <0 0x80000000>;
};
- vcc_sd: sdmmc-regulator {
+ dc12_vbat: dc12-vbat {
compatible = "regulator-fixed";
- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pwr>;
- regulator-name = "vcc_sd";
+ regulator-name = "dc12_vbat";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vboot_3v3: vboot-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vboot_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- startup-delay-us = <100000>;
- vin-supply = <&vcc_io>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
};
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
+ };
+
+ vboot_5v: vboot-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vboot_sv";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
};
-};
-&dmc {
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- /* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+ v3g_3v3: v3g-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "v3g_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
+ };
+
+ vsus_5v: vsus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vsus_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_io>;
+ };
+
+ vusb1_5v: vusb1-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vusb1_5v";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vsus_5v>;
+ };
+
+ vusb2_5v: vusb2-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vusb2_5v";
+ enable-active-high;
+ gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_pwr_en>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vsus_5v>;
+ };
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ };
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
};
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@@ -103,12 +201,12 @@
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int &global_pwroff>;
- wakeup-source;
- rockchip,system-power-controller;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ rockchip,system-power-controller;
+ wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
@@ -123,23 +221,23 @@
vcc12-supply = <&vcc_io>;
regulators {
- vdd_cpu: vdd_log: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ vdd_cpu: DCDC_REG1 {
+ regulator-name = "vdd_arm";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
- regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_gpu";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
- regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@@ -147,20 +245,20 @@
};
vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
@@ -168,11 +266,11 @@
};
vcca_tp: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_tp";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_tp";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
@@ -180,22 +278,22 @@
};
vcc_codec: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_codec";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_codec";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-name = "vdd_10";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@@ -203,11 +301,11 @@
};
vcc_gps: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_gps";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_gps";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -215,11 +313,11 @@
};
vccio_sd: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
@@ -227,11 +325,11 @@
};
vcc10_lcd: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc10_lcd";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-name = "vcc10_lcd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -239,11 +337,11 @@
};
vcc_18: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_18";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -251,34 +349,34 @@
};
vcc18_lcd: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc18_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
- vcc33_sd: SWITCH_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ vcc_sd: SWITCH_REG1 {
+ regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc33_sd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_lan: SWITCH_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_lan";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_lan";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
@@ -287,10 +385,11 @@
};
};
-&sdmmc {
- u-boot,dm-pre-reloc;
+&i2c2 {
status = "okay";
+};
+&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
@@ -300,10 +399,44 @@
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
+ status = "okay";
};
&uart2 {
- u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&phy_pwr_en>;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
status = "okay";
};
@@ -312,16 +445,44 @@
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ gmac {
+ phy_int: phy-int {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_pmeb: phy-pmeb {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rst: phy-rst {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+ };
+
pmic {
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
- sdmmc {
- sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ usb_host {
+ phy_pwr_en: phy-pwr-en {
+ rockchip,pins = <RK_GPIO2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
+ usb2_pwr_en: usb2-pwr-en {
+ rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_otg {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <RK_GPIO0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+
};
};
};
diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts
index 362ea42..4bf53a7 100644
--- a/arch/arm/dts/stm32429i-eval.dts
+++ b/arch/arm/dts/stm32429i-eval.dts
@@ -230,6 +230,7 @@
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
bus-width = <4>;
+ max-frequency = <14000000>;
};
&timers1 {
diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts
new file mode 100644
index 0000000..4f6d38a
--- /dev/null
+++ b/arch/arm/dts/stm32746g-eval.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2018 - Christophe Priouzeau <christophe.priouzeau@st.com>
+ *
+ * Based on:
+ * stm32f746-disco.dts from U-boot 2018.01
+ * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+#include <dt-bindings/memory/stm32-sdram.h>
+
+/ {
+ model = "STMicroelectronics STM32F746G-EVAL board";
+ compatible = "st,stm32f746g-eval", "st,stm32f746";
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p1 rw rootwait";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x2000000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ spi0 = &qspi;
+ mmc0 = &sdio;
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ led1 {
+ compatible = "st,led1";
+ led-gpio = <&gpiof 10 0>;
+ };
+
+ button1 {
+ compatible = "st,button1";
+ button-gpio = <&gpioc 13 0>;
+ };
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&pinctrl {
+ usart1_pins_a: usart1@0 {
+ pins1 {
+ pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
+ bias-disable;
+ };
+ };
+
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+ <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+ <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+ <STM32F746_PA2_FUNC_ETH_MDIO>,
+ <STM32F746_PC1_FUNC_ETH_MDC>,
+ <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+ <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+ <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+ <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ slew-rate = <2>;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ pins {
+ pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
+ <STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/
+ <STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */
+ <STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */
+ <STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */
+ <STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */
+ <STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */
+ <STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */
+ <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
+ <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
+ <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
+ <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
+ <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
+ <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
+ <STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */
+ <STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */
+
+ <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
+ <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
+ <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
+ <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
+ <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
+ <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
+ <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
+ <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
+ <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
+ <STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */
+ <STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/
+ <STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */
+ <STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */
+ <STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */
+ <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
+ <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
+
+ <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
+ <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
+ <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
+ <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
+
+ <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
+ <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
+
+ <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
+ <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
+ <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
+ <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
+ <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
+ <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
+ <STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */
+ <STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */
+ <STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */
+ <STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */
+ <STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */
+ <STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */
+
+ <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
+ <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
+ <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
+ <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
+ <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
+ <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
+ slew-rate = <2>;
+ };
+ };
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mac {
+ status = "okay";
+ pinctrl-0 = <ðernet_mii>;
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&fmc {
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ */
+ bank1: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
+ CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
+ TWR_1 TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
+
+&sdio {
+ status = "okay";
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <25000000>;
+};
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 9a9e4e5..4a67719 100644
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -1,3 +1,11 @@
+/{
+ soc {
+ timer5: timer@40000c00 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
&pinctrl {
usart1_pins_a: usart1@0 {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 9e8d2a0..e47f762 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -89,6 +89,37 @@
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
};
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiok 3 0>;
+ status = "okay";
+ };
+
+ panel-rgb@0 {
+ compatible = "simple-panel";
+ backlight = <&backlight>;
+ enable-gpios = <&gpioi 12 0>;
+ status = "okay";
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <41>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <0>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
};
&clk_hse {
@@ -183,6 +214,40 @@
slew-rate = <2>;
};
};
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
+ <STM32F746_PG12_FUNC_LCD_B4>,
+ <STM32F746_PI9_FUNC_LCD_VSYNC>,
+ <STM32F746_PI10_FUNC_LCD_HSYNC>,
+ <STM32F746_PI14_FUNC_LCD_CLK>,
+ <STM32F746_PI15_FUNC_LCD_R0>,
+ <STM32F746_PJ0_FUNC_LCD_R1>,
+ <STM32F746_PJ1_FUNC_LCD_R2>,
+ <STM32F746_PJ2_FUNC_LCD_R3>,
+ <STM32F746_PJ3_FUNC_LCD_R4>,
+ <STM32F746_PJ4_FUNC_LCD_R5>,
+ <STM32F746_PJ5_FUNC_LCD_R6>,
+ <STM32F746_PJ6_FUNC_LCD_R7>,
+ <STM32F746_PJ7_FUNC_LCD_G0>,
+ <STM32F746_PJ8_FUNC_LCD_G1>,
+ <STM32F746_PJ9_FUNC_LCD_G2>,
+ <STM32F746_PJ10_FUNC_LCD_G3>,
+ <STM32F746_PJ11_FUNC_LCD_G4>,
+ <STM32F746_PJ13_FUNC_LCD_B1>,
+ <STM32F746_PJ14_FUNC_LCD_B2>,
+ <STM32F746_PJ15_FUNC_LCD_B3>,
+ <STM32F746_PK0_FUNC_LCD_G5>,
+ <STM32F746_PK1_FUNC_LCD_G6>,
+ <STM32F746_PK2_FUNC_LCD_G7>,
+ <STM32F746_PK4_FUNC_LCD_B5>,
+ <STM32F746_PK5_FUNC_LCD_B6>,
+ <STM32F746_PK6_FUNC_LCD_B7>,
+ <STM32F746_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
};
&usart1 {
@@ -250,3 +315,8 @@
bus-width = <4>;
max-frequency = <25000000>;
};
+
+<dc {
+ status = "okay";
+ pinctrl-0 = <<dc_pins>;
+};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 46d148e..8581df9 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -323,6 +323,22 @@
pinctrl-names = "default", "opendrain";
max-frequency = <48000000>;
};
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+ };
+
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+ u-boot,dm-pre-reloc;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
new file mode 100644
index 0000000..ddfa079
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -0,0 +1,155 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/ {
+ soc {
+ ddr: ddr@0x5A003000{
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp1-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ clocks = <&rcc_clk AXIDCG>,
+ <&rcc_clk DDRC1>,
+ <&rcc_clk DDRC2>,
+ <&rcc_clk DDRPHYC>,
+ <&rcc_clk DDRCAPB>,
+ <&rcc_clk DDRPHYCAPB>;
+
+ clock-names = "axidcg",
+ "ddrc1",
+ "ddrc2",
+ "ddrphyc",
+ "ddrcapb",
+ "ddrphycapb";
+
+ st,mem-name = DDR_MEM_NAME;
+ st,mem-speed = <DDR_MEM_SPEED>;
+ st,mem-size = <DDR_MEM_SIZE>;
+
+ st,ctl-reg = <
+ DDR_MSTR
+ DDR_MRCTRL0
+ DDR_MRCTRL1
+ DDR_DERATEEN
+ DDR_DERATEINT
+ DDR_PWRCTL
+ DDR_PWRTMG
+ DDR_HWLPCTL
+ DDR_RFSHCTL0
+ DDR_RFSHCTL3
+ DDR_CRCPARCTL0
+ DDR_ZQCTL0
+ DDR_DFITMG0
+ DDR_DFITMG1
+ DDR_DFILPCFG0
+ DDR_DFIUPD0
+ DDR_DFIUPD1
+ DDR_DFIUPD2
+ DDR_DFIPHYMSTR
+ DDR_ODTMAP
+ DDR_DBG0
+ DDR_DBG1
+ DDR_DBGCMD
+ DDR_POISONCFG
+ DDR_PCCFG
+ >;
+
+ st,ctl-timing = <
+ DDR_RFSHTMG
+ DDR_DRAMTMG0
+ DDR_DRAMTMG1
+ DDR_DRAMTMG2
+ DDR_DRAMTMG3
+ DDR_DRAMTMG4
+ DDR_DRAMTMG5
+ DDR_DRAMTMG6
+ DDR_DRAMTMG7
+ DDR_DRAMTMG8
+ DDR_DRAMTMG14
+ DDR_ODTCFG
+ >;
+
+ st,ctl-map = <
+ DDR_ADDRMAP1
+ DDR_ADDRMAP2
+ DDR_ADDRMAP3
+ DDR_ADDRMAP4
+ DDR_ADDRMAP5
+ DDR_ADDRMAP6
+ DDR_ADDRMAP9
+ DDR_ADDRMAP10
+ DDR_ADDRMAP11
+ >;
+
+ st,ctl-perf = <
+ DDR_SCHED
+ DDR_SCHED1
+ DDR_PERFHPR1
+ DDR_PERFLPR1
+ DDR_PERFWR1
+ DDR_PCFGR_0
+ DDR_PCFGW_0
+ DDR_PCFGQOS0_0
+ DDR_PCFGQOS1_0
+ DDR_PCFGWQOS0_0
+ DDR_PCFGWQOS1_0
+ DDR_PCFGR_1
+ DDR_PCFGW_1
+ DDR_PCFGQOS0_1
+ DDR_PCFGQOS1_1
+ DDR_PCFGWQOS0_1
+ DDR_PCFGWQOS1_1
+ >;
+
+ st,phy-reg = <
+ DDR_PGCR
+ DDR_ACIOCR
+ DDR_DXCCR
+ DDR_DSGCR
+ DDR_DCR
+ DDR_ODTCR
+ DDR_ZQ0CR1
+ DDR_DX0GCR
+ DDR_DX1GCR
+ DDR_DX2GCR
+ DDR_DX3GCR
+ >;
+
+ st,phy-timing = <
+ DDR_PTR0
+ DDR_PTR1
+ DDR_PTR2
+ DDR_DTPR0
+ DDR_DTPR1
+ DDR_DTPR2
+ DDR_MR0
+ DDR_MR1
+ DDR_MR2
+ DDR_MR3
+ >;
+
+ st,phy-cal = <
+ DDR_DX0DLLCR
+ DDR_DX0DQTR
+ DDR_DX0DQSTR
+ DDR_DX1DLLCR
+ DDR_DX1DQTR
+ DDR_DX1DQSTR
+ DDR_DX2DLLCR
+ DDR_DX2DQTR
+ DDR_DX2DQSTR
+ DDR_DX3DLLCR
+ DDR_DX3DQTR
+ DDR_DX3DQSTR
+ >;
+
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
new file mode 100644
index 0000000..352e470
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/* STM32MP157C ED1 and ED2 BOARD configuration
+ * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
+ * Reference used NT5CC256M16DP-DI from NANYA
+ *
+ * DDR type / Platform DDR3/3L
+ * freq 533MHz
+ * width 32
+ * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
+ * DDR density 8
+ * timing mode optimized
+ * Scheduling/QoS options : type = 2
+ * address mapping : RBC
+ */
+
+#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
+#define DDR_MEM_SPEED 533
+#define DDR_MEM_SIZE 0x40000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0081008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B2414
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F070707
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00001201
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100B03
+#define DDR_PCFGQOS1_1 0x00800100
+#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200001F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000208
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x0000005B
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
new file mode 100644
index 0000000..1eca802
--- /dev/null
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -0,0 +1,145 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ gpio25 = &gpioz;
+ };
+
+ config {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+
+ stgen: stgen@5C008000 {
+ compatible = "st,stm32-stgen";
+ reg = <0x5C008000 0x1000>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&clk_hsi {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lsi {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_csi {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc_rst {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc_reboot {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioz {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
new file mode 100644
index 0000000..b84899a
--- /dev/null
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -0,0 +1,338 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/reset-controller/stm32mp1-resets.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ aliases {
+ serial3 = &uart4;
+ };
+
+ intc: interrupt-controller@a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_csi: clk-csi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc_clk UART4_K>;
+ status = "disabled";
+ };
+
+ sdmmc3: sdmmc@48004000 {
+ compatible = "st,stm32-sdmmc2";
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
+ reg-names = "sdmmc", "delay";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
+ clocks = <&rcc_clk SDMMC3_K>;
+ resets = <&rcc_rst SDMMC3_R>;
+ st,idma = <1>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ rcc: rcc@50000000 {
+ compatible = "syscon", "simple-mfd";
+
+ reg = <0x50000000 0x1000>;
+
+ rcc_clk: rcc-clk@50000000 {
+ #clock-cells = <1>;
+ compatible = "st,stm32mp1-rcc-clk";
+ };
+
+ rcc_rst: rcc-reset@50000000 {
+ #reset-cells = <1>;
+ compatible = "st,stm32mp1-rcc-rst";
+ };
+
+ rcc_reboot: rcc-reboot@50000000 {
+ compatible = "syscon-reboot";
+ regmap = <&rcc>;
+ offset = <0x404>;
+ mask = <0x1>;
+ };
+ };
+
+ pinctrl: pin-controller {
+ compatible = "st,stm32mp157-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50002000 0xa400>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc_clk GPIOA>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ status = "disabled";
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc_clk GPIOB>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ status = "disabled";
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc_clk GPIOC>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ status = "disabled";
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&rcc_clk GPIOD>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ status = "disabled";
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&rcc_clk GPIOE>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ status = "disabled";
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&rcc_clk GPIOF>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ status = "disabled";
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&rcc_clk GPIOG>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ status = "disabled";
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&rcc_clk GPIOH>;
+ st,bank-name = "GPIOH";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ status = "disabled";
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&rcc_clk GPIOI>;
+ st,bank-name = "GPIOI";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ status = "disabled";
+ };
+
+ gpioj: gpio@5000b000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x400>;
+ clocks = <&rcc_clk GPIOJ>;
+ st,bank-name = "GPIOJ";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ status = "disabled";
+ };
+
+ gpiok: gpio@5000c000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa000 0x400>;
+ clocks = <&rcc_clk GPIOK>;
+ st,bank-name = "GPIOK";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pin-controller-z {
+ compatible = "st,stm32mp157-z-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x54004000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@54004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&rcc_clk GPIOZ>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ status = "disabled";
+ };
+ };
+
+ sdmmc1: sdmmc@58005000 {
+ compatible = "st,stm32-sdmmc2";
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+ reg-names = "sdmmc", "delay";
+ clocks = <&rcc_clk SDMMC1_K>;
+ resets = <&rcc_rst SDMMC1_R>;
+ st,idma = <1>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ sdmmc2: sdmmc@58007000 {
+ compatible = "st,stm32-sdmmc2";
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+ reg-names = "sdmmc", "delay";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
+ clocks = <&rcc_clk SDMMC2_K>;
+ resets = <&rcc_rst SDMMC2_R>;
+ st,idma = <1>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@5c002000 {
+ compatible = "st,stm32f7-i2c";
+ reg = <0x5c002000 0x400>;
+ interrupt-names = "event", "error", "wakeup";
+ clocks = <&rcc_clk I2C4_K>;
+ resets = <&rcc_rst I2C4_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
new file mode 100644
index 0000000..2caa939
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -0,0 +1,155 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ i2c3 = &i2c4;
+ };
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c4 {
+ u-boot,dm-pre-reloc;
+};
+
+&pmic {
+ u-boot,dm-pre-reloc;
+};
+
+/* CLOCK init */
+&rcc_clk {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_DISABLED
+ CLK_SDMMC12_PLL3R
+ CLK_STGEN_HSE
+ CLK_I2C46_PCLK5
+ CLK_I2C12_PCLK1
+ CLK_SDMMC3_PLL3R
+ CLK_I2C35_PCLK1
+ CLK_UART1_PCLK5
+ CLK_UART24_PCLK1
+ CLK_UART35_PCLK1
+ CLK_UART6_PCLK2
+ CLK_UART78_PCLK1
+ >;
+
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
+ pll1: st,pll@0 {
+ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
+ frac = < 0x800 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
+ pll3: st,pll@2 {
+ cfg = < 3 128 3 20 7 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
+ pll4: st,pll@3 {
+ cfg = < 5 126 8 8 8 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+/* SPL part **************************************/
+/* MMC1 boot */
+&sdmmc1_b4_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1_dir_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1 {
+ u-boot,dm-spl;
+};
+
+/* MMC2 boot */
+&sdmmc2_b4_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc2_d47_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
new file mode 100644
index 0000000..129cd02
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+ model = "STMicroelectronics STM32MP157C pmic eval daughter";
+ compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x40000000>;
+ };
+};
+
+&gpioa {
+ status = "okay";
+};
+
+&gpiob {
+ status = "okay";
+};
+
+&gpioc {
+ status = "okay";
+};
+
+&gpiod {
+ status = "okay";
+};
+
+&gpioe {
+ status = "okay";
+};
+
+&gpiof {
+ status = "okay";
+};
+
+&gpiog {
+ status = "okay";
+};
+
+&gpioh {
+ status = "okay";
+};
+
+&gpioi {
+ status = "okay";
+};
+
+&gpioj {
+ status = "okay";
+};
+
+&gpiok {
+ status = "okay";
+};
+
+&gpioz {
+ status = "okay";
+};
+
+&pinctrl {
+ uart4_pins_a: uart4@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_dir_pins_a: sdmmc1-dir@0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+ sdmmc2_b4_pins_a: sdmmc2-b4@0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_pins_a: sdmmc2-d47@0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+};
+
+&pinctrl_z {
+ i2c4_pins_a: i2c4@0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ pmic: stpmu1@33 {
+ compatible = "st,stpmu1";
+ reg = <0x33>;
+ interrupts = <0 2>;
+ interrupt-parent = <&gpioa>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ broken-cd;
+ st,dirpol;
+ st,negedge;
+ st,pin-ckin;
+ bus-width = <4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,dirpol;
+ st,negedge;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
index 9c61bea..32a263c 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
@@ -4,25 +4,38 @@
};
soc {
- emac: ethernet@01c30000 {
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun50i-a64-system-controller",
+ "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+
+ emac: ethernet@1c30000 {
compatible = "allwinner,sun50i-a64-emac";
- reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
- reg-names = "emac", "syscon";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
- reset-names = "ahb";
+ reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
- clock-names = "ahb";
+ clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
- phy = <&phy1>;
+ phy-handle = <&ext_rgmii_phy>;
status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};
};
};
@@ -30,21 +43,17 @@
&pio {
rmii_pins: rmii_pins {
- allwinner,pins = "PD10", "PD11", "PD13", "PD14",
- "PD17", "PD18", "PD19", "PD20",
- "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <3>;
- allwinner,pull = <0>;
+ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
+ "PD18", "PD19", "PD20", "PD22", "PD23";
+ function = "emac";
+ drive-strength = <40>;
};
rgmii_pins: rgmii_pins {
- allwinner,pins = "PD8", "PD9", "PD10", "PD11",
- "PD12", "PD13", "PD15",
- "PD16", "PD17", "PD18", "PD19",
- "PD20", "PD21", "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <3>;
- allwinner,pull = <0>;
+ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
+ "PD13", "PD15", "PD16", "PD17", "PD18",
+ "PD19", "PD20", "PD21", "PD22", "PD23";
+ function = "emac";
+ drive-strength = <40>;
};
};
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
index 780d59a..d1c347d 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -108,10 +108,13 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-mode = "rgmii";
- phy = <&phy1>;
+ phy-handle = <&ext_rgmii_phy>;
status = "okay";
+};
- phy1: ethernet-phy@1 {
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
new file mode 100644
index 0000000..c56620a
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som204-evb.dts"
+
+/ {
+ model = "Olimex A20-SOM204-EVB-eMMC";
+ compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: mmc2_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
new file mode 100644
index 0000000..c183920
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Olimex A20-SOM204-EVB";
+ compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart4;
+ serial2 = &uart7;
+ spi0 = &spi1;
+ spi1 = &spi2;
+ ethernet1 = &rtl8723bs;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ stat {
+ label = "a20-som204-evb:green:stat";
+ gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led1 {
+ label = "a20-som204-evb:green:led1";
+ gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led2 {
+ label = "a20-som204-evb:yellow:led2";
+ gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ rtl_pwrseq: rtl_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy3>;
+ phy-mode = "rgmii";
+ phy-supply = <®_vcc3v3>;
+
+ snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+/* Exposed to UEXT1 */
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/* Exposed to UEXT2 */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&rtl_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ bt_uart_pins: bt_uart_pins@0 {
+ pins = "PG6", "PG7", "PG8";
+ function = "uart3";
+ };
+};
+
+#include "axp209.dtsi"
+
+®_ahci_5v {
+ gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pg";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>,
+ <&spi1_cs0_pins_a>;
+ status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>,
+ <&spi2_cs0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+/* Used for RTL8723BS bluetooth */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_uart_pins>;
+ status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi
index ea50dda..ffd2148 100644
--- a/arch/arm/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/dts/sun8i-a23-a33.dtsi
@@ -289,6 +289,23 @@
function = "uart1";
};
+ nand_pins_a: nand-base0@0 {
+ pins = "PC0", "PC1", "PC2", "PC5",
+ "PC8", "PC9", "PC10", "PC11",
+ "PC12", "PC13", "PC14", "PC15";
+ function = "nand0";
+ };
+
+ nand_cs0_pins_a: nand-cs@0 {
+ pins = "PC4";
+ function = "nand0";
+ };
+
+ nand_rb0_pins_a: nand-rb@0 {
+ pins = "PC6";
+ function = "nand0";
+ };
+
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi
index 0fe73e1..bab6c18 100644
--- a/arch/arm/dts/sun8i-a83t.dtsi
+++ b/arch/arm/dts/sun8i-a83t.dtsi
@@ -227,6 +227,7 @@
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
+ reg = <0x01c19000 0x400>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
status = "disabled";
diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
index 20d489c..e0efcb3 100644
--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -100,14 +100,10 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&mmc0 {
diff --git a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
index 97b993f..c8fd69f 100644
--- a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
+++ b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
@@ -125,15 +125,10 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&ir {
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
index 5113059..78f6c24 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
@@ -48,12 +48,8 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
index caa1a69..d97fdac 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts
@@ -55,6 +55,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@@ -110,14 +111,10 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&ir {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts
index 8df5c74..adab1cbf 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts
@@ -53,6 +53,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -95,14 +96,10 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&mmc0 {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
index b8340f74..afba264 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
@@ -53,6 +53,7 @@
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -167,12 +168,8 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
index e7079b2..136e441 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
@@ -82,7 +82,13 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
phy-mode = "rgmii";
- /delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
};
&mmc2 {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
index f97b040..51aaf49 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
@@ -69,8 +69,15 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
- /delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};
&pio {
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index afa6079..d9d31fa 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -144,9 +144,10 @@
#size-cells = <1>;
ranges;
- syscon: syscon@01c00000 {
- compatible = "allwinner,sun8i-h3-syscon","syscon";
- reg = <0x01c00000 0x34>;
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun8i-h3-system-controller",
+ "syscon";
+ reg = <0x01c00000 0x1000>;
};
dma: dma-controller@01c02000 {
@@ -339,15 +340,12 @@
interrupt-controller;
#interrupt-cells = <3>;
- emac_rgmii_pins: emac0@0 {
- allwinner,pins = "PD0", "PD1", "PD2", "PD3",
- "PD4", "PD5", "PD7",
- "PD8", "PD9", "PD10",
- "PD12", "PD13", "PD15",
- "PD16", "PD17";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ emac_rgmii_pins: emac0 {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD7", "PD8", "PD9", "PD10",
+ "PD12", "PD13", "PD15", "PD16", "PD17";
+ function = "emac";
+ drive-strength = <40>;
};
mmc0_pins_a: mmc0@0 {
@@ -466,16 +464,51 @@
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
- reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
- reg-names = "emac", "syscon";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
- reset-names = "ahb", "ephy";
- clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
- clock-names = "ahb", "ephy";
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio-parent-bus = <&mdio>;
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+
+ external_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
gic: interrupt-controller@01c81000 {
diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
index dce688e..72a8505 100644
--- a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
+++ b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
@@ -61,3 +61,17 @@
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+ status = "okay";
+
+ nand@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-mode = "hw";
+ };
+};
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 40f27bb..8b5b363 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -352,6 +352,7 @@
<&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
+ has-transaction-translator;
};
usb1: usb@5a810100 {
@@ -365,6 +366,7 @@
<&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
+ has-transaction-translator;
};
usb2: usb@5a820100 {
@@ -378,6 +380,7 @@
<&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
+ has-transaction-translator;
};
mioctrl@5b3e0000 {
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index 4f8f386..0393bce 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -276,6 +276,7 @@
<&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
+ has-transaction-translator;
};
usb1: usb@5a810100 {
@@ -289,6 +290,7 @@
<&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
+ has-transaction-translator;
};
usb2: usb@5a820100 {
@@ -302,6 +304,7 @@
<&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
+ has-transaction-translator;
};
soc-glue@5f800000 {
@@ -314,6 +317,24 @@
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-ld4-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@130 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x130 0x8>;
+ };
+ };
+
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts
index 3f9ce6d..c2466cd 100644
--- a/arch/arm/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -91,3 +91,7 @@
&usb1 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 9b3ce13..e9d3a3d 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -327,6 +327,7 @@
<&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
+ has-transaction-translator;
};
usb3: usb@5a810100 {
@@ -340,6 +341,7 @@
<&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
+ has-transaction-translator;
};
soc-glue@5f800000 {
@@ -352,6 +354,29 @@
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-pro4-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@130 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x130 0x8>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x14>;
+ };
+ };
+
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>;
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index c3b627c..a4de9b8 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -359,6 +359,39 @@
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-pro5-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@130 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x130 0x8>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x28>;
+ };
+
+ efuse@300 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x300 0x14>;
+ };
+
+ efuse@400 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x400 0x8>;
+ };
+ };
+
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>;
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 549d930..7822c9e 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -415,6 +415,24 @@
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x58>;
+ };
+ };
+
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts
index f549610..0463a8f 100644
--- a/arch/arm/dts/uniphier-pxs3-ref.dts
+++ b/arch/arm/dts/uniphier-pxs3-ref.dts
@@ -45,6 +45,14 @@
status = "okay";
};
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
+
&gpio {
xirq4 {
gpio-hog;
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index 9c3aad5..87ab5e7 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -203,8 +203,8 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 0>,
- <&pinctrl 96 0 0>,
- <&pinctrl 160 0 0>;
+ <&pinctrl 104 0 0>,
+ <&pinctrl 168 0 0>;
gpio-ranges-group-names = "gpio_range0",
"gpio_range1",
"gpio_range2";
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index c759ac6..fc7585b 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -280,6 +280,7 @@
<&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
+ has-transaction-translator;
};
usb1: usb@5a810100 {
@@ -293,6 +294,7 @@
<&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
+ has-transaction-translator;
};
usb2: usb@5a820100 {
@@ -306,6 +308,7 @@
<&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
+ has-transaction-translator;
};
soc-glue@5f800000 {
@@ -318,6 +321,24 @@
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-sld8-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x14>;
+ };
+ };
+
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
index 4804da5..5f8a0d2 100644
--- a/arch/arm/dts/zynq-cc108.dts
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -1,13 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CC108 board DTS
*
- * (C) Copyright 2007-2013 Xilinx, Inc.
+ * (C) Copyright 2007-2018 Xilinx, Inc.
* (C) Copyright 2007-2013 Michal Simek
* (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
*
* Michal SIMEK <monstr@monstr.eu>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
@@ -70,23 +69,23 @@
label = "qspi-fsbl-uboot-bs";
reg = <0x0 0x400000>; /* 4MB */
};
- partition@0x400000 {
+ partition@400000 {
label = "qspi-linux";
reg = <0x400000 0x400000>; /* 4MB */
};
- partition@0x800000 {
+ partition@800000 {
label = "qspi-rootfs";
reg = <0x800000 0x400000>; /* 4MB */
};
- partition@0xc00000 {
+ partition@c00000 {
label = "qspi-devicetree";
reg = <0xc00000 0x100000>; /* 1MB */
};
- partition@0xd00000 {
+ partition@d00000 {
label = "qspi-scratch";
reg = <0xd00000 0x200000>; /* 2MB */
};
- partition@0xf00000 {
+ partition@f00000 {
label = "qspi-uboot-env";
reg = <0xf00000 0x100000>; /* 1MB */
};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index da698a1..bb22466 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Xilinx ZC702 board DTS
- *
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -114,7 +111,7 @@
scl-gpios = <&gpio0 50 0>;
sda-gpios = <&gpio0 51 0>;
- i2cswitch@74 {
+ i2c-mux@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@@ -154,7 +151,7 @@
#size-cells = <0>;
reg = <2>;
eeprom@54 {
- compatible = "at,24c08";
+ compatible = "atmel,24c08";
reg = <0x54>;
};
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index d342306..f24364b 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Xilinx ZC706 board DTS
- *
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -65,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
- i2cswitch@74 {
+ i2c-mux@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@@ -105,7 +102,7 @@
#size-cells = <0>;
reg = <2>;
eeprom@54 {
- compatible = "at,24c08";
+ compatible = "atmel,24c08";
reg = <0x54>;
};
};
@@ -333,3 +330,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
};
+
+&watchdog0 {
+ reset-on-timeout;
+};
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index cc5ba98..a779672 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZC770 XM010 board DTS
*
- * Copyright (C) 2013 - 2015 Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2013-2018 Xilinx, Inc.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -55,8 +54,8 @@
status = "okay";
clock-frequency = <400000>;
- m24c02_eeprom@52 {
- compatible = "at,24c02";
+ eeprom: eeprom@52 {
+ compatible = "atmel,24c02";
reg = <0x52>;
};
@@ -75,14 +74,17 @@
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
- compatible = "sst25wf080";
+ compatible = "sst25wf080", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <1000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@test {
- label = "spi-flash";
- reg = <0x0 0x100000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "data";
+ reg = <0x0 0x100000>;
+ };
};
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 7f08961..3fe6eb5 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZC770 XM013 board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2013-2018 Xilinx, Inc.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -42,8 +41,8 @@
status = "okay";
clock-frequency = <400000>;
- m24c02_eeprom@52 {
- compatible = "at,24c02";
+ eeprom: eeprom@52 {
+ compatible = "atmel,24c02";
reg = <0x52>;
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 699cd2c..19d5b27 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZC770 XM012 board DTS
*
- * Copyright (C) 2013 - 2015 Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2013-2018 Xilinx, Inc.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -38,8 +37,8 @@
status = "okay";
clock-frequency = <400000>;
- m24c02_eeprom@52 {
- compatible = "at,24c02";
+ eeprom0: eeprom@52 {
+ compatible = "atmel,24c02";
reg = <0x52>;
};
};
@@ -48,8 +47,8 @@
status = "okay";
clock-frequency = <400000>;
- m24c02_eeprom@52 {
- compatible = "at,24c02";
+ eeprom1: eeprom@52 {
+ compatible = "atmel,24c02";
reg = <0x52>;
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index 81a6aa5..efd0833 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZC770 XM013 board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -68,7 +67,7 @@
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
- eeprom: at25@0 {
+ eeprom: eeprom@0 {
at25,byte-len = <8192>;
at25,addr-mode = <2>;
at25,page-size = <32>;
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index a9ff0e6..24eccf1 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Xilinx ZED board DTS
- *
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynq-zturn-myir.dts b/arch/arm/dts/zynq-zturn-myir.dts
deleted file mode 100644
index a5ecfcc..0000000
--- a/arch/arm/dts/zynq-zturn-myir.dts
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
- * Copyright (C) 2017 Alexander Graf <agraf@suse.de>
- *
- * Based on zynq-zed.dts which is:
- * Copyright (C) 2011 - 2014 Xilinx
- * Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-/dts-v1/;
-/include/ "zynq-7000.dtsi"
-
-/ {
- model = "Zynq Z-Turn MYIR Board";
- compatible = "xlnx,zynq-7000";
-
- aliases {
- ethernet0 = &gem0;
- serial0 = &uart1;
- serial1 = &uart0;
- spi0 = &qspi;
- mmc0 = &sdhci0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x0 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- led_r {
- label = "led_r";
- gpios = <&gpio0 0x72 0x1>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led_g {
- label = "led_g";
- gpios = <&gpio0 0x73 0x1>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led_b {
- label = "led_b";
- gpios = <&gpio0 0x74 0x1>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- usr_led1 {
- label = "usr_led1";
- gpios = <&gpio0 0x0 0x1>;
- default-state = "off";
- linux,default-trigger = "none";
- };
-
- usr_led2 {
- label = "usr_led2";
- gpios = <&gpio0 0x9 0x1>;
- default-state = "off";
- linux,default-trigger = "none";
- };
- };
-
- gpio-beep {
- compatible = "gpio-beeper";
- label = "pl-beep";
- gpios = <&gpio0 0x75 0x0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- autorepeat;
- K1 {
- label = "K1";
- gpios = <&gpio0 0x32 0x1>;
- linux,code = <0x66>;
- gpio-key,wakeup;
- autorepeat;
- };
- };
-};
-
-&clkc {
- ps-clk-frequency = <33333333>;
- fclk-enable = <0xf>;
-};
-
-&qspi {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&gem0 {
- status = "okay";
- phy-mode = "rgmii-id";
- phy-handle = <ðernet_phy>;
-
- ethernet_phy: ethernet-phy@0 {
- reg = <0x0>;
- };
-};
-
-&sdhci0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&uart1 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&can0 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <400000>;
-
- stlm75@49 {
- status = "okay";
- compatible = "lm75";
- reg = <0x49>;
- };
-
- adxl345@53 {
- compatible = "adi,adxl34x", "adxl34x";
- reg = <0x53>;
- interrupt-parent = <&intc>;
- interrupts = <0x0 0x1e 0x4>;
- };
-};
diff --git a/arch/arm/dts/zynq-zturn.dts b/arch/arm/dts/zynq-zturn.dts
new file mode 100644
index 0000000..8aa384b
--- /dev/null
+++ b/arch/arm/dts/zynq-zturn.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
+ * Copyright (C) 2017 Alexander Graf <agraf@suse.de>
+ *
+ * Based on zynq-zed.dts which is:
+ * Copyright (C) 2011 - 2014 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ *
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq Z-Turn MYIR Board";
+ compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ usr-led1 {
+ label = "usr-led1";
+ gpios = <&gpio0 0x0 0x1>;
+ default-state = "off";
+ };
+
+ usr-led2 {
+ label = "usr-led2";
+ gpios = <&gpio0 0x9 0x1>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ K1 {
+ label = "K1";
+ gpios = <&gpio0 0x32 0x1>;
+ linux,code = <0x66>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&can0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ stlm75@49 {
+ status = "okay";
+ compatible = "lm75";
+ reg = <0x49>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
+ reg = <0x53>;
+ interrupt-parent = <&intc>;
+ interrupts = <0x0 0x1e 0x4>;
+ };
+};
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index 52ec5a4..3844822 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Digilent ZYBO board DTS
- *
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
new file mode 100644
index 0000000..b18d8d1
--- /dev/null
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2017, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/ {
+ fclk0: fclk0 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 71>;
+ };
+
+ fclk1: fclk1 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 72>;
+ };
+
+ fclk2: fclk2 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 73>;
+ };
+
+ fclk3: fclk3 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 74>;
+ };
+
+ pss_ref_clk: pss_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ video_clk: video_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ pss_alt_ref_clk: pss_alt_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ gt_crx_ref_clk: gt_crx_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <108000000>;
+ };
+
+ aux_ref_clk: aux_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clkc: clkc {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clkc";
+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
+ clock-output-names = "iopll", "rpll", "apll", "dpll",
+ "vpll", "iopll_to_fpd", "rpll_to_fpd",
+ "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
+ "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
+ "dbg_trace", "dbg_tstmp", "dp_video_ref",
+ "dp_audio_ref", "dp_stc_ref", "gdma_ref",
+ "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
+ "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
+ "topsw_main", "topsw_lsbus", "gtgref0_ref",
+ "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
+ "usb1_bus_ref", "usb3_dual_ref", "usb0",
+ "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
+ "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
+ "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
+ "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
+ "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
+ "uart0_ref", "uart1_ref", "spi0_ref",
+ "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
+ "can0_ref", "can1_ref", "can0", "can1",
+ "dll_ref", "adma_ref", "timestamp_ref",
+ "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
+ };
+
+ dp_aclk: dp_aclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-accuracy = <100>;
+ };
+};
+
+&can0 {
+ clocks = <&clkc 63>, <&clkc 31>;
+};
+
+&can1 {
+ clocks = <&clkc 64>, <&clkc 31>;
+};
+
+&cpu0 {
+ clocks = <&clkc 10>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&gpu {
+ clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
+};
+
+&lpd_dma_chan1 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&nand0 {
+ clocks = <&clkc 60>, <&clkc 31>;
+};
+
+&gem0 {
+ clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem1 {
+ clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem2 {
+ clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem3 {
+ clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gpio {
+ clocks = <&clkc 31>;
+};
+
+&i2c0 {
+ clocks = <&clkc 61>;
+};
+
+&i2c1 {
+ clocks = <&clkc 62>;
+};
+
+&pcie {
+ clocks = <&clkc 23>;
+};
+
+&qspi {
+ clocks = <&clkc 53>, <&clkc 31>;
+};
+
+&sata {
+ clocks = <&clkc 22>;
+};
+
+&sdhci0 {
+ clocks = <&clkc 54>, <&clkc 31>;
+};
+
+&sdhci1 {
+ clocks = <&clkc 55>, <&clkc 31>;
+};
+
+&spi0 {
+ clocks = <&clkc 58>, <&clkc 31>;
+};
+
+&spi1 {
+ clocks = <&clkc 59>, <&clkc 31>;
+};
+
+&uart0 {
+ clocks = <&clkc 56>, <&clkc 31>;
+};
+
+&uart1 {
+ clocks = <&clkc 57>, <&clkc 31>;
+};
+
+&usb0 {
+ clocks = <&clkc 32>, <&clkc 34>;
+};
+
+&usb1 {
+ clocks = <&clkc 33>, <&clkc 34>;
+};
+
+&watchdog0 {
+ clocks = <&clkc 75>;
+};
+
+&xilinx_ams {
+ clocks = <&clkc 70>;
+};
+
+&xilinx_drm {
+ clocks = <&clkc 16>;
+};
+
+&xlnx_dp {
+ clocks = <&dp_aclk>, <&clkc 17>;
+};
+
+&xlnx_dpdma {
+ clocks = <&clkc 20>;
+};
+
+&xlnx_dp_snd_codec0 {
+ clocks = <&clkc 17>;
+};
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index f6e83e1..a8664e8 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/ {
@@ -26,6 +25,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
+ u-boot,dm-pre-reloc;
};
clk250: clk250 {
diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
deleted file mode 100644
index 12d9fe1..0000000
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * clock specification for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/ {
- misc_clk: misc_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- u-boot,dm-pre-reloc;
- };
-
- i2c_clk: i2c_clk {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <111111111>;
- };
-
- sata_clk: sata_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <75000000>;
- };
-
- dp_aclk: clock0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-accuracy = <100>;
- };
-
- clk100: clk100 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- clk600: clk600 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- };
-
- dp_aud_clk: clock1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <22579200>;
- clock-accuracy = <100>;
- };
-};
-
-&can0 {
- clocks = <&misc_clk &misc_clk>;
-};
-
-&can1 {
- clocks = <&misc_clk &misc_clk>;
-};
-
-&fpd_dma_chan1 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan2 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan3 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan4 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan5 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan6 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan7 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan8 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&gem0 {
- clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
-};
-
-&gpio {
- clocks = <&misc_clk>;
-};
-
-&i2c0 {
- clocks = <&i2c_clk>;
-};
-
-&i2c1 {
- clocks = <&i2c_clk>;
-};
-
-&nand0 {
- clocks = <&misc_clk &misc_clk>;
-};
-
-&qspi {
- clocks = <&misc_clk &misc_clk>;
-};
-
-&sata {
- clocks = <&sata_clk>;
-};
-
-&sdhci0 {
- clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&sdhci1 {
- clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&spi0 {
- clocks = <&misc_clk &misc_clk>;
-};
-
-&spi1 {
- clocks = <&misc_clk &misc_clk>;
-};
-
-&uart0 {
- clocks = <&misc_clk &misc_clk>;
-};
-
-&usb0 {
- clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&usb1 {
- clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&watchdog0 {
- clocks= <&misc_clk>;
-};
-
-&xilinx_drm {
- clocks = <&misc_clk>;
-};
-
-&xlnx_dp {
- clocks = <&dp_aclk>, <&dp_aud_clk>;
-};
-
-&xlnx_dp_snd_codec0 {
- clocks = <&dp_aud_clk>;
-};
-
-&xlnx_dpdma {
- clocks = <&misc_clk>;
-};
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
deleted file mode 100644
index a16ffdc..0000000
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * dts file for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2014 - 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-ep108-clk.dtsi"
-
-/ {
- model = "ZynqMP EP108";
-
- aliases {
- ethernet0 = &gem0;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- serial0 = &uart0;
- spi0 = &qspi;
- spi1 = &spi0;
- spi2 = &spi1;
- usb0 = &usb0;
- usb1 = &usb1;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-};
-
-&can0 {
- status = "okay";
-};
-
-&can1 {
- status = "okay";
-};
-
-&gem0 {
- status = "okay";
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
- phy0: phy@0 {
- reg = <0>;
- max-speed = <100>;
- };
-};
-
-&gpio {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <400000>;
- eeprom@54 {
- compatible = "atmel,24c64";
- reg = <0x54>;
- };
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <400000>;
- eeprom@55 {
- compatible = "atmel,24c64";
- reg = <0x55>;
- };
-};
-
-&nand0 {
- status = "okay";
- arasan,has-mdma;
- num-cs = <1>;
-
- partition@0 { /* for testing purpose */
- label = "nand-fsbl-uboot";
- reg = <0x0 0x0 0x400000>;
- };
- partition@1 { /* for testing purpose */
- label = "nand-linux";
- reg = <0x0 0x400000 0x1400000>;
- };
- partition@2 { /* for testing purpose */
- label = "nand-device-tree";
- reg = <0x0 0x1800000 0x400000>;
- };
- partition@3 { /* for testing purpose */
- label = "nand-rootfs";
- reg = <0x0 0x1C00000 0x1400000>;
- };
- partition@4 { /* for testing purpose */
- label = "nand-bitstream";
- reg = <0x0 0x3000000 0x400000>;
- };
- partition@5 { /* for testing purpose */
- label = "nand-misc";
- reg = <0x0 0x3400000 0xFCC00000>;
- };
-};
-
-&qspi {
- status = "okay";
- flash@0 {
- compatible = "m25p80";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <10000000>;
- partition@qspi-fsbl-uboot { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@qspi-linux { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@qspi-device-tree { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@qspi-rootfs { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5E0000>;
- };
- };
-};
-
-&sata {
- status = "okay";
- ceva,broken-gen2;
- /* SATA Phy OOB timing settings */
- ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
- ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
- ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
- ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
- ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
- ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
- ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
- ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
-};
-
-&sdhci0 {
- status = "okay";
- bus-width = <8>;
- xlnx,mio_bank = <2>;
-};
-
-&sdhci1 {
- status = "okay";
- xlnx,mio_bank = <1>;
-};
-
-&spi0 {
- status = "okay";
- num-cs = <1>;
- spi0_flash0: spi0_flash0@0 {
- compatible = "m25p80";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- spi0_flash0@0 {
- label = "spi0_flash0";
- reg = <0x0 0x100000>;
- };
- };
-};
-
-&spi1 {
- status = "okay";
- num-cs = <1>;
- spi1_flash0: spi1_flash0@0 {
- compatible = "m25p80";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- spi1_flash0@0 {
- label = "spi1_flash0";
- reg = <0x0 0x100000>;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&dwc3_0 {
- status = "okay";
- dr_mode = "peripheral";
- maximum-speed = "high-speed";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&dwc3_1 {
- status = "okay";
- dr_mode = "host";
- maximum-speed = "high-speed";
-};
-
-&watchdog0 {
- status = "okay";
-};
-
-&xlnx_dp {
- xlnx,max-pclock-frequency = <200000>;
-};
-
-&xlnx_dpdma {
- xlnx,axi-clock-freq = <200000000>;
-};
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
new file mode 100644
index 0000000..ea1ca56
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1232
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZC1232 RevA";
+ compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80"; /* 32MB FIXME */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
new file mode 100644
index 0000000..2493883
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1254
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "ZynqMP ZC1254 RevA";
+ compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zc1275-revA.dts
new file mode 100644
index 0000000..2543a67
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1275-revA.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "ZynqMP ZC1275 RevA";
+ compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 04d82c4..c794c91 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -1,17 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
@@ -40,7 +39,6 @@
};
};
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
@@ -93,8 +91,9 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
- eeprom@55 {
- compatible = "at,24c64"; /* 24AA64 */
+
+ eeprom: eeprom@55 {
+ compatible = "atmel,24c64"; /* 24AA64 */
reg = <0x55>;
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 7dfe960..afa90a8 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -1,17 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
@@ -50,7 +49,6 @@
status = "okay";
};
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
@@ -180,15 +178,15 @@
&spi0 {
status = "okay";
num-cs = <1>;
- spi0_flash0: spi0_flash0@0 {
- compatible = "m25p80";
+ spi0_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
+ compatible = "sst,sst25wf080", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
- spi0_flash0@0 {
- label = "spi0_flash0";
+ partition@0 {
+ label = "data";
reg = <0x0 0x100000>;
};
};
@@ -197,15 +195,15 @@
&spi1 {
status = "okay";
num-cs = <1>;
- spi1_flash0: spi1_flash0@0 {
- compatible = "mtd_dataflash";
+ spi1_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
+ compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <20000000>;
reg = <0>;
- spi1_flash0@0 {
- label = "spi1_flash0";
+ partition@0 {
+ label = "data";
reg = <0x0 0x84000>;
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644
index 0000000..d6a0103
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm017-dc3 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 { /* VSC8211 */
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+/* just eeprom here */
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+/* MT29F64G08AECDBJ4-6 */
+&nand0 {
+ status = "okay";
+ arasan,has-mdma;
+ num-cs = <2>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x0 0x1C00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand-misc";
+ reg = <0x0 0x3400000 0xFCC00000>;
+ };
+
+ partition@6 { /* for testing purpose */
+ label = "nand1-fsbl-uboot";
+ reg = <0x1 0x0 0x400000>;
+ };
+ partition@7 { /* for testing purpose */
+ label = "nand1-linux";
+ reg = <0x1 0x400000 0x1400000>;
+ };
+ partition@8 { /* for testing purpose */
+ label = "nand1-device-tree";
+ reg = <0x1 0x1800000 0x400000>;
+ };
+ partition@9 { /* for testing purpose */
+ label = "nand1-rootfs";
+ reg = <0x1 0x1C00000 0x1400000>;
+ };
+ partition@10 { /* for testing purpose */
+ label = "nand1-bitstream";
+ reg = <0x1 0x3000000 0x400000>;
+ };
+ partition@11 { /* for testing purpose */
+ label = "nand1-misc";
+ reg = <0x1 0x3400000 0xFCC00000>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&sdhci1 { /* emmc with some settings */
+ status = "okay";
+};
+
+/* main */
+&uart0 {
+ status = "okay";
+};
+
+/* DB9 */
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 648e3ba..fb49b4f 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -1,17 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
- * (C) Copyright 2015 - 2016, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm018-dc4";
@@ -52,7 +51,6 @@
status = "okay";
};
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index f3020a5..0632b18 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -1,18 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
@@ -38,7 +37,6 @@
};
};
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
@@ -84,18 +82,33 @@
status = "okay";
};
-/* FIXME: Add device */
&i2c0 {
status = "okay";
};
-/* FIXME: Add device */
&i2c1 {
status = "okay";
};
&sdhci0 {
status = "okay";
+ no-1-8-v;
+};
+
+&ttc0 {
+ status = "okay";
+};
+
+&ttc1 {
+ status = "okay";
+};
+
+&ttc2 {
+ status = "okay";
+};
+
+&ttc3 {
+ status = "okay";
};
&uart0 {
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
new file mode 100644
index 0000000..9114f98
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU100 revC
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Nathalie Chan King Choy
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU100 RevC";
+ compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
+
+ aliases {
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &dcc;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw4 {
+ label = "sw4";
+ gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
+ <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
+ <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
+ <&xilinx_ams 9>, <&xilinx_ams 10>,
+ <&xilinx_ams 11>, <&xilinx_ams 12>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds2 {
+ label = "ds2";
+ gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds3 {
+ label = "ds3";
+ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx"; /* WLAN tx */
+ default-state = "off";
+ };
+
+ ds4 {
+ label = "ds4";
+ gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0rx"; /* WLAN rx */
+ default-state = "off";
+ };
+
+ ds5 {
+ label = "ds5";
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ };
+
+ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+ label = "vbus_det";
+ gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ ltc2954: ltc2954 { /* U7 */
+ compatible = "lltc,ltc2954", "lltc,ltc2952";
+ trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */
+ /* If there is HW watchdog on mezzanine this signal should be connected there */
+ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */
+ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */
+ };
+
+ wmmcsdio_fixed: fixedregulator-mmcsdio {
+ compatible = "regulator-fixed";
+ regulator-name = "wmmcsdio_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sdio_pwrseq: sdio_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
+ "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
+ "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
+ "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
+ "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
+ "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
+ "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
+ "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
+ "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
+ "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
+ "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
+ "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ i2c-mux@75 { /* u11 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2csw_0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ label = "LS-I2C0";
+ };
+ i2csw_1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ label = "LS-I2C1";
+ };
+ i2csw_2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ label = "HS-I2C2";
+ };
+ i2csw_3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ label = "HS-I2C3";
+ };
+ i2csw_4: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pmic: pmic@5e { /* Custom TI PMIC u33 */
+ compatible = "ti,tps65086";
+ reg = <0x5e>;
+ interrupt-parent = <&gpio>;
+ interrupts = <77 GPIO_ACTIVE_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+ i2csw_5: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* PS_PMBUS */
+ ina226@40 { /* u35 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ /* MIO31 is alert which should be routed to PMUFW */
+ };
+ };
+ i2csw_6: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /*
+ * Not Connected
+ */
+ };
+ i2csw_7: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /*
+ * usb5744 (DNP) - U5
+ * 100kHz - this is default freq for us
+ */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+ broken-cd; /* CD has to be enabled by default */
+ disable-wp;
+ xlnx,mio_bank = <0>;
+};
+
+&sdhci1 {
+ status = "okay";
+ bus-width = <0x4>;
+ xlnx,mio_bank = <0>;
+ non-removable;
+ disable-wp;
+ cap-power-off-card;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vqmmc-supply = <&wmmcsdio_fixed>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wifi@2 {
+ compatible = "ti,wl1831";
+ reg = <2>;
+ interrupt-parent = <&gpio>;
+ interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
+ };
+};
+
+&serdes {
+ status = "okay";
+};
+
+&spi0 { /* Low Speed connector */
+ status = "okay";
+ label = "LS-SPI0";
+};
+
+&spi1 { /* High Speed connector */
+ status = "okay";
+ label = "HS-SPI1";
+};
+
+&uart0 {
+ status = "okay";
+ bluetooth {
+ compatible = "ti,wl1831-st";
+ enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ };
+
+};
+
+&uart1 {
+ status = "okay";
+
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;
+ maximum-speed = "super-speed";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+ phy-names = "usb3-phy";
+ phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;
+ maximum-speed = "super-speed";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
index 323a674..6647e97 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.0
*
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include "zynqmp-zcu102-revB.dts"
@@ -15,23 +14,23 @@
compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
-&eeprom {
+&eeprom {
#address-cells = <1>;
#size-cells = <1>;
- board_sn: board_sn@0 {
+ board_sn: board-sn@0 {
reg = <0x0 0x14>;
};
- eth_mac: eth_mac@20 {
+ eth_mac: eth-mac@20 {
reg = <0x20 0x6>;
};
- board_name: board_name@d0 {
+ board_name: board-name@d0 {
reg = <0xd0 0x6>;
};
- board_revision: board_revision@e0 {
+ board_revision: board-revision@e0 {
reg = <0xe0 0x3>;
};
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 64a883b..b7c638b 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -1,19 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -52,7 +51,7 @@
sw19 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
- linux,code = <108>; /* down */
+ linux,code = <KEY_DOWN>;
gpio-key,wakeup;
autorepeat;
};
@@ -70,15 +69,12 @@
&can1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
status = "okay";
};
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
@@ -115,8 +111,6 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gem3_default>;
phy0: phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
@@ -127,8 +121,6 @@
&gpio {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -138,19 +130,8 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c0_default>;
- pinctrl-1 = <&pinctrl_i2c0_gpio>;
- scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
- /*
- * Enable all GTs to out from U-Boot
- * i2c mw 20 6 0 - setup IO to output
- * i2c mw 20 2 ef - setup output values on pins 0-7
- * i2c mw 20 3 ff - setup output values on pins 10-17
- */
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
@@ -194,7 +175,7 @@
};
};
- tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
+ tca6416_u61: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
@@ -220,12 +201,12 @@
*/
};
- i2cswitch@75 { /* u60 */
+ i2c-mux@75 { /* u60 */
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
- i2c@0 { /* i2c mw 75 0 1 */
+ i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -281,7 +262,7 @@
shunt-resistor = <5000>;
};
};
- i2c@1 { /* i2c mw 75 0 1 */
+ i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
@@ -327,97 +308,85 @@
shunt-resistor = <5000>;
};
};
- i2c@2 { /* i2c mw 75 0 1 */
+ i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* MAXIM_PMBUS - 00 */
max15301@a { /* u46 */
- compatible = "max15301";
+ compatible = "maxim,max15301";
reg = <0xa>;
};
max15303@b { /* u4 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0xb>;
};
max15303@10 { /* u13 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x10>;
};
max15301@13 { /* u47 */
- compatible = "max15301";
+ compatible = "maxim,max15301";
reg = <0x13>;
};
max15303@14 { /* u7 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x14>;
};
max15303@15 { /* u6 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x15>;
};
max15303@16 { /* u10 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x16>;
};
max15303@17 { /* u9 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x17>;
};
max15301@18 { /* u63 */
- compatible = "max15301";
+ compatible = "maxim,max15301";
reg = <0x18>;
};
max15303@1a { /* u49 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x1a>;
};
max15303@1d { /* u18 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x1d>;
};
max15303@20 { /* u8 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
status = "disabled"; /* unreachable */
reg = <0x20>;
};
-/* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
-drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
-*/
- max20751@72 { /* u95 FIXME - not detected */
- compatible = "max20751";
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
reg = <0x72>;
};
- max20751@73 { /* u96 FIXME - not detected */
- compatible = "max20751";
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
reg = <0x73>;
};
};
/* Bus 3 is not connected */
};
-
- /* FIXME PMOD - j160 */
- /* FIXME MSP430F - u41 - not detected */
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1_default>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
- /* FIXME PL i2c via PCA9306 - u45 */
- /* FIXME MSP430 - u41 - not detected */
- i2cswitch@74 { /* u34 */
+ /* PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
- i2c@0 { /* i2c mw 74 0 1 */
+ i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -430,25 +399,25 @@
* 768B - 1024B address 0x57
*/
eeprom: eeprom@54 { /* u23 */
- compatible = "at,24c08";
+ compatible = "atmel,24c08";
reg = <0x54>;
};
};
- i2c@1 { /* i2c mw 74 0 2 */
+ i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
- si5341: clock-generator1@36 { /* SI5341 - u69 */
- compatible = "si5341";
+ si5341: clock-generator@36 { /* SI5341 - u69 */
+ compatible = "silabs,si5341";
reg = <0x36>;
};
};
- i2c@2 { /* i2c mw 74 0 4 */
+ i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- si570_1: clock-generator2@5d { /* USER SI570 - u42 */
+ si570_1: clock-generator@5d { /* USER SI570 - u42 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
@@ -457,11 +426,11 @@
clock-frequency = <300000000>;
};
};
- i2c@3 { /* i2c mw 74 0 8 */
+ i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
- si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
@@ -470,11 +439,11 @@
clock-frequency = <148500000>;
};
};
- i2c@4 { /* i2c mw 74 0 10 */
+ i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- si5328: clock-generator4@69 {/* SI5328 - u20 */
+ si5328: clock-generator@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
/*
@@ -487,7 +456,7 @@
/* 5 - 7 unconnected */
};
- i2cswitch@75 {
+ i2c-mux@75 {
compatible = "nxp,pca9548"; /* u135 */
#address-cells = <1>;
#size-cells = <0>;
@@ -511,29 +480,24 @@
reg = <2>;
/* SYSMON */
};
- i2c@3 { /* i2c mw 75 0 8 */
+ i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
- dev@19 { /* u-boot detection */
- compatible = "xxx";
+ dev@19 {
reg = <0x19>;
};
- dev@30 { /* u-boot detection */
- compatible = "xxx";
+ dev@30 {
reg = <0x30>;
};
- dev@35 { /* u-boot detection */
- compatible = "xxx";
+ dev@35 {
reg = <0x35>;
};
- dev@36 { /* u-boot detection */
- compatible = "xxx";
+ dev@36 {
reg = <0x36>;
};
- dev@51 { /* u-boot detection - maybe SPD */
- compatible = "xxx";
+ dev@51 {
reg = <0x51>;
};
};
@@ -564,269 +528,6 @@
};
};
-&pinctrl0 {
- status = "okay";
- pinctrl_i2c0_default: i2c0-default {
- mux {
- groups = "i2c0_3_grp";
- function = "i2c0";
- };
-
- conf {
- groups = "i2c0_3_grp";
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
- };
-
- pinctrl_i2c0_gpio: i2c0-gpio {
- mux {
- groups = "gpio0_14_grp", "gpio0_15_grp";
- function = "gpio0";
- };
-
- conf {
- groups = "gpio0_14_grp", "gpio0_15_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
- };
-
- pinctrl_i2c1_default: i2c1-default {
- mux {
- groups = "i2c1_4_grp";
- function = "i2c1";
- };
-
- conf {
- groups = "i2c1_4_grp";
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
- };
-
- pinctrl_i2c1_gpio: i2c1-gpio {
- mux {
- groups = "gpio0_16_grp", "gpio0_17_grp";
- function = "gpio0";
- };
-
- conf {
- groups = "gpio0_16_grp", "gpio0_17_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
- };
-
- pinctrl_uart0_default: uart0-default {
- mux {
- groups = "uart0_4_grp";
- function = "uart0";
- };
-
- conf {
- groups = "uart0_4_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO18";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO19";
- bias-disable;
- };
- };
-
- pinctrl_uart1_default: uart1-default {
- mux {
- groups = "uart1_5_grp";
- function = "uart1";
- };
-
- conf {
- groups = "uart1_5_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO21";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO20";
- bias-disable;
- };
- };
-
- pinctrl_usb0_default: usb0-default {
- mux {
- groups = "usb0_0_grp";
- function = "usb0";
- };
-
- conf {
- groups = "usb0_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO52", "MIO53", "MIO55";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
- "MIO60", "MIO61", "MIO62", "MIO63";
- bias-disable;
- };
- };
-
- pinctrl_gem3_default: gem3-default {
- mux {
- function = "ethernet3";
- groups = "ethernet3_0_grp";
- };
-
- conf {
- groups = "ethernet3_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
- "MIO75";
- bias-high-impedance;
- low-power-disable;
- };
-
- conf-tx {
- pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
- "MIO69";
- bias-disable;
- low-power-enable;
- };
-
- mux-mdio {
- function = "mdio3";
- groups = "mdio3_0_grp";
- };
-
- conf-mdio {
- groups = "mdio3_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- bias-disable;
- };
- };
-
- pinctrl_can1_default: can1-default {
- mux {
- function = "can1";
- groups = "can1_6_grp";
- };
-
- conf {
- groups = "can1_6_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO25";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO24";
- bias-disable;
- };
- };
-
- pinctrl_sdhci1_default: sdhci1-default {
- mux {
- groups = "sdio1_0_grp";
- function = "sdio1";
- };
-
- conf {
- groups = "sdio1_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- bias-disable;
- };
-
- mux-cd {
- groups = "sdio1_0_cd_grp";
- function = "sdio1_cd";
- };
-
- conf-cd {
- groups = "sdio1_0_cd_grp";
- bias-high-impedance;
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- mux-wp {
- groups = "sdio1_0_wp_grp";
- function = "sdio1_wp";
- };
-
- conf-wp {
- groups = "sdio1_0_wp_grp";
- bias-high-impedance;
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
- };
-
- pinctrl_gpio_default: gpio-default {
- mux-sw {
- function = "gpio0";
- groups = "gpio0_22_grp", "gpio0_23_grp";
- };
-
- conf-sw {
- groups = "gpio0_22_grp", "gpio0_23_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- mux-msp {
- function = "gpio0";
- groups = "gpio0_13_grp", "gpio0_38_grp";
- };
-
- conf-msp {
- groups = "gpio0_13_grp", "gpio0_38_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- io-standard = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-pull-up {
- pins = "MIO22", "MIO23";
- bias-pull-up;
- };
-
- conf-pull-none {
- pins = "MIO13", "MIO38";
- bias-disable;
- };
- };
-};
-
&pcie {
status = "okay";
};
@@ -883,8 +584,6 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sdhci1_default>;
no-1-8-v; /* for 1.0 silicon */
xlnx,mio_bank = <1>;
};
@@ -895,21 +594,15 @@
&uart0 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index c771a94..af4d868 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include "zynqmp-zcu102-revA.dts"
@@ -27,14 +26,12 @@
/delete-node/ phy@21;
};
-/* Different qspi 512Mbit version */
-
/* Fix collision with u61 */
&i2c0 {
- i2cswitch@75 {
+ i2c-mux@75 {
i2c@2 {
max15303@1b { /* u8 */
- compatible = "max15303";
+ compatible = "maxim,max15303";
reg = <0x1b>;
};
/delete-node/ max15303@20;
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
new file mode 100644
index 0000000..a0e13d8
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU104 RevA";
+ compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
+ compatible = "idt,8t49n287";
+ reg = <0x6c>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x43>;
+ };
+ irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x4d>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ tca6416_u97: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - IRPS5401_ALERT_B
+ * 1 - HDMI_8T49N241_INT_ALM
+ * 2 - MAX6643_OT_B
+ * 3 - MAX6643_FANFAIL_B
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7 - FMC_LPC_PRSNT_M2C_B
+ * 4, 10 - 17 - not connected
+ */
+ };
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ /* 3, 6 not connected */
+ };
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80"; /* n25q512a 128MiB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ xlnx,mio_bank = <1>;
+ disable-wp;
+};
+
+&serdes {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+ maximum-speed = "super-speed";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
new file mode 100644
index 0000000..6e3cf5a
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU104 RevC";
+ compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - IRPS5401_ALERT_B
+ * 1 - HDMI_8T49N241_INT_ALM
+ * 2 - MAX6643_OT_B
+ * 3 - MAX6643_FANFAIL_B
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7 - FMC_LPC_PRSNT_M2C_B
+ * 4, 10 - 17 - not connected
+ */
+ };
+
+ /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
+ compatible = "idt,8t49n287";
+ reg = <0x6c>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x43>;
+ };
+ irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x4d>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ /* 3, 6 not connected */
+ };
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80"; /* n25q512a 128MiB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ xlnx,mio_bank = <1>;
+ disable-wp;
+};
+
+&serdes {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+ maximum-speed = "super-speed";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
new file mode 100644
index 0000000..bbcd260
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -0,0 +1,596 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU106 RevA";
+ compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - SFP_SI5328_INT_ALM
+ * 1 - HDMI_SI5328_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMC_HPC0_PRSNT_M2C_B
+ * 11 - FMC_HPC1_PRSNT_M2C_B
+ * 2-4, 7, 12-17 - not connected
+ */
+ };
+
+ tca6416_u61: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2c-mux@75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226@40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226@41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226@40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301@a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301@13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303@17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303@1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303@1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ max15303@1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator@36 { /* SI5341 - u69 */
+ compatible = "si5341";
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ compatible = "silabs,si5328";
+ reg = <0x69>;
+ };
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>; /* FAN controller */
+ temp@4c {/* lm96163 - u128 */
+ compatible = "national,lm96163";
+ reg = <0x4c>;
+ };
+ };
+ /* 6 - 7 unconnected */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ dev@19 { /* u-boot detection */
+ compatible = "xxx";
+ reg = <0x19>;
+ };
+ dev@30 { /* u-boot detection */
+ compatible = "xxx";
+ reg = <0x30>;
+ };
+ dev@35 { /* u-boot detection */
+ compatible = "xxx";
+ reg = <0x35>;
+ };
+ dev@36 { /* u-boot detection */
+ compatible = "xxx";
+ reg = <0x36>;
+ };
+ dev@51 { /* u-boot detection - maybe SPD */
+ compatible = "xxx";
+ reg = <0x51>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ flash@0 {
+ compatible = "m25p80"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ xlnx,mio_bank = <1>;
+};
+
+&serdes {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
new file mode 100644
index 0000000..4002d78
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU111
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU111 RevA";
+ compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u22: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - MAX6643_OT_B
+ * 1 - MAX6643_FANFAIL_B
+ * 2 - MIO26_PMU_INPUT_LS
+ * 4 - SFP_SI5382_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMCP_HSPC_PRSNT_M2C_B
+ * 11 - CLK_SPI_MUX_SEL0
+ * 12 - CLK_SPI_MUX_SEL1
+ * 16 - IRPS5401_ALERT_B
+ * 17 - INA226_PMBUS_ALERT
+ * 3, 7, 13-15 - not connected
+ */
+ };
+
+ i2c-mux@75 { /* u23 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ ina226@40 { /* u67 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u59 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u61 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u60 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u64 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u69 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ ina226@47 { /* u66 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@48 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ ina226@49 { /* u63 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u3 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u71 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4c { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4d { /* u73 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4e { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x43>;
+ };
+ irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x44>;
+ };
+ irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x45>;
+ };
+ /* u68 IR38064 +0 */
+ /* u70 IR38060 +1 */
+ /* u74 IR38060 +2 */
+ /* u75 IR38060 +6 */
+ /* J19 header too */
+
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ i2c-mux@74 { /* u26 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u88 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator@36 { /* SI5341 - u46 */
+ compatible = "si5341";
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator@69 { /* SI5328 - u48 */
+ compatible = "silabs,si5328";
+ reg = <0x69>;
+ };
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ sc18is603@2f { /* sc18is602 - u93 */
+ compatible = "nxp,sc18is603";
+ reg = <0x2f>;
+ /* 4 gpios for CS not handled by driver */
+ /*
+ * USB2ANY cable or
+ * LMK04208 - u90 or
+ * LMX2594 - u102 or
+ * LMX2594 - u103 or
+ * LMX2594 - u104
+ */
+ };
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* FMC connector */
+ };
+ /* 7 NC */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u27 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ dev@19 { /* u-boot detection FIXME */
+ compatible = "xxx";
+ reg = <0x19>;
+ };
+ dev@30 { /* u-boot detection */
+ compatible = "xxx";
+ reg = <0x30>;
+ };
+ dev@35 { /* u-boot detection */
+ compatible = "xxx";
+ reg = <0x35>;
+ };
+ dev@36 { /* u-boot detection */
+ compatible = "xxx";
+ reg = <0x36>;
+ };
+ dev@51 { /* u-boot detection - maybe SPD */
+ compatible = "xxx";
+ reg = <0x51>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ flash@0 {
+ compatible = "m25p80"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ xlnx,mio_bank = <1>;
+};
+
+&serdes {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 5bdab61..80ac9a6 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP
*
@@ -5,7 +6,10 @@
*
* Michal Simek <michal.simek@xilinx.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
*/
/ {
@@ -98,155 +102,6 @@
u-boot,dm-pre-reloc;
};
- power-domains {
- compatible = "xlnx,zynqmp-genpd";
-
- pd_usb0: pd-usb0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x16>;
- };
-
- pd_usb1: pd-usb1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x17>;
- };
-
- pd_sata: pd-sata {
- #power-domain-cells = <0x0>;
- pd-id = <0x1c>;
- };
-
- pd_spi0: pd-spi0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x23>;
- };
-
- pd_spi1: pd-spi1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x24>;
- };
-
- pd_uart0: pd-uart0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x21>;
- };
-
- pd_uart1: pd-uart1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x22>;
- };
-
- pd_eth0: pd-eth0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x1d>;
- };
-
- pd_eth1: pd-eth1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x1e>;
- };
-
- pd_eth2: pd-eth2 {
- #power-domain-cells = <0x0>;
- pd-id = <0x1f>;
- };
-
- pd_eth3: pd-eth3 {
- #power-domain-cells = <0x0>;
- pd-id = <0x20>;
- };
-
- pd_i2c0: pd-i2c0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x25>;
- };
-
- pd_i2c1: pd-i2c1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x26>;
- };
-
- pd_dp: pd-dp {
- #power-domain-cells = <0x0>;
- pd-id = <0x29>;
- };
-
- pd_gdma: pd-gdma {
- #power-domain-cells = <0x0>;
- pd-id = <0x2a>;
- };
-
- pd_adma: pd-adma {
- #power-domain-cells = <0x0>;
- pd-id = <0x2b>;
- };
-
- pd_ttc0: pd-ttc0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x18>;
- };
-
- pd_ttc1: pd-ttc1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x19>;
- };
-
- pd_ttc2: pd-ttc2 {
- #power-domain-cells = <0x0>;
- pd-id = <0x1a>;
- };
-
- pd_ttc3: pd-ttc3 {
- #power-domain-cells = <0x0>;
- pd-id = <0x1b>;
- };
-
- pd_sd0: pd-sd0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x27>;
- };
-
- pd_sd1: pd-sd1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x28>;
- };
-
- pd_nand: pd-nand {
- #power-domain-cells = <0x0>;
- pd-id = <0x2c>;
- };
-
- pd_qspi: pd-qspi {
- #power-domain-cells = <0x0>;
- pd-id = <0x2d>;
- };
-
- pd_gpio: pd-gpio {
- #power-domain-cells = <0x0>;
- pd-id = <0x2e>;
- };
-
- pd_can0: pd-can0 {
- #power-domain-cells = <0x0>;
- pd-id = <0x2f>;
- };
-
- pd_can1: pd-can1 {
- #power-domain-cells = <0x0>;
- pd-id = <0x30>;
- };
-
- pd_pcie: pd-pcie {
- #power-domain-cells = <0x0>;
- pd-id = <0x3b>;
- };
-
- pd_gpu: pd-gpu {
- #power-domain-cells = <0x0>;
- pd-id = <0x3a 0x14 0x15>;
- };
- };
-
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
@@ -390,7 +245,6 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
- power-domains = <&pd_can0>;
};
can1: can@ff070000 {
@@ -402,7 +256,6 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
- power-domains = <&pd_can1>;
};
cci: cci@fd6e0000 {
@@ -435,7 +288,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14e8>;
- power-domains = <&pd_gdma>;
};
fpd_dma_chan2: dma@fd510000 {
@@ -448,7 +300,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14e9>;
- power-domains = <&pd_gdma>;
};
fpd_dma_chan3: dma@fd520000 {
@@ -461,7 +312,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ea>;
- power-domains = <&pd_gdma>;
};
fpd_dma_chan4: dma@fd530000 {
@@ -474,7 +324,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14eb>;
- power-domains = <&pd_gdma>;
};
fpd_dma_chan5: dma@fd540000 {
@@ -487,7 +336,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ec>;
- power-domains = <&pd_gdma>;
};
fpd_dma_chan6: dma@fd550000 {
@@ -500,7 +348,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ed>;
- power-domains = <&pd_gdma>;
};
fpd_dma_chan7: dma@fd560000 {
@@ -513,7 +360,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ee>;
- power-domains = <&pd_gdma>;
};
fpd_dma_chan8: dma@fd570000 {
@@ -526,7 +372,6 @@
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ef>;
- power-domains = <&pd_gdma>;
};
gpu: gpu@fd4b0000 {
@@ -537,7 +382,6 @@
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
clock-names = "gpu", "gpu_pp0", "gpu_pp1";
- power-domains = <&pd_gpu>;
};
/* LPDDMA default allows only secured access. inorder to enable
@@ -547,105 +391,97 @@
lpd_dma_chan1: dma@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffa80000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 77 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x868>;
- power-domains = <&pd_adma>;
};
lpd_dma_chan2: dma@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffa90000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 78 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x869>;
- power-domains = <&pd_adma>;
};
lpd_dma_chan3: dma@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffaa0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 79 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86a>;
- power-domains = <&pd_adma>;
};
lpd_dma_chan4: dma@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffab0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 80 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86b>;
- power-domains = <&pd_adma>;
};
lpd_dma_chan5: dma@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffac0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 81 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86c>;
- power-domains = <&pd_adma>;
};
lpd_dma_chan6: dma@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffad0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 82 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86d>;
- power-domains = <&pd_adma>;
};
lpd_dma_chan7: dma@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffae0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 83 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86e>;
- power-domains = <&pd_adma>;
};
lpd_dma_chan8: dma@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffaf0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 84 4>;
+ clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86f>;
- power-domains = <&pd_adma>;
};
mc: memory-controller@fd070000 {
@@ -666,7 +502,6 @@
#size-cells = <1>;
#stream-id-cells = <1>;
iommus = <&smmu 0x872>;
- power-domains = <&pd_nand>;
};
gem0: ethernet@ff0b0000 {
@@ -680,7 +515,6 @@
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x874>;
- power-domains = <&pd_eth0>;
};
gem1: ethernet@ff0c0000 {
@@ -694,7 +528,6 @@
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x875>;
- power-domains = <&pd_eth1>;
};
gem2: ethernet@ff0d0000 {
@@ -708,7 +541,6 @@
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x876>;
- power-domains = <&pd_eth2>;
};
gem3: ethernet@ff0e0000 {
@@ -722,7 +554,6 @@
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x877>;
- power-domains = <&pd_eth3>;
};
gpio: gpio@ff0a0000 {
@@ -735,7 +566,6 @@
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
gpio-controller;
- power-domains = <&pd_gpio>;
};
i2c0: i2c@ff020000 {
@@ -746,7 +576,6 @@
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- power-domains = <&pd_i2c0>;
};
i2c1: i2c@ff030000 {
@@ -757,7 +586,6 @@
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- power-domains = <&pd_i2c1>;
};
ocm: memory-controller@ff960000 {
@@ -781,7 +609,8 @@
<0 116 4>,
<0 115 4>, /* MSI_1 [63...32] */
<0 114 4>; /* MSI_0 [31...0] */
- interrupt-names = "misc","dummy","intx", "msi1", "msi0";
+ interrupt-names = "misc", "dummy", "intx",
+ "msi1", "msi0";
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
@@ -795,7 +624,6 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
- power-domains = <&pd_pcie>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
@@ -817,7 +645,6 @@
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x873>;
- power-domains = <&pd_qspi>;
};
rtc: rtc@ffa60000 {
@@ -867,7 +694,6 @@
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
- power-domains = <&pd_sata>;
#stream-id-cells = <4>;
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
<&smmu 0x4c2>, <&smmu 0x4c3>;
@@ -885,7 +711,6 @@
xlnx,device_id = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x870>;
- power-domains = <&pd_sd0>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
};
@@ -901,7 +726,6 @@
xlnx,device_id = <1>;
#stream-id-cells = <1>;
iommus = <&smmu 0x871>;
- power-domains = <&pd_sd1>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
};
@@ -935,7 +759,6 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
- power-domains = <&pd_spi0>;
};
spi1: spi@ff050000 {
@@ -947,7 +770,6 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
- power-domains = <&pd_spi1>;
};
ttc0: timer@ff110000 {
@@ -957,7 +779,6 @@
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
- power-domains = <&pd_ttc0>;
};
ttc1: timer@ff120000 {
@@ -967,7 +788,6 @@
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
- power-domains = <&pd_ttc1>;
};
ttc2: timer@ff130000 {
@@ -977,7 +797,6 @@
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
- power-domains = <&pd_ttc2>;
};
ttc3: timer@ff140000 {
@@ -987,7 +806,6 @@
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
- power-domains = <&pd_ttc3>;
};
uart0: serial@ff000000 {
@@ -998,7 +816,6 @@
interrupts = <0 21 4>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
- power-domains = <&pd_uart0>;
};
uart1: serial@ff010000 {
@@ -1009,7 +826,6 @@
interrupts = <0 22 4>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
- power-domains = <&pd_uart1>;
};
usb0: usb0@ff9d0000 {
@@ -1019,7 +835,6 @@
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
- power-domains = <&pd_usb0>;
ranges;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
@@ -1045,7 +860,6 @@
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
- power-domains = <&pd_usb1>;
ranges;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
@@ -1106,7 +920,6 @@
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "aclk", "aud_clk";
- power-domains = <&pd_dp>;
xlnx,dp-version = "v1.2";
xlnx,max-lanes = <2>;
xlnx,max-link-rate = <540000>;
@@ -1129,7 +942,6 @@
xlnx,output-fmt = "rgb";
xlnx,vid-fmt = "yuyv";
xlnx,gfx-fmt = "rgb565";
- power-domains = <&pd_dp>;
};
xlnx_dpdma: dma@fd4c0000 {
@@ -1139,7 +951,6 @@
interrupts = <0 122 4>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
- power-domains = <&pd_dp>;
dma-channels = <6>;
#dma-cells = <1>;
dma-video0channel {
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 9dbcd3a..eeebf16 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -122,6 +122,12 @@
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
void prcm_init(void);
void enable_basic_clocks(void);
+
+void rtc_only_update_board_type(u32 btype);
+u32 rtc_only_get_board_type(void);
+void rtc_only_prcm_init(void);
+void rtc_only_enable_basic_clocks(void);
+
void do_enable_clocks(u32 *const *, u32 *const *, u8);
void do_disable_clocks(u32 *const *, u32 *const *, u8);
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index e8d7d54..b8b2db6 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -68,6 +68,9 @@
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
+/* EMIF Control register bits */
+#define EMIF_CTRL_DEVOFF BIT(0)
+
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
#include <asm/ti-common/omap_wdt.h>
@@ -386,8 +389,19 @@
};
struct prm_device_inst {
- unsigned int prm_rstctrl;
- unsigned int prm_rstst;
+ unsigned int rstctrl;
+ unsigned int rstst;
+ unsigned int rsttime;
+ unsigned int sram_count;
+ unsigned int ldo_sram_core_set; /* offset 0x10 */
+ unsigned int ldo_sram_core_ctr;
+ unsigned int ldo_sram_mpu_setu;
+ unsigned int ldo_sram_mpu_ctrl;
+ unsigned int io_count; /* offset 0x20 */
+ unsigned int io_pmctrl;
+ unsigned int vc_val_bypass;
+ unsigned int resv1;
+ unsigned int emif_ctrl; /* offset 0x30 */
};
struct cm_dpll {
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
index 92b1c5e..5f0164c 100644
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
@@ -19,7 +19,6 @@
#define CONFIG_SYS_NS16550_CLK 100000000
#define CONFIG_SYS_NS16550_CLK_DIV 54
#define CONFIG_SERIAL_MULTI
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 0x18023000
/* Ethernet */
diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h
index 786deae..d3f3be3 100644
--- a/arch/arm/include/asm/arch-bcmnsp/configs.h
+++ b/arch/arm/include/asm/arch-bcmnsp/configs.h
@@ -16,7 +16,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 0x03b9aca0
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 0x18000300
#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac..af68af4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
+#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
+
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
@@ -200,6 +205,8 @@
/* Device Configuration and Pin Control */
#define DCFG_DCSR_PORCR1 0x0
+#define DCFG_DCSR_ECCCR2 0x524
+#define DISABLE_PFE_ECC BIT(13)
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
@@ -390,6 +397,29 @@
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO BIT(3)
+#define SCFG_RGMIIPCR_SETSP_1000M BIT(2)
+#define SCFG_RGMIIPCR_SETSP_100M 0
+#define SCFG_RGMIIPCR_SETSP_10M BIT(1)
+#define SCFG_RGMIIPCR_SETFD BIT(0)
+
+/* PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0 BIT(31)
+#define SCFG_PFEASBCR_AWCACHE0 BIT(30)
+#define SCFG_PFEASBCR_ARCACHE1 BIT(29)
+#define SCFG_PFEASBCR_AWCACHE1 BIT(28)
+#define SCFG_PFEASBCR_ARSNP BIT(27)
+#define SCFG_PFEASBCR_AWSNP BIT(26)
+
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20)
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u8 res_000[0x100-0x000];
@@ -407,7 +437,12 @@
u8 res_140[0x158-0x140];
u32 altcbar;
u32 qspi_cfg;
- u8 res_160[0x180-0x160];
+ u8 res_160[0x164 - 0x160];
+ u32 wr_qos1;
+ u32 wr_qos2;
+ u32 rd_qos1;
+ u32 rd_qos2;
+ u8 res_174[0x180 - 0x174];
u32 dmamcr;
u8 res_184[0x188-0x184];
u32 gic_align;
@@ -438,7 +473,21 @@
u32 usb_refclk_selcr1;
u32 usb_refclk_selcr2;
u32 usb_refclk_selcr3;
- u8 res_424[0x600-0x424];
+ u8 res_424[0x434 - 0x424];
+ u32 rgmiipcr;
+ u32 res_438;
+ u32 rgmiipsr;
+ u32 pfepfcssr1;
+ u32 pfeintencr1;
+ u32 pfepfcssr2;
+ u32 pfeintencr2;
+ u32 pfeerrcr;
+ u32 pfeeerrintencr;
+ u32 pfeasbcr;
+ u32 pfebsbcr;
+ u8 res_460[0x484 - 0x460];
+ u32 mdioselcr;
+ u8 res_468[0x600 - 0x488];
u32 scratchrw[4];
u8 res_610[0x680-0x610];
u32 corebcr;
@@ -591,6 +640,16 @@
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+ u32 gpibe;
+};
+
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
#define SMMU_SCR1 (SMMU_BASE + 0x4)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+ CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
{CSU_CSLX_USB3, CSU_ALL_RW},
{CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_PFE, CSU_ALL_RW},
{CSU_CSLX_SERDES, CSU_ALL_RW},
{CSU_CSLX_QDMA, CSU_ALL_RW},
{CSU_CSLX_LPUART2, CSU_ALL_RW},
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cb760b5..d9bfddb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -127,6 +127,9 @@
int setup_chip_volt(void);
/* Setup core vdd in unit mV */
int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
#endif
void cpu_name(char *name);
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 3b7f6bd..988a851 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -27,12 +27,6 @@
#define CONFIG_SYS_NS16550_CLK 13000000
#endif
-#if !defined(CONFIG_LPC32XX_HSUART)
-#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
-#else
-#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART
-#endif
-
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
index d995b7d..eaae10b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
@@ -80,413 +80,4 @@
};
check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK = 1 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO = 0,
- GPIO0A3_I2C1_SDA,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO = 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO = 0,
- GPIO0A1_I2C0_SDA,
- GPIO0A1_PWM2,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO = 0,
- GPIO0A0_I2C0_SCL,
- GPIO0A0_PWM1,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO = 0,
- GPIO0B6_MMC1_D3,
- GPIO0B6_I2S1_SCLK,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO = 0,
- GPIO0B5_MMC1_D2,
- GPIO0B5_I2S1_SDI,
-
- GPIO0B4_SHIFT = 8,
- GPIO0B4_MASK = 3 << GPIO0B4_SHIFT,
- GPIO0B4_GPIO = 0,
- GPIO0B4_MMC1_D1,
- GPIO0B4_I2S1_LRCKTX,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO = 0,
- GPIO0B3_MMC1_D0,
- GPIO0B3_I2S1_LRCKRX,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO = 0,
- GPIO0B1_MMC1_CLKOUT,
- GPIO0B1_I2S1_MCLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK = 3,
- GPIO0B0_GPIO = 0,
- GPIO0B0_MMC1_CMD,
- GPIO0B0_I2S1_SDO,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = 1 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO = 0,
- GPIO0C4_DRIVE_VBUS,
-
- GPIO0C3_SHIFT = 6,
- GPIO0C3_MASK = 1 << GPIO0C3_SHIFT,
- GPIO0C3_GPIO = 0,
- GPIO0C3_UART0_CTSN,
-
- GPIO0C2_SHIFT = 4,
- GPIO0C2_MASK = 1 << GPIO0C2_SHIFT,
- GPIO0C2_GPIO = 0,
- GPIO0C2_UART0_RTSN,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = 1 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO = 0,
- GPIO0C1_UART0_SIN,
-
-
- GPIO0C0_SHIFT = 0,
- GPIO0C0_MASK = 1 << GPIO0C0_SHIFT,
- GPIO0C0_GPIO = 0,
- GPIO0C0_UART0_SOUT,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
- GPIO0D4_GPIO = 0,
- GPIO0D4_SPDIF,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
- GPIO0D3_GPIO = 0,
- GPIO0D3_PWM3,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
- GPIO0D2_GPIO = 0,
- GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A5_SHIFT = 10,
- GPIO1A5_MASK = 1 << GPIO1A5_SHIFT,
- GPIO1A5_GPIO = 0,
- GPIO1A5_I2S_SDI,
-
- GPIO1A4_SHIFT = 8,
- GPIO1A4_MASK = 1 << GPIO1A4_SHIFT,
- GPIO1A4_GPIO = 0,
- GPIO1A4_I2S_SD0,
-
- GPIO1A3_SHIFT = 6,
- GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
- GPIO1A3_GPIO = 0,
- GPIO1A3_I2S_LRCKTX,
-
- GPIO1A2_SHIFT = 4,
- GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
- GPIO1A2_GPIO = 0,
- GPIO1A2_I2S_LRCKRX,
- GPIO1A2_PWM1_0,
-
- GPIO1A1_SHIFT = 2,
- GPIO1A1_MASK = 1 << GPIO1A1_SHIFT,
- GPIO1A1_GPIO = 0,
- GPIO1A1_I2S_SCLK,
-
- GPIO1A0_SHIFT = 0,
- GPIO1A0_MASK = 1 << GPIO1A0_SHIFT,
- GPIO1A0_GPIO = 0,
- GPIO1A0_I2S_MCLK,
-
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_MMC0_CMD,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 1 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_HDMI_HPD,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 1 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_HDMI_SCL,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 1 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_HDMI_SDA,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 1 << GPIO1B0_SHIFT,
- GPIO1B0_GPIO = 0,
- GPIO1B0_HDMI_CEC,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_MMC0_D3,
- GPIO1C5_JTAG_TMS,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_MMC0_D2,
- GPIO1C4_JTAG_TCK,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_MMC0_D1,
- GPIO1C3_UART2_SOUT,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
- GPIO1C2_GPIO = 0,
- GPIO1C2_MMC0_D0,
- GPIO1C2_UART2_SIN,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_MMC0_DETN,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
- GPIO1C0_GPIO = 0,
- GPIO1C0_MMC0_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_NAND_D7,
- GPIO1D7_EMMC_D7,
- GPIO1D7_SPI_CSN1,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_NAND_D6,
- GPIO1D6_EMMC_D6,
- GPIO1D6_SPI_CSN0,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_NAND_D5,
- GPIO1D5_EMMC_D5,
- GPIO1D5_SPI_TXD,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_NAND_D4,
- GPIO1D4_EMMC_D4,
- GPIO1D4_SPI_RXD,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_NAND_D3,
- GPIO1D3_EMMC_D3,
- GPIO1D3_SFC_SIO3,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_NAND_D2,
- GPIO1D2_EMMC_D2,
- GPIO1D2_SFC_SIO2,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_NAND_D1,
- GPIO1D1_EMMC_D1,
- GPIO1D1_SFC_SIO1,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
- GPIO1D0_GPIO = 0,
- GPIO1D0_NAND_D0,
- GPIO1D0_EMMC_D0,
- GPIO1D0_SFC_SIO0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 1 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_TESTCLK_OUT,
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
- GPIO2A6_GPIO = 0,
- GPIO2A6_NAND_CS0,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_NAND_RDY,
- GPIO2A4_EMMC_CMD,
- GPIO2A3_SFC_CLK,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_NAND_RDN,
- GPIO2A4_SFC_CSN1,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_NAND_WRN,
- GPIO2A4_SFC_CSN0,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_NAND_CLE,
- GPIO2A1_EMMC_CLKOUT,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_NAND_ALE,
- GPIO2A0_SPI_CLK,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 1 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_MAC_RXER,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_MAC_CLKOUT,
- GPIO2B6_MAC_CLKIN,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_MAC_TXEN,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 1 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_MAC_MDIO,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_MAC_CRS,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
- GPIO2C7_SHIFT = 14,
- GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
- GPIO2C7_GPIO = 0,
- GPIO2C7_UART1_SOUT,
- GPIO2C7_TESTCLK_OUT1,
-
- GPIO2C6_SHIFT = 12,
- GPIO2C6_MASK = 1 << GPIO2C6_SHIFT,
- GPIO2C6_GPIO = 0,
- GPIO2C6_UART1_SIN,
-
- GPIO2C5_SHIFT = 10,
- GPIO2C5_MASK = 1 << GPIO2C5_SHIFT,
- GPIO2C5_GPIO = 0,
- GPIO2C5_I2C2_SCL,
-
- GPIO2C4_SHIFT = 8,
- GPIO2C4_MASK = 1 << GPIO2C4_SHIFT,
- GPIO2C4_GPIO = 0,
- GPIO2C4_I2C2_SDA,
-
- GPIO2C3_SHIFT = 6,
- GPIO2C3_MASK = 1 << GPIO2C3_SHIFT,
- GPIO2C3_GPIO = 0,
- GPIO2C3_MAC_TXD0,
-
- GPIO2C2_SHIFT = 4,
- GPIO2C2_MASK = 1 << GPIO2C2_SHIFT,
- GPIO2C2_GPIO = 0,
- GPIO2C2_MAC_TXD1,
-
- GPIO2C1_SHIFT = 2,
- GPIO2C1_MASK = 1 << GPIO2C1_SHIFT,
- GPIO2C1_GPIO = 0,
- GPIO2C1_MAC_RXD0,
-
- GPIO2C0_SHIFT = 0,
- GPIO2C0_MASK = 1 << GPIO2C0_SHIFT,
- GPIO2C0_GPIO = 0,
- GPIO2C0_MAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
- GPIO2D6_GPIO = 0,
- GPIO2D6_I2S_SDO1,
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
- GPIO2D5_GPIO = 0,
- GPIO2D5_I2S_SDO2,
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
- GPIO2D4_GPIO = 0,
- GPIO2D4_I2S_SDO3,
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 1 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_MAC_MDC,
-};
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
index ce7bac5..905288e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
@@ -69,386 +69,6 @@
};
check_member(rk3188_grf, flash_cmd_p, 0x01a4);
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D7_SHIFT = 14,
- GPIO0D7_MASK = 1,
- GPIO0D7_GPIO = 0,
- GPIO0D7_SPI1_CSN0,
-
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = 1,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SPI1_CLK,
-
- GPIO0D5_SHIFT = 10,
- GPIO0D5_MASK = 1,
- GPIO0D5_GPIO = 0,
- GPIO0D5_SPI1_TXD,
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 1,
- GPIO0D4_GPIO = 0,
- GPIO0D4_SPI0_RXD,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 3,
- GPIO0D3_GPIO = 0,
- GPIO0D3_FLASH_CSN3,
- GPIO0D3_EMMC_RSTN_OUT,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 3,
- GPIO0D2_GPIO = 0,
- GPIO0D2_FLASH_CSN2,
- GPIO0D2_EMMC_CMD,
-
- GPIO0D1_SHIFT = 2,
- GPIO0D1_MASK = 1,
- GPIO0D1_GPIO = 0,
- GPIO0D1_FLASH_CSN1,
-
- GPIO0D0_SHIFT = 0,
- GPIO0D0_MASK = 3,
- GPIO0D0_GPIO = 0,
- GPIO0D0_FLASH_DQS,
- GPIO0D0_EMMC_CLKOUT
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A7_SHIFT = 14,
- GPIO1A7_MASK = 3,
- GPIO1A7_GPIO = 0,
- GPIO1A7_UART1_RTS_N,
- GPIO1A7_SPI0_CSN0,
-
- GPIO1A6_SHIFT = 12,
- GPIO1A6_MASK = 3,
- GPIO1A6_GPIO = 0,
- GPIO1A6_UART1_CTS_N,
- GPIO1A6_SPI0_CLK,
-
- GPIO1A5_SHIFT = 10,
- GPIO1A5_MASK = 3,
- GPIO1A5_GPIO = 0,
- GPIO1A5_UART1_SOUT,
- GPIO1A5_SPI0_TXD,
-
- GPIO1A4_SHIFT = 8,
- GPIO1A4_MASK = 3,
- GPIO1A4_GPIO = 0,
- GPIO1A4_UART1_SIN,
- GPIO1A4_SPI0_RXD,
-
- GPIO1A3_SHIFT = 6,
- GPIO1A3_MASK = 1,
- GPIO1A3_GPIO = 0,
- GPIO1A3_UART0_RTS_N,
-
- GPIO1A2_SHIFT = 4,
- GPIO1A2_MASK = 1,
- GPIO1A2_GPIO = 0,
- GPIO1A2_UART0_CTS_N,
-
- GPIO1A1_SHIFT = 2,
- GPIO1A1_MASK = 1,
- GPIO1A1_GPIO = 0,
- GPIO1A1_UART0_SOUT,
-
- GPIO1A0_SHIFT = 0,
- GPIO1A0_MASK = 1,
- GPIO1A0_GPIO = 0,
- GPIO1A0_UART0_SIN,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 1,
- GPIO1B7_GPIO = 0,
- GPIO1B7_SPI0_CSN1,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3,
- GPIO1B6_GPIO = 0,
- GPIO1B6_SPDIF_TX,
- GPIO1B6_SPI1_CSN1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK = 3,
- GPIO1B5_GPIO = 0,
- GPIO1B5_UART3_RTS_N,
- GPIO1B5_RESERVED,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3,
- GPIO1B4_GPIO = 0,
- GPIO1B4_UART3_CTS_N,
- GPIO1B4_GPS_RFCLK,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3,
- GPIO1B3_GPIO = 0,
- GPIO1B3_UART3_SOUT,
- GPIO1B3_GPS_SIG,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART3_SIN,
- GPIO1B2_GPS_MAG,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART2_SOUT,
- GPIO1B1_JTAG_TDO,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 3,
- GPIO1B0_GPIO = 0,
- GPIO1B0_UART2_SIN,
- GPIO1B0_JTAG_TDI,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 1,
- GPIO1D7_GPIO = 0,
- GPIO1D7_I2C4_SCL,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 1,
- GPIO1D6_GPIO = 0,
- GPIO1D6_I2C4_SDA,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 1,
- GPIO1D5_GPIO = 0,
- GPIO1D5_I2C2_SCL,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 1,
- GPIO1D4_GPIO = 0,
- GPIO1D4_I2C2_SDA,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 1,
- GPIO1D3_GPIO = 0,
- GPIO1D3_I2C1_SCL,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 1,
- GPIO1D2_GPIO = 0,
- GPIO1D2_I2C1_SDA,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 1,
- GPIO1D1_GPIO = 0,
- GPIO1D1_I2C0_SCL,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 1,
- GPIO1D0_GPIO = 0,
- GPIO1D0_I2C0_SDA,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
- GPIO3A7_SHIFT = 14,
- GPIO3A7_MASK = 1,
- GPIO3A7_GPIO = 0,
- GPIO3A7_SDMMC0_DATA3,
-
- GPIO3A6_SHIFT = 12,
- GPIO3A6_MASK = 1,
- GPIO3A6_GPIO = 0,
- GPIO3A6_SDMMC0_DATA2,
-
- GPIO3A5_SHIFT = 10,
- GPIO3A5_MASK = 1,
- GPIO3A5_GPIO = 0,
- GPIO3A5_SDMMC0_DATA1,
-
- GPIO3A4_SHIFT = 8,
- GPIO3A4_MASK = 1,
- GPIO3A4_GPIO = 0,
- GPIO3A4_SDMMC0_DATA0,
-
- GPIO3A3_SHIFT = 6,
- GPIO3A3_MASK = 1,
- GPIO3A3_GPIO = 0,
- GPIO3A3_SDMMC0_CMD,
-
- GPIO3A2_SHIFT = 4,
- GPIO3A2_MASK = 1,
- GPIO3A2_GPIO = 0,
- GPIO3A2_SDMMC0_CLKOUT,
-
- GPIO3A1_SHIFT = 2,
- GPIO3A1_MASK = 1,
- GPIO3A1_GPIO = 0,
- GPIO3A1_SDMMC0_PWREN,
-
- GPIO3A0_SHIFT = 0,
- GPIO3A0_MASK = 1,
- GPIO3A0_GPIO = 0,
- GPIO3A0_SDMMC0_RSTN,
-};
-
-/* GRF_GPIO3B_IOMUX */
-enum {
- GPIO3B7_SHIFT = 14,
- GPIO3B7_MASK = 3,
- GPIO3B7_GPIO = 0,
- GPIO3B7_CIF_DATA11,
- GPIO3B7_I2C3_SCL,
-
- GPIO3B6_SHIFT = 12,
- GPIO3B6_MASK = 3,
- GPIO3B6_GPIO = 0,
- GPIO3B6_CIF_DATA10,
- GPIO3B6_I2C3_SDA,
-
- GPIO3B5_SHIFT = 10,
- GPIO3B5_MASK = 3,
- GPIO3B5_GPIO = 0,
- GPIO3B5_CIF_DATA1,
- GPIO3B5_HSADC_DATA9,
-
- GPIO3B4_SHIFT = 8,
- GPIO3B4_MASK = 3,
- GPIO3B4_GPIO = 0,
- GPIO3B4_CIF_DATA0,
- GPIO3B4_HSADC_DATA8,
-
- GPIO3B3_SHIFT = 6,
- GPIO3B3_MASK = 1,
- GPIO3B3_GPIO = 0,
- GPIO3B3_CIF_CLKOUT,
-
- GPIO3B2_SHIFT = 4,
- GPIO3B2_MASK = 1,
- GPIO3B2_GPIO = 0,
- /* no muxes */
-
- GPIO3B1_SHIFT = 2,
- GPIO3B1_MASK = 1,
- GPIO3B1_GPIO = 0,
- GPIO3B1_SDMMC0_WRITE_PRT,
-
- GPIO3B0_SHIFT = 0,
- GPIO3B0_MASK = 1,
- GPIO3B0_GPIO = 0,
- GPIO3B0_SDMMC_DETECT_N,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C7_SHIFT = 14,
- GPIO3C7_MASK = 3,
- GPIO3C7_GPIO = 0,
- GPIO3C7_SDMMC1_WRITE_PRT,
- GPIO3C7_RMII_CRS_DVALID,
- GPIO3C7_RESERVED,
-
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 3,
- GPIO3C6_GPIO = 0,
- GPIO3C6_SDMMC1_DECTN,
- GPIO3C6_RMII_RX_ERR,
- GPIO3C6_RESERVED,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 3,
- GPIO3C5_GPIO = 0,
- GPIO3C5_SDMMC1_CLKOUT,
- GPIO3C5_RMII_CLKOUT,
- GPIO3C5_RMII_CLKIN,
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = 3,
- GPIO3C4_GPIO = 0,
- GPIO3C4_SDMMC1_DATA3,
- GPIO3C4_RMII_RXD1,
- GPIO3C4_RESERVED,
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = 3,
- GPIO3C3_GPIO = 0,
- GPIO3C3_SDMMC1_DATA2,
- GPIO3C3_RMII_RXD0,
- GPIO3C3_RESERVED,
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = 3,
- GPIO3C2_GPIO = 0,
- GPIO3C2_SDMMC1_DATA1,
- GPIO3C2_RMII_TXD0,
- GPIO3C2_RESERVED,
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = 3,
- GPIO3C1_GPIO = 0,
- GPIO3C1_SDMMC1_DATA0,
- GPIO3C1_RMII_TXD1,
- GPIO3C1_RESERVED,
-
- GPIO3C0_SHIFT = 0,
- GPIO3C0_MASK = 3,
- GPIO3C0_GPIO = 0,
- GPIO3C0_SDMMC1_CMD,
- GPIO3C0_RMII_TX_EN,
- GPIO3C0_RESERVED,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
- GPIO3D6_SHIFT = 12,
- GPIO3D6_MASK = 3,
- GPIO3D6_GPIO = 0,
- GPIO3D6_PWM_3,
- GPIO3D6_JTAG_TMS,
- GPIO3D6_HOST_DRV_VBUS,
-
- GPIO3D5_SHIFT = 10,
- GPIO3D5_MASK = 3,
- GPIO3D5_GPIO = 0,
- GPIO3D5_PWM_2,
- GPIO3D5_JTAG_TCK,
- GPIO3D5_OTG_DRV_VBUS,
-
- GPIO3D4_SHIFT = 8,
- GPIO3D4_MASK = 3,
- GPIO3D4_GPIO = 0,
- GPIO3D4_PWM_1,
- GPIO3D4_JTAG_TRSTN,
-
- GPIO3D3_SHIFT = 6,
- GPIO3D3_MASK = 3,
- GPIO3D3_GPIO = 0,
- GPIO3D3_PWM_0,
-
- GPIO3D2_SHIFT = 4,
- GPIO3D2_MASK = 3,
- GPIO3D2_GPIO = 0,
- GPIO3D2_SDMMC1_INT_N,
-
- GPIO3D1_SHIFT = 2,
- GPIO3D1_MASK = 3,
- GPIO3D1_GPIO = 0,
- GPIO3D1_SDMMC1_BACKEND_PWR,
- GPIO3D1_MII_MDCLK,
-
- GPIO3D0_SHIFT = 0,
- GPIO3D0_MASK = 3,
- GPIO3D0_GPIO = 0,
- GPIO3D0_SDMMC1_PWR_EN,
- GPIO3D0_MII_MD,
-};
-
/* GRF_SOC_CON0 */
enum {
HSADC_CLK_DIR_SHIFT = 15,
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index b541e2c..91e8d2d 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -324,13 +324,29 @@
check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
enum {
+ /* GRF_GPIO2A_IOMUX */
+ GRF_GPIO2A0_SEL_SHIFT = 0,
+ GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
+ GRF_I2C2_SDA = 2,
+ GRF_GPIO2A1_SEL_SHIFT = 2,
+ GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
+ GRF_I2C2_SCL = 2,
+ GRF_GPIO2A7_SEL_SHIFT = 14,
+ GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
+ GRF_I2C7_SDA = 2,
+
/* GRF_GPIO2B_IOMUX */
- GRF_GPIO2B1_SEL_SHIFT = 0,
+ GRF_GPIO2B0_SEL_SHIFT = 0,
+ GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT,
+ GRF_I2C7_SCL = 2,
+ GRF_GPIO2B1_SEL_SHIFT = 2,
GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
GRF_SPI2TPM_RXD = 1,
- GRF_GPIO2B2_SEL_SHIFT = 2,
+ GRF_I2C6_SDA = 2,
+ GRF_GPIO2B2_SEL_SHIFT = 4,
GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
GRF_SPI2TPM_TXD = 1,
+ GRF_I2C6_SCL = 2,
GRF_GPIO2B3_SEL_SHIFT = 6,
GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
GRF_SPI2TPM_CLK = 1,
@@ -414,6 +430,14 @@
GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
GRF_MAC_TXCLK = 1,
+ /* GRF_GPIO4A_IOMUX */
+ GRF_GPIO4A1_SEL_SHIFT = 2,
+ GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT,
+ GRF_I2C1_SDA = 1,
+ GRF_GPIO4A2_SEL_SHIFT = 4,
+ GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT,
+ GRF_I2C1_SCL = 1,
+
/* GRF_GPIO4B_IOMUX */
GRF_GPIO4B0_SEL_SHIFT = 0,
GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
@@ -575,6 +599,12 @@
PMUGRF_GPIO1B2_SEL_SHIFT = 4,
PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
PMUGRF_SPI1EC_CSN0 = 2,
+ PMUGRF_GPIO1B3_SEL_SHIFT = 6,
+ PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT,
+ PMUGRF_I2C4_SDA = 1,
+ PMUGRF_GPIO1B4_SEL_SHIFT = 8,
+ PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT,
+ PMUGRF_I2C4_SCL = 1,
PMUGRF_GPIO1B6_SEL_SHIFT = 12,
PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
PMUGRF_PWM_3B = 1,
diff --git a/arch/arm/include/asm/arch-stm32/gpio.h b/arch/arm/include/asm/arch-stm32/gpio.h
new file mode 100644
index 0000000..d24e809
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32/gpio.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+enum stm32_gpio_port {
+ STM32_GPIO_PORT_A = 0,
+ STM32_GPIO_PORT_B,
+ STM32_GPIO_PORT_C,
+ STM32_GPIO_PORT_D,
+ STM32_GPIO_PORT_E,
+ STM32_GPIO_PORT_F,
+ STM32_GPIO_PORT_G,
+ STM32_GPIO_PORT_H,
+ STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+ STM32_GPIO_PIN_0 = 0,
+ STM32_GPIO_PIN_1,
+ STM32_GPIO_PIN_2,
+ STM32_GPIO_PIN_3,
+ STM32_GPIO_PIN_4,
+ STM32_GPIO_PIN_5,
+ STM32_GPIO_PIN_6,
+ STM32_GPIO_PIN_7,
+ STM32_GPIO_PIN_8,
+ STM32_GPIO_PIN_9,
+ STM32_GPIO_PIN_10,
+ STM32_GPIO_PIN_11,
+ STM32_GPIO_PIN_12,
+ STM32_GPIO_PIN_13,
+ STM32_GPIO_PIN_14,
+ STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+ STM32_GPIO_MODE_IN = 0,
+ STM32_GPIO_MODE_OUT,
+ STM32_GPIO_MODE_AF,
+ STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+ STM32_GPIO_OTYPE_PP = 0,
+ STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+ STM32_GPIO_SPEED_2M = 0,
+ STM32_GPIO_SPEED_25M,
+ STM32_GPIO_SPEED_50M,
+ STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+ STM32_GPIO_PUPD_NO = 0,
+ STM32_GPIO_PUPD_UP,
+ STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+ STM32_GPIO_AF0 = 0,
+ STM32_GPIO_AF1,
+ STM32_GPIO_AF2,
+ STM32_GPIO_AF3,
+ STM32_GPIO_AF4,
+ STM32_GPIO_AF5,
+ STM32_GPIO_AF6,
+ STM32_GPIO_AF7,
+ STM32_GPIO_AF8,
+ STM32_GPIO_AF9,
+ STM32_GPIO_AF10,
+ STM32_GPIO_AF11,
+ STM32_GPIO_AF12,
+ STM32_GPIO_AF13,
+ STM32_GPIO_AF14,
+ STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+ enum stm32_gpio_port port;
+ enum stm32_gpio_pin pin;
+};
+
+struct stm32_gpio_ctl {
+ enum stm32_gpio_mode mode;
+ enum stm32_gpio_otype otype;
+ enum stm32_gpio_speed speed;
+ enum stm32_gpio_pupd pupd;
+ enum stm32_gpio_af af;
+};
+
+struct stm32_gpio_regs {
+ u32 moder; /* GPIO port mode */
+ u32 otyper; /* GPIO port output type */
+ u32 ospeedr; /* GPIO port output speed */
+ u32 pupdr; /* GPIO port pull-up/pull-down */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 lckr; /* GPIO port configuration lock */
+ u32 afr[2]; /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+ struct stm32_gpio_regs *regs;
+};
+
+#endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h
new file mode 100644
index 0000000..7bea20b
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32/stm32f.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_STM32F_H
+#define _ASM_ARCH_STM32F_H
+
+#define STM32_PERIPH_BASE 0x40000000UL
+
+#define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
+
+#define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800)
+#define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00)
+
+void stm32_flash_latency_cfg(int latency);
+
+#endif /* _ASM_ARCH_STM32F_H */
+
diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h
deleted file mode 100644
index 7dd5077..0000000
--- a/arch/arm/include/asm/arch-stm32f4/fmc.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2013
- * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _MACH_FMC_H_
-#define _MACH_FMC_H_
-
-struct stm32_fmc_regs {
- u32 sdcr1; /* Control register 1 */
- u32 sdcr2; /* Control register 2 */
- u32 sdtr1; /* Timing register 1 */
- u32 sdtr2; /* Timing register 2 */
- u32 sdcmr; /* Mode register */
- u32 sdrtr; /* Refresh timing register */
- u32 sdsr; /* Status register */
-};
-
-/*
- * FMC registers base
- */
-#define STM32_SDRAM_FMC_BASE 0xA0000140
-#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
-
-/* Control register SDCR */
-#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
-#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
-#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
-#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
-#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
-#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
-#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
-#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
-#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
-
-/* Timings register SDTR */
-#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
-#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
-#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
-#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
-#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
-#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
-#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
-
-
-#define FMC_SDCMR_NRFS_SHIFT 5
-
-#define FMC_SDCMR_MODE_NORMAL 0
-#define FMC_SDCMR_MODE_START_CLOCK 1
-#define FMC_SDCMR_MODE_PRECHARGE 2
-#define FMC_SDCMR_MODE_AUTOREFRESH 3
-#define FMC_SDCMR_MODE_WRITE_MODE 4
-#define FMC_SDCMR_MODE_SELFREFRESH 5
-#define FMC_SDCMR_MODE_POWERDOWN 6
-
-#define FMC_SDCMR_BANK_1 (1 << 4)
-#define FMC_SDCMR_BANK_2 (1 << 3)
-
-#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
-
-#define FMC_SDSR_BUSY (1 << 5)
-
-#define FMC_BUSY_WAIT() do { \
- __asm__ __volatile__ ("dsb" : : : "memory"); \
- while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
- ; \
- } while (0)
-
-
-#endif /* _MACH_FMC_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h
index 6173fa1..16cdf25 100644
--- a/arch/arm/include/asm/arch-stm32f4/gpio.h
+++ b/arch/arm/include/asm/arch-stm32f4/gpio.h
@@ -11,150 +11,6 @@
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
-#if (CONFIG_STM32_USART == 1)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#elif (CONFIG_STM32_USART == 2)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_D
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_5
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_6
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#elif (CONFIG_STM32_USART == 3)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_C
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_10
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_11
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#elif (CONFIG_STM32_USART == 6)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_G
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_14
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_9
-#define STM32_GPIO_USART STM32_GPIO_AF8
-
-#else
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#endif
-
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
-};
-
-static inline unsigned stm32_gpio_to_port(unsigned gpio)
-{
- return gpio / 16;
-}
-
-static inline unsigned stm32_gpio_to_pin(unsigned gpio)
-{
- return gpio % 16;
-}
+#include <asm/arch-stm32/gpio.h>
#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 0449fce..9039312 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -11,17 +11,12 @@
#ifndef _MACH_STM32_H_
#define _MACH_STM32_H_
+#include <asm/arch-stm32/stm32f.h>
+
/*
* Peripheral memory map
*/
#define STM32_SYSMEM_BASE 0x1FFF0000
-#define STM32_PERIPH_BASE 0x40000000
-#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
-#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
-#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
-#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000)
-
-#define STM32_BUS_MASK 0xFFFF0000
/*
* Register maps
@@ -37,18 +32,10 @@
*/
#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10)
#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE)
-
-#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
-#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
-
-#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
-
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 16 * 1024,
[4] = 64 * 1024,
[5 ... 11] = 128 * 1024
};
-void stm32_flash_latency_cfg(int latency);
-
#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h
deleted file mode 100644
index 9a967ac..0000000
--- a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __STM32_DEFS_H__
-#define __STM32_DEFS_H__
-#include <asm/arch/stm32_periph.h>
-
-int clock_setup(enum periph_clock);
-
-#endif
-
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h
deleted file mode 100644
index fa45a5c..0000000
--- a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PERIPH_H
-#define __ASM_ARM_ARCH_PERIPH_H
-
-/*
- * Peripherals required for pinmux configuration. List will
- * grow with support for more devices getting added.
- * Numbering based on interrupt table.
- *
- */
-enum periph_id {
- UART1_GPIOA_9_10 = 0,
- UART2_GPIOD_5_6,
-};
-
-enum periph_clock {
- USART1_CLOCK_CFG = 0,
- USART2_CLOCK_CFG,
- GPIO_A_CLOCK_CFG,
- GPIO_B_CLOCK_CFG,
- GPIO_C_CLOCK_CFG,
- GPIO_D_CLOCK_CFG,
- GPIO_E_CLOCK_CFG,
- GPIO_F_CLOCK_CFG,
- GPIO_G_CLOCK_CFG,
- GPIO_H_CLOCK_CFG,
- GPIO_I_CLOCK_CFG,
- GPIO_J_CLOCK_CFG,
- GPIO_K_CLOCK_CFG,
-};
-
-#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h
index 68ecdc8..5db10ed 100644
--- a/arch/arm/include/asm/arch-stm32f7/gpio.h
+++ b/arch/arm/include/asm/arch-stm32f7/gpio.h
@@ -7,120 +7,7 @@
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
-#include <asm/gpio.h>
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
-};
-
-static inline unsigned stm32_gpio_to_port(unsigned gpio)
-{
- return gpio / 16;
-}
-
-static inline unsigned stm32_gpio_to_pin(unsigned gpio)
-{
- return gpio % 16;
-}
+#include <asm/arch-stm32/gpio.h>
#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h
deleted file mode 100644
index b43dc61..0000000
--- a/arch/arm/include/asm/arch-stm32f7/gpt.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _STM32_GPT_H
-#define _STM32_GPT_H
-
-#include <asm/arch/stm32.h>
-
-struct gpt_regs {
- u32 cr1;
- u32 cr2;
- u32 smcr;
- u32 dier;
- u32 sr;
- u32 egr;
- u32 ccmr1;
- u32 ccmr2;
- u32 ccer;
- u32 cnt;
- u32 psc;
- u32 arr;
- u32 reserved;
- u32 ccr1;
- u32 ccr2;
- u32 ccr3;
- u32 ccr4;
- u32 reserved1;
- u32 dcr;
- u32 dmar;
- u32 tim2_5_or;
-};
-
-struct gpt_regs *const gpt1_regs_ptr =
- (struct gpt_regs *)TIM2_BASE;
-
-/* Timer control1 register */
-#define GPT_CR1_CEN BIT(0)
-#define GPT_MODE_AUTO_RELOAD BIT(7)
-
-/* Auto reload register for free running config */
-#define GPT_FREE_RUNNING 0xFFFFFFFF
-
-/* Timer, HZ specific defines */
-#define CONFIG_STM32_HZ 1000
-
-/* Timer Event Generation registers */
-#define TIM_EGR_UG BIT(0)
-
-#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index f54e6f1..c1f1ba2 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -8,48 +8,7 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-/* STM32F746 */
-#define ITCM_FLASH_BASE 0x00200000UL
-#define AXIM_FLASH_BASE 0x08000000UL
-
-#define ITCM_SRAM_BASE 0x00000000UL
-#define DTCM_SRAM_BASE 0x20000000UL
-#define SRAM1_BASE 0x20010000UL
-#define SRAM2_BASE 0x2004C000UL
-
-#define PERIPH_BASE 0x40000000UL
-
-#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
-#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000)
-
-#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
-#define USART2_BASE (APB1_PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1_PERIPH_BASE + 0x4800)
-#define PWR_BASE (APB1_PERIPH_BASE + 0x7000)
-
-#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
-#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800)
-
-#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000)
-#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400)
-#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800)
-#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800)
-#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
-
-
-#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140)
+#include <asm/arch-stm32/stm32f.h>
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
@@ -57,11 +16,4 @@
[5 ... 7] = 256 * 1024
};
-#define STM32_BUS_MASK GENMASK(31, 16)
-
-#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-
-
-void stm32_flash_latency_cfg(int latency);
-
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_defs.h b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h
deleted file mode 100644
index 9a967ac..0000000
--- a/arch/arm/include/asm/arch-stm32f7/stm32_defs.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __STM32_DEFS_H__
-#define __STM32_DEFS_H__
-#include <asm/arch/stm32_periph.h>
-
-int clock_setup(enum periph_clock);
-
-#endif
-
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
deleted file mode 100644
index 7b8f66a..0000000
--- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PERIPH_H
-#define __ASM_ARM_ARCH_PERIPH_H
-
-/*
- * Peripherals required for pinmux configuration. List will
- * grow with support for more devices getting added.
- * Numbering based on interrupt table.
- *
- */
-enum periph_id {
- PERIPH_ID_USART1 = 37,
-
- PERIPH_ID_QUADSPI = 92,
-};
-
-enum periph_clock {
- TIMER2_CLOCK_CFG,
-};
-
-#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/syscfg.h b/arch/arm/include/asm/arch-stm32f7/syscfg.h
index 49e78f2..310eec5 100644
--- a/arch/arm/include/asm/arch-stm32f7/syscfg.h
+++ b/arch/arm/include/asm/arch-stm32f7/syscfg.h
@@ -23,16 +23,7 @@
*/
#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
-/* SYSCFG memory remap register */
-#define SYSCFG_MEMRMP_MEM_BOOT BIT(0)
-#define SYSCFG_MEMRMP_SWP_FMC BIT(10)
-
/* SYSCFG peripheral mode configuration register */
-#define SYSCFG_PMC_ADCXDC2 BIT(16)
#define SYSCFG_PMC_MII_RMII_SEL BIT(23)
-/* Compensation cell control register */
-#define SYSCFG_CMPCR_CMP_PD BIT(0)
-#define SYSCFG_CMPCR_READY BIT(8)
-
#endif
diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h
index 092bf3a..2873c7b 100644
--- a/arch/arm/include/asm/arch-stm32h7/gpio.h
+++ b/arch/arm/include/asm/arch-stm32h7/gpio.h
@@ -7,120 +7,7 @@
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
-#include <asm/gpio.h>
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
-};
-
-static inline unsigned stm32_gpio_to_port(unsigned gpio)
-{
- return gpio / 16;
-}
-
-static inline unsigned stm32_gpio_to_pin(unsigned gpio)
-{
- return gpio % 16;
-}
+#include <asm/arch-stm32/gpio.h>
#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d328df9..d35aa47 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -192,6 +192,7 @@
#define ATB_DIV_1 0
#define ATB_DIV_2 1
#define ATB_DIV_4 2
+#define AHB_DIV_1 0
#define CPU_CLK_SRC_OSC24M 1
#define CPU_CLK_SRC_PLL1 2
@@ -317,6 +318,11 @@
#define AHB_GATE_OFFSET_LCD0 3
#endif
+#define CCM_NAND_CTRL_M(x) ((x) - 1)
+#define CCM_NAND_CTRL_N(x) ((x) << 16)
+#define CCM_NAND_CTRL_PLL6 (0x1 << 24)
+#define CCM_NAND_CTRL_ENABLE (0x1 << 31)
+
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
#define CCM_MMC_CTRL_N(x) ((x) << 16)
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 084d55a..3daf0e8 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -11,6 +11,10 @@
#define PAYLOAD_ARG_CNT 5
#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
+#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D
+#define KEY_PTR_LEN 32
+
+#define ZYNQMP_FPGA_BIT_NS 5
enum {
IDCODE,
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index b5ffffd..3d3085e 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -41,8 +41,8 @@
obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
endif
-obj-$(CONFIG_$(SPL_)USE_ARCH_MEMSET) += memset.o
-obj-$(CONFIG_$(SPL_)USE_ARCH_MEMCPY) += memcpy.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
obj-y += sections.o
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index cfc236f..91a64be 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -448,6 +448,11 @@
}
void boot_jump_vxworks(bootm_headers_t *images)
{
+#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI)
+ armv8_setup_psci();
+ smp_kick_all_cpus();
+#endif
+
/* ARM VxWorks requires device tree physical address to be passed */
((void (*)(void *))images->ep)(images->ft_addr);
}
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 80869ad..cda4d48 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -20,6 +20,7 @@
*/
#include <common.h>
+#include <efi_loader.h>
#include <asm/proc-armv/ptrace.h>
#include <asm/u-boot-arm.h>
#include <efi_loader.h>
@@ -51,6 +52,11 @@
reset_cpu (0);
}
+static void show_efi_loaded_images(struct pt_regs *regs)
+{
+ efi_print_image_infos((void *)instruction_pointer(regs));
+}
+
void show_regs (struct pt_regs *regs)
{
unsigned long __maybe_unused flags;
@@ -106,6 +112,7 @@
printf ("undefined instruction\n");
fixup_pc(pt_regs, -4);
show_regs (pt_regs);
+ show_efi_loaded_images(pt_regs);
bad_mode ();
}
@@ -115,6 +122,7 @@
printf ("software interrupt\n");
fixup_pc(pt_regs, -4);
show_regs (pt_regs);
+ show_efi_loaded_images(pt_regs);
bad_mode ();
}
@@ -124,6 +132,7 @@
printf ("prefetch abort\n");
fixup_pc(pt_regs, -8);
show_regs (pt_regs);
+ show_efi_loaded_images(pt_regs);
bad_mode ();
}
@@ -133,6 +142,7 @@
printf ("data abort\n");
fixup_pc(pt_regs, -8);
show_regs (pt_regs);
+ show_efi_loaded_images(pt_regs);
bad_mode ();
}
@@ -142,6 +152,7 @@
printf ("not used\n");
fixup_pc(pt_regs, -8);
show_regs (pt_regs);
+ show_efi_loaded_images(pt_regs);
bad_mode ();
}
@@ -151,6 +162,7 @@
printf ("fast interrupt request\n");
fixup_pc(pt_regs, -8);
show_regs (pt_regs);
+ show_efi_loaded_images(pt_regs);
bad_mode ();
}
@@ -160,5 +172,6 @@
printf ("interrupt request\n");
fixup_pc(pt_regs, -8);
show_regs (pt_regs);
+ show_efi_loaded_images(pt_regs);
bad_mode ();
}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6907263..3621dfa 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -85,6 +85,7 @@
select BOARD_LATE_INIT
select DM
select DM_SERIAL
+ select DM_SPI
select DM_GPIO
select DM_ETH
@@ -199,6 +200,8 @@
bool "Aries MA5D4EVK Evaluation Kit"
select SAMA5D4
select SUPPORT_SPL
+ select DM
+ select DM_SPI
config TARGET_MEESC
bool "Support meesc"
@@ -219,6 +222,7 @@
select SUPPORT_SPL
select DM
select DM_SERIAL
+ select DM_SPI
select DM_GPIO
select DM_ETH
@@ -235,6 +239,8 @@
bool "Support VINCO"
select SAMA5D4
select SUPPORT_SPL
+ select DM
+ select DM_SPI
config TARGET_WB45N
bool "Support Laird WB45N"
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 08ad1bf..fbda8d5 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -233,9 +233,15 @@
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
+#define AT91_PMC_USB_USBS_MASK 0x1
+#define AT91_PMC_USB_USBS_OFFSET 0
+#define AT91_PMC_USB_USBS_(x) (x & 0x1)
#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
+#define AT91_PMC_USB_DIV_MASK 0xf
+#define AT91_PMC_USB_DIV_OFFSET 8
+#define AT91_PMC_USB_DIV_(x) ((x & 0xf) << 8)
#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */
#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h
index 478b1f1..d055480 100644
--- a/arch/arm/mach-bcm283x/include/mach/msg.h
+++ b/arch/arm/mach-bcm283x/include/mach/msg.h
@@ -18,9 +18,10 @@
/**
* bcm2835_get_mmc_clock() - get the frequency of the MMC clock
*
+ * @clock_id: ID of clock to get frequency for
* @return clock frequency, or -ve on error
*/
-int bcm2835_get_mmc_clock(void);
+int bcm2835_get_mmc_clock(u32 clock_id);
/**
* bcm2835_get_video_size() - get the current display size
diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
index 92e93ad..ad29f3b 100644
--- a/arch/arm/mach-bcm283x/msg.c
+++ b/arch/arm/mach-bcm283x/msg.c
@@ -65,7 +65,7 @@
return 0;
}
-int bcm2835_get_mmc_clock(void)
+int bcm2835_get_mmc_clock(u32 clock_id)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1);
int ret;
@@ -76,7 +76,7 @@
BCM2835_MBOX_INIT_HDR(msg_clk);
BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE);
- msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
+ msg_clk->get_clock_rate.body.req.clock_id = clock_id;
ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr);
if (ret) {
diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c
index b62cb8a..aa02d3f 100644
--- a/arch/arm/mach-bcm283x/reset.c
+++ b/arch/arm/mach-bcm283x/reset.c
@@ -63,6 +63,7 @@
switch (reset_type) {
case EFI_RESET_COLD:
case EFI_RESET_WARM:
+ case EFI_RESET_PLATFORM_SPECIFIC:
reset_cpu(0);
break;
case EFI_RESET_SHUTDOWN:
@@ -82,9 +83,9 @@
while (1) { }
}
-void efi_reset_system_init(void)
+efi_status_t efi_reset_system_init(void)
{
- efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
+ return efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
}
#endif
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 3075283..5e7baba 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -58,6 +58,7 @@
config SOC_DA8XX
bool
select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+ select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
config MACH_DAVINCI_DA850_EVM
bool
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index 461ff77..7b9d961 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <i2c.h>
#include <net.h>
#include <asm/arch/hardware.h>
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 7eefab5..9ca7bad 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -561,10 +561,8 @@
}
/* Verify if IVT DCD pointer is NULL */
- if (ivt->dcd) {
- puts("Error: DCD pointer must be NULL\n");
- goto hab_authentication_exit;
- }
+ if (ivt->dcd)
+ puts("Warning: DCD pointer should be NULL\n");
start = ddr_start;
bytes = image_size;
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c
index b9214f7..ab4164c 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -46,6 +46,14 @@
PTE_BLOCK_NON_SHARE
},
{
+ /* PCI regions */
+ .phys = 0xe8000000UL,
+ .virt = 0xe8000000UL,
+ .size = 0x02000000UL, /* 32MiB master PCI space */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
/* List terminator */
0,
}
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 62c25c4..3bb1ecb 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -74,6 +74,7 @@
config TI814X
bool "TI814X SoC"
+ select SPECIFY_CONSOLE_INDEX
help
Support for AM335x SOC from Texas Instruments.
The AM335x high performance SOC features a Cortex-A8
@@ -81,6 +82,7 @@
config TI816X
bool "TI816X SoC"
+ select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
help
@@ -90,6 +92,7 @@
config AM43XX
bool "AM43XX SoC"
+ select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DM
@@ -111,6 +114,7 @@
config AM33XX
bool "AM33XX SoC"
+ select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_NAND_AM33XX_BCH
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 9a9ccd7..76da6d9 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -239,6 +239,20 @@
endchoice
+config SPL_RTC_DDR_SUPPORT
+ bool
+ depends on SPL
+ prompt "Enable RTC-DDR ONLY Support"
+ help
+ If you want RTC-DDR ONLY Support, say Y. RTC Only with DDR in
+ self-refresh mode is a special power saving mode where in all
+ the other voltages are turned off apart from the RTC domain and DDR.
+ So only RTC is alive and ticking and one can program it to wake
+ up after a predetermined period. Once RTC alarm fires, the PMIC
+ powers up all the voltage domains. U-Boot takes a special path
+ as the DDR has contents is in self-refresh and restore path is
+ followed.
+
endif
if AM43XX || AM33XX
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index ea0caba..e1d4ddb 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -147,6 +147,16 @@
}
#endif
+/*
+ * RTC only with DDR in self-refresh mode magic value, checked against during
+ * boot to see if we have a valid config. This should be in sync with the value
+ * that will be in drivers/soc/ti/pm33xx.c.
+ */
+#define RTC_MAGIC_VAL 0x8cd0
+
+/* Board type field bit shift for RTC only with DDR in self-refresh mode */
+#define RTC_BOARD_TYPE_SHIFT 16
+
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
@@ -252,6 +262,48 @@
#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
+ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
+static void rtc32k_unlock(struct davinci_rtc *rtc)
+{
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(RTC_KICK0R_WE, &rtc->kick0r);
+ writel(RTC_KICK1R_WE, &rtc->kick1r);
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+/*
+ * Write contents of the RTC_SCRATCH1 register based on board type
+ * Two things are passed
+ * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
+ * control gets to kernel, kernel reads the scratchpad register and gets to
+ * know that bootloader has rtc_only support.
+ *
+ * Second important thing is the board type (16:31). This is needed in the
+ * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
+ * identify the board type and we go ahead and copy the board strings to
+ * am43xx_board_name.
+ */
+void update_rtc_magic(void)
+{
+ struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+ u32 magic = RTC_MAGIC_VAL;
+
+ magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
+
+ rtc32k_unlock(rtc);
+
+ /* write magic */
+ writel(magic, &rtc->scratch1);
+}
+#endif
+
/*
* In the case of non-SPL based booting we'll want to call these
* functions a tiny bit later as it will require gd to be set and cleared
@@ -261,7 +313,9 @@
{
prcm_init();
set_mux_conf_regs();
-
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+ update_rtc_magic();
+#endif
return 0;
}
@@ -278,13 +332,7 @@
{
struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(RTC_KICK0R_WE, &rtc->kick0r);
- writel(RTC_KICK1R_WE, &rtc->kick1r);
+ rtc32k_unlock(rtc);
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
writel((1 << 3) | (1 << 6), &rtc->osc);
@@ -321,8 +369,68 @@
;
}
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+/*
+ * Check if we are executing rtc-only + DDR mode, and resume from it if needed
+ */
+static void rtc_only(void)
+{
+ struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+ struct prm_device_inst *prm_device =
+ (struct prm_device_inst *)PRM_DEVICE_INST;
+
+ u32 scratch1;
+ void (*resume_func)(void);
+
+ scratch1 = readl(&rtc->scratch1);
+
+ /*
+ * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
+ * written to this register when we want to wake up from RTC only
+ * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
+ * bits 0-15: RTC_MAGIC_VAL
+ * bits 16-31: board type (needed for sdram_init)
+ */
+ if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
+ return;
+
+ rtc32k_unlock(rtc);
+
+ /* Clear RTC magic */
+ writel(0, &rtc->scratch1);
+
+ /*
+ * Update board type based on value stored on RTC_SCRATCH1, this
+ * is done so that we don't need to read the board type from eeprom
+ * over i2c bus which is expensive
+ */
+ rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
+
+ /*
+ * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
+ * are resuming from self-refresh. This avoids an unnecessary re-init
+ * of the DDR. The re-init takes time and we would need to wait for
+ * it to complete before accessing DDR to avoid L3 NOC errors.
+ */
+ writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
+
+ rtc_only_prcm_init();
+ sdram_init();
+
+ /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
+ writel(0, &prm_device->emif_ctrl);
+
+ resume_func = (void *)readl(&rtc->scratch0);
+ if (resume_func)
+ resume_func();
+}
+#endif
+
void s_init(void)
{
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+ rtc_only();
+#endif
}
void early_system_init(void)
diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c
index 3d17698..ad28d20 100644
--- a/arch/arm/mach-omap2/am33xx/clock.c
+++ b/arch/arm/mach-omap2/am33xx/clock.c
@@ -244,3 +244,13 @@
scale_vcores();
setup_dplls();
}
+
+void rtc_only_prcm_init(void)
+{
+ const struct dpll_params *params;
+
+ rtc_only_enable_basic_clocks();
+
+ params = get_dpll_ddr_params();
+ do_setup_dpll(&dpll_ddr_regs, params);
+}
diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
index 73ea955..117a63e 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
@@ -124,6 +124,27 @@
writel(0x4, &cmdpll->clkselmacclk);
}
+void rtc_only_enable_basic_clocks(void)
+{
+ u32 *const clk_domains[] = {
+ &cmper->emifclkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en[] = {
+ &cmper->gpio5clkctrl,
+ &cmper->emiffwclkctrl,
+ &cmper->emifclkctrl,
+ &cmper->otfaemifclkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+ /* Select the Master osc clk as Timer2 clock source */
+ writel(0x1, &cmdpll->clktimer2clk);
+}
+
#ifdef CONFIG_TI_EDMA3
void enable_edma3_clocks(void)
{
diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c
index 68c7705..9b429c9 100644
--- a/arch/arm/mach-omap2/am33xx/emif4.c
+++ b/arch/arm/mach-omap2/am33xx/emif4.c
@@ -95,8 +95,13 @@
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+#ifndef CONFIG_SPL_RTC_DDR_SUPPORT
/* Allow EMIF to control DDR_RESET */
writel(0x00000000, &ddrctrl->ddrioctrl);
+#else
+ /* Override EMIF DDR_RESET control */
+ writel(0x80000000, &ddrctrl->ddrioctrl);
+#endif /* CONFIG_SPL_RTC_DDR_SUPPORT */
#endif
/* Program EMIF instance */
diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c
index d11670c..1d39625 100644
--- a/arch/arm/mach-omap2/utils.c
+++ b/arch/arm/mach-omap2/utils.c
@@ -5,8 +5,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <environment.h>
#include <asm/setup.h>
#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+
static void do_cancel_out(u32 *num, u32 *den, u32 factor)
{
while (1) {
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index a96938c..bcadb21 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -71,12 +71,16 @@
select DM
select DM_SERIAL
select SUPPORT_SPL
- select SPL_DM if SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_STOUT
bool "Stout board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
endchoice
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index ba87d21..ce15741 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -18,9 +18,6 @@
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
-#if defined(CONFIG_RCAR_GEN3)
- rcar_gen3_memmap_fixup();
-#endif
dcache_enable();
}
#endif
diff --git a/arch/arm/mach-rmobile/include/mach/boot0.h b/arch/arm/mach-rmobile/include/mach/boot0.h
new file mode 100644
index 0000000..6104469
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/boot0.h
@@ -0,0 +1,24 @@
+/*
+ * Specialty padding for the RCar Gen2 SPL JTAG loading
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+_start:
+ ARM_VECTORS
+
+#ifdef CONFIG_SPL_BUILD
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+#endif
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index ff0ca63..94ea366 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -41,7 +41,6 @@
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
u32 rmobile_get_cpu_rev_fraction(void);
-void rcar_gen3_memmap_fixup(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_H */
diff --git a/arch/arm/mach-rmobile/lowlevel_init_ca15.S b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
index a5dbbea..806a3bc 100644
--- a/arch/arm/mach-rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
@@ -11,6 +11,7 @@
#include <linux/linkage.h>
ENTRY(lowlevel_init)
+#ifndef CONFIG_SPL_BUILD
mrc p15, 0, r4, c0, c0, 5 /* mpidr */
orr r4, r4, r4, lsr #6
and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
@@ -83,6 +84,7 @@
bl s_init
ldr lr, [sp]
+#endif
mov pc, lr
nop
ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c
index 801e392..52cd000 100644
--- a/arch/arm/mach-rmobile/memmap-gen3.c
+++ b/arch/arm/mach-rmobile/memmap-gen3.c
@@ -9,17 +9,24 @@
#include <common.h>
#include <asm/armv8/mmu.h>
-static struct mm_region r8a7795_mem_map[] = {
+static struct mm_region gen3_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
+ .virt = 0xc0000000UL,
+ .phys = 0xc0000000UL,
+ .size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -29,85 +36,4 @@
}
};
-static struct mm_region r8a7796_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xe0000000UL,
- .phys = 0xe0000000UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-static struct mm_region r8a77970_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xe0000000UL,
- .phys = 0xe0000000UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-static struct mm_region r8a77995_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xe0000000UL,
- .phys = 0xe0000000UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = r8a7795_mem_map;
-
-void rcar_gen3_memmap_fixup(void)
-{
- u32 cpu_type = rmobile_get_cpu_type();
-
- switch (cpu_type) {
- case RMOBILE_CPU_TYPE_R8A7795:
- mem_map = r8a7795_mem_map;
- break;
- case RMOBILE_CPU_TYPE_R8A7796:
- case RMOBILE_CPU_TYPE_R8A77965:
- mem_map = r8a7796_mem_map;
- break;
- case RMOBILE_CPU_TYPE_R8A77970:
- mem_map = r8a77970_mem_map;
- break;
- case RMOBILE_CPU_TYPE_R8A77995:
- mem_map = r8a77995_mem_map;
- break;
- }
-}
+struct mm_region *mem_map = gen3_mem_map;
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index f79b1a2..1353284 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -13,6 +13,8 @@
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
+ select STM32_TIMER
+ select TIMER
config STM32F7
bool "stm32f7 family"
@@ -27,6 +29,8 @@
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
+ select STM32_TIMER
+ select TIMER
select SUPPORT_SPL
select SPL
select SPL_BOARD_INIT
@@ -46,6 +50,7 @@
select SPL_RAM
select SPL_SERIAL_SUPPORT
select SPL_SYS_MALLOC_SIMPLE
+ select SPL_TIMER
select SPL_XIP_SUPPORT
config STM32H7
@@ -62,7 +67,9 @@
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
+ select STM32_TIMER
select SYSCON
+ select TIMER
source "arch/arm/mach-stm32/stm32f4/Kconfig"
source "arch/arm/mach-stm32/stm32f7/Kconfig"
diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile
index c2806af..d0f2a96 100644
--- a/arch/arm/mach-stm32/Makefile
+++ b/arch/arm/mach-stm32/Makefile
@@ -5,5 +5,3 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += soc.o
-obj-$(CONFIG_STM32F4) += stm32f4/
-obj-$(CONFIG_STM32F7) += stm32f7/
diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c
index df20d54..f6fd0b2 100644
--- a/arch/arm/mach-stm32/soc.c
+++ b/arch/arm/mach-stm32/soc.c
@@ -15,35 +15,21 @@
struct mpu_region_config stm32_region_config[] = {
/*
- * Make all 4GB cacheable & executable. We are overriding it
- * with next region for any requirement. e.g. below region1,
- * 2 etc.
- * In other words, the area not coming in following
- * regions configuration is the one configured here in region_0
- * (cacheable & executable).
+ * Make SDRAM area cacheable & executable.
*/
+#if defined(CONFIG_STM32F4)
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
- O_I_WB_RD_WR_ALLOC, REGION_4GB },
+ O_I_WB_RD_WR_ALLOC, REGION_16MB },
+#endif
- /* armv7m code area */
- { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_512MB },
+#if defined(CONFIG_STM32F7)
+ { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_16MB },
+#endif
- /* Device area : Not executable */
- { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
- DEVICE_NON_SHARED, REGION_512MB },
-
- /*
- * Armv7m fixed configuration: strongly ordered & not
- * executable, not cacheable
- */
- { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_512MB },
-
-#if !defined(CONFIG_STM32H7)
- /* Device area : Not executable */
- { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
- DEVICE_NON_SHARED, REGION_512MB },
+#if defined(CONFIG_STM32H7)
+ { 0xD0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_32MB },
#endif
};
diff --git a/arch/arm/mach-stm32/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile
deleted file mode 100644
index 86c81bb..0000000
--- a/arch/arm/mach-stm32/stm32f4/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2015
-# Kamil Lulko, <kamil.lulko@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += timer.o
diff --git a/arch/arm/mach-stm32/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c
deleted file mode 100644
index 00b1d4a..0000000
--- a/arch/arm/mach-stm32/stm32f4/timer.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/armv7m.h>
-#include <asm/arch/stm32.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000)
-
-#define RCC_APB1ENR_TIM2EN (1 << 0)
-
-struct stm32_tim2_5 {
- u32 cr1;
- u32 cr2;
- u32 smcr;
- u32 dier;
- u32 sr;
- u32 egr;
- u32 ccmr1;
- u32 ccmr2;
- u32 ccer;
- u32 cnt;
- u32 psc;
- u32 arr;
- u32 reserved1;
- u32 ccr1;
- u32 ccr2;
- u32 ccr3;
- u32 ccr4;
- u32 reserved2;
- u32 dcr;
- u32 dmar;
- u32 or;
-};
-
-#define TIM_CR1_CEN (1 << 0)
-
-#define TIM_EGR_UG (1 << 0)
-
-int timer_init(void)
-{
- struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
-
- writel(((CONFIG_SYS_CLK_FREQ / 2) / CONFIG_SYS_HZ_CLOCK) - 1,
- &tim->psc);
-
- writel(0xFFFFFFFF, &tim->arr);
- writel(TIM_CR1_CEN, &tim->cr1);
- setbits_le32(&tim->egr, TIM_EGR_UG);
-
- gd->arch.tbl = 0;
- gd->arch.tbu = 0;
- gd->arch.lastinc = 0;
-
- return 0;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
- struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
- u32 now;
-
- now = readl(&tim->cnt);
-
- if (now >= gd->arch.lastinc)
- gd->arch.tbl += (now - gd->arch.lastinc);
- else
- gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
-
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-void reset_timer(void)
-{
- struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
- gd->arch.lastinc = readl(&tim->cnt);
- gd->arch.tbl = 0;
-}
-
-/* delay x useconds */
-void __udelay(ulong usec)
-{
- unsigned long long start;
-
- start = get_ticks(); /* get current timestamp */
- while ((get_ticks() - start) < usec)
- ; /* loop till time has passed */
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ_CLOCK;
-}
diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile
deleted file mode 100644
index 8132c13..0000000
--- a/arch/arm/mach-stm32/stm32f7/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2016, STMicroelectronics - All Rights Reserved
-# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += timer.o
diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c
deleted file mode 100644
index 69d37a7..0000000
--- a/arch/arm/mach-stm32/stm32f7/timer.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_defs.h>
-#include <asm/arch/gpt.h>
-
-#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-int timer_init(void)
-{
- /* Timer2 clock configuration */
- clock_setup(TIMER2_CLOCK_CFG);
- /* Stop the timer */
- writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
-
- writel((CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ_CLOCK) - 1,
- &gpt1_regs_ptr->psc);
-
- /* Configure timer for auto-reload */
- writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
- &gpt1_regs_ptr->cr1);
-
- /* load value for free running */
- writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
-
- /* start timer */
- writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
-
- writel(readl(&gpt1_regs_ptr->egr) | TIM_EGR_UG, &gpt1_regs_ptr->egr);
-
- /* Reset the timer */
- lastdec = READ_TIMER();
- timestamp = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong start = get_timer_masked();
- ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
- ulong rndoff;
-
- rndoff = (usec % 10) ? 1 : 0;
-
- /* tenudelcnt timer tick gives 10 microsecconds delay */
- tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
- while ((ulong) (get_timer_masked() - start) < tmo)
- ;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = READ_TIMER();
-
- if (now >= lastdec) {
- /* normal mode */
- timestamp += now - lastdec;
- } else {
- /* we have an overflow ... */
- timestamp += now + GPT_FREE_RUNNING - lastdec;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-void udelay_masked(unsigned long usec)
-{
- return udelay(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_STM32_HZ;
-}
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
new file mode 100644
index 0000000..8ca97bf
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -0,0 +1,53 @@
+if ARCH_STM32MP
+
+config SPL
+ select SPL_BOARD_INIT
+ select SPL_CLK
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_FRAMEWORK
+ select SPL_GPIO_SUPPORT
+ select SPL_LIBCOMMON_SUPPORT
+ select SPL_LIBGENERIC_SUPPORT
+ select SPL_OF_CONTROL
+ select SPL_OF_TRANSLATE
+ select SPL_PINCTRL
+ select SPL_REGMAP
+ select SPL_RESET_SUPPORT
+ select SPL_SERIAL_SUPPORT
+ select SPL_SYSCON
+ select SPL_DRIVERS_MISC_SUPPORT
+ imply SPL_LIBDISK_SUPPORT
+
+config SYS_SOC
+ default "stm32mp"
+
+config TARGET_STM32MP1
+ bool "Support stm32mp1xx"
+ select CPU_V7
+ select PINCTRL_STM32
+ select STM32_RESET
+ select SYSRESET_SYSCON
+ help
+ target STMicroelectronics SOC STM32MP1 family
+ STMicroelectronics MPU with core ARMv7
+
+config SYS_TEXT_BASE
+ prompt "U-Boot base address"
+ default 0xC0100000
+ help
+ configure the U-Boot base address
+ when DDR driver is used:
+ DDR + 1MB (0xC0100000)
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
+ hex "Partition on MMC2 to use to load U-Boot from"
+ depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ default 1
+ help
+ Partition on the second MMC to load U-Boot from when the MMC is being
+ used in raw mode
+
+source "board/st/stm32mp1/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
new file mode 100644
index 0000000..a495c53
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+obj-y += cpu.o
+obj-y += dram_init.o
+obj-y += syscon.o
+
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk
new file mode 100644
index 0000000..34e59c6
--- /dev/null
+++ b/arch/arm/mach-stm32mp/config.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32
+
+MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
+
+spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log
+
+spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
new file mode 100644
index 0000000..f9f3bf9
--- /dev/null
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+#include <common.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/uclass.h>
+
+/* RCC register */
+#define RCC_TZCR (STM32_RCC_BASE + 0x00)
+#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
+#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
+#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
+#define RCC_BDCR_VSWRST BIT(31)
+#define RCC_BDCR_RTCSRC GENMASK(17, 16)
+#define RCC_DBGCFGR_DBGCKEN BIT(8)
+
+/* Security register */
+#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
+#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
+
+#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
+#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
+#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
+
+#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
+
+#define PWR_CR1 (STM32_PWR_BASE + 0x00)
+#define PWR_CR1_DBP BIT(8)
+
+/* DBGMCU register */
+#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
+#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
+#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
+#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
+#define DBGMCU_IDC_DEV_ID_SHIFT 0
+#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
+#define DBGMCU_IDC_REV_ID_SHIFT 16
+
+/* boot interface from Bootrom
+ * - boot instance = bit 31:16
+ * - boot device = bit 15:0
+ */
+#define BOOTROM_PARAM_ADDR 0x2FFC0078
+#define BOOTROM_MODE_MASK GENMASK(15, 0)
+#define BOOTROM_MODE_SHIFT 0
+#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
+#define BOOTROM_INSTANCE_SHIFT 16
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+static void security_init(void)
+{
+ /* Disable the backup domain write protection */
+ /* the protection is enable at each reset by hardware */
+ /* And must be disable by software */
+ setbits_le32(PWR_CR1, PWR_CR1_DBP);
+
+ while (!(readl(PWR_CR1) & PWR_CR1_DBP))
+ ;
+
+ /* If RTC clock isn't enable so this is a cold boot then we need
+ * to reset the backup domain
+ */
+ if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
+ setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
+ ;
+ clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ }
+
+ /* allow non secure access in Write/Read for all peripheral */
+ writel(GENMASK(25, 0), ETZPC_DECPROT0);
+
+ /* Open SYSRAM for no secure access */
+ writel(0x0, ETZPC_TZMA1_SIZE);
+
+ /* enable TZC1 TZC2 clock */
+ writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
+
+ /* Region 0 set to no access by default */
+ /* bit 0 / 16 => nsaid0 read/write Enable
+ * bit 1 / 17 => nsaid1 read/write Enable
+ * ...
+ * bit 15 / 31 => nsaid15 read/write Enable
+ */
+ writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
+ /* bit 30 / 31 => Secure Global Enable : write/read */
+ /* bit 0 / 1 => Region Enable for filter 0/1 */
+ writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
+
+ /* Enable Filter 0 and 1 */
+ setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
+
+ /* RCC trust zone deactivated */
+ writel(0x0, RCC_TZCR);
+
+ /* TAMP: deactivate the internal tamper
+ * Bit 23 ITAMP8E: monotonic counter overflow
+ * Bit 20 ITAMP5E: RTC calendar overflow
+ * Bit 19 ITAMP4E: HSE monitoring
+ * Bit 18 ITAMP3E: LSE monitoring
+ * Bit 16 ITAMP1E: RTC power domain supply monitoring
+ */
+ writel(0x0, TAMP_CR1);
+}
+
+/*
+ * Debug init
+ */
+static void dbgmcu_init(void)
+{
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+
+ /* Freeze IWDG2 if Cortex-A7 is in debug mode */
+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+}
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+
+static u32 get_bootmode(void)
+{
+ u32 boot_mode;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
+ u32 bootrom_device, bootrom_instance;
+
+ bootrom_device =
+ (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
+ bootrom_instance =
+ (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
+ boot_mode =
+ ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
+ ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
+ BOOT_INSTANCE_MASK);
+
+ /* save the boot mode in TAMP backup register */
+ clrsetbits_le32(TAMP_BOOT_CONTEXT,
+ TAMP_BOOT_MODE_MASK,
+ boot_mode << TAMP_BOOT_MODE_SHIFT);
+#else
+ /* read TAMP backup register */
+ boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
+ TAMP_BOOT_MODE_SHIFT;
+#endif
+ return boot_mode;
+}
+
+/*
+ * Early system init
+ */
+int arch_cpu_init(void)
+{
+ /* early armv7 timer init: needed for polling */
+ timer_init();
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ dbgmcu_init();
+
+ security_init();
+#endif
+ /* get bootmode from BootRom context: saved in TAMP register */
+ get_bootmode();
+
+ return 0;
+}
+
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+
+static u32 read_idc(void)
+{
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+
+ return readl(DBGMCU_IDC);
+}
+
+u32 get_cpu_rev(void)
+{
+ return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
+}
+
+u32 get_cpu_type(void)
+{
+ return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ char *cpu_s, *cpu_r;
+
+ switch (get_cpu_type()) {
+ case CPU_STMP32MP15x:
+ cpu_s = "15x";
+ break;
+ default:
+ cpu_s = "?";
+ break;
+ }
+
+ switch (get_cpu_rev()) {
+ case CPU_REVA:
+ cpu_r = "A";
+ break;
+ case CPU_REVB:
+ cpu_r = "B";
+ break;
+ default:
+ cpu_r = "?";
+ break;
+ }
+
+ printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r);
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+static void setup_boot_mode(void)
+{
+ char cmd[60];
+ u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
+ u32 boot_mode =
+ (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
+ int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+
+ pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n",
+ __func__, boot_ctx, boot_mode, instance);
+
+ switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
+ case BOOT_SERIAL_UART:
+ sprintf(cmd, "%d", instance);
+ env_set("boot_device", "uart");
+ env_set("boot_instance", cmd);
+ break;
+ case BOOT_SERIAL_USB:
+ env_set("boot_device", "usb");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_SD:
+ case BOOT_FLASH_EMMC:
+ sprintf(cmd, "%d", instance);
+ env_set("boot_device", "mmc");
+ env_set("boot_instance", cmd);
+ break;
+ case BOOT_FLASH_NAND:
+ env_set("boot_device", "nand");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_NOR:
+ env_set("boot_device", "nor");
+ env_set("boot_instance", "0");
+ break;
+ default:
+ pr_debug("unexpected boot mode = %x\n", boot_mode);
+ break;
+ }
+}
+
+int arch_misc_init(void)
+{
+ setup_boot_mode();
+
+ return 0;
+}
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
new file mode 100644
index 0000000..ecb4c98
--- /dev/null
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("RAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get RAM size: %d\n", ret);
+ return ret;
+ }
+ debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h
new file mode 100644
index 0000000..b635001
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __MACH_STM32MP_DDR_H_
+#define __MACH_STM32MP_DDR_H_
+
+int board_ddr_power_init(void);
+
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h
new file mode 100644
index 0000000..5952557
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/gpio.h
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+#include <asm/gpio.h>
+
+enum stm32_gpio_port {
+ STM32_GPIO_PORT_A = 0,
+ STM32_GPIO_PORT_B,
+ STM32_GPIO_PORT_C,
+ STM32_GPIO_PORT_D,
+ STM32_GPIO_PORT_E,
+ STM32_GPIO_PORT_F,
+ STM32_GPIO_PORT_G,
+ STM32_GPIO_PORT_H,
+ STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+ STM32_GPIO_PIN_0 = 0,
+ STM32_GPIO_PIN_1,
+ STM32_GPIO_PIN_2,
+ STM32_GPIO_PIN_3,
+ STM32_GPIO_PIN_4,
+ STM32_GPIO_PIN_5,
+ STM32_GPIO_PIN_6,
+ STM32_GPIO_PIN_7,
+ STM32_GPIO_PIN_8,
+ STM32_GPIO_PIN_9,
+ STM32_GPIO_PIN_10,
+ STM32_GPIO_PIN_11,
+ STM32_GPIO_PIN_12,
+ STM32_GPIO_PIN_13,
+ STM32_GPIO_PIN_14,
+ STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+ STM32_GPIO_MODE_IN = 0,
+ STM32_GPIO_MODE_OUT,
+ STM32_GPIO_MODE_AF,
+ STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+ STM32_GPIO_OTYPE_PP = 0,
+ STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+ STM32_GPIO_SPEED_2M = 0,
+ STM32_GPIO_SPEED_25M,
+ STM32_GPIO_SPEED_50M,
+ STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+ STM32_GPIO_PUPD_NO = 0,
+ STM32_GPIO_PUPD_UP,
+ STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+ STM32_GPIO_AF0 = 0,
+ STM32_GPIO_AF1,
+ STM32_GPIO_AF2,
+ STM32_GPIO_AF3,
+ STM32_GPIO_AF4,
+ STM32_GPIO_AF5,
+ STM32_GPIO_AF6,
+ STM32_GPIO_AF7,
+ STM32_GPIO_AF8,
+ STM32_GPIO_AF9,
+ STM32_GPIO_AF10,
+ STM32_GPIO_AF11,
+ STM32_GPIO_AF12,
+ STM32_GPIO_AF13,
+ STM32_GPIO_AF14,
+ STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+ enum stm32_gpio_port port;
+ enum stm32_gpio_pin pin;
+};
+
+struct stm32_gpio_ctl {
+ enum stm32_gpio_mode mode;
+ enum stm32_gpio_otype otype;
+ enum stm32_gpio_speed speed;
+ enum stm32_gpio_pupd pupd;
+ enum stm32_gpio_af af;
+};
+
+struct stm32_gpio_regs {
+ u32 moder; /* GPIO port mode */
+ u32 otyper; /* GPIO port output type */
+ u32 ospeedr; /* GPIO port output speed */
+ u32 pupdr; /* GPIO port pull-up/pull-down */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 lckr; /* GPIO port configuration lock */
+ u32 afr[2]; /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+ struct stm32_gpio_regs *regs;
+};
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
new file mode 100644
index 0000000..c7a2789
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+/*
+ * Peripheral memory map
+ * only address used before device tree parsing
+ */
+#define STM32_RCC_BASE 0x50000000
+#define STM32_PWR_BASE 0x50001000
+#define STM32_DBGMCU_BASE 0x50081000
+#define STM32_TZC_BASE 0x5C006000
+#define STM32_ETZPC_BASE 0x5C007000
+#define STM32_TAMP_BASE 0x5C00A000
+
+#define STM32_SYSRAM_BASE 0x2FFC0000
+#define STM32_SYSRAM_SIZE SZ_256K
+
+#define STM32_DDR_BASE 0xC0000000
+#define STM32_DDR_SIZE SZ_1G
+
+#ifndef __ASSEMBLY__
+/* enumerated used to identify the SYSCON driver instance */
+enum {
+ STM32MP_SYSCON_UNKNOWN,
+ STM32MP_SYSCON_STGEN,
+};
+
+/*
+ * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
+ * - boot device = bit 8:4
+ * - boot instance = bit 3:0
+ */
+#define BOOT_TYPE_MASK 0xF0
+#define BOOT_TYPE_SHIFT 4
+#define BOOT_INSTANCE_MASK 0x0F
+#define BOOT_INSTANCE_SHIFT 0
+
+enum boot_device {
+ BOOT_FLASH_SD = 0x10,
+ BOOT_FLASH_SD_1 = 0x11,
+ BOOT_FLASH_SD_2 = 0x12,
+ BOOT_FLASH_SD_3 = 0x13,
+
+ BOOT_FLASH_EMMC = 0x20,
+ BOOT_FLASH_EMMC_1 = 0x21,
+ BOOT_FLASH_EMMC_2 = 0x22,
+ BOOT_FLASH_EMMC_3 = 0x23,
+
+ BOOT_FLASH_NAND = 0x30,
+ BOOT_FLASH_NAND_FMC = 0x31,
+
+ BOOT_FLASH_NOR = 0x40,
+ BOOT_FLASH_NOR_QSPI = 0x41,
+
+ BOOT_SERIAL_UART = 0x50,
+ BOOT_SERIAL_UART_1 = 0x51,
+ BOOT_SERIAL_UART_2 = 0x52,
+ BOOT_SERIAL_UART_3 = 0x53,
+ BOOT_SERIAL_UART_4 = 0x54,
+ BOOT_SERIAL_UART_5 = 0x55,
+ BOOT_SERIAL_UART_6 = 0x56,
+ BOOT_SERIAL_UART_7 = 0x57,
+ BOOT_SERIAL_UART_8 = 0x58,
+
+ BOOT_SERIAL_USB = 0x60,
+ BOOT_SERIAL_USB_OTG = 0x62,
+};
+
+/* TAMP registers */
+#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
+#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
+
+#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
+#define TAMP_BOOT_MODE_SHIFT 8
+#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
+#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+
+#endif /* __ASSEMBLY__*/
+#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
new file mode 100644
index 0000000..a8c20d1
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#define CPU_STMP32MP15x 0x500
+
+/* return CPU_STMP32MPxx constants */
+u32 get_cpu_type(void);
+
+#define CPU_REVA 0x1000
+#define CPU_REVB 0x2000
+
+/* return CPU_REV constants */
+u32 get_cpu_rev(void);
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
new file mode 100644
index 0000000..bfb3e50
--- /dev/null
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <asm/io.h>
+
+u32 spl_boot_device(void)
+{
+ u32 boot_mode;
+
+ boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
+ TAMP_BOOT_MODE_SHIFT;
+ clrsetbits_le32(TAMP_BOOT_CONTEXT,
+ TAMP_BOOT_MODE_MASK,
+ boot_mode << TAMP_BOOT_MODE_SHIFT);
+
+ switch (boot_mode) {
+ case BOOT_FLASH_SD_1:
+ case BOOT_FLASH_EMMC_1:
+ return BOOT_DEVICE_MMC1;
+ case BOOT_FLASH_SD_2:
+ case BOOT_FLASH_EMMC_2:
+ return BOOT_DEVICE_MMC2;
+ }
+
+ return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ return MMCSD_MODE_RAW;
+}
+
+int spl_boot_partition(const u32 boot_device)
+{
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
+ case BOOT_DEVICE_MMC2:
+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2;
+ default:
+ return -EINVAL;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ arch_cpu_init();
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("Clock init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+ if (ret) {
+ debug("Reset init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ return;
+ }
+
+ /* enable console uart printing */
+ preloader_console_init();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c
new file mode 100644
index 0000000..5641745
--- /dev/null
+++ b/arch/arm/mach-stm32mp/syscon.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/stm32.h>
+
+static const struct udevice_id stm32mp_syscon_ids[] = {
+ { .compatible = "st,stm32-stgen",
+ .data = STM32MP_SYSCON_STGEN },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_stm32mp) = {
+ .name = "stmp32mp_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = stm32mp_syscon_ids,
+ .bind = dm_scan_fdt_dev,
+};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1fededd..b868f0e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -6,6 +6,73 @@
config IDENT_STRING
default " Allwinner Technology"
+config DRAM_SUN4I
+ bool
+ help
+ Select this dram controller driver for Sun4/5/7i platforms,
+ like A10/A13/A20.
+
+config DRAM_SUN6I
+ bool
+ help
+ Select this dram controller driver for Sun6i platforms,
+ like A31/A31s.
+
+config DRAM_SUN8I_A23
+ bool
+ help
+ Select this dram controller driver for Sun8i platforms,
+ for A23 SOC.
+
+config DRAM_SUN8I_A33
+ bool
+ help
+ Select this dram controller driver for Sun8i platforms,
+ for A33 SOC.
+
+config DRAM_SUN8I_A83T
+ bool
+ help
+ Select this dram controller driver for Sun8i platforms,
+ for A83T SOC.
+
+config DRAM_SUN9I
+ bool
+ help
+ Select this dram controller driver for Sun9i platforms,
+ like A80.
+
+config SUN6I_P2WI
+ bool "Allwinner sun6i internal P2WI controller"
+ help
+ If you say yes to this option, support will be included for the
+ P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
+ SOCs.
+ The P2WI looks like an SMBus controller (which supports only byte
+ accesses), except that it only supports one slave device.
+ This interface is used to connect to specific PMIC devices (like the
+ AXP221).
+
+config SUN6I_PRCM
+ bool
+ help
+ Support for the PRCM (Power/Reset/Clock Management) unit available
+ in A31 SoC.
+
+config AXP_PMIC_BUS
+ bool "Sunxi AXP PMIC bus access helpers"
+ help
+ Select this PMIC bus access helpers for Sunxi platform PRCM or other
+ AXP family PMIC devices.
+
+config SUN8I_RSB
+ bool "Allwinner sunXi Reduced Serial Bus Driver"
+ help
+ Say y here to enable support for Allwinner's Reduced Serial Bus
+ (RSB) support. This controller is responsible for communicating
+ with various RSB based devices, such as AXP223, AXP8XX PMICs,
+ and AC100/AC200 ICs.
+
config SUNXI_HIGH_SRAM
bool
default n
@@ -71,6 +138,7 @@
bool "sun4i (Allwinner A10)"
select CPU_V7
select ARM_CORTEX_CPU_IS_UP
+ select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
@@ -78,8 +146,10 @@
bool "sun5i (Allwinner A13)"
select CPU_V7
select ARM_CORTEX_CPU_IS_UP
+ select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
+ imply CONS_INDEX_2 if !DM_SERIAL
config MACH_SUN6I
bool "sun6i (Allwinner A31)"
@@ -87,6 +157,9 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN6I
+ select SUN6I_P2WI
+ select SUN6I_PRCM
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -97,6 +170,7 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -107,9 +181,11 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN8I_A23
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply CONS_INDEX_5 if !DM_SERIAL
config MACH_SUN8I_A33
bool "sun8i (Allwinner A33)"
@@ -117,13 +193,16 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN8I_A33
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply CONS_INDEX_5 if !DM_SERIAL
config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7
+ select DRAM_SUN8I_A83T
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
select SUPPORT_SPL
@@ -163,8 +242,11 @@
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
+ select DRAM_SUN9I
+ select SUN6I_PRCM
select SUNXI_HIGH_SRAM
select SUNXI_GEN_SUN6I
+ select SUN8I_RSB
select SUPPORT_SPL
config MACH_SUN50I
@@ -193,6 +275,8 @@
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
+ select SUN8I_RSB
+ select SUN6I_PRCM
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
default y if MACH_SUN8I_A83T
@@ -847,4 +931,12 @@
default 0x2fe00000 if MACH_SUN9I
default 0x4fe00000 if MACH_SUN50I
+config SPL_SPI_SUNXI
+ bool "Support for SPI Flash on Allwinner SoCs in SPL"
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
+ help
+ Enable support for SPI Flash. This option allows SPL to read from
+ sunxi SPI Flash. It uses the same method as the boot ROM, so does
+ not need any extra configuration.
+
endif
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 2a3c379..1831753 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -16,12 +16,10 @@
ifndef CONFIG_MACH_SUN9I
obj-y += usb_phy.o
endif
-obj-$(CONFIG_MACH_SUN6I) += prcm.o
-obj-$(CONFIG_MACH_SUN8I) += prcm.o
-obj-$(CONFIG_MACH_SUN9I) += prcm.o
-obj-$(CONFIG_MACH_SUN6I) += p2wi.o
-obj-$(CONFIG_MACH_SUN8I) += rsb.o
-obj-$(CONFIG_MACH_SUN9I) += rsb.o
+obj-$(CONFIG_SUN6I_P2WI) += p2wi.o
+obj-$(CONFIG_SUN6I_PRCM) += prcm.o
+obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
+obj-$(CONFIG_SUN8I_RSB) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
@@ -34,21 +32,14 @@
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
-obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
-
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
-obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
-obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
-obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
+obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
+obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o
+obj-$(CONFIG_DRAM_SUN8I_A23) += dram_sun8i_a23.o
+obj-$(CONFIG_DRAM_SUN8I_A33) += dram_sun8i_a33.o
+obj-$(CONFIG_DRAM_SUN8I_A83T) += dram_sun8i_a83t.o
+obj-$(CONFIG_DRAM_SUN9I) += dram_sun9i.o
+obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
-obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
endif
diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
similarity index 100%
rename from drivers/mtd/spi/sunxi_spi_spl.c
rename to arch/arm/mach-sunxi/spl_spi_sunxi.c
diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c
index 1369cd0..3c27038 100644
--- a/arch/arm/mach-zynq/clk.c
+++ b/arch/arm/mach-zynq/clk.c
@@ -94,7 +94,8 @@
clk_free(&clk);
- if (rate == (unsigned long)-ENOSYS)
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO))
printf("%10s%20s\n", name, "unknown");
else
printf("%10s%20lu\n", name, rate);
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 840dbf1..e80905c 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -15,6 +15,7 @@
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
+dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi
index 54964a7..015acc9 100644
--- a/arch/mips/dts/brcm,bcm6318.dtsi
+++ b/arch/mips/dts/brcm,bcm6318.dtsi
@@ -153,5 +153,35 @@
reg = <0x10004000 0x38>;
u-boot,dm-pre-reloc;
};
+
+ ehci: usb-controller@10005000 {
+ compatible = "brcm,bcm6318-ehci", "generic-ehci";
+ reg = <0x10005000 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ ohci: usb-controller@10005100 {
+ compatible = "brcm,bcm6318-ohci", "generic-ohci";
+ reg = <0x10005100 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ usbh: usb-phy@10005200 {
+ compatible = "brcm,bcm6318-usbh";
+ reg = <0x10005200 0x30>;
+ #phy-cells = <0>;
+ clocks = <&periph_clk BCM6318_CLK_USB>;
+ clock-names = "usbh";
+ power-domains = <&periph_pwr BCM6318_PWR_USB>;
+ resets = <&periph_rst BCM6318_RST_USBH>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 4d4e36c..ade0b49 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -183,6 +183,36 @@
status = "disabled";
};
+ ehci: usb-controller@10002500 {
+ compatible = "brcm,bcm63268-ehci", "generic-ehci";
+ reg = <0x10002500 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ ohci: usb-controller@10002600 {
+ compatible = "brcm,bcm63268-ohci", "generic-ohci";
+ reg = <0x10002600 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ usbh: usb-phy@10002700 {
+ compatible = "brcm,bcm63268-usbh";
+ reg = <0x10002700 0x38>;
+ #phy-cells = <0>;
+ clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>;
+ clock-names = "usbh", "usb_ref";
+ power-domains = <&periph_pwr BCM63268_PWR_USBH>;
+ resets = <&periph_rst BCM63268_RST_USBH>;
+
+ status = "disabled";
+ };
+
memory-controller@10003000 {
compatible = "brcm,bcm6328-mc";
reg = <0x10003000 0x894>;
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index 67d9278..4fbbcec 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -153,6 +153,36 @@
#power-domain-cells = <1>;
};
+ ehci: usb-controller@10002500 {
+ compatible = "brcm,bcm6328-ehci", "generic-ehci";
+ reg = <0x10002500 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ ohci: usb-controller@10002600 {
+ compatible = "brcm,bcm6328-ohci", "generic-ohci";
+ reg = <0x10002600 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ usbh: usb-phy@10002700 {
+ compatible = "brcm,bcm6328-usbh";
+ reg = <0x10002700 0x38>;
+ #phy-cells = <0>;
+ clocks = <&periph_clk BCM6328_CLK_USBH>;
+ clock-names = "usbh";
+ power-domains = <&periph_pwr BCM6328_PWR_USBH>;
+ resets = <&periph_rst BCM6328_RST_USBH>;
+
+ status = "disabled";
+ };
+
memory-controller@10003000 {
compatible = "brcm,bcm6328-mc";
reg = <0x10003000 0x864>;
diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
index 540b9fe..92fb91a 100644
--- a/arch/mips/dts/brcm,bcm6348.dtsi
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -135,6 +135,26 @@
status = "disabled";
};
+ ohci: usb-controller@fffe1b00 {
+ compatible = "brcm,bcm6348-ohci", "generic-ohci";
+ reg = <0xfffe1b00 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ usbh: usb-phy@fffe1c00 {
+ compatible = "brcm,bcm6348-usbh";
+ reg = <0xfffe1c00 0x4>;
+ #phy-cells = <0>;
+ clocks = <&periph_clk BCM6348_CLK_USBH>;
+ clock-names = "usbh";
+ resets = <&periph_rst BCM6348_RST_USBH>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe2300 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe2300 0x38>;
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
index 1662783..b63b53b 100644
--- a/arch/mips/dts/brcm,bcm6358.dtsi
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -164,5 +164,32 @@
reg = <0xfffe1200 0x4c>;
u-boot,dm-pre-reloc;
};
+
+ ehci: usb-controller@fffe1300 {
+ compatible = "brcm,bcm6358-ehci", "generic-ehci";
+ reg = <0xfffe1300 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ ohci: usb-controller@fffe1400 {
+ compatible = "brcm,bcm6358-ohci", "generic-ohci";
+ reg = <0xfffe1400 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ usbh: usb-phy@fffe1500 {
+ compatible = "brcm,bcm6358-usbh";
+ reg = <0xfffe1500 0x28>;
+ #phy-cells = <0>;
+ resets = <&periph_rst BCM6358_RST_USBH>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi
new file mode 100644
index 0000000..f695ec3
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6362.dtsi
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6362-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power-domain/bcm6362-power-domain.h>
+#include <dt-bindings/reset/bcm6362-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6362";
+
+ aliases {
+ spi0 = &lsspi;
+ spi1 = &hsspi;
+ };
+
+ cpus {
+ reg = <0x10000000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133333333>;
+ };
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk: periph-clk {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0x10000004 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ pll_cntl: syscon@10000008 {
+ compatible = "syscon";
+ reg = <0x10000008 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ periph_rst: reset-controller@10000010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
+
+ wdt: watchdog@1000005c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x1000005c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ gpio1: gpio-controller@10000080 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10000080 0x4>, <0x10000088 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@10000084 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10000084 0x4>, <0x1000008c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@10000100 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000100 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@10000120 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000120 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ lsspi: spi@10000800 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0x10000800 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6362_CLK_SPI>;
+ resets = <&periph_rst BCM6362_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
+ hsspi: spi@10001000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10001000 0x600>;
+ clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ resets = <&periph_rst BCM6362_RST_SPI>;
+ spi-max-frequency = <50000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
+ leds: led-controller@10001900 {
+ compatible = "brcm,bcm6328-leds";
+ reg = <0x10001900 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ periph_pwr: power-controller@10001848 {
+ compatible = "brcm,bcm6328-power-domain";
+ reg = <0x10001848 0x4>;
+ #power-domain-cells = <1>;
+ };
+
+ ehci: usb-controller@10002500 {
+ compatible = "brcm,bcm6362-ehci", "generic-ehci";
+ reg = <0x10002500 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ ohci: usb-controller@10002600 {
+ compatible = "brcm,bcm6362-ohci", "generic-ohci";
+ reg = <0x10002600 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ usbh: usb-phy@10002700 {
+ compatible = "brcm,bcm6368-usbh";
+ reg = <0x10002700 0x38>;
+ #phy-cells = <0>;
+ clocks = <&periph_clk BCM6362_CLK_USBH>;
+ clock-names = "usbh";
+ power-domains = <&periph_pwr BCM6362_PWR_USBH>;
+ resets = <&periph_rst BCM6362_RST_USBH>;
+
+ status = "disabled";
+ };
+
+ memory-controller@10003000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x10003000 0x864>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi
index 1bb538a..fc1c5a2 100644
--- a/arch/mips/dts/brcm,bcm6368.dtsi
+++ b/arch/mips/dts/brcm,bcm6368.dtsi
@@ -164,5 +164,34 @@
reg = <0x10001200 0x4c>;
u-boot,dm-pre-reloc;
};
+
+ ehci: usb-controller@10001500 {
+ compatible = "brcm,bcm6368-ehci", "generic-ehci";
+ reg = <0x10001500 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ ohci: usb-controller@10001600 {
+ compatible = "brcm,bcm6368-ohci", "generic-ohci";
+ reg = <0x10001600 0x100>;
+ phys = <&usbh>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ usbh: usb-phy@10001700 {
+ compatible = "brcm,bcm6368-usbh";
+ reg = <0x10001700 0x38>;
+ #phy-cells = <0>;
+ clocks = <&periph_clk BCM6368_CLK_USBH>;
+ clock-names = "usbh";
+ resets = <&periph_rst BCM6368_RST_USBH>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/dts/comtrend,ar-5315u.dts b/arch/mips/dts/comtrend,ar-5315u.dts
index 4e4d69b..af3159a 100644
--- a/arch/mips/dts/comtrend,ar-5315u.dts
+++ b/arch/mips/dts/comtrend,ar-5315u.dts
@@ -21,6 +21,10 @@
};
};
+&ehci {
+ status = "okay";
+};
+
&leds {
status = "okay";
@@ -67,6 +71,10 @@
};
};
+&ohci {
+ status = "okay";
+};
+
&spi {
status = "okay";
@@ -83,3 +91,7 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts
index 6067881..3a97315 100644
--- a/arch/mips/dts/comtrend,ar-5387un.dts
+++ b/arch/mips/dts/comtrend,ar-5387un.dts
@@ -21,6 +21,10 @@
};
};
+&ehci {
+ status = "okay";
+};
+
&leds {
status = "okay";
@@ -51,6 +55,10 @@
};
};
+&ohci {
+ status = "okay";
+};
+
&spi {
status = "okay";
@@ -67,3 +75,7 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
index c909a52..74dc090 100644
--- a/arch/mips/dts/comtrend,ct-5361.dts
+++ b/arch/mips/dts/comtrend,ct-5361.dts
@@ -39,6 +39,10 @@
status = "okay";
};
+&ohci {
+ status = "okay";
+};
+
&pflash {
status = "okay";
};
@@ -47,3 +51,7 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts
index 54e738c..9bbecbc 100644
--- a/arch/mips/dts/comtrend,vr-3032u.dts
+++ b/arch/mips/dts/comtrend,vr-3032u.dts
@@ -21,6 +21,10 @@
};
};
+&ehci {
+ status = "okay";
+};
+
&leds {
status = "okay";
brcm,serial-leds;
@@ -64,7 +68,15 @@
};
};
+&ohci {
+ status = "okay";
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/dts/comtrend,wap-5813n.dts b/arch/mips/dts/comtrend,wap-5813n.dts
index 29386e2..f1f5430 100644
--- a/arch/mips/dts/comtrend,wap-5813n.dts
+++ b/arch/mips/dts/comtrend,wap-5813n.dts
@@ -51,10 +51,18 @@
};
};
+&ehci {
+ status = "okay";
+};
+
&gpio0 {
status = "okay";
};
+&ohci {
+ status = "okay";
+};
+
&pflash {
status = "okay";
};
@@ -63,3 +71,7 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts
index 31c7d7e..a1e9c15 100644
--- a/arch/mips/dts/huawei,hg556a.dts
+++ b/arch/mips/dts/huawei,hg556a.dts
@@ -90,10 +90,18 @@
};
};
+&ehci {
+ status = "okay";
+};
+
&gpio0 {
status = "okay";
};
+&ohci {
+ status = "okay";
+};
+
&pflash {
status = "okay";
};
@@ -102,3 +110,7 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts
new file mode 100644
index 0000000..8dc7d7e
--- /dev/null
+++ b/arch/mips/dts/netgear,dgnd3700v2.dts
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6362.dtsi"
+
+/ {
+ model = "Netgear DGND3700v2";
+ compatible = "netgear,dgnd3700v2", "brcm,bcm6362";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ inet_green {
+ label = "DGND3700v2:green:inet";
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ dsl_green {
+ label = "DGND3700v2:green:dsl";
+ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+ };
+
+ power_amber {
+ label = "DGND3700v2:red:power";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ehci {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+ brcm,serial-leds;
+ brcm,serial-dat-low;
+ brcm,serial-shift-inv;
+ brcm,serial-mux;
+
+ led@8 {
+ reg = <8>;
+ label = "DGND3700v2:green:power";
+ };
+
+ led@9 {
+ reg = <9>;
+ active-low;
+ label = "DGND3700v2:green:wps";
+ };
+
+ led@10 {
+ reg = <10>;
+ active-low;
+ label = "DGND3700v2:green:usb1";
+ };
+
+ led@11 {
+ reg = <11>;
+ active-low;
+ label = "DGND3700v2:green:usb2";
+ };
+
+ led@12 {
+ reg = <12>;
+ active-low;
+ label = "DGND3700v2:amber:inet";
+ };
+
+ led@13 {
+ reg = <13>;
+ active-low;
+ label = "DGND3700v2:green:ethernet";
+ };
+
+ led@14 {
+ reg = <14>;
+ active-low;
+ label = "DGND3700v2:amber:dsl";
+ };
+
+ led@16 {
+ reg = <16>;
+ active-low;
+ label = "DGND3700v2:amber:usb1";
+ };
+
+ led@17 {
+ reg = <17>;
+ active-low;
+ label = "DGND3700v2:amber:usb2";
+ };
+
+ led@18 {
+ reg = <18>;
+ active-low;
+ label = "DGND3700v2:amber:ethernet";
+ };
+};
+
+&ohci {
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts
index f2092e9..473372f 100644
--- a/arch/mips/dts/sfr,nb4-ser.dts
+++ b/arch/mips/dts/sfr,nb4-ser.dts
@@ -50,6 +50,10 @@
};
};
+&ehci {
+ status = "okay";
+};
+
&gpio0 {
status = "okay";
};
@@ -83,6 +87,10 @@
};
};
+&ohci {
+ status = "okay";
+};
+
&pflash {
status = "okay";
};
@@ -91,3 +99,7 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&usbh {
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index e4a0118..10900bf 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -12,6 +12,7 @@
default "bcm6348" if SOC_BMIPS_BCM6348
default "bcm6358" if SOC_BMIPS_BCM6358
default "bcm6368" if SOC_BMIPS_BCM6368
+ default "bcm6362" if SOC_BMIPS_BCM6362
default "bcm63268" if SOC_BMIPS_BCM63268
choice
@@ -94,6 +95,17 @@
help
This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
+config SOC_BMIPS_BCM6362
+ bool "BMIPS BCM6362 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6362 family including BCM6361 and BCM6362.
+
config SOC_BMIPS_BCM63268
bool "BMIPS BCM63268 family"
select SUPPORTS_BIG_ENDIAN
@@ -188,6 +200,17 @@
ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
(miniPCIe).
+config BOARD_NETGEAR_DGND3700V2
+ bool "Netgear DGND3700v2"
+ depends on SOC_BMIPS_BCM6362
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and
+ 32 MB of flash (NAND).
+ Between its different peripherals there's a BCM53125 switch with 5
+ ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a
+ BCM43228 (miniPCIe).
+
config BOARD_SAGEM_FAST1704
bool "Sagem F@ST1704"
depends on SOC_BMIPS_BCM6338
@@ -235,6 +258,7 @@
source "board/comtrend/wap5813n/Kconfig"
source "board/huawei/hg556a/Kconfig"
source "board/netgear/cg3100d/Kconfig"
+source "board/netgear/dgnd3700v2/Kconfig"
source "board/sagem/f@st1704/Kconfig"
source "board/sfr/nb4_ser/Kconfig"
diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts
index 19dc36f..7832efb 100644
--- a/arch/nds32/dts/ag101p.dts
+++ b/arch/nds32/dts/ag101p.dts
@@ -67,5 +67,6 @@
fifo-depth = <0x10>;
reg = <0x98e00000 0x1000>;
interrupts = <5 4>;
+ cap-sd-highspeed;
};
};
diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
index b074e84..9d55c97 100644
--- a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
+++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
@@ -44,8 +44,6 @@
#define CONFIG_FTGPIO010_BASE 0xf0700000
/* I2C */
#define CONFIG_FTIIC010_BASE 0xf0a00000
-/* SD Controller */
-#define CONFIG_FTSDC010_BASE 0xf0e00000
/* The following address was not defined in Linux */
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
index 490f28b..0f4c3ef 100644
--- a/arch/nds32/include/asm/arch-ag101/ag101.h
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -69,8 +69,6 @@
#define CONFIG_RESERVED_04_BASE 0x98C00000
/* Compat Flash Controller */
#define CONFIG_FTCFC010_BASE 0x98D00000
-/* SD Controller */
-#define CONFIG_FTSDC010_BASE 0x98E00000
/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
#define CONFIG_FTSSP010_02_BASE 0x99400000
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
index c5ee3d9..a8aef93 100644
--- a/arch/nds32/include/asm/arch-ag102/ag102.h
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -56,8 +56,6 @@
#define CONFIG_FTSSP010_01_BASE 0x94100000
/* UART1 - APB STUART Controller (UART0 in Linux) */
#define CONFIG_FTUART010_01_BASE 0x94200000
-/* FTSDC010 SD Controller */
-#define CONFIG_FTSDC010_BASE 0x94400000
/* APB - SSP with HDA/AC97 Controller */
#define CONFIG_FTSSP010_02_BASE 0x94500000
/* UART2 - APB STUART Controller (UART1 in Linux) */
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index e4b3043..13a7956 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -30,9 +30,11 @@
select SYS_FSL_DDR_BE
imply CMD_REGINFO
-config 8xx
+config MPC8xx
bool "MPC8xx"
+ select BOARD_EARLY_INIT_F
imply CMD_REGINFO
+ imply MPC8xx_WATCHDOG
endchoice
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index e1fee11..3bdaa5f 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 5a7db33..b0e90a0 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -1,5 +1,5 @@
menu "mpc8xx CPU"
- depends on 8xx
+ depends on MPC8xx
config SYS_CPU
default "mpc8xx"
@@ -25,6 +25,10 @@
endchoice
+config MPC8xx_WATCHDOG
+ bool "Watchdog"
+ select HW_WATCHDOG
+
config 8xx_GCLK_FREQ
int "CPU GCLK Frequency"
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index 40f3892..35ff18a 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -12,6 +12,5 @@
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
-obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-y += speed.o
obj-y += cache.o
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 1120fd7..d17ad84 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -21,9 +21,9 @@
#include <watchdog.h>
#include <command.h>
#include <mpc8xx.h>
-#include <commproc.h>
#include <netdev.h>
#include <asm/cache.h>
+#include <asm/cpm_8xx.h>
#include <linux/compiler.h>
#include <asm/io.h>
@@ -36,13 +36,13 @@
static int check_CPU(long clock, uint pvr, uint immr)
{
- immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint k;
char buf[32];
/* the highest 16 bits should be 0x0050 for a 860 */
- if ((pvr >> 16) != 0x0050)
+ if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
return -1;
k = (immr << 16) |
@@ -90,7 +90,7 @@
int checkcpu(void)
{
ulong clock = gd->cpu_clk;
- uint immr = get_immr(0); /* Return full IMMR contents */
+ uint immr = get_immr(); /* Return full IMMR contents */
uint pvr = get_pvr();
puts("CPU: ");
@@ -237,8 +237,7 @@
*/
unsigned long get_tbclk(void)
{
- uint immr = get_immr(0); /* Return full IMMR contents */
- immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
ulong oscclk, factor, pll;
if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
@@ -271,31 +270,6 @@
return oscclk / 16;
}
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_WATCHDOG)
-void watchdog_reset(void)
-{
- int re_enable = disable_interrupts();
-
- reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
- if (re_enable)
- enable_interrupts();
-}
-#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_WATCHDOG)
-
-void reset_8xx_watchdog(immap_t __iomem *immr)
-{
- /*
- * All other boards use the MPC8xx Internal Watchdog
- */
- out_be16(&immr->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
- out_be16(&immr->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
-}
-#endif /* CONFIG_WATCHDOG */
-
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index dc601a1..99e8c85 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -9,7 +9,7 @@
#include <watchdog.h>
#include <mpc8xx.h>
-#include <commproc.h>
+#include <asm/cpm_8xx.h>
#include <asm/io.h>
/*
@@ -26,11 +26,12 @@
/* SYPCR - contains watchdog control (11-9) */
- out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
+#ifndef CONFIG_HW_WATCHDOG
+ /* deactivate watchdog if not enabled in config */
+ out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
+#endif
-#if defined(CONFIG_WATCHDOG)
- reset_8xx_watchdog(immr);
-#endif /* CONFIG_WATCHDOG */
+ WATCHDOG_RESET();
/* SIUMCR - contains debug pin configuration (11-6) */
setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
index 2284979..8e73255 100644
--- a/arch/powerpc/cpu/mpc8xx/immap.c
+++ b/arch/powerpc/cpu/mpc8xx/immap.c
@@ -12,8 +12,8 @@
#include <common.h>
#include <command.h>
-#include <asm/8xx_immap.h>
-#include <commproc.h>
+#include <asm/immap_8xx.h>
+#include <asm/cpm_8xx.h>
#include <asm/iopin_8xx.h>
#include <asm/io.h>
@@ -342,6 +342,26 @@
return 0;
}
+#ifdef CONFIG_CMD_REGINFO
+void print_reginfo(void)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ sit8xx_t __iomem *timers = &immap->im_sit;
+
+ printf("\nSystem Configuration registers\n"
+ "\tIMMR\t0x%08X\n", get_immr());
+ do_siuinfo(NULL, 0, 0, NULL);
+
+ printf("Memory Controller Registers\n");
+ do_memcinfo(NULL, 0, 0, NULL);
+
+ printf("\nSystem Integration Timers\n");
+ printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
+ in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
+ printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
+}
+#endif
+
/***************************************************/
U_BOOT_CMD(
diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c
index 846148a..20f9664 100644
--- a/arch/powerpc/cpu/mpc8xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc8xx/interrupts.c
@@ -8,9 +8,9 @@
#include <common.h>
#include <mpc8xx.h>
#include <mpc8xx_irq.h>
+#include <asm/cpm_8xx.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <commproc.h>
/************************************************************************/
diff --git a/arch/powerpc/cpu/mpc8xx/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c
deleted file mode 100644
index 277d275..0000000
--- a/arch/powerpc/cpu/mpc8xx/reginfo.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2000
- * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <asm/io.h>
-#include <asm/ppc.h>
-
-void print_reginfo(void)
-{
- immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
- memctl8xx_t __iomem *memctl = &immap->im_memctl;
- sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf;
- sit8xx_t __iomem *timers = &immap->im_sit;
-
- /* Hopefully more PowerPC knowledgable people will add code to display
- * other useful registers
- */
-
- printf("\nSystem Configuration registers\n"
- "\tIMMR\t0x%08X\n", get_immr(0));
-
- printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
- printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr));
-
- printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt));
- printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr));
-
- printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
- in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask));
- printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
- in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec));
- printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
- in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr));
-
- printf("Memory Controller Registers\n");
- printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0),
- in_be32(&memctl->memc_or0));
- printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1),
- in_be32(&memctl->memc_or1));
- printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2),
- in_be32(&memctl->memc_or2));
- printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3),
- in_be32(&memctl->memc_or3));
- printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4),
- in_be32(&memctl->memc_or4));
- printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5),
- in_be32(&memctl->memc_or5));
- printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6),
- in_be32(&memctl->memc_or6));
- printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7),
- in_be32(&memctl->memc_or7));
- printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr),
- in_be32(&memctl->memc_mbmr));
- printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat),
- in_be16(&memctl->memc_mptpr));
- printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr));
-
- printf("\nSystem Integration Timers\n");
- printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
- in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
- printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
-
- /*
- * May be some CPM info here?
- */
-}
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index fa8f87c..f8eb4a1 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -17,8 +17,7 @@
*/
int get_clocks(void)
{
- uint immr = get_immr(0); /* Return full IMMR contents */
- immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint sccr = in_be32(&immap->im_clkrst.car_sccr);
uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2);
diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index 202ea81..62ac80b 100644
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S
@@ -130,12 +130,6 @@
/* initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
- lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
- ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
- /* Note: R0 is still 0 here */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
-
/*
* Disable serialized ifetch and show cycles
* (i.e. set processor to normal mode).
@@ -151,6 +145,25 @@
ori r2, r2, CONFIG_SYS_DER@l
mtspr DER, r2
+ /* set up the stack in internal DPRAM */
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
+ addi r1, r3, -8
+
+ bl board_init_f_alloc_reserve
+ addi r1, r3, -8
+
+ /* Zeroise the CPM dpram */
+ lis r4, CONFIG_SYS_IMMR@h
+ ori r4, r4, (0x2000 - 4)
+ li r0, (0x2000 / 4)
+ mtctr r0
+ li r0, 0
+1: stwu r0, 4(r4)
+ bdnz 1b
+
+ bl board_init_f_init_reserve
+
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable ! */
@@ -158,7 +171,7 @@
GET_GOT /* initialize GOT access */
- /* r3: IMMR */
+ lis r3, CONFIG_SYS_IMMR@h
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f /* run 1st part of board init code (from Flash) */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 0801d2c..445a366 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -7,7 +7,7 @@
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
@@ -72,7 +72,7 @@
#define L2CACHE_NONE 0x03 /* NONE */
#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
-#ifdef CONFIG_8xx
+#ifdef CONFIG_MPC8xx
/* Cache control on the MPC8xx is provided through some additional
* special purpose registers.
*/
@@ -139,6 +139,6 @@
mtspr(DC_ADR, val);
}
#endif
-#endif /* CONFIG_8xx */
+#endif /* CONFIG_MPC8xx */
#endif
diff --git a/include/commproc.h b/arch/powerpc/include/asm/cpm_8xx.h
similarity index 98%
rename from include/commproc.h
rename to arch/powerpc/include/asm/cpm_8xx.h
index 9536b13..85903d2 100644
--- a/include/commproc.h
+++ b/arch/powerpc/include/asm/cpm_8xx.h
@@ -16,7 +16,7 @@
#ifndef __CPM_8XX__
#define __CPM_8XX__
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
/* CPM Command register.
*/
@@ -51,14 +51,14 @@
/*
* DPRAM defines and allocation functions
*/
-#define CPM_SERIAL_BASE 0x0800
-#define CPM_I2C_BASE 0x0820
-#define CPM_SPI_BASE 0x0840
-#define CPM_FEC_BASE 0x0860
-#define CPM_SERIAL2_BASE 0x08E0
-#define CPM_SCC_BASE 0x0900
-#define CPM_POST_BASE 0x0980
-#define CPM_WLKBD_BASE 0x0a00
+#define CPM_SERIAL_BASE 0x1800
+#define CPM_I2C_BASE 0x1820
+#define CPM_SPI_BASE 0x1840
+#define CPM_FEC_BASE 0x1860
+#define CPM_SERIAL2_BASE 0x18e0
+#define CPM_SCC_BASE 0x1900
+#define CPM_POST_BASE 0x1980
+#define CPM_WLKBD_BASE 0x1a00
#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 35a02b6..016dc19 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -19,7 +19,7 @@
u8 sdhc_adapter;
#endif
#endif
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
unsigned long brg_clk;
#endif
#if defined(CONFIG_CPM2)
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/immap_8xx.h
similarity index 100%
rename from arch/powerpc/include/asm/8xx_immap.h
rename to arch/powerpc/include/asm/immap_8xx.h
diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
index 15679a2..3b4e1b6 100644
--- a/arch/powerpc/include/asm/iopin_8xx.h
+++ b/arch/powerpc/include/asm/iopin_8xx.h
@@ -11,7 +11,7 @@
#define _ASM_IOPIN_8XX_H_
#include <linux/types.h>
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
#include <asm/io.h>
#ifdef __KERNEL__
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 5e0aa08..8e76c38 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -13,8 +13,8 @@
#ifndef __ASSEMBLY__
-#if defined(CONFIG_8xx)
-#include <asm/8xx_immap.h>
+#if defined(CONFIG_MPC8xx)
+#include <asm/immap_8xx.h>
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
@@ -40,14 +40,11 @@
#include <asm/processor.h>
-#if defined(CONFIG_8xx)
-static inline uint get_immr(uint mask)
+static inline uint get_immr(void)
{
- uint immr = mfspr(SPRN_IMMR);
-
- return mask ? (immr & mask) : immr;
+ return mfspr(SPRN_IMMR);
}
-#endif
+
static inline uint get_pvr(void)
{
return mfspr(PVR);
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 57b11b8..6fbe8c4 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -973,10 +973,8 @@
* differentiated by the version number in the Communication Processor
* Module (CPM).
*/
-#define PVR_821 0x00500000
-#define PVR_823 PVR_821
-#define PVR_850 PVR_821
-#define PVR_860 PVR_821
+#define PVR_8xx 0x00500000
+
#define PVR_7400 0x000C0000
/*
diff --git a/arch/powerpc/include/asm/xilinx_irq.h b/arch/powerpc/include/asm/xilinx_irq.h
deleted file mode 100644
index 5766bde..0000000
--- a/arch/powerpc/include/asm/xilinx_irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
- * SPDX-License-Identifier: GPL-2.0+
-*/
-#ifndef XILINX_IRQ_H
-#define XILINX_IRQ_H
-
-#define intc XPAR_INTC_0_BASEADDR
-#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
-#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
-#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
-#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
-#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
-#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
-#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
-#define MER (intc + (7 * 4)) /* Master Enable Register */
-
-#define IRQ_MASK(irq) (1 << (irq & 0x1f))
-
-#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
-
-#endif
diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S
index 6a07663..cd0a663 100644
--- a/arch/riscv/cpu/nx25/start.S
+++ b/arch/riscv/cpu/nx25/start.S
@@ -45,6 +45,8 @@
.global trap_entry
handle_reset:
+ li t0, CONFIG_SYS_SDRAM_BASE
+ SREG a2, 0(t0)
la t0, trap_entry
csrw mtvec, t0
csrwi mstatus, 0
diff --git a/arch/riscv/dts/ae250.dts b/arch/riscv/dts/ae250.dts
index 5dc4fb0..9a38345 100644
--- a/arch/riscv/dts/ae250.dts
+++ b/arch/riscv/dts/ae250.dts
@@ -74,6 +74,7 @@
fifo-depth = <0x10>;
reg = <0xf0e00000 0x1000>;
interrupts = <17 4>;
+ cap-sd-highspeed;
};
spi: spi@f0b00000 {
diff --git a/arch/riscv/include/asm/bootm.h b/arch/riscv/include/asm/bootm.h
index 0a644bb..9a90f23 100644
--- a/arch/riscv/include/asm/bootm.h
+++ b/arch/riscv/include/asm/bootm.h
@@ -13,53 +13,4 @@
#include <asm/setup.h>
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
-# define BOOTM_ENABLE_TAGS 1
-#else
-# define BOOTM_ENABLE_TAGS 0
-#endif
-
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-# define BOOTM_ENABLE_MEMORY_TAGS 1
-#else
-# define BOOTM_ENABLE_MEMORY_TAGS 0
-#endif
-
-#ifdef CONFIG_CMDLINE_TAG
- #define BOOTM_ENABLE_CMDLINE_TAG 1
-#else
- #define BOOTM_ENABLE_CMDLINE_TAG 0
-#endif
-
-#ifdef CONFIG_INITRD_TAG
- #define BOOTM_ENABLE_INITRD_TAG 1
-#else
- #define BOOTM_ENABLE_INITRD_TAG 0
-#endif
-
-#ifdef CONFIG_SERIAL_TAG
- #define BOOTM_ENABLE_SERIAL_TAG 1
-void get_board_serial(struct tag_serialnr *serialnr);
-#else
- #define BOOTM_ENABLE_SERIAL_TAG 0
-static inline void get_board_serial(struct tag_serialnr *serialnr)
-{
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
- #define BOOTM_ENABLE_REVISION_TAG 1
-u32 get_board_rev(void);
-#else
- #define BOOTM_ENABLE_REVISION_TAG 0
-static inline u32 get_board_rev(void)
-{
- return 0;
-}
-#endif
-
#endif
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index 5ff6d59..dbf8d45 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -121,7 +121,9 @@
#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
-#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
+#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
+ typeof(_PTE) (PTE) = (_PTE); \
+ typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
@@ -151,27 +153,31 @@
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
-#define write_csr(reg, val) ({ \
+#define write_csr(reg, _val) ({ \
+typeof(_val) (val) = (_val); \
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
else \
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
-#define swap_csr(reg, val) ({ unsigned long __tmp; \
+#define swap_csr(reg, _val) ({ unsigned long __tmp; \
+typeof(_val) (val) = (_val); \
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
else \
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
__tmp; })
-#define set_csr(reg, bit) ({ unsigned long __tmp; \
+#define set_csr(reg, _bit) ({ unsigned long __tmp; \
+typeof(_bit) (bit) = (_bit); \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; })
-#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
+typeof(_bit) (bit) = (_bit); \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 0cce98a..bd352c2 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -17,6 +17,6 @@
#include <asm-generic/global_data.h>
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("gp")
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index e7f63ed..1df6b1b 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -416,19 +416,17 @@
#define eth_io_copy_and_sum(s, c, l, b) \
eth_copy_and_sum((s), __mem_pci(c), (l), (b))
-static inline int
-check_signature(unsigned long io_addr, const unsigned char *signature,
- int length)
+static inline int check_signature(ulong io_addr, const uchar *s, int len)
{
int retval = 0;
do {
- if (readb(io_addr) != *signature)
+ if (readb(io_addr) != *s)
goto out;
io_addr++;
- signature++;
- length--;
- } while (length);
+ s++;
+ len--;
+ } while (len);
retval = 1;
out:
return retval;
@@ -455,18 +453,17 @@
eth_copy_and_sum((a), __mem_isa(b), (c), (d))
static inline int
-isa_check_signature(unsigned long io_addr, const unsigned char *signature,
- int length)
+isa_check_signature(ulong io_addr, const uchar *s, int len)
{
int retval = 0;
do {
- if (isa_readb(io_addr) != *signature)
+ if (isa_readb(io_addr) != *s)
goto out;
io_addr++;
- signature++;
- length--;
- } while (length);
+ s++;
+ len--;
+ } while (len);
retval = 1;
out:
return retval;
diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h
index 6892b66..7438dbe 100644
--- a/arch/riscv/include/asm/posix_types.h
+++ b/arch/riscv/include/asm/posix_types.h
@@ -69,19 +69,23 @@
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
-#define __FD_SET(fd, fdsetp) \
+#define __FD_SET(_fd, fdsetp) \
+ typeof(_fd) (fd) = (_fd); \
(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31)))
#undef __FD_CLR
-#define __FD_CLR(fd, fdsetp) \
+#define __FD_CLR(_fd, fdsetp) \
+ typeof(_fd) (fd) = (_fd); \
(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31)))
#undef __FD_ISSET
-#define __FD_ISSET(fd, fdsetp) \
+#define __FD_ISSET(_fd, fdsetp) \
+ typeof(_fd) (fd) = (_fd); \
((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0)
#undef __FD_ZERO
-#define __FD_ZERO(fdsetp) \
+#define __FD_ZERO(_fdsetp) \
+ typeof(_fdsetp) (fd) = (_fdsetp); \
(memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
#endif
diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
index 76d6869..651078f 100644
--- a/arch/riscv/include/asm/ptrace.h
+++ b/arch/riscv/include/asm/ptrace.h
@@ -65,8 +65,7 @@
return GET_IP(regs);
}
-static inline void instruction_pointer_set(struct pt_regs *regs,
- unsigned long val)
+static inline void instruction_pointer_set(struct pt_regs *regs, ulong val)
{
SET_IP(regs, val);
}
@@ -82,8 +81,7 @@
return GET_USP(regs);
}
-static inline void user_stack_pointer_set(struct pt_regs *regs,
- unsigned long val)
+static inline void user_stack_pointer_set(struct pt_regs *regs, ulong val)
{
SET_USP(regs, val);
}
@@ -97,8 +95,7 @@
return GET_FP(regs);
}
-static inline void frame_pointer_set(struct pt_regs *regs,
- unsigned long val)
+static inline void frame_pointer_set(struct pt_regs *regs, ulong val)
{
SET_FP(regs, val);
}
diff --git a/arch/riscv/include/asm/setup.h b/arch/riscv/include/asm/setup.h
index 731b0d9..4b18243 100644
--- a/arch/riscv/include/asm/setup.h
+++ b/arch/riscv/include/asm/setup.h
@@ -145,14 +145,18 @@
int (*parse)(const struct tag *);
};
-#define tag_member_present(tag, member) \
+#define tag_member_present(_tag, member) \
+ typeof(_tag) (tag) = (_tag); \
((unsigned long)(&((struct tag *)0L)->member + 1) \
<= (tag)->hdr.size * 4)
-#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_next(_t) \
+ typeof(_t) (t) = (_t); \
+ ((struct tag *)((u32 *)(t) + (t)->hdr.size))
#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
-#define for_each_tag(t, base) \
+#define for_each_tag(_t, base) \
+ typeof(_t) (t) = (_t); \
for (t = base; t->hdr.size; t = tag_next(t))
#ifdef __KERNEL__
diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
index 038cdae..0fc3424 100644
--- a/arch/riscv/include/asm/string.h
+++ b/arch/riscv/include/asm/string.h
@@ -26,8 +26,11 @@
#undef __HAVE_ARCH_MEMSET
#ifdef CONFIG_MARCO_MEMSET
-#define memset(p, v, n) \
- ({ \
+#define memset(_p, _v, _n) \
+ (typeof(_p) (p) = (_p); \
+ typeof(_v) (v) = (_v); \
+ typeof(_n) (n) = (_n); \
+ { \
if ((n) != 0) { \
if (__builtin_constant_p((v)) && (v) == 0) \
__memzero((p), (n)); \
@@ -37,7 +40,10 @@
(p); \
})
-#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#define memzero(_p, _n) \
+ (typeof(_p) (p) = (_p); \
+ typeof(_n) (n) = (_n); \
+ { if ((n) != 0) __memzero((p), (n)); (p); })
#endif
#endif /* __ASM_RISCV_STRING_H */
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 44ce38b..9242fa8 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -21,36 +21,12 @@
return 0;
}
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
-static void setup_start_tag(bd_t *bd);
-
-# ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags(bd_t *bd);
-# endif
-static void setup_commandline_tag(bd_t *bd, char *commandline);
-
-# ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
-# endif
-static void setup_end_tag(bd_t *bd);
-
-static struct tag *params;
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
-
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
bd_t *bd = gd->bd;
char *s;
int machid = bd->bi_arch_number;
- void (*theKernel)(int zero, int arch, uint params);
-
-#ifdef CONFIG_CMDLINE_TAG
- char *commandline = env_get("bootargs");
-#endif
+ void (*theKernel)(int arch, uint params);
/*
* allow the PREP bootm subcommand, it is required for bootm to work
@@ -61,7 +37,7 @@
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
- theKernel = (void (*)(int, int, uint))images->ep;
+ theKernel = (void (*)(int, uint))images->ep;
s = env_get("machid");
if (s) {
@@ -82,167 +58,16 @@
hang();
}
#endif
- } else if (BOOTM_ENABLE_TAGS) {
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
- setup_start_tag(bd);
-#ifdef CONFIG_SERIAL_TAG
- setup_serial_tag(¶ms);
-#endif
-#ifdef CONFIG_REVISION_TAG
- setup_revision_tag(¶ms);
-#endif
-#ifdef CONFIG_SETUP_MEMORY_TAGS
- setup_memory_tags(bd);
-#endif
-#ifdef CONFIG_CMDLINE_TAG
- setup_commandline_tag(bd, commandline);
-#endif
-#ifdef CONFIG_INITRD_TAG
- if (images->rd_start && images->rd_end)
- setup_initrd_tag(bd, images->rd_start, images->rd_end);
-#endif
- setup_end_tag(bd);
-#endif
+ }
/* we assume that the kernel is in place */
printf("\nStarting kernel ...\n\n");
-#ifdef CONFIG_USB_DEVICE
- {
- extern void udc_disconnect(void);
- udc_disconnect();
- }
-#endif
- }
cleanup_before_linux();
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
- theKernel(0, machid, (unsigned long)images->ft_addr);
- else
- theKernel(0, machid, bd->bi_boot_params);
+ theKernel(machid, (unsigned long)images->ft_addr);
+
/* does not return */
return 1;
}
-
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
-static void setup_start_tag(bd_t *bd)
-{
- params = (struct tag *)bd->bi_boot_params;
-
- params->hdr.tag = ATAG_CORE;
- params->hdr.size = tag_size(tag_core);
-
- params->u.core.flags = 0;
- params->u.core.pagesize = 0;
- params->u.core.rootdev = 0;
-
- params = tag_next(params);
-}
-
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags(bd_t *bd)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- params->hdr.tag = ATAG_MEM;
- params->hdr.size = tag_size(tag_mem32);
-
- params->u.mem.start = bd->bi_dram[i].start;
- params->u.mem.size = bd->bi_dram[i].size;
-
- params = tag_next(params);
- }
-}
-#endif /* CONFIG_SETUP_MEMORY_TAGS */
-
-static void setup_commandline_tag(bd_t *bd, char *commandline)
-{
- char *p;
-
- if (!commandline)
- return;
-
- /* eat leading white space */
- for (p = commandline; *p == ' '; p++)
- ;
-
- /* skip non-existent command lines so the kernel will still
- * use its default command line.
- */
- if (*p == '\0')
- return;
-
- params->hdr.tag = ATAG_CMDLINE;
- params->hdr.size =
- (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
-
- strcpy(params->u.cmdline.cmdline, p)
- ;
-
- params = tag_next(params);
-}
-
-#ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
-{
- /* an ATAG_INITRD node tells the kernel where the compressed
- * ramdisk can be found. ATAG_RDIMG is a better name, actually.
- */
- params->hdr.tag = ATAG_INITRD2;
- params->hdr.size = tag_size(tag_initrd);
-
- params->u.initrd.start = initrd_start;
- params->u.initrd.size = initrd_end - initrd_start;
-
- params = tag_next(params);
-}
-#endif /* CONFIG_INITRD_TAG */
-
-#ifdef CONFIG_SERIAL_TAG
-void setup_serial_tag(struct tag **tmp)
-{
- struct tag *params;
- struct tag_serialnr serialnr;
- void get_board_serial(struct tag_serialnr *serialnr);
-
- params = *tmp;
- get_board_serial(&serialnr);
- params->hdr.tag = ATAG_SERIAL;
- params->hdr.size = tag_size(tag_serialnr);
- params->u.serialnr.low = serialnr.low;
- params->u.serialnr.high = serialnr.high;
- params = tag_next(params);
- *tmp = params;
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-void setup_revision_tag(struct tag **in_params)
-{
- u32 rev;
- u32 get_board_rev(void);
-
- rev = get_board_rev();
- params->hdr.tag = ATAG_REVISION;
- params->hdr.size = tag_size(tag_revision);
- params->u.revision.rev = rev;
- params = tag_next(params);
-}
-#endif /* CONFIG_REVISION_TAG */
-
-static void setup_end_tag(bd_t *bd)
-{
- params->hdr.tag = ATAG_NONE;
- params->hdr.size = 0;
-}
-
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 075db8b..923f752 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -63,7 +63,7 @@
static void _exit_trap(int code, uint epc, struct pt_regs *regs)
{
- static const char *exception_code[] = {
+ static const char * const exception_code[] = {
"Instruction address misaligned",
"Instruction access fault",
"Illegal instruction",
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index b0f0ca8..06d0e8c 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -27,6 +27,10 @@
testfdt3 = "/b-test";
testfdt5 = "/some-bus/c-test@5";
testfdt8 = "/a-test";
+ fdt_dummy0 = "/translation-test@8000/dev@0,0";
+ fdt_dummy1 = "/translation-test@8000/dev@1,100";
+ fdt_dummy2 = "/translation-test@8000/dev@2,200";
+ fdt_dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
usb0 = &usb_0;
usb1 = &usb_1;
usb2 = &usb_2;
@@ -487,6 +491,50 @@
reg = <9 1>;
};
};
+
+ translation-test@8000 {
+ compatible = "simple-bus";
+ reg = <0x8000 0x4000>;
+
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+
+ ranges = <0 0x0 0x8000 0x1000
+ 1 0x100 0x9000 0x1000
+ 2 0x200 0xA000 0x1000
+ 3 0x300 0xB000 0x1000
+ >;
+
+ dev@0,0 {
+ compatible = "denx,u-boot-fdt-dummy";
+ reg = <0 0x0 0x1000>;
+ };
+
+ dev@1,100 {
+ compatible = "denx,u-boot-fdt-dummy";
+ reg = <1 0x100 0x1000>;
+
+ };
+
+ dev@2,200 {
+ compatible = "denx,u-boot-fdt-dummy";
+ reg = <2 0x200 0x1000>;
+ };
+
+
+ noxlatebus@3,300 {
+ compatible = "simple-bus";
+ reg = <3 0x300 0x1000>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ dev@42 {
+ compatible = "denx,u-boot-fdt-dummy";
+ reg = <0x42>;
+ };
+ };
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index 9dc6c81..01b5ba4 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -64,6 +64,14 @@
*/
int sandbox_clk_test_get(struct udevice *dev);
/**
+ * sandbox_clk_test_get_bulk - Ask the sandbox clock test device to request its
+ * clocks with the bulk clk API.
+ *
+ * @dev: The sandbox clock test (client) devivce.
+ * @return: 0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_get_bulk(struct udevice *dev);
+/**
* sandbox_clk_test_get_rate - Ask the sandbox clock test device to query a
* clock's rate.
*
@@ -91,6 +99,14 @@
*/
int sandbox_clk_test_enable(struct udevice *dev, int id);
/**
+ * sandbox_clk_test_enable_bulk - Ask the sandbox clock test device to enable
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev: The sandbox clock test (client) devivce.
+ * @return: 0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_enable_bulk(struct udevice *dev);
+/**
* sandbox_clk_test_disable - Ask the sandbox clock test device to disable a
* clock.
*
@@ -100,6 +116,14 @@
*/
int sandbox_clk_test_disable(struct udevice *dev, int id);
/**
+ * sandbox_clk_test_disable_bulk - Ask the sandbox clock test device to disable
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev: The sandbox clock test (client) devivce.
+ * @return: 0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_disable_bulk(struct udevice *dev);
+/**
* sandbox_clk_test_free - Ask the sandbox clock test device to free its
* clocks.
*
@@ -107,5 +131,13 @@
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_free(struct udevice *dev);
+/**
+ * sandbox_clk_test_release_bulk - Ask the sandbox clock test device to release
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev: The sandbox clock test (client) devivce.
+ * @return: 0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_release_bulk(struct udevice *dev);
#endif
diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h
index 7146aa5..0cd7702 100644
--- a/arch/sandbox/include/asm/reset.h
+++ b/arch/sandbox/include/asm/reset.h
@@ -14,8 +14,12 @@
int sandbox_reset_query(struct udevice *dev, unsigned long id);
int sandbox_reset_test_get(struct udevice *dev);
+int sandbox_reset_test_get_bulk(struct udevice *dev);
int sandbox_reset_test_assert(struct udevice *dev);
+int sandbox_reset_test_assert_bulk(struct udevice *dev);
int sandbox_reset_test_deassert(struct udevice *dev);
+int sandbox_reset_test_deassert_bulk(struct udevice *dev);
int sandbox_reset_test_free(struct udevice *dev);
+int sandbox_reset_test_release_bulk(struct udevice *dev);
#endif
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 472ada5..69074f4 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -94,12 +94,16 @@
EFI_LDS := elf_x86_64_efi.lds
EFI_CRT0 := crt0_x86_64_efi.o
EFI_RELOC := reloc_x86_64_efi.o
-EFI_TARGET := --target=efi-app-ia32
else
EFI_LDS := elf_ia32_efi.lds
EFI_CRT0 := crt0_ia32_efi.o
EFI_RELOC := reloc_ia32_efi.o
+endif
+
+ifdef CONFIG_X86_64
EFI_TARGET := --target=efi-app-x86_64
+else
+EFI_TARGET := --target=efi-app-ia32
endif
endif
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index 90768a9..6aba614 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -10,8 +10,11 @@
#include <asm/video/edid.h>
/* setup data types */
-#define SETUP_NONE 0
-#define SETUP_E820_EXT 1
+enum {
+ SETUP_NONE = 0,
+ SETUP_E820_EXT,
+ SETUP_DTB,
+};
/* extensible setup data list node */
struct setup_data {
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 832a5d7..7c32245 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -6,7 +6,6 @@
#include <common.h>
#include <debug_uart.h>
-#include <init_helpers.h>
#include <spl.h>
#include <asm/cpu.h>
#include <asm/mtrr.h>
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 2a82bc8..6af1bf4 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -14,6 +14,7 @@
*/
#include <common.h>
+#include <malloc.h>
#include <asm/acpi_table.h>
#include <asm/io.h>
#include <asm/ptrace.h>
@@ -25,6 +26,7 @@
#include <asm/arch/timestamp.h>
#endif
#include <linux/compiler.h>
+#include <linux/libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -95,6 +97,38 @@
}
}
+static int setup_device_tree(struct setup_header *hdr, const void *fdt_blob)
+{
+ int bootproto = get_boot_protocol(hdr);
+ struct setup_data *sd;
+ int size;
+
+ if (bootproto < 0x0209)
+ return -ENOTSUPP;
+
+ if (!fdt_blob)
+ return 0;
+
+ size = fdt_totalsize(fdt_blob);
+ if (size < 0)
+ return -EINVAL;
+
+ size += sizeof(struct setup_data);
+ sd = (struct setup_data *)malloc(size);
+ if (!sd) {
+ printf("Not enough memory for DTB setup data\n");
+ return -ENOMEM;
+ }
+
+ sd->next = hdr->setup_data;
+ sd->type = SETUP_DTB;
+ sd->len = fdt_totalsize(fdt_blob);
+ memcpy(sd->data, fdt_blob, sd->len);
+ hdr->setup_data = (unsigned long)sd;
+
+ return 0;
+}
+
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
ulong *load_addressp)
{
@@ -261,6 +295,7 @@
hdr->acpi_rsdp_addr = acpi_get_rsdp_addr();
#endif
+ setup_device_tree(hdr, (const void *)env_get_hex("fdtaddr", 0));
setup_video(&setup_base->screen_info);
return 0;
diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
index 8cffb6b..52a89dc 100644
--- a/board/AndesTech/adp-ae3xx/adp-ae3xx.c
+++ b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
@@ -12,7 +12,6 @@
#include <netdev.h>
#endif
#include <linux/io.h>
-#include <faraday/ftsdc010.h>
#include <faraday/ftsmc020.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -75,13 +74,3 @@
return 0;
}
}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_FTSDC010
- ftsdc010_mmc_init(0);
-#endif
-#endif
- return 0;
-}
diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c
index f918c63..82928e7 100644
--- a/board/AndesTech/adp-ag101p/adp-ag101p.c
+++ b/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -14,7 +14,6 @@
#include <asm/io.h>
#include <asm/mach-types.h>
-#include <faraday/ftsdc010.h>
#include <faraday/ftsmc020.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -82,13 +81,3 @@
return 0;
}
}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_FTSDC010
- ftsdc010_mmc_init(0);
-#endif
-#endif
- return 0;
-}
diff --git a/board/AndesTech/nx25-ae250/nx25-ae250.c b/board/AndesTech/nx25-ae250/nx25-ae250.c
index 12f2d35..6e31be3 100644
--- a/board/AndesTech/nx25-ae250/nx25-ae250.c
+++ b/board/AndesTech/nx25-ae250/nx25-ae250.c
@@ -11,7 +11,6 @@
#include <netdev.h>
#endif
#include <linux/io.h>
-#include <faraday/ftsdc010.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,12 +65,11 @@
return 0;
}
-int board_mmc_init(bd_t *bis)
+void *board_fdt_blob_setup(void)
{
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_FTSDC010
- ftsdc010_mmc_init(0);
-#endif
-#endif
- return 0;
+ void **ptr = (void *)CONFIG_SYS_SDRAM_BASE;
+ if (fdt_magic(*ptr) == FDT_MAGIC)
+ return (void *)*ptr;
+
+ return (void *)CONFIG_SYS_FDT_BASE;
}
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index d82b8cd..f0a97fa 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -11,6 +11,7 @@
*/
#include <version.h>
#include <common.h>
+#include <environment.h>
#include <errno.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index b03c0a3..c693aae 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index f639a37..3e070d2 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <command.h>
+#include <environment.h>
#include <i2c.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
index 52f3664..3bd9fa9 100644
--- a/board/LaCie/netspace_v2/netspace_v2.c
+++ b/board/LaCie/netspace_v2/netspace_v2.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <command.h>
+#include <environment.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index ac3e3a3..e205396 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -50,29 +50,6 @@
int board_early_init_f(void)
{
- const void *blob = gd->fdt_blob;
- const char *bank_name;
- const char *compat = "marvell,armada-3700-pinctl";
- int off, len;
- void __iomem *addr;
-
- /* FIXME
- * Temporary WA for setting correct pin control values
- * until the real pin control driver is awailable.
- */
- off = fdt_node_offset_by_compatible(blob, -1, compat);
- while (off != -FDT_ERR_NOTFOUND) {
- bank_name = fdt_getprop(blob, off, "bank-name", &len);
- addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
- blob, off, "reg", 0, NULL, true);
- if (!strncmp(bank_name, "armada-3700-nb", len))
- writel(PINCTRL_NB_REG_VALUE, addr);
- else if (!strncmp(bank_name, "armada-3700-sb", len))
- writel(PINCTRL_SB_REG_VALUE, addr);
-
- off = fdt_node_offset_by_compatible(blob, off, compat);
- }
-
return 0;
}
diff --git a/board/amarula/vyasa-rk3288/MAINTAINERS b/board/amarula/vyasa-rk3288/MAINTAINERS
index 10397fc..08ea208 100644
--- a/board/amarula/vyasa-rk3288/MAINTAINERS
+++ b/board/amarula/vyasa-rk3288/MAINTAINERS
@@ -4,3 +4,5 @@
F: board/amarula/vyasa-rk3288
F: include/configs/vyasa-rk3288.h
F: configs/vyasa-rk3288_defconfig
+F: arch/arm/dts/rk3288-vyasa.dts
+F: arch/arm/dts/rk3288-vyasa-u-boot.dtsi
diff --git a/board/amarula/vyasa-rk3288/vyasa-rk3288.c b/board/amarula/vyasa-rk3288/vyasa-rk3288.c
index 7985671..82f8c4e 100644
--- a/board/amarula/vyasa-rk3288/vyasa-rk3288.c
+++ b/board/amarula/vyasa-rk3288/vyasa-rk3288.c
@@ -9,6 +9,13 @@
#ifndef CONFIG_TPL_BUILD
#include <spl.h>
+void board_boot_order(u32 *spl_boot_list)
+{
+ /* eMMC prior to sdcard. */
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c
index 5e19856..83b1b6e 100644
--- a/board/amlogic/khadas-vim/khadas-vim.c
+++ b/board/amlogic/khadas-vim/khadas-vim.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/mem.h>
diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c
index 6be6e2a..5795340 100644
--- a/board/amlogic/libretech-cc/libretech-cc.c
+++ b/board/amlogic/libretech-cc/libretech-cc.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index 0cb5714..8645f22 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 5fde534..7c0abbc 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
diff --git a/board/aries/ma5d4evk/ma5d4evk.c b/board/aries/ma5d4evk/ma5d4evk.c
index 956c297..9f8b8dc 100644
--- a/board/aries/ma5d4evk/ma5d4evk.c
+++ b/board/aries/ma5d4evk/ma5d4evk.c
@@ -30,7 +30,8 @@
static u8 boot_mode_sf;
-#ifdef CONFIG_ATMEL_SPI
+/* FIXME gpio code here need to handle through DM_GPIO */
+#ifndef CONFIG_DM_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
@@ -57,7 +58,7 @@
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_SPI0);
}
-#endif /* CONFIG_ATMEL_SPI */
+#endif /* CONFIG_DM_SPI */
#ifdef CONFIG_CMD_USB
static void ma5d4evk_usb_hw_init(void)
@@ -292,7 +293,7 @@
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifdef CONFIG_ATMEL_SPI
+#ifndef CONFIG_DM_SPI
ma5d4evk_spi0_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
@@ -358,7 +359,7 @@
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#ifdef CONFIG_ATMEL_SPI
+#ifndef CONFIG_DM_SPI
ma5d4evk_spi0_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c
index b143e04..9cd0ec8 100644
--- a/board/armltd/vexpress/vexpress_tc2.c
+++ b/board/armltd/vexpress/vexpress_tc2.c
@@ -18,7 +18,7 @@
bool armv7_boot_nonsec_default(void)
{
#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT
- return false
+ return false;
#else
/*
* The Serial Configuration Controller (SCC) register at address 0x700
diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c
index 60ddf00..91b86e0 100644
--- a/board/atmel/common/mac_eeprom.c
+++ b/board/atmel/common/mac_eeprom.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <i2c_eeprom.h>
#include <netdev.h>
diff --git a/board/birdland/bav335x/Kconfig b/board/birdland/bav335x/Kconfig
index 3380ed3..4005366 100644
--- a/board/birdland/bav335x/Kconfig
+++ b/board/birdland/bav335x/Kconfig
@@ -12,16 +12,6 @@
config SYS_CONFIG_NAME
default "bav335x"
-config CONS_INDEX
- int "UART used for console"
- range 1 6
- default 1
- help
- The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
- in documentation, etc) available to it. Depending on your specific
- board you may want something other than UART0 as for example the IDK
- uses UART3 so enter 4 here.
-
config BAV_VERSION
int "BAV335x Version (1=A, 2=B)"
range 1 2
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index 8733a9a..d8e92b1 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c
@@ -18,7 +18,6 @@
#ifndef CONFIG_DM_ETH
#include <netdev.h>
#endif
-#include <spi.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-types.h>
@@ -415,25 +414,6 @@
{
}
-/* SPI chip select control - only used for FPGA programming */
-#ifdef CONFIG_ATMEL_SPI
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* We don't use chipselects for FPGA programming */
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* We don't use chipselects for FPGA programming */
-}
-#endif /* CONFIG_ATMEL_SPI */
-
static struct atmel_serial_platdata at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index 2d01ac2..8ae4207 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <net.h>
#include <malloc.h>
#include <netdev.h>
diff --git a/board/compulab/cl-som-am57x/eth.c b/board/compulab/cl-som-am57x/eth.c
index b615fb9..9f9525e 100644
--- a/board/compulab/cl-som-am57x/eth.c
+++ b/board/compulab/cl-som-am57x/eth.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <cpsw.h>
+#include <environment.h>
#include <miiphy.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c
index f8b1cda..dfa81f5 100644
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <mmc.h>
#include <phy.h>
#include <netdev.h>
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 673de03..c72efc5 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -12,6 +12,7 @@
#include <ahci.h>
#include <dm.h>
#include <dwc_ahsata.h>
+#include <environment.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <mtd_node.h>
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
index 6f6ba49..6eabd38 100644
--- a/board/compulab/cm_t335/cm_t335.c
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <errno.h>
#include <miiphy.h>
#include <cpsw.h>
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index d5cfba4..e8f604f 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <status_led.h>
#include <netdev.h>
#include <net.h>
diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c
index 0ff49dc..e4e3460 100644
--- a/board/compulab/cm_t3517/cm_t3517.c
+++ b/board/compulab/cm_t3517/cm_t3517.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <status_led.h>
#include <net.h>
#include <netdev.h>
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index 3e6235a..a1aeafb 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <fdt_support.h>
#include <usb.h>
#include <mmc.h>
diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c
index c928881..6939a2c 100644
--- a/board/cssi/MCR3000/MCR3000.c
+++ b/board/cssi/MCR3000/MCR3000.c
@@ -16,6 +16,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
+
static const uint cs1_dram_table_66[] = {
/* DRAM - single read. (offset 0 in upm RAM) */
0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
diff --git a/board/cssi/MCR3000/nand.c b/board/cssi/MCR3000/nand.c
index 8e5b0d0..4c6fc86 100644
--- a/board/cssi/MCR3000/nand.c
+++ b/board/cssi/MCR3000/nand.c
@@ -17,7 +17,7 @@
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
unsigned short pddat = 0;
diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds
index cd042ca..990cca4 100644
--- a/board/cssi/MCR3000/u-boot.lds
+++ b/board/cssi/MCR3000/u-boot.lds
@@ -18,14 +18,14 @@
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
arch/powerpc/lib/built-in.o (.text*)
board/cssi/MCR3000/built-in.o (.text*)
- disk/built-in.o (.text*)
drivers/net/built-in.o (.text*)
+ . = DEFINED(env_offset) ? env_offset : .;
+ env/embedded.o (.text.environment)
+
*(.text)
}
_etext = .;
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 83c9f29..37a0d72 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index b00d0e4..1d8b831 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -19,6 +19,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
+#include <environment.h>
#include <errno.h>
#include <fsl_esdhc.h>
#include <fuse.h>
diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig
index 6217a8f..f28ba6e 100644
--- a/board/eets/pdu001/Kconfig
+++ b/board/eets/pdu001/Kconfig
@@ -17,22 +17,6 @@
config SYS_CONFIG_NAME
default "pdu001"
-config CONS_INDEX
- int "UART used for console"
- range 1 6
- default 4
- help
- The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
- in documentation, etc) available to it. The best choice for the
- PDU001 is UART3 as it is wired to the header K2; enter 4 here to
- use UART3. UART0 is connected to the EIA-485 transceiver. If you
- really need to use it, you are advised to remove the transceiver U14
- from the board. UART1 is wired to the backplane and therefore
- accessible from there or by the backplane connector K1 of the PDU.
- Any other UART then UART3 (enter 4 here), UART1 (enter 2 here) or
- UART0 (enter 1 here) are not sensible since they are not wired to
- any connector and therefore difficult to access.
-
choice
prompt "State of Run LED"
default PDU001_RUN_LED_RED
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 38bd91b..22d521b 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,6 +12,35 @@
config SYS_CONFIG_NAME
default "ls1012afrdm"
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select PHYLIB
+ imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x1
+
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
index dbfa2ce..1e53c96 100644
--- a/board/freescale/ls1012afrdm/Makefile
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1012afrdm.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
new file mode 100644
index 0000000..cc6deb2
--- /dev/null
+++ b/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST 0x00000100
+
+static inline void ls1012afrdm_reset_phy(void)
+{
+ unsigned int val;
+ struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+ setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
+
+ val = in_be32(&pgpio->gpdat);
+ setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
+ mdelay(10);
+
+ val = in_be32(&pgpio->gpdat);
+ setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
+ mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+ static int init_done;
+ struct mii_dev *bus;
+ struct pfe_mdio_info mac_mdio_info;
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ if (!init_done) {
+ ls1012afrdm_reset_phy();
+
+ mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+
+ init_done = 1;
+ }
+
+ if (priv->gemac_port) {
+ mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ }
+
+ pfe_set_mdio(priv->gemac_port,
+ miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+ if (!priv->gemac_port)
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ else
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ .phy_interface = 0,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+ .phy_interface = 1,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata1,
+};
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 9afd1c4..0145886 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -57,11 +57,6 @@
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index fc9250b..c0b12ed 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,6 +12,51 @@
config SYS_CONFIG_NAME
default "ls1012aqds"
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select PHYLIB
+ imply PHY_VITESSE
+ imply PHY_REALTEK
+ imply PHY_AQUANTIA
+ imply PHYLIB_10G
+
+config PFE_RGMII_RESET_WA
+ def_bool y
+
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x1e
+
+config PFE_EMAC2_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x1
+
+config PFE_SGMII_2500_PHY1_ADDR
+ hex "PFE DDR base address"
+ default 0x1
+
+config PFE_SGMII_2500_PHY2_ADDR
+ hex "PFE DDR base address"
+ default 0x2
+
+endif
+
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
index 0b813f9..5aba9ca 100644
--- a/board/freescale/ls1012aqds/Makefile
+++ b/board/freescale/ls1012aqds/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1012aqds.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
new file mode 100644
index 0000000..f8026a2
--- /dev/null
+++ b/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include "../common/qixis.h"
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include "ls1012aqds_qixis.h"
+
+#define EMI_NONE 0xFF
+#define EMI1_RGMII 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+static const char * const mdio_names[] = {
+ "NULL",
+ "LS1012AQDS_MDIO_RGMII",
+ "LS1012AQDS_MDIO_SLOT1",
+ "LS1012AQDS_MDIO_SLOT2",
+ "NULL",
+};
+
+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct ls1012aqds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void ls1012aqds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct ls1012aqds_mdio *priv = bus->priv;
+
+ ls1012aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls1012aqds_mdio *priv = bus->priv;
+
+ ls1012aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls1012aqds_mdio *priv = bus->priv;
+
+ if (priv->realbus->reset)
+ return priv->realbus->reset(priv->realbus);
+ else
+ return -1;
+}
+
+static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct ls1012aqds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate ls1012aqds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate ls1012aqds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls1012aqds_mdio_read;
+ bus->write = ls1012aqds_mdio_write;
+ bus->reset = ls1012aqds_mdio_reset;
+ sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+ static int init_done;
+ struct mii_dev *bus;
+ static const char *mdio_name;
+ struct pfe_mdio_info mac_mdio_info;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u8 data8;
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ ls1012aqds_mux_mdio(EMI1_SLOT1);
+
+ if (!init_done) {
+ mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ init_done = 1;
+ }
+
+ if (priv->gemac_port) {
+ mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ }
+
+ switch (srds_s1) {
+ case 0x3508:
+ printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+#ifdef CONFIG_PFE_RGMII_RESET_WA
+ /*
+ * Work around for FPGA registers initialization
+ * This is needed for RGMII to work.
+ */
+ printf("Reset RGMII WA....\n");
+ data8 = QIXIS_READ(rst_frc[0]);
+ data8 |= 0x2;
+ QIXIS_WRITE(rst_frc[0], data8);
+ data8 = QIXIS_READ(rst_frc[0]);
+
+ data8 = QIXIS_READ(res8[6]);
+ data8 |= 0xff;
+ QIXIS_WRITE(res8[6], data8);
+ data8 = QIXIS_READ(res8[6]);
+#endif
+ if (priv->gemac_port) {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+
+ /* MAC2 */
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(priv->gemac_port, bus);
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_RGMII);
+
+ } else {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+
+ /* MAC1 */
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(priv->gemac_port, bus);
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ }
+
+ break;
+
+ case 0x2205:
+ printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+ /*
+ * Work around for FPGA registers initialization
+ * This is needed for RGMII to work.
+ */
+ printf("Reset SLOT1 SLOT2....\n");
+ data8 = QIXIS_READ(rst_frc[2]);
+ data8 |= 0xc0;
+ QIXIS_WRITE(rst_frc[2], data8);
+ mdelay(100);
+ data8 = QIXIS_READ(rst_frc[2]);
+ data8 &= 0x3f;
+ QIXIS_WRITE(rst_frc[2], data8);
+
+ if (priv->gemac_port) {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+ /* MAC2 */
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(1, bus);
+ pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+
+ data8 = QIXIS_READ(brdcfg[12]);
+ data8 |= 0x20;
+ QIXIS_WRITE(brdcfg[12], data8);
+
+ } else {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+
+ /* MAC1 */
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(0, bus);
+ pfe_set_phy_address_mode(0,
+ CONFIG_PFE_SGMII_2500_PHY1_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ }
+ break;
+
+ default:
+ printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
+ break;
+ }
+ return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ .phy_interface = 0,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+ .phy_interface = 1,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata1,
+};
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 406194d..4577917 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -25,9 +25,9 @@
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
+#include "ls1012aqds_pfe.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -128,11 +128,6 @@
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc0_path[] = "/soc/esdhc@1560000";
@@ -161,12 +156,102 @@
return 0;
}
+static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
+ char *enet_path, char *mdio_path)
+{
+ do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
+ &prop_val.busid, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
+ &prop_val.phyid, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
+ &prop_val.mux_val, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "phy-mode",
+ prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
+ do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
+ &prop_val.phy_mask, PFE_PROP_LEN, 1);
+ return 0;
+}
+
+static void fdt_fsl_fixup_of_pfe(void *blob)
+{
+ int i = 0;
+ struct pfe_prop_val prop_val;
+ void *l_blob = blob;
+
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ for (i = 0; i < NUM_ETH_NODE; i++) {
+ switch (srds_s1) {
+ case SERDES_1_G_PROTOCOL:
+ if (i == 0) {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_1_1G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_1_1G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_1_1G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_1G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii";
+ pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+ ETH_1_MDIO);
+ } else {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_2_1G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_2_1G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_2_1G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_1G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "rgmii";
+ pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+ ETH_2_MDIO);
+ }
+ break;
+ case SERDES_2_5_G_PROTOCOL:
+ if (i == 0) {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_1_2_5G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_1_2_5G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_1_2_5G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_2_5G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii-2500";
+ pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+ ETH_1_MDIO);
+ } else {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_2_2_5G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_2_2_5G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_2_2_5G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_2_5G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii-2500";
+ pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+ ETH_2_MDIO);
+ }
+ break;
+ default:
+ printf("serdes:[%d]\n", srds_s1);
+ }
+ }
+}
+
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
arch_fixup_fdt(blob);
ft_cpu_setup(blob, bd);
+ fdt_fsl_fixup_of_pfe(blob);
return 0;
}
diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
new file mode 100644
index 0000000..b06f722
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define ETH_1_1G_BUS_ID 0x1
+#define ETH_1_1G_PHY_ID 0x1e
+#define ETH_1_1G_MDIO_MUX 0x2
+#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD
+#define ETH_1_1G_PHY_MODE "sgmii"
+#define ETH_2_1G_BUS_ID 0x1
+#define ETH_2_1G_PHY_ID 0x1
+#define ETH_2_1G_MDIO_MUX 0x1
+#define ETH_2_1G_PHY_MODE "rgmii"
+
+#define ETH_1_2_5G_BUS_ID 0x0
+#define ETH_1_2_5G_PHY_ID 0x1
+#define ETH_1_2_5G_MDIO_MUX 0x2
+#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
+#define ETH_2_5G_PHY_MODE "sgmii-2500"
+#define ETH_2_2_5G_BUS_ID 0x1
+#define ETH_2_2_5G_PHY_ID 0x2
+#define ETH_2_2_5G_MDIO_MUX 0x3
+
+#define SERDES_1_G_PROTOCOL 0x3508
+#define SERDES_2_5_G_PROTOCOL 0x2205
+
+#define PFE_PROP_LEN 4
+
+#define ETH_1_PATH "/pfe@04000000/ethernet@0"
+#define ETH_1_MDIO ETH_1_PATH "/mdio@0"
+
+#define ETH_2_PATH "/pfe@04000000/ethernet@1"
+#define ETH_2_MDIO ETH_2_PATH "/mdio@0"
+
+#define NUM_ETH_NODE 2
+
+struct pfe_prop_val {
+ int busid;
+ int phyid;
+ int mux_val;
+ int phy_mask;
+ char *phy_mode;
+};
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
index 584f604..7a1ba3d 100644
--- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -11,7 +11,7 @@
/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xe0
-#define BRDCFG4_EMISEL_SHIFT 5
+#define BRDCFG4_EMISEL_SHIFT 6
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index d13b08e..493d477 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,6 +12,35 @@
config SYS_CONFIG_NAME
default "ls1012ardb"
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select PHYLIB
+ imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x1
+
+endif
+
source "board/freescale/common/Kconfig"
endif
@@ -30,6 +59,36 @@
config SYS_CONFIG_NAME
default "ls1012a2g5rdb"
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select PHYLIB
+ imply CONFIG_PHYLIB_10G
+ imply CONFIG_PHY_AQUANTIA
+
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x1
+
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
index 05fa9d9..70c7b33 100644
--- a/board/freescale/ls1012ardb/Makefile
+++ b/board/freescale/ls1012ardb/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1012ardb.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
new file mode 100644
index 0000000..8e6cd0a
--- /dev/null
+++ b/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <i2c.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+#ifdef CONFIG_TARGET_LS1012ARDB
+ /* Through reset IO expander reset both RGMII and SGMII PHYs */
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+ mdelay(10);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+ mdelay(10);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+ mdelay(50);
+#endif
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+ static int init_done;
+ struct mii_dev *bus;
+ struct pfe_mdio_info mac_mdio_info;
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ if (!init_done) {
+ ls1012ardb_reset_phy();
+ mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ init_done = 1;
+ }
+
+ pfe_set_mdio(priv->gemac_port,
+ miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+ switch (srds_s1) {
+ case 0x3508:
+ if (!priv->gemac_port) {
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ } else {
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_RGMII_TXID);
+ }
+ break;
+ case 0x2208:
+ if (!priv->gemac_port) {
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ } else {
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ }
+ break;
+ default:
+ printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+ break;
+ }
+ return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ .phy_interface = 0,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+ .phy_interface = 1,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata1,
+};
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index c9557bb..ed5a8e6 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -114,10 +114,6 @@
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
int board_early_init_f(void)
{
diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS
index 371e5db..4d804d9 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -15,6 +15,8 @@
F: include/configs/ls1088aqds.h
F: configs/ls1088aqds_qspi_defconfig
F: configs/ls1088aqds_sdcard_qspi_defconfig
+F: configs/ls1088aqds_defconfig
+F: configs/ls1088aqds_sdcard_ifc_defconfig
LS1088AQDS_QSPI_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal@nxp.com>
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 56e454f..a5fa050 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -31,6 +31,9 @@
int board_early_init_f(void)
{
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
+ i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
return 0;
}
@@ -168,6 +171,7 @@
return 0;
}
+#endif
bool if_board_diff_clk(void)
{
@@ -221,7 +225,6 @@
return 66666666;
}
-#endif
int select_i2c_ch_pca9547(u8 ch)
{
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 4ddc7e1..332c506 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -22,6 +22,7 @@
#include <asm/setup.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
+#include <environment.h>
#include <hwconfig.h>
#include <i2c.h>
#include <fdt_support.h>
diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
index 90dbccc..0010998 100644
--- a/board/ge/mx53ppd/mx53ppd.c
+++ b/board/ge/mx53ppd/mx53ppd.c
@@ -20,6 +20,7 @@
#include <linux/errno.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/mx5_video.h>
+#include <environment.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig
index 9171502..f7f1055 100644
--- a/board/hisilicon/hikey/Kconfig
+++ b/board/hisilicon/hikey/Kconfig
@@ -12,11 +12,4 @@
config SYS_CONFIG_NAME
default "hikey"
-config CONS_INDEX
- int "UART used for console"
- range 1 4
- default 4
- help
- The hi6220 SoC has 5 UARTs. For example to use UART0 enter 1 here.
-
endif
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index f0ace03..91bc9c2 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -21,6 +21,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <environment.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <input.h>
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
index a938a2c..f427abf 100644
--- a/board/l+g/vinco/vinco.c
+++ b/board/l+g/vinco/vinco.c
@@ -33,7 +33,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_ATMEL_SPI
+/* FIXME gpio code here need to handle through DM_GPIO */
+#ifndef CONFIG_DM_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
@@ -166,7 +167,7 @@
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifdef CONFIG_ATMEL_SPI
+#ifndef CONFIG_DM_SPI
vinco_spi0_hw_init();
#endif
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index e6c2526..fe1183b 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -16,6 +16,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c
index 0d33cc4..8dbf410 100644
--- a/board/micronas/vct/scc.c
+++ b/board/micronas/vct/scc.c
@@ -524,12 +524,14 @@
struct scc_dma_state *dma_state;
int return_value = 0;
union scc_dma_cfg dma_cfg;
- u32 *buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
+ u32 *buffer_tag_list;
u32 tag_count, t, t_valid;
if ((id >= SCC_MAX) || (id < 0))
return -EINVAL;
+ buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
+
/* if the register is only configured by hw, cannot write! */
if (1 == scc_descriptor_table[id].hw_dma_cfg)
return -EACCES;
diff --git a/board/netgear/dgnd3700v2/Kconfig b/board/netgear/dgnd3700v2/Kconfig
new file mode 100644
index 0000000..11af188
--- /dev/null
+++ b/board/netgear/dgnd3700v2/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_DGND3700V2
+
+config SYS_BOARD
+ default "dgnd3700v2"
+
+config SYS_VENDOR
+ default "netgear"
+
+config SYS_CONFIG_NAME
+ default "netgear_dgnd3700v2"
+
+endif
diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS
new file mode 100644
index 0000000..998077b
--- /dev/null
+++ b/board/netgear/dgnd3700v2/MAINTAINERS
@@ -0,0 +1,6 @@
+NETGEAR DGND3700V2 BOARD
+M: Ãlvaro Fernández Rojas <noltari@gmail.com>
+S: Maintained
+F: board/netgear/dgnd3700v2/
+F: include/configs/netgear_dgnd3700v2.h
+F: configs/netgear_dgnd3700v2_ram_defconfig
diff --git a/board/netgear/dgnd3700v2/Makefile b/board/netgear/dgnd3700v2/Makefile
new file mode 100644
index 0000000..89fd6c8
--- /dev/null
+++ b/board/netgear/dgnd3700v2/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += dgnd3700v2.o
diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c
new file mode 100644
index 0000000..3ae7f6a
--- /dev/null
+++ b/board/netgear/dgnd3700v2/dgnd3700v2.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define GPIO_BASE_6362 0x10000080
+
+#define GPIO_MODE_6362_REG 0x18
+#define GPIO_MODE_6362_SERIAL_LED_DATA BIT(2)
+#define GPIO_MODE_6362_SERIAL_LED_CLK BIT(3)
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE);
+
+ /* Enable Serial LEDs */
+ setbits_be32(gpio_regs + GPIO_MODE_6362_REG,
+ GPIO_MODE_6362_SERIAL_LED_DATA |
+ GPIO_MODE_6362_SERIAL_LED_CLK);
+
+ return 0;
+}
+#endif
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 52ad5b6..c57625b 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c
index 47b069e..a1b407d 100644
--- a/board/phytec/phycore_rk3288/phycore-rk3288.c
+++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <i2c.h>
#include <i2c_eeprom.h>
#include <netdev.h>
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 177f4af..3049505 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -8,6 +8,7 @@
#include <inttypes.h>
#include <config.h>
#include <dm.h>
+#include <environment.h>
#include <efi_loader.h>
#include <fdt_support.h>
#include <fdt_simplefb.h>
@@ -91,11 +92,36 @@
};
static const struct rpi_model rpi_models_new_scheme[] = {
+ [0x0] = {
+ "Model A",
+ DTB_DIR "bcm2835-rpi-a.dtb",
+ false,
+ },
+ [0x1] = {
+ "Model B",
+ DTB_DIR "bcm2835-rpi-b.dtb",
+ true,
+ },
+ [0x2] = {
+ "Model A+",
+ DTB_DIR "bcm2835-rpi-a-plus.dtb",
+ false,
+ },
+ [0x3] = {
+ "Model B+",
+ DTB_DIR "bcm2835-rpi-b-plus.dtb",
+ true,
+ },
[0x4] = {
"2 Model B",
DTB_DIR "bcm2836-rpi-2-b.dtb",
true,
},
+ [0x6] = {
+ "Compute Module",
+ DTB_DIR "bcm2835-rpi-cm.dtb",
+ false,
+ },
[0x8] = {
"3 Model B",
DTB_DIR "bcm2837-rpi-3-b.dtb",
@@ -106,11 +132,21 @@
DTB_DIR "bcm2835-rpi-zero.dtb",
false,
},
+ [0xA] = {
+ "Compute Module 3",
+ DTB_DIR "bcm2837-rpi-cm3.dtb",
+ false,
+ },
[0xC] = {
"Zero W",
DTB_DIR "bcm2835-rpi-zero-w.dtb",
false,
},
+ [0xD] = {
+ "3 Model B+",
+ DTB_DIR "bcm2837-rpi-3-b-plus.dtb",
+ true,
+ },
};
static const struct rpi_model rpi_models_old_scheme[] = {
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 0bf8160..f2200ef 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -10,6 +10,7 @@
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index 574dcda..5dc3073 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -12,6 +12,7 @@
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 54e1269..99d4ba6 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -10,6 +10,7 @@
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 8fa648e..e7b47ae 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -11,6 +11,7 @@
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 562be04..3566bcc 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
diff --git a/board/renesas/porter/Makefile b/board/renesas/porter/Makefile
index b0cfb1b..c237ee5 100644
--- a/board/renesas/porter/Makefile
+++ b/board/renesas/porter/Makefile
@@ -7,4 +7,8 @@
# SPDX-License-Identifier: GPL-2.0
#
+ifdef CONFIG_SPL_BUILD
+obj-y := porter_spl.o
+else
obj-y := porter.o qos.o
+endif
diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
index 320841f..acd4f91 100644
--- a/board/renesas/porter/porter.c
+++ b/board/renesas/porter/porter.c
@@ -136,25 +136,3 @@
if (ret)
hang();
}
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-void board_init_f(ulong dummy)
-{
- board_early_init_f();
-}
-
-void spl_board_init(void)
-{
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
- /* Boot from SPI NOR with YMODEM UART fallback. */
- spl_boot_list[0] = BOOT_DEVICE_SPI;
- spl_boot_list[1] = BOOT_DEVICE_UART;
- spl_boot_list[2] = BOOT_DEVICE_NONE;
-}
-#endif
diff --git a/board/renesas/porter/porter_spl.c b/board/renesas/porter/porter_spl.c
new file mode 100644
index 0000000..55f4cac
--- /dev/null
+++ b/board/renesas/porter/porter_spl.c
@@ -0,0 +1,491 @@
+/*
+ * board/renesas/porter/porter_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF0_MSTP721 BIT(21)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+
+ while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x60000000 },
+ { 0x0094, 0x60000000 },
+ { 0x0098, 0x00800200 },
+ { 0x009c, 0x00000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x000244c8 },
+ { 0x002c, 0x00000000 },
+ { 0x0030, 0x00002400 },
+ { 0x0034, 0x01520000 },
+ { 0x0038, 0x00724003 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x00000000 },
+ { 0x0044, 0x00000000 },
+ { 0x0048, 0x00000000 },
+ { 0x004c, 0x00000000 },
+ { 0x0050, 0x00000000 },
+ { 0x0054, 0x00000000 },
+ { 0x0058, 0x00000000 },
+ { 0x005c, 0x00000000 },
+ { 0x0160, 0x00000000 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x00ec3fff },
+ { 0x000c, 0x3bc001e7 },
+ { 0x0010, 0x5bffffff },
+ { 0x0014, 0x1ffffffb },
+ { 0x0018, 0x01bffff0 },
+ { 0x001c, 0xcf7fffff },
+ { 0x0074, 0x0381fc00 },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0xffffffdf },
+ { 0x0104, 0xc883c3ff },
+ { 0x0108, 0x1201f3c9 },
+ { 0x010c, 0x00000000 },
+ { 0x0110, 0xffffeb04 },
+ { 0x0114, 0xc003ffff },
+ { 0x0118, 0x0800000f },
+ { 0x011c, 0x00187ff0 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x2000, 0x04381000 },
+ { 0x5000, 0x00000000 },
+ { 0x5800, 0x000e0000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x00000000 },
+ { 0x2000, 0x04381010 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0x00000000 },
+ { 0x5000, 0x00400000 },
+ { 0x5400, 0x00000000 },
+ { 0x5800, 0x000e0380 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0xff70ff70 },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0280, 0x0000a55a },
+ { 0x4000, 0x0000a55a },
+ { 0x4008, 0x00000001 },
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0001c000 },
+ };
+
+ static const struct reg_config dbsc_config3r0d0[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181885 },
+ { 0x0290, 0x00000070 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000080 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000090 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x000000a0 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x000000b0 },
+ { 0x02a0, 0x7c000880 },
+ { 0x0290, 0x000000c0 },
+ { 0x02a0, 0x7c000880 },
+ { 0x0290, 0x000000d0 },
+ { 0x02a0, 0x7c000880 },
+ { 0x0290, 0x000000e0 },
+ { 0x02a0, 0x7c000880 },
+ };
+ static const struct reg_config dbsc_config3r0d1[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181885 },
+ { 0x0290, 0x00000070 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000080 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000090 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x000000a0 },
+ { 0x02a0, 0x7c000887 },
+ };
+
+ static const struct reg_config dbsc_config3r2[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181224 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf004649b },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000006d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000006 },
+ { 0x0064, 0x00000020 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000200 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20042004 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c561 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcdb60 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d9cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014a00b9 },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf00464db },
+ { 0x4008, 0x00000000 },
+ { 0x4000, 0x00000000 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+ static const u32 prr_base = 0xff000044;
+ const u16 prr_rev = readl(prr_base) & 0x7fff;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+ writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+ writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
+ }
+
+ if (prr_rev == 0x4700) {
+ for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
+ writel(dbsc_config3r0d0[i].val,
+ dbsc3_0_base | dbsc_config3r0d0[i].off);
+ }
+ for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
+ writel(dbsc_config3r0d1[i].val,
+ dbsc3_1_base | dbsc_config3r0d1[i].off);
+ }
+ } else if (prr_rev != 0x4710) {
+ for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
+ writel(dbsc_config3r2[i].val,
+ dbsc3_0_base | dbsc_config3r2[i].off);
+ writel(dbsc_config3r2[i].val,
+ dbsc3_1_base | dbsc_config3r2[i].off);
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+ writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
+ }
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+ writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+ writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+ writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+ writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+ }
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
index 4a76fb7..5da6f39 100644
--- a/board/renesas/sh7752evb/sh7752evb.c
+++ b/board/renesas/sh7752evb/sh7752evb.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
index ca9e144..8604d88 100644
--- a/board/renesas/sh7753evb/sh7753evb.c
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
index 3f970fc..1c598fb 100644
--- a/board/renesas/sh7757lcr/sh7757lcr.c
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index a8de402..9e2080b 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -11,6 +11,7 @@
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/stout/Makefile b/board/renesas/stout/Makefile
index cb7c61d..b8875bb 100644
--- a/board/renesas/stout/Makefile
+++ b/board/renesas/stout/Makefile
@@ -8,4 +8,8 @@
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := stout.o cpld.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := stout_spl.o
+else
+obj-y := stout.o cpld.o qos.o
+endif
diff --git a/board/renesas/stout/cpld.c b/board/renesas/stout/cpld.c
index 5640e1d..fc1e30c 100644
--- a/board/renesas/stout/cpld.c
+++ b/board/renesas/stout/cpld.c
@@ -13,10 +13,10 @@
#include <asm/gpio.h>
#include "cpld.h"
-#define SCLK GPIO_GP_3_24
-#define SSTBZ GPIO_GP_3_25
-#define MOSI GPIO_GP_3_26
-#define MISO GPIO_GP_3_27
+#define SCLK (92 + 24)
+#define SSTBZ (92 + 25)
+#define MOSI (92 + 26)
+#define MISO (92 + 27)
#define CPLD_ADDR_MODE 0x00 /* RW */
#define CPLD_ADDR_MUX 0x01 /* RW */
@@ -91,10 +91,10 @@
val |= PUPR3_SD3_DAT1;
writel(val, PUPR3);
- gpio_request(SCLK, NULL);
- gpio_request(SSTBZ, NULL);
- gpio_request(MOSI, NULL);
- gpio_request(MISO, NULL);
+ gpio_request(SCLK, "SCLK");
+ gpio_request(SSTBZ, "SSTBZ");
+ gpio_request(MOSI, "MOSI");
+ gpio_request(MISO, "MISO");
gpio_direction_output(SCLK, 0);
gpio_direction_output(SSTBZ, 1);
diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index d681148..d7e8129 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c
@@ -14,6 +14,7 @@
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
@@ -58,14 +59,7 @@
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIFA0_MSTP204 (1 << 4)
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI2_MSTP312 (1 << 12)
-#define ETHER_MSTP813 (1 << 13)
-
-#define MSTPSR3 0xE6150048
-#define SMSTPCR3 0xE615013C
+#define TMU0_MSTP125 BIT(25)
#define SD2CKCR 0xE6150078
#define SD2_97500KHZ 0x7
@@ -74,12 +68,6 @@
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIFA0 */
- mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
- /* SDHI0,2 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
/*
* SD0 clock is set to 97.5MHz by default.
@@ -90,66 +78,37 @@
return 0;
}
+#define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7790_pinmux_init();
-
cpld_init();
-#ifdef CONFIG_SH_ETHER
- /* ETHER Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ1, NULL);
-
- gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */
- gpio_direction_output(GPIO_GP_3_31, 0);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
mdelay(20);
- gpio_set_value(GPIO_GP_3_31, 1);
- udelay(1);
-#endif
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
- int ret = -ENODEV;
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
-#ifdef CONFIG_SH_ETHER
- u32 val;
- unsigned char enetaddr[6];
+ return 0;
+}
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
-
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
-#endif
-
- return ret;
+ return 0;
}
/* Stout has KSZ8041NL/RNL */
@@ -166,67 +125,6 @@
return 0;
}
-int board_mmc_init(bd_t *bis)
-{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DAT0, NULL);
- gpio_request(GPIO_FN_SD0_DAT1, NULL);
- gpio_request(GPIO_FN_SD0_DAT2, NULL);
- gpio_request(GPIO_FN_SD0_DAT3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD2_DAT0, NULL);
- gpio_request(GPIO_FN_SD2_DAT1, NULL);
- gpio_request(GPIO_FN_SD2_DAT2, NULL);
- gpio_request(GPIO_FN_SD2_DAT3, NULL);
- gpio_request(GPIO_FN_SD2_CLK, NULL);
- gpio_request(GPIO_FN_SD2_CMD, NULL);
- gpio_request(GPIO_FN_SD2_CD, NULL);
-
- /* SDHI0 - needs CPLD mux setup */
- gpio_request(GPIO_GP_3_30, NULL);
- gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */
- gpio_request(GPIO_GP_5_24, NULL);
- gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
- if (ret)
- return ret;
-
- /* SDHI2 - needs CPLD mux setup */
- gpio_request(GPIO_GP_3_29, NULL);
- gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */
- gpio_request(GPIO_GP_5_25, NULL);
- gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
- return ret;
-}
-
-
-int dram_init(void)
-{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
-
const struct rmobile_sysinfo sysinfo = {
CONFIG_ARCH_RMOBILE_BOARD_STRING
};
-
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIFA0_BASE,
- .type = PORT_SCIFA,
- .clk = CONFIG_MP_CLK_FREQ,
-};
-
-U_BOOT_DEVICE(stout_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
diff --git a/board/renesas/stout/stout_spl.c b/board/renesas/stout/stout_spl.c
new file mode 100644
index 0000000..ed443fd
--- /dev/null
+++ b/board/renesas/stout/stout_spl.c
@@ -0,0 +1,477 @@
+/*
+ * board/renesas/stout/stout_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIFA0_MSTP204 BIT(4)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+
+ while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x00140300 },
+ { 0x0094, 0x09500000 },
+ { 0x0098, 0xc0000084 },
+ { 0x0020, 0x01a33492 },
+ { 0x0024, 0x10000000 },
+ { 0x0028, 0x08449252 },
+ { 0x002c, 0x2925b322 },
+ { 0x0030, 0x0c311249 },
+ { 0x0034, 0x10124000 },
+ { 0x0038, 0x00001295 },
+ { 0x003c, 0x50890000 },
+ { 0x0040, 0x0eaa56aa },
+ { 0x0044, 0x55550000 },
+ { 0x0048, 0x00000005 },
+ { 0x004c, 0x54800000 },
+ { 0x0050, 0x3736db55 },
+ { 0x0054, 0x29148da3 },
+ { 0x0058, 0x48c446e1 },
+ { 0x005c, 0x2a3a54dc },
+ { 0x0160, 0x00000023 },
+ { 0x0004, 0xfca0ffff },
+ { 0x0008, 0x3fbffbf0 },
+ { 0x000c, 0x3ffdffff },
+ { 0x0010, 0x00ffffff },
+ { 0x0014, 0xfc3ffff3 },
+ { 0x0018, 0xe4fdfff7 },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0104, 0xffffbfff },
+ { 0x0108, 0xb1ffffe1 },
+ { 0x010c, 0xffffffff },
+ { 0x0110, 0xffffffff },
+ { 0x0114, 0xe047beab },
+ { 0x0118, 0x00000203 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x3000, 0x4000, 0x5000
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x4000, 0x00c00000 },
+ { 0x5000, 0x63020000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x00000000 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0x00c00000 },
+ { 0x5000, 0xe3020000 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x02150326 },
+ { 0x38, 0x077f077f },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0280, 0x0000a55a },
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0001c000 },
+ };
+
+ static const struct reg_config dbsc_config3r0d0[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181885 },
+ { 0x0290, 0x00000070 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000080 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000090 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x000000a0 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x000000b0 },
+ { 0x02a0, 0x7c000880 },
+ { 0x0290, 0x000000c0 },
+ { 0x02a0, 0x7c000880 },
+ { 0x0290, 0x000000d0 },
+ { 0x02a0, 0x7c000880 },
+ { 0x0290, 0x000000e0 },
+ { 0x02a0, 0x7c000880 },
+ };
+
+ static const struct reg_config dbsc_config3r0d1[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181885 },
+ { 0x0290, 0x00000070 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000080 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x00000090 },
+ { 0x02a0, 0x7c000887 },
+ { 0x0290, 0x000000a0 },
+ { 0x02a0, 0x7c000887 },
+ };
+
+ static const struct reg_config dbsc_config3r2[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181224 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf004649b },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000006d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000006 },
+ { 0x0064, 0x00000020 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000200 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20042004 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c4e1 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcdb60 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d9cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+ static const u32 prr_base = 0xff000044;
+ const u16 prr_rev = readl(prr_base) & 0x7fff;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+ writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+ writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
+ }
+
+ if (prr_rev == 0x4500) {
+ for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
+ writel(dbsc_config3r0d0[i].val,
+ dbsc3_0_base | dbsc_config3r0d0[i].off);
+ }
+ for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
+ writel(dbsc_config3r0d1[i].val,
+ dbsc3_1_base | dbsc_config3r0d1[i].off);
+ }
+ } else if (prr_rev != 0x4510) {
+ for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
+ writel(dbsc_config3r2[i].val,
+ dbsc3_0_base | dbsc_config3r2[i].off);
+ writel(dbsc_config3r2[i].val,
+ dbsc3_1_base | dbsc_config3r2[i].off);
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+ writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
+ }
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+ writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+ writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+ writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+ writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+ }
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c
index 790a921..0f2abe2 100644
--- a/board/rockchip/tinker_rk3288/tinker-rk3288.c
+++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <i2c_eeprom.h>
#include <netdev.h>
diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c
index cced08b..0cc8421 100644
--- a/board/samtec/vining_2000/vining_2000.c
+++ b/board/samtec/vining_2000/vining_2000.c
@@ -18,6 +18,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
+#include <environment.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <i2c.h>
diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c
index 229b12f..14ac7ef 100644
--- a/board/samtec/vining_fpga/socfpga.c
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <asm/gpio.h>
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index 7fa2673..f3e82d4 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -9,6 +9,7 @@
#if !defined(CONFIG_SPL_BUILD)
#include <common.h>
+#include <environment.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 8bbb035..ab54e58 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -14,6 +14,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 71541ba..3534b2a 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -283,6 +283,8 @@
return 0;
}
+/* FIXME gpio code here need to handle through DM_GPIO */
+#ifndef CONFIG_DM_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
@@ -297,6 +299,7 @@
{
at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
}
+#endif
#ifdef CONFIG_USB_GADGET_AT91
#include <linux/usb/at91_udc.h>
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
index 0429e6f..e736afb 100644
--- a/board/silica/pengwyn/board.c
+++ b/board/silica/pengwyn/board.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/ddr_defs.h>
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 8da7028..c4f2633 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -7,14 +7,16 @@
#include <common.h>
#include <dm.h>
+#include <lcd.h>
#include <ram.h>
#include <spl.h>
+#include <splash.h>
+#include <st_logo_data.h>
+#include <video.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/stm32_periph.h>
-#include <asm/arch/stm32_defs.h>
#include <asm/arch/syscfg.h>
#include <asm/gpio.h>
@@ -155,5 +157,10 @@
STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
#endif
+#if defined(CONFIG_CMD_BMP)
+ bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
+ BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
+#endif /* CONFIG_CMD_BMP */
+
return 0;
}
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
new file mode 100644
index 0000000..5ab9415
--- /dev/null
+++ b/board/st/stm32mp1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_STM32MP1
+
+config SYS_BOARD
+ default "stm32mp1"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp1"
+
+endif
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
new file mode 100644
index 0000000..65266bc
--- /dev/null
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32MP1 BOARD
+M: Patrick Delaunay <patrick.delaunay@st.com>
+S: Maintained
+F: board/st/stm32mp1
+F: include/configs/stm32mp1.h
+F: configs/stm32mp15_basic_defconfig
+F: arch/arm/dts/stm32mp157*
diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile
new file mode 100644
index 0000000..eaf45b7
--- /dev/null
+++ b/board/st/stm32mp1/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += stm32mp1.o
+endif
+
+obj-y += board.o
diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README
new file mode 100644
index 0000000..42a39d0
--- /dev/null
+++ b/board/st/stm32mp1/README
@@ -0,0 +1,226 @@
+#
+# Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+U-Boot on STMicroelectronics STM32MP1
+======================================
+
+1. Summary
+==========
+This is a quick instruction for setup stm32mp1 boards.
+
+2. Supported devices
+====================
+U-Boot supports one STMP32MP1 SoCs: STM32MP157
+
+The STM32MP157 is a Cortex-A MPU aimed at various applications.
+It features:
+- Dual core Cortex-A7 application core
+- 2D/3D image composition with GPU
+- Standard memories interface support
+- Standard connectivity, widely inherited from the STM32 MCU family
+- Comprehensive security support
+
+Everything is supported in Linux but U-Boot is limited to:
+1. UART
+2. SDCard/MMC controller (SDMMC)
+
+And the necessary drivers
+1. I2C
+2. STPMU1
+3. Clock, Reset
+
+Currently the following boards are supported:
++ stm32mp157c-ed1
+
+3. Boot Sequences
+=================
+
+BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel)
+
+with FSBL = First Stage Bootloader
+ SSBL = Second Stage Bootloader
+
+One boot configuration is supported:
+
+ The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
+ BootRom => FSBL = U-Boot SPL => SSBL = U-Boot
+ SPL has limited security initialisation
+ U-Boot is running in secure mode and provide a secure monitor to the kernel
+ with only PSCI support (Power State Coordination Interface defined by ARM)
+
+All the STM32MP1 board supported by U-Boot use the same generic board
+stm32mp1 which support all the bootable devices.
+
+Each board is configurated only with the associated device tree.
+
+4. Device Tree Selection
+========================
+
+You need to select the appropriate device tree for your board,
+the supported device trees for stm32mp157 are:
+
++ ed1: daughter board with pmic stpmu1
+ dts: stm32mp157c-ed1
+
+5. Build Procedure
+==================
+
+1. Install required tools for U-Boot
+
+ + install package needed in U-Boot makefile
+ (libssl-dev, swig, libpython-dev...)
+ + install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
+ from SDK for STM32MP1, or any crosstoolchains from your distribution)
+
+2. Set the cross compiler:
+
+ # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
+ (you can use any gcc cross compiler compatible with U-Boot)
+
+3. Select the output directory (optional)
+
+ # export KBUILD_OUTPUT=/path/to/output
+
+ for example: use one output directory for each configuration
+ # export KBUILD_OUTPUT=stm32mp15_basic
+
+4. Configure the U-Boot:
+
+ # make <defconfig_file>
+
+ - For basic boot mode: "stm32mp15_basic_defconfig"
+
+5. Configure the device-tree and build the U-Boot image:
+
+ # make DEVICE_TREE=<name> all
+
+
+ example:
+ basic boot on ed1
+ # export KBUILD_OUTPUT=stm32mp15_basic
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157c-ed1 all
+
+6. Output files
+
+ BootRom and ATF expect binaries with STM32 image header
+ SPL expects file with U-Boot uImage header
+
+ So in the output directory (selected by KBUILD_OUTPUT),
+ you can found the needed files:
+
+ + FSBL = spl/u-boot-spl.stm32
+ + SSBL = u-boot.img
+
+6. Switch Setting for Boot Mode
+===============================
+
+You can select the boot mode, on the board ed1 with the switch SW1
+
+ -----------------------------------
+ Boot Mode BOOT2 BOOT1 BOOT0
+ -----------------------------------
+ Reserved 0 0 0
+ NOR 0 0 1
+ SD-Card 1 1 1
+ SD-Card 1 0 1
+ eMMC 0 1 0
+ NAND 0 1 1
+ Recovery 1 1 0
+ Recovery 0 0 0
+
+Recovery is a boot from serial link (UART/USB) and it is used with
+STM32CubeProgrammer tool to load executable in RAM and to update the flash
+devices available on the board (NOR/NAND/eMMC/SDCARD).
+The communication between HOST and board is based on
+- for UARTs : the uart protocol used with all MCU STM32
+- for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)
+
+7. Prepare an SDCard
+===================
+
+The minimal requirements for STMP32MP1 boot up to U-Boot are:
+- GPT partitioning (with gdisk or with sgdisk)
+- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
+- one ssbl partition for U-Boot
+
+Then the minimal GPT partition is:
+ ----- ------- --------- -------------
+ | Num | Name | Size | Content |
+ ----- ------- -------- --------------
+ | 1 | fsbl1 | 256 KiB | ATF or SPL |
+ | 2 | fsbl2 | 256 KiB | ATF or SPL |
+ | 3 | ssbl | enought | U-Boot |
+ | * | - | - | Boot/Rootfs|
+ ----- ------- --------- -------------
+
+(*) add bootable partition for extlinux.conf
+ following Generic Distribution
+ (doc/README.distro for use)
+
+ according the used card reader select the block device
+ (/dev/sdx or /dev/mmcblk0)
+ in the next example I use /dev/mmcblk0
+
+for example: with gpt table with 128 entries
+
+ a) remove previous formatting
+ # sgdisk -o /dev/<SDCard dev>
+
+ b) create minimal image
+ # sgdisk --resize-table=128 -a 1 \
+ -n 1:34:545 -c 1:fsbl1 \
+ -n 2:546:1057 -c 2:fsbl2 \
+ -n 3:1058:5153 -c 3:ssbl \
+ -p /dev/<SDCard dev>
+
+ you can add other partition for kernel (rootfs for example)
+
+ c) copy the FSBL (2 times) and SSBL file on the correct partition.
+ in this example in partition 1 to 3
+
+ for basic boot mode : <SDCard dev> = /dev/mmcblk0
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
+ # dd if=u-boot.img of=/dev/mmcblk0p3
+
+To boot from SDCard, select BootPinMode = 1 1 1 and reset.
+
+8. Prepare eMMC
+===============
+You can use U-Boot to copy binary in eMMC.
+
+In the next example, you need to boot from SDCARD and the images (u-boot-spl.stm32, u-boot.img)
+are presents on SDCARD (mmc 0) in ext4 partition 4 (bootfs).
+
+To boot from SDCard, select BootPinMode = 1 1 1 and reset.
+
+Then you update the eMMC with the next U-Boot command :
+
+a) prepare GPT on eMMC,
+ example with 2 partitions, bootfs and roots:
+
+ # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512"
+ # gpt write mmc 1 ${emmc_part}
+
+b) copy SPL on eMMC on firts boot partition
+ (SPL max size is 256kB, with LBA 512, 0x200)
+
+ # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32
+ # mmc dev 1
+ # mmc partconf 1 1 1 1
+ # mmc write ${fileaddr} 0 200
+ # mmc partconf 1 1 1 0
+
+b) copy U-Boot in first GPT partition of eMMC
+
+ # ext4load mmc 0:4 0xC0000000 u-boot.img
+ # mmc dev 1
+ # part start mmc 1 1 partstart
+ # part size mmc 1 1 partsize
+ # mmc write ${fileaddr} ${partstart} ${partsize}
+
+To boot from eMMC, select BootPinMode = 0 1 0 and reset.
diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
new file mode 100644
index 0000000..03f900a
--- /dev/null
+++ b/board/st/stm32mp1/board.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+
+#ifdef CONFIG_PMIC_STPMU1
+int board_ddr_power_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmu1), &dev);
+ if (ret)
+ /* No PMIC on board */
+ return 0;
+
+ /* Set LDO3 to sync mode */
+ ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMU1_LDO3_MODE;
+ ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
+ ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
+
+ ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+
+ /* Set BUCK2 to 1.35V */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+ STPMU1_BUCK_OUTPUT_MASK,
+ STPMU1_BUCK2_1350000V);
+ if (ret < 0)
+ return ret;
+
+ /* Enable BUCK2 and VREF */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+ STPMU1_BUCK_EN, STPMU1_BUCK_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
+ STPMU1_VREF_EN, STPMU1_VREF_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable LDO3 */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+ STPMU1_LDO_EN, STPMU1_LDO_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ return 0;
+}
+#endif
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
new file mode 100644
index 0000000..b7e5f24
--- /dev/null
+++ b/board/st/stm32mp1/spl.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <post.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+#include <asm/arch/ddr.h>
+
+void spl_board_init(void)
+{
+ /* Keep vdd on during the reset cycle */
+#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT)
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmu1), &dev);
+ if (!ret)
+ pmic_clrsetbits(dev,
+ STPMU1_MASK_RESET_BUCK,
+ STPMU1_MASK_RESET_BUCK3,
+ STPMU1_MASK_RESET_BUCK3);
+#endif
+}
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
new file mode 100644
index 0000000..84c971c
--- /dev/null
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/arch/stm32.h>
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+ return 0;
+}
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 5eb8bbe..6dd48c0 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -311,6 +311,12 @@
S: Maintained
F: configs/Nintendo_NES_Classic_Edition_defconfig
+OLIMEX A20-SOM204 BOARD
+M: Stefan Mavrodiev <stefan@olimex.com>
+S: Maintained
+F: configs/A20-Olimex-SOM204-EVB_defconfig
+F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+
ORANGEPI WIN/WIN PLUS BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64
index c492f74..df1dbc8 100644
--- a/board/sunxi/README.sunxi64
+++ b/board/sunxi/README.sunxi64
@@ -38,6 +38,12 @@
$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin
(adjust the actual path accordingly)
+If you run into size issues with the resulting U-Boot image file, it might
+help to use a release build, by using "DEBUG=0" when building bl31.bin.
+As sometimes the ATF build process is a bit picky about the toolchain used,
+or if you can't be bothered with building ATF, there are known working
+binaries in the firmware repository[3], purely for convenience reasons.
+
SPL/U-Boot
------------
Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM
@@ -95,9 +101,8 @@
(replace /dev/sdx with you SD card device file name, which could be
/dev/mmcblk[x] as well).
-Alternatively you can concatenate the SPL and the U-Boot FIT image into a
+Alternatively you can use the SPL and the U-Boot FIT image combined into a
single file and transfer that instead:
-$ cat spl/sunxi-spl.bin u-boot.itb > u-boot-sunxi-with-spl.bin
# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
You can partition the microSD card, but leave the first MB unallocated (most
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index e08e22f..322dd9e 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -286,10 +286,9 @@
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
-#ifdef CONFIG_MACH_SUN9I
- setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
-#else
- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
+ defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
+ setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
#endif
setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
}
diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index e6b69da..18f7666 100644
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -47,6 +47,18 @@
}
#ifdef CONFIG_ISA_ARCV2
+
+void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+ kernel_entry = (void (*)(int, int, uint))entry;
+
+ smp_set_core_boot_addr(entry, -1);
+ smp_kick_all_cpus();
+ kernel_entry(zero, arch, params);
+}
+
#define RESET_VECTOR_ADDR 0x0
void smp_set_core_boot_addr(unsigned long addr, int corenr)
diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
index d034bc4..e22bd1e 100644
--- a/board/synopsys/hsdk/MAINTAINERS
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -1,5 +1,5 @@
-AXS10X BOARD
-M: Alexey Brodkin <abrodkin@synopsys.com>
+HSDK BOARD
+M: Eugeniy Paltsev <paltsev@synopsys.com>
S: Maintained
F: board/synopsys/hsdk/
F: configs/hsdk_defconfig
diff --git a/board/synopsys/hsdk/Makefile b/board/synopsys/hsdk/Makefile
index d84dd03..7ecff3d 100644
--- a/board/synopsys/hsdk/Makefile
+++ b/board/synopsys/hsdk/Makefile
@@ -5,3 +5,5 @@
#
obj-y += hsdk.o
+obj-y += env-lib.o
+obj-y += clk-lib.o
diff --git a/board/synopsys/hsdk/clk-lib.c b/board/synopsys/hsdk/clk-lib.c
new file mode 100644
index 0000000..1ce54af
--- /dev/null
+++ b/board/synopsys/hsdk/clk-lib.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <clk.h>
+#include <dm/device.h>
+
+#include "clk-lib.h"
+
+#define HZ_IN_MHZ 1000000
+#define ceil(x, y) ({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; })
+
+int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl)
+{
+ int ret;
+ ulong mhz_rate, priv_rate;
+ struct clk clk;
+
+ /* Dummy fmeas device, just to be able to use standard clk_* api */
+ struct udevice fmeas = {
+ .name = "clk-fmeas",
+ .node = ofnode_path("/clk-fmeas"),
+ };
+
+ ret = clk_get_by_name(&fmeas, name, &clk);
+ if (ret) {
+ pr_err("clock '%s' not found, err=%d\n", name, ret);
+ return ret;
+ }
+
+ if (ctl & CLK_ON) {
+ ret = clk_enable(&clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+ return ret;
+ }
+
+ if ((ctl & CLK_SET) && rate) {
+ priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate;
+ ret = clk_set_rate(&clk, priv_rate);
+ if (ret)
+ return ret;
+ }
+
+ if (ctl & CLK_OFF) {
+ ret = clk_disable(&clk);
+ if (ret) {
+ pr_err("clock '%s' can't be disabled, err=%d\n", name, ret);
+ return ret;
+ }
+ }
+
+ priv_rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+
+ mhz_rate = ceil(priv_rate, HZ_IN_MHZ);
+
+ if (ctl & CLK_MHZ)
+ priv_rate = mhz_rate;
+
+ if ((ctl & CLK_GET) && rate)
+ *rate = priv_rate;
+
+ if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ))
+ printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate);
+ else if (ctl & CLK_PRINT)
+ printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate);
+ else
+ debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate);
+
+ return 0;
+}
diff --git a/board/synopsys/hsdk/clk-lib.h b/board/synopsys/hsdk/clk-lib.h
new file mode 100644
index 0000000..3b7dbc5
--- /dev/null
+++ b/board/synopsys/hsdk/clk-lib.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_CLK_LIB_H
+#define __BOARD_CLK_LIB_H
+
+#include <common.h>
+
+enum clk_ctl_ops {
+ CLK_SET = BIT(0), /* set frequency */
+ CLK_GET = BIT(1), /* get frequency */
+ CLK_ON = BIT(2), /* enable clock */
+ CLK_OFF = BIT(3), /* disable clock */
+ CLK_PRINT = BIT(4), /* print frequency */
+ CLK_MHZ = BIT(5) /* all values in MHZ instead of HZ */
+};
+
+/*
+ * Depending on the clk_ctl_ops enable / disable /
+ * set clock rate from 'rate' argument / read clock to 'rate' argument /
+ * print clock rate. If CLK_MHZ flag set in clk_ctl_ops 'rate' is in MHz,
+ * otherwise - in Hz.
+ *
+ * This function expects "clk-fmeas" node in device tree:
+ * / {
+ * clk-fmeas {
+ * clocks = <&cpu_pll>, <&sys_pll>;
+ * clock-names = "cpu-pll", "sys-pll";
+ * };
+ * };
+ */
+int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl);
+
+#endif /* __BOARD_CLK_LIB_H */
diff --git a/board/synopsys/hsdk/env-lib.c b/board/synopsys/hsdk/env-lib.c
new file mode 100644
index 0000000..6b53d92
--- /dev/null
+++ b/board/synopsys/hsdk/env-lib.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "env-lib.h"
+
+#define MAX_CMD_LEN 25
+
+static void env_clear_common(u32 index, const struct env_map_common *map)
+{
+ map[index].val->val = 0;
+ map[index].val->set = false;
+}
+
+static int env_read_common(u32 index, const struct env_map_common *map)
+{
+ u32 val;
+
+ if (!env_get_yesno(map[index].env_name)) {
+ if (map[index].type == ENV_HEX) {
+ val = (u32)env_get_hex(map[index].env_name, 0);
+ debug("ENV: %s: = %#x\n", map[index].env_name, val);
+ } else {
+ val = (u32)env_get_ulong(map[index].env_name, 10, 0);
+ debug("ENV: %s: = %d\n", map[index].env_name, val);
+ }
+
+ map[index].val->val = val;
+ map[index].val->set = true;
+ }
+
+ return 0;
+}
+
+static void env_clear_core(u32 index, const struct env_map_percpu *map)
+{
+ for (u32 i = 0; i < NR_CPUS; i++) {
+ (*map[index].val)[i].val = 0;
+ (*map[index].val)[i].set = false;
+ }
+}
+
+static int env_read_core(u32 index, const struct env_map_percpu *map)
+{
+ u32 val;
+ char command[MAX_CMD_LEN];
+
+ for (u32 i = 0; i < NR_CPUS; i++) {
+ sprintf(command, "%s_%u", map[index].env_name, i);
+ if (!env_get_yesno(command)) {
+ if (map[index].type == ENV_HEX) {
+ val = (u32)env_get_hex(command, 0);
+ debug("ENV: %s: = %#x\n", command, val);
+ } else {
+ val = (u32)env_get_ulong(command, 10, 0);
+ debug("ENV: %s: = %d\n", command, val);
+ }
+
+ (*map[index].val)[i].val = val;
+ (*map[index].val)[i].set = true;
+ }
+ }
+
+ return 0;
+}
+
+static int env_validate_common(u32 index, const struct env_map_common *map)
+{
+ u32 value = map[index].val->val;
+ bool set = map[index].val->set;
+ u32 min = map[index].min;
+ u32 max = map[index].max;
+
+ /* Check if environment is mandatory */
+ if (map[index].mandatory && !set) {
+ pr_err("Variable \'%s\' is mandatory, but it is not defined\n",
+ map[index].env_name);
+
+ return -EINVAL;
+ }
+
+ /* Check environment boundary */
+ if (set && (value < min || value > max)) {
+ if (map[index].type == ENV_HEX)
+ pr_err("Variable \'%s\' must be between %#x and %#x\n",
+ map[index].env_name, min, max);
+ else
+ pr_err("Variable \'%s\' must be between %u and %u\n",
+ map[index].env_name, min, max);
+
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int env_validate_core(u32 index, const struct env_map_percpu *map,
+ bool (*cpu_used)(u32))
+{
+ u32 value;
+ bool set;
+ bool mandatory = map[index].mandatory;
+ u32 min, max;
+
+ for (u32 i = 0; i < NR_CPUS; i++) {
+ set = (*map[index].val)[i].set;
+ value = (*map[index].val)[i].val;
+
+ /* Check if environment is mandatory */
+ if (cpu_used(i) && mandatory && !set) {
+ pr_err("CPU %u is used, but \'%s_%u\' is not defined\n",
+ i, map[index].env_name, i);
+
+ return -EINVAL;
+ }
+
+ min = map[index].min[i];
+ max = map[index].max[i];
+
+ /* Check environment boundary */
+ if (set && (value < min || value > max)) {
+ if (map[index].type == ENV_HEX)
+ pr_err("Variable \'%s_%u\' must be between %#x and %#x\n",
+ map[index].env_name, i, min, max);
+ else
+ pr_err("Variable \'%s_%u\' must be between %d and %d\n",
+ map[index].env_name, i, min, max);
+
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+void envs_cleanup_core(const struct env_map_percpu *map)
+{
+ /* Cleanup env struct first */
+ for (u32 i = 0; map[i].env_name; i++)
+ env_clear_core(i, map);
+}
+
+void envs_cleanup_common(const struct env_map_common *map)
+{
+ /* Cleanup env struct first */
+ for (u32 i = 0; map[i].env_name; i++)
+ env_clear_common(i, map);
+}
+
+int envs_read_common(const struct env_map_common *map)
+{
+ int ret;
+
+ for (u32 i = 0; map[i].env_name; i++) {
+ ret = env_read_common(i, map);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int envs_validate_common(const struct env_map_common *map)
+{
+ int ret;
+
+ for (u32 i = 0; map[i].env_name; i++) {
+ ret = env_validate_common(i, map);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int envs_read_validate_common(const struct env_map_common *map)
+{
+ int ret;
+
+ envs_cleanup_common(map);
+
+ ret = envs_read_common(map);
+ if (ret)
+ return ret;
+
+ ret = envs_validate_common(map);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int envs_read_validate_core(const struct env_map_percpu *map,
+ bool (*cpu_used)(u32))
+{
+ int ret;
+
+ envs_cleanup_core(map);
+
+ for (u32 i = 0; map[i].env_name; i++) {
+ ret = env_read_core(i, map);
+ if (ret)
+ return ret;
+ }
+
+ for (u32 i = 0; map[i].env_name; i++) {
+ ret = env_validate_core(i, map, cpu_used);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int envs_process_and_validate(const struct env_map_common *common,
+ const struct env_map_percpu *core,
+ bool (*cpu_used)(u32))
+{
+ int ret;
+
+ ret = envs_read_validate_common(common);
+ if (ret)
+ return ret;
+
+ ret = envs_read_validate_core(core, cpu_used);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int args_envs_read_search(const struct env_map_common *map,
+ int argc, char *const argv[])
+{
+ for (int i = 0; map[i].env_name; i++) {
+ if (!strcmp(argv[0], map[i].env_name))
+ return i;
+ }
+
+ pr_err("Unexpected argument '%s', can't parse\n", argv[0]);
+
+ return -ENOENT;
+}
+
+static int arg_read_set(const struct env_map_common *map, u32 i, int argc,
+ char *const argv[])
+{
+ char *endp = argv[1];
+
+ if (map[i].type == ENV_HEX)
+ map[i].val->val = simple_strtoul(argv[1], &endp, 16);
+ else
+ map[i].val->val = simple_strtoul(argv[1], &endp, 10);
+
+ map[i].val->set = true;
+
+ if (*endp == '\0')
+ return 0;
+
+ pr_err("Unexpected argument '%s', can't parse\n", argv[1]);
+
+ map[i].val->set = false;
+
+ return -EINVAL;
+}
+
+int args_envs_enumerate(const struct env_map_common *map, int enum_by,
+ int argc, char *const argv[])
+{
+ u32 i;
+
+ if (argc % enum_by) {
+ pr_err("unexpected argument number: %d\n", argc);
+ return -EINVAL;
+ }
+
+ while (argc > 0) {
+ i = args_envs_read_search(map, argc, argv);
+ if (i < 0)
+ return i;
+
+ debug("ARG: found '%s' with index %d\n", map[i].env_name, i);
+
+ if (i < 0) {
+ pr_err("unknown arg: %s\n", argv[0]);
+ return -EINVAL;
+ }
+
+ if (arg_read_set(map, i, argc, argv))
+ return -EINVAL;
+
+ debug("ARG: value.s '%s' == %#x\n", argv[1], map[i].val->val);
+
+ argc -= enum_by;
+ argv += enum_by;
+ }
+
+ return 0;
+}
diff --git a/board/synopsys/hsdk/env-lib.h b/board/synopsys/hsdk/env-lib.h
new file mode 100644
index 0000000..606e802
--- /dev/null
+++ b/board/synopsys/hsdk/env-lib.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_ENV_LIB_H
+#define __BOARD_ENV_LIB_H
+
+#include <common.h>
+#include <config.h>
+#include <linux/kernel.h>
+
+enum env_type {
+ ENV_DEC,
+ ENV_HEX
+};
+
+typedef struct {
+ u32 val;
+ bool set;
+} u32_env;
+
+struct env_map_common {
+ const char *const env_name;
+ enum env_type type;
+ bool mandatory;
+ u32 min;
+ u32 max;
+ u32_env *val;
+};
+
+struct env_map_percpu {
+ const char *const env_name;
+ enum env_type type;
+ bool mandatory;
+ u32 min[NR_CPUS];
+ u32 max[NR_CPUS];
+ u32_env (*val)[NR_CPUS];
+};
+
+void envs_cleanup_common(const struct env_map_common *map);
+int envs_read_common(const struct env_map_common *map);
+int envs_validate_common(const struct env_map_common *map);
+int envs_read_validate_common(const struct env_map_common *map);
+
+void envs_cleanup_core(const struct env_map_percpu *map);
+int envs_read_validate_core(const struct env_map_percpu *map,
+ bool (*cpu_used)(u32));
+int envs_process_and_validate(const struct env_map_common *common,
+ const struct env_map_percpu *core,
+ bool (*cpu_used)(u32));
+
+int args_envs_enumerate(const struct env_map_common *map,
+ int enum_by, int argc, char *const argv[]);
+
+#endif /* __BOARD_ENV_LIB_H */
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 7641978..65f937f 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -1,34 +1,1024 @@
/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <config.h>
+#include <linux/printk.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/arcregs.h>
+#include <fdt_support.h>
#include <dwmmc.h>
#include <malloc.h>
+#include <usb.h>
+
+#include "clk-lib.h"
+#include "env-lib.h"
DECLARE_GLOBAL_DATA_PTR;
-#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
-#define CREG_PAE (CREG_BASE + 0x180)
-#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
-#define CREG_CPU_START (CREG_BASE + 0x400)
+#define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0)
+#define MASTER_CPU_ID 0
+#define APERTURE_SHIFT 28
+#define NO_CCM 0x10
+#define SLAVE_CPU_READY 0x12345678
+#define BOOTSTAGE_1 1 /* after SP, FP setup, before HW init */
+#define BOOTSTAGE_2 2 /* after HW init, before self halt */
+#define BOOTSTAGE_3 3 /* after self halt */
+#define BOOTSTAGE_4 4 /* before app launch */
+#define BOOTSTAGE_5 5 /* after app launch, unreachable */
-int board_early_init_f(void)
+#define RESET_VECTOR_ADDR 0x0
+
+#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
+#define CREG_CPU_START (CREG_BASE + 0x400)
+#define CREG_CPU_START_MASK 0xF
+
+#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
+#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
+#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
+
+/* Uncached access macros */
+#define arc_read_uncached_32(ptr) \
+({ \
+ unsigned int __ret; \
+ __asm__ __volatile__( \
+ " ld.di %0, [%1] \n" \
+ : "=r"(__ret) \
+ : "r"(ptr)); \
+ __ret; \
+})
+
+#define arc_write_uncached_32(ptr, data)\
+({ \
+ __asm__ __volatile__( \
+ " st.di %0, [%1] \n" \
+ : \
+ : "r"(data), "r"(ptr)); \
+})
+
+struct hsdk_env_core_ctl {
+ u32_env entry[NR_CPUS];
+ u32_env iccm[NR_CPUS];
+ u32_env dccm[NR_CPUS];
+};
+
+struct hsdk_env_common_ctl {
+ bool halt_on_boot;
+ u32_env core_mask;
+ u32_env cpu_freq;
+ u32_env axi_freq;
+ u32_env tun_freq;
+ u32_env nvlim;
+ u32_env icache;
+ u32_env dcache;
+};
+
+/*
+ * Uncached cross-cpu structure. All CPUs must access to this structure fields
+ * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
+ * implement ld.di / st.di instructions). Simultaneous cached and uncached
+ * access to this area will lead to data loss.
+ * We flush all data caches in board_early_init_r() as we don't want to have
+ * any dirty line in L1d$ or SL$ in this area.
+ */
+struct hsdk_cross_cpu {
+ /* slave CPU ready flag */
+ u32 ready_flag;
+ /* address of the area, which can be used for stack by slave CPU */
+ u32 stack_ptr;
+ /* slave CPU status - bootstage number */
+ s32 status[NR_CPUS];
+
+ /*
+ * Slave CPU data - it is copy of corresponding fields in
+ * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
+ * required for slave CPUs initialization.
+ * This fields can be populated by copying from hsdk_env_core_ctl
+ * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
+ * function.
+ */
+ u32 entry[NR_CPUS];
+ u32 iccm[NR_CPUS];
+ u32 dccm[NR_CPUS];
+
+ u32 core_mask;
+ u32 icache;
+ u32 dcache;
+
+ u8 cache_padding[ARCH_DMA_MINALIGN];
+} __aligned(ARCH_DMA_MINALIGN);
+
+/* Place for slave CPUs temporary stack */
+static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
+
+static struct hsdk_env_common_ctl env_common = {};
+static struct hsdk_env_core_ctl env_core = {};
+static struct hsdk_cross_cpu cross_cpu_data;
+
+static const struct env_map_common env_map_common[] = {
+ { "core_mask", ENV_HEX, true, 0x1, 0xF, &env_common.core_mask },
+ { "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
+ { "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
+ { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
+ {}
+};
+
+static const struct env_map_common env_map_clock[] = {
+ { "cpu_freq", ENV_DEC, false, 100, 1000, &env_common.cpu_freq },
+ { "axi_freq", ENV_DEC, false, 200, 800, &env_common.axi_freq },
+ { "tun_freq", ENV_DEC, false, 0, 150, &env_common.tun_freq },
+ {}
+};
+
+static const struct env_map_percpu env_map_core[] = {
+ { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
+ { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
+ {}
+};
+
+static const struct env_map_common env_map_mask[] = {
+ { "core_mask", ENV_HEX, false, 0x1, 0xF, &env_common.core_mask },
+ {}
+};
+
+static const struct env_map_percpu env_map_go[] = {
+ { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
+ {}
+};
+
+static void sync_cross_cpu_data(void)
{
- /* In current chip PAE support for DMA is broken, disabling it. */
- writel(0, (void __iomem *) CREG_PAE);
+ u32 value;
- /* Really apply settings made above */
- writel(1, (void __iomem *) CREG_PAE_UPDATE);
+ for (u32 i = 0; i < NR_CPUS; i++) {
+ value = env_core.entry[i].val;
+ arc_write_uncached_32(&cross_cpu_data.entry[i], value);
+ }
+
+ for (u32 i = 0; i < NR_CPUS; i++) {
+ value = env_core.iccm[i].val;
+ arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
+ }
+
+ for (u32 i = 0; i < NR_CPUS; i++) {
+ value = env_core.dccm[i].val;
+ arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
+ }
+
+ value = env_common.core_mask.val;
+ arc_write_uncached_32(&cross_cpu_data.core_mask, value);
+
+ value = env_common.icache.val;
+ arc_write_uncached_32(&cross_cpu_data.icache, value);
+
+ value = env_common.dcache.val;
+ arc_write_uncached_32(&cross_cpu_data.dcache, value);
+}
+
+/* Can be used only on master CPU */
+static bool is_cpu_used(u32 cpu_id)
+{
+ return !!(env_common.core_mask.val & BIT(cpu_id));
+}
+
+/* TODO: add ICCM BCR and DCCM BCR runtime check */
+static void init_slave_cpu_func(u32 core)
+{
+ u32 val;
+
+ /* Remap ICCM to another memory region if it exists */
+ val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
+ if (val != NO_CCM)
+ write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
+
+ /* Remap DCCM to another memory region if it exists */
+ val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
+ if (val != NO_CCM)
+ write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
+
+ if (arc_read_uncached_32(&cross_cpu_data.icache))
+ icache_enable();
+ else
+ icache_disable();
+
+ if (arc_read_uncached_32(&cross_cpu_data.dcache))
+ dcache_enable();
+ else
+ dcache_disable();
+}
+
+static void init_cluster_nvlim(void)
+{
+ u32 val = env_common.nvlim.val << APERTURE_SHIFT;
+
+ flush_dcache_all();
+ write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
+ write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
+ flush_n_invalidate_dcache_all();
+}
+
+static void init_master_icache(void)
+{
+ if (icache_status()) {
+ /* I$ is enabled - we need to disable it */
+ if (!env_common.icache.val)
+ icache_disable();
+ } else {
+ /* I$ is disabled - we need to enable it */
+ if (env_common.icache.val) {
+ icache_enable();
+
+ /* invalidate I$ right after enable */
+ invalidate_icache_all();
+ }
+ }
+}
+
+static void init_master_dcache(void)
+{
+ if (dcache_status()) {
+ /* D$ is enabled - we need to disable it */
+ if (!env_common.dcache.val)
+ dcache_disable();
+ } else {
+ /* D$ is disabled - we need to enable it */
+ if (env_common.dcache.val)
+ dcache_enable();
+
+ /* TODO: probably we need ti invalidate D$ right after enable */
+ }
+}
+
+static int cleanup_before_go(void)
+{
+ disable_interrupts();
+ sync_n_cleanup_cache_all();
return 0;
}
-#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
-#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
-#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
+void slave_cpu_set_boot_addr(u32 addr)
+{
+ /* All cores have reset vector pointing to 0 */
+ writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+ /* Make sure other cores see written value in memory */
+ sync_n_cleanup_cache_all();
+}
+
+static inline void halt_this_cpu(void)
+{
+ __builtin_arc_flag(1);
+}
+
+static void smp_kick_cpu_x(u32 cpu_id)
+{
+ int cmd = readl((void __iomem *)CREG_CPU_START);
+
+ if (cpu_id > NR_CPUS)
+ return;
+
+ cmd &= ~CREG_CPU_START_MASK;
+ cmd |= (1 << cpu_id);
+ writel(cmd, (void __iomem *)CREG_CPU_START);
+}
+
+static u32 prepare_cpu_ctart_reg(void)
+{
+ int cmd = readl((void __iomem *)CREG_CPU_START);
+
+ cmd &= ~CREG_CPU_START_MASK;
+
+ return cmd | env_common.core_mask.val;
+}
+
+/* slave CPU entry for configuration */
+__attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
+{
+ __asm__ __volatile__(
+ "ld.di r8, [%0]\n"
+ "mov %%sp, r8\n"
+ "mov %%fp, %%sp\n"
+ : /* no output */
+ : "r" (&cross_cpu_data.stack_ptr));
+
+ invalidate_icache_all();
+
+ arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
+ init_slave_cpu_func(CPU_ID_GET());
+
+ arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
+ arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
+
+ /* Halt the processor until the master kick us again */
+ halt_this_cpu();
+
+ /*
+ * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
+ * cores but we leave them for gebug purposes.
+ */
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+
+ arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
+
+ /* get the updated entry - invalidate i$ */
+ invalidate_icache_all();
+
+ arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
+
+ /* Run our program */
+ ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
+
+ /* This bootstage is unreachable as we don't return from app we launch */
+ arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
+
+ /* Something went terribly wrong */
+ while (true)
+ halt_this_cpu();
+}
+
+static void clear_cross_cpu_data(void)
+{
+ arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
+ arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
+
+ for (u32 i = 0; i < NR_CPUS; i++)
+ arc_write_uncached_32(&cross_cpu_data.status[i], 0);
+}
+
+static noinline void do_init_slave_cpu(u32 cpu_id)
+{
+ /* attempts number for check clave CPU ready_flag */
+ u32 attempts = 100;
+ u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
+
+ if (cpu_id >= NR_CPUS)
+ return;
+
+ arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
+
+ /* Use global unique place for each slave cpu stack */
+ arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
+
+ debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
+ debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
+ slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
+
+ smp_kick_cpu_x(cpu_id);
+
+ debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
+ arc_read_uncached_32(&cross_cpu_data.ready_flag));
+
+ while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
+ mdelay(10);
+
+ /* Just to be sure that slave cpu is halted after it set ready_flag */
+ mdelay(20);
+
+ /*
+ * Only print error here if we reach timeout as there is no option to
+ * halt slave cpu (or check that slave cpu is halted)
+ */
+ if (!attempts)
+ pr_err("CPU %u is not responding after init!\n", cpu_id);
+
+ /* Check current stage of slave cpu */
+ if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
+ pr_err("CPU %u status is unexpected: %d\n", cpu_id,
+ arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
+
+ debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
+ arc_read_uncached_32(&cross_cpu_data.ready_flag));
+ debug("CPU %u: status: %d [after timeout]\n", cpu_id,
+ arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
+}
+
+static void do_init_slave_cpus(void)
+{
+ clear_cross_cpu_data();
+ sync_cross_cpu_data();
+
+ debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
+
+ for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
+ if (is_cpu_used(i))
+ do_init_slave_cpu(i);
+}
+
+static void do_init_master_cpu(void)
+{
+ /*
+ * Setup master caches even if master isn't used as we want to use
+ * same cache configuration on all running CPUs
+ */
+ init_master_icache();
+ init_master_dcache();
+}
+
+enum hsdk_axi_masters {
+ M_HS_CORE = 0,
+ M_HS_RTT,
+ M_AXI_TUN,
+ M_HDMI_VIDEO,
+ M_HDMI_AUDIO,
+ M_USB_HOST,
+ M_ETHERNET,
+ M_SDIO,
+ M_GPU,
+ M_DMAC_0,
+ M_DMAC_1,
+ M_DVFS
+};
+
+#define UPDATE_VAL 1
+
+/*
+ * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
+ * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
+ * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
+ * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
+ * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
+ * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
+ * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
+ * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
+ * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
+ * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
+ * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
+ * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
+ * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
+ *
+ * Please read ARC HS Development IC Specification, section 17.2 for more
+ * information about apertures configuration.
+ * NOTE: we intentionally modify default settings in U-boot. Default settings
+ * are specified in "Table 111 CREG Address Decoder register reset values".
+ */
+
+#define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m)))
+#define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
+#define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
+#define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
+#define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
+
+#define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
+
+#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
+#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
+
+void init_memory_bridge(void)
+{
+ u32 reg;
+
+ /*
+ * M_HS_CORE has one unic register - BOOT.
+ * We need to clean boot mirror (BOOT[1:0]) bits in them.
+ */
+ reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
+ writel(reg, CREG_AXI_M_HS_CORE_BOOT);
+ writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
+ writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
+ writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
+ writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
+ writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
+
+ writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
+ writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
+ writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
+ writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
+ writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
+ writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
+ writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
+ writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
+ writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
+ writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
+ writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
+ writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
+ writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
+ writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
+ writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
+ writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
+ writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
+
+ writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
+ writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
+ writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
+ writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
+
+ writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
+ writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
+ writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
+ writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
+
+ writel(0x00000000, CREG_PAE);
+ writel(UPDATE_VAL, CREG_PAE_UPDT);
+}
+
+static void setup_clocks(void)
+{
+ ulong rate;
+
+ /* Setup CPU clock */
+ if (env_common.cpu_freq.set) {
+ rate = env_common.cpu_freq.val;
+ soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
+ }
+
+ /* Setup TUN clock */
+ if (env_common.tun_freq.set) {
+ rate = env_common.tun_freq.val;
+ if (rate)
+ soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
+ else
+ soc_clk_ctl("tun-clk", NULL, CLK_OFF);
+ }
+
+ if (env_common.axi_freq.set) {
+ rate = env_common.axi_freq.val;
+ soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
+ }
+}
+
+static void do_init_cluster(void)
+{
+ /*
+ * A multi-core ARC HS configuration always includes only one
+ * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
+ * cores.
+ */
+ init_cluster_nvlim();
+}
+
+static int check_master_cpu_id(void)
+{
+ if (CPU_ID_GET() == MASTER_CPU_ID)
+ return 0;
+
+ pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
+
+ return -ENOENT;
+}
+
+static noinline int prepare_cpus(void)
+{
+ int ret;
+
+ ret = check_master_cpu_id();
+ if (ret)
+ return ret;
+
+ ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
+ if (ret)
+ return ret;
+
+ printf("CPU start mask is %#x\n", env_common.core_mask.val);
+
+ do_init_slave_cpus();
+ do_init_master_cpu();
+ do_init_cluster();
+
+ return 0;
+}
+
+static int hsdk_go_run(u32 cpu_start_reg)
+{
+ /* Cleanup caches, disable interrupts */
+ cleanup_before_go();
+
+ if (env_common.halt_on_boot)
+ halt_this_cpu();
+
+ /*
+ * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
+ * cores but we leave them for gebug purposes.
+ */
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+
+ /* Kick chosen slave CPUs */
+ writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
+
+ if (is_cpu_used(MASTER_CPU_ID))
+ ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
+ else
+ halt_this_cpu();
+
+ pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
+
+ /*
+ * We will never return after executing our program if master cpu used
+ * otherwise halt master cpu manually.
+ */
+ while (true)
+ halt_this_cpu();
+
+ return 0;
+}
+
+int board_prep_linux(bootm_headers_t *images)
+{
+ int ret, ofst;
+ char mask[15];
+
+ ret = envs_read_validate_common(env_map_mask);
+ if (ret)
+ return ret;
+
+ /* Rollback to default values */
+ if (!env_common.core_mask.set) {
+ env_common.core_mask.val = ALL_CPU_MASK;
+ env_common.core_mask.set = true;
+ }
+
+ printf("CPU start mask is %#x\n", env_common.core_mask.val);
+
+ if (!is_cpu_used(MASTER_CPU_ID))
+ pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
+
+ /*
+ * If we want to launch linux on all CPUs we don't need to patch
+ * linux DTB as it is default configuration
+ */
+ if (env_common.core_mask.val == ALL_CPU_MASK)
+ return 0;
+
+ if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
+ pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
+ return 0;
+ }
+
+ /* patch '/possible-cpus' property according to cpu mask */
+ ofst = fdt_path_offset(images->ft_addr, "/");
+ sprintf(mask, "%s%s%s%s",
+ is_cpu_used(0) ? "0," : "",
+ is_cpu_used(1) ? "1," : "",
+ is_cpu_used(2) ? "2," : "",
+ is_cpu_used(3) ? "3," : "");
+ ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
+ /*
+ * If we failed to patch '/possible-cpus' property we don't need break
+ * linux loading process: kernel will handle it but linux will print
+ * warning like "Timeout: CPU1 FAILED to comeup !!!".
+ * So warn here about error, but return 0 like no error had occurred.
+ */
+ if (ret)
+ pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
+ ret);
+
+ return 0;
+}
+
+void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+ void (*kernel_entry)(int zero, int arch, uint params);
+ u32 cpu_start_reg;
+
+ kernel_entry = (void (*)(int, int, uint))entry;
+
+ /* Prepare CREG_CPU_START for kicking chosen CPUs */
+ cpu_start_reg = prepare_cpu_ctart_reg();
+
+ /* In case of run without hsdk_init */
+ slave_cpu_set_boot_addr(entry);
+
+ /* In case of run with hsdk_init */
+ for (u32 i = 0; i < NR_CPUS; i++) {
+ env_core.entry[i].val = entry;
+ env_core.entry[i].set = true;
+ }
+ /* sync cross_cpu struct as we updated core-entry variables */
+ sync_cross_cpu_data();
+
+ /* Kick chosen slave CPUs */
+ writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
+
+ if (is_cpu_used(0))
+ kernel_entry(zero, arch, params);
+}
+
+static int hsdk_go_prepare_and_run(void)
+{
+ /* Prepare CREG_CPU_START for kicking chosen CPUs */
+ u32 reg = prepare_cpu_ctart_reg();
+
+ if (env_common.halt_on_boot)
+ printf("CPU will halt before application start, start application with debugger.\n");
+
+ return hsdk_go_run(reg);
+}
+
+static int do_hsdk_go(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret;
+
+ /*
+ * Check for 'halt' parameter. 'halt' = enter halt-mode just before
+ * starting the application; can be used for debug.
+ */
+ if (argc > 1) {
+ env_common.halt_on_boot = !strcmp(argv[1], "halt");
+ if (!env_common.halt_on_boot) {
+ pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ ret = check_master_cpu_id();
+ if (ret)
+ return ret;
+
+ ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
+ if (ret)
+ return ret;
+
+ /* sync cross_cpu struct as we updated core-entry variables */
+ sync_cross_cpu_data();
+
+ ret = hsdk_go_prepare_and_run();
+
+ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ hsdk_go, 3, 0, do_hsdk_go,
+ "Synopsys HSDK specific command",
+ " - Boot stand-alone application on HSDK\n"
+ "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
+);
+
+static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ static bool done = false;
+ int ret;
+
+ /* hsdk_init can be run only once */
+ if (done) {
+ printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = prepare_cpus();
+ if (!ret)
+ done = true;
+
+ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ hsdk_init, 1, 0, do_hsdk_init,
+ "Synopsys HSDK specific command",
+ "- Init HSDK HW\n"
+);
+
+static int do_hsdk_clock_set(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret = 0;
+
+ /* Strip off leading subcommand argument */
+ argc--;
+ argv++;
+
+ envs_cleanup_common(env_map_clock);
+
+ if (!argc) {
+ printf("Set clocks to values specified in environment\n");
+ ret = envs_read_common(env_map_clock);
+ } else {
+ printf("Set clocks to values specified in args\n");
+ ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
+ }
+
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ ret = envs_validate_common(env_map_clock);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ /* Setup clock tree HW */
+ setup_clocks();
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_get(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong rate;
+
+ if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
+ return CMD_RET_FAILURE;
+
+ if (env_set_ulong("cpu_freq", rate))
+ return CMD_RET_FAILURE;
+
+ if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
+ return CMD_RET_FAILURE;
+
+ if (env_set_ulong("tun_freq", rate))
+ return CMD_RET_FAILURE;
+
+ if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
+ return CMD_RET_FAILURE;
+
+ if (env_set_ulong("axi_freq", rate))
+ return CMD_RET_FAILURE;
+
+ printf("Clock values are saved to environment\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_print(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ /* Main clocks */
+ soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ /*
+ * NOTE: as of today we don't use some peripherals like HDMI / EBI
+ * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
+ * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
+ * functional and we can print their clocks if it is required
+ */
+
+ /* CPU clock domain */
+ soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
+ printf("\n");
+
+ /* SYS clock domain */
+ soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
+/* soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); */
+ soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
+/* soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
+ soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
+ printf("\n");
+
+ /* DDR clock domain */
+ soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
+ printf("\n");
+
+ /* HDMI clock domain */
+/* soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); */
+/* soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); */
+/* printf("\n"); */
+
+ /* TUN clock domain */
+ soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
+ printf("\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+cmd_tbl_t cmd_hsdk_clock[] = {
+ U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
+ U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
+ U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
+ U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
+};
+
+static int do_hsdk_clock(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'hsdk_clock' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
+ if (!c)
+ return CMD_RET_USAGE;
+
+ return c->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
+ "Synopsys HSDK specific clock command",
+ "set - Set clock to values specified in environment / command line arguments\n"
+ "hsdk_clock get - Save clock values to environment\n"
+ "hsdk_clock print - Print main clock values to console\n"
+ "hsdk_clock print_all - Print all clock values to console\n"
+);
+
+/* init calls */
+int board_early_init_f(void)
+{
+ /*
+ * Setup AXI apertures unconditionally as we want to have DDR
+ * in 0x00000000 region when we are kicking slave cpus.
+ */
+ init_memory_bridge();
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /*
+ * TODO: Init USB here to be able read environment from USB MSD.
+ * It can be done with usb_init() call. We can't do it right now
+ * due to brocken USB IP SW reset and lack of USB IP HW reset in
+ * linux kernel (if we init USB here we will break USB in linux)
+ */
+
+ /*
+ * Flush all d$ as we want to use uncached area with st.di / ld.di
+ * instructions and we don't want to have any dirty line in L1d$ or SL$
+ * in this area. It is enough to flush all d$ once here as we access to
+ * uncached area with regular st (non .di) instruction only when we copy
+ * data during u-boot relocation.
+ */
+ flush_dcache_all();
+
+ printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ /*
+ * Populate environment with clock frequency values -
+ * run hsdk_clock get callback without uboot command run.
+ */
+ do_hsdk_clock_get(NULL, 0, 0, NULL);
+
+ return 0;
+}
int board_mmc_init(bd_t *bis)
{
@@ -44,7 +1034,7 @@
* Switch SDIO external ciu clock divider from default div-by-8 to
* minimum possible div-by-2.
*/
- writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
+ writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
memset(host, 0, sizeof(struct dwmci_host));
host->name = "Synopsys Mobile storage";
@@ -57,28 +1047,3 @@
return 0;
}
-
-#define RESET_VECTOR_ADDR 0x0
-
-void smp_set_core_boot_addr(unsigned long addr, int corenr)
-{
- /* All cores have reset vector pointing to 0 */
- writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
-
- /* Make sure other cores see written value in memory */
- flush_dcache_all();
-}
-
-void smp_kick_all_cpus(void)
-{
-#define BITS_START_CORE1 1
-#define BITS_START_CORE2 2
-#define BITS_START_CORE3 3
-
- int cmd = readl((void __iomem *)CREG_CPU_START);
-
- cmd |= (1 << BITS_START_CORE1) |
- (1 << BITS_START_CORE2) |
- (1 << BITS_START_CORE3);
- writel(cmd, (void __iomem *)CREG_CPU_START);
-}
diff --git a/board/tcl/sl50/Kconfig b/board/tcl/sl50/Kconfig
index d0068d9..1b3f5cf 100644
--- a/board/tcl/sl50/Kconfig
+++ b/board/tcl/sl50/Kconfig
@@ -12,14 +12,4 @@
config SYS_CONFIG_NAME
default "am335x_sl50"
-config CONS_INDEX
- int "UART used for console"
- range 1 6
- default 1
- help
- The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
- in documentation, etc) available to it. Depending on your specific
- board you may want something other than UART0 as for example the IDK
- uses UART3 so enter 4 here.
-
endif
diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c
index e5bec57..c4dad69 100644
--- a/board/technologic/ts4800/ts4800.c
+++ b/board/technologic/ts4800/ts4800.c
@@ -17,6 +17,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/mx5_video.h>
+#include <environment.h>
#include <mmc.h>
#include <input.h>
#include <fsl_esdhc.h>
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index c6690fa..1d8b605 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <misc.h>
#include <spl.h>
#include <syscon.h>
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 97374bd..b66ca1a 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -12,16 +12,6 @@
config SYS_CONFIG_NAME
default "am335x_evm"
-config CONS_INDEX
- int "UART used for console"
- range 1 6
- default 1
- help
- The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
- in documentation, etc) available to it. Depending on your specific
- board you may want something other than UART0 as for example the IDK
- uses UART3 so enter 4 here.
-
config NOR
bool "Support for NOR flash"
help
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b144fd1..c33bf58 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -264,7 +264,7 @@
if (board_is_evm_sk())
return &dpll_ddr3_303MHz[ind];
- else if (board_is_bone_lt() || board_is_icev2())
+ else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
return &dpll_ddr3_400MHz[ind];
else if (board_is_evm_15_or_later())
return &dpll_ddr3_303MHz[ind];
@@ -295,7 +295,7 @@
if (bone_not_connected_to_ac_power())
freq = MPUPLL_M_600;
- if (board_is_bone_lt())
+ if (board_is_pb() || board_is_bone_lt())
freq = MPUPLL_M_1000;
switch (freq) {
@@ -341,7 +341,7 @@
* Override what we have detected since we know if we have
* a Beaglebone Black it supports 1GHz.
*/
- if (board_is_bone_lt())
+ if (board_is_pb() || board_is_bone_lt())
freq = MPUPLL_M_1000;
switch (freq) {
@@ -542,7 +542,7 @@
if (board_is_evm_sk())
config_ddr(303, &ioregs_evmsk, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
- else if (board_is_bone_lt())
+ else if (board_is_pb() || board_is_bone_lt())
config_ddr(400, &ioregs_bonelt,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
@@ -563,8 +563,8 @@
}
#endif
-#if !defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
static void request_and_set_gpio(int gpio, char *name, int val)
{
int ret;
@@ -621,8 +621,8 @@
gpmc_init();
#endif
-#if !defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
if (board_is_icev2()) {
int rv;
u32 reg;
@@ -767,6 +767,16 @@
}
#endif
+ if (!env_get("serial#")) {
+ char *board_serial = env_get("board_serial");
+ char *ethaddr = env_get("ethaddr");
+
+ if (!board_serial || !strncmp(board_serial, "unknown", 7))
+ env_set("serial#", ethaddr);
+ else
+ env_set("serial#", board_serial);
+ }
+
return 0;
}
#endif
@@ -931,6 +941,8 @@
return 0;
else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
return 0;
+ else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
+ return 0;
else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
return 0;
else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index e13fcff..bab5b77 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -34,6 +34,11 @@
return board_ti_is("A335BNLT");
}
+static inline int board_is_pb(void)
+{
+ return board_ti_is("A335PBGL");
+}
+
static inline int board_is_bbg1(void)
{
return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
@@ -41,7 +46,7 @@
static inline int board_is_beaglebonex(void)
{
- return board_is_bone() || board_is_bone_lt() || board_is_bbg1();
+ return board_is_pb() || board_is_bone() || board_is_bone_lt() || board_is_bbg1();
}
static inline int board_is_evm_sk(void)
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index ad85b3a..aa18760 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -390,6 +390,9 @@
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
+ } else if (board_is_pb()) {
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
} else if (board_is_icev2()) {
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(gpio0_18_pin_mux);
diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
index 83645ac..bf09806 100644
--- a/board/ti/am43xx/MAINTAINERS
+++ b/board/ti/am43xx/MAINTAINERS
@@ -7,4 +7,5 @@
F: configs/am43xx_evm_ethboot_defconfig
F: configs/am43xx_evm_qspiboot_defconfig
F: configs/am43xx_evm_usbhost_boot_defconfig
+F: configs/am43xx_evm_rtconly_defconfig
F: configs/am43xx_hs_evm_defconfig
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 715960a..0431cd4 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <i2c.h>
#include <linux/errno.h>
#include <spl.h>
@@ -520,6 +521,62 @@
writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
}
+enum {
+ RTC_BOARD_EPOS = 1,
+ RTC_BOARD_EVM14,
+ RTC_BOARD_EVM12,
+ RTC_BOARD_GPEVM,
+ RTC_BOARD_SK,
+};
+
+/*
+ * In the rtc_only+DRR in self-refresh boot path we have the board type info
+ * in the rtc scratch pad register hence we bypass the costly i2c reads to
+ * eeprom and directly programthe board name string
+ */
+void rtc_only_update_board_type(u32 btype)
+{
+ const char *name = "";
+ const char *rev = "1.0";
+
+ switch (btype) {
+ case RTC_BOARD_EPOS:
+ name = "AM43EPOS";
+ break;
+ case RTC_BOARD_EVM14:
+ name = "AM43__GP";
+ rev = "1.4";
+ break;
+ case RTC_BOARD_EVM12:
+ name = "AM43__GP";
+ rev = "1.2";
+ break;
+ case RTC_BOARD_GPEVM:
+ name = "AM43__GP";
+ break;
+ case RTC_BOARD_SK:
+ name = "AM43__SK";
+ break;
+ }
+ ti_i2c_eeprom_am_set(name, rev);
+}
+
+u32 rtc_only_get_board_type(void)
+{
+ if (board_is_eposevm())
+ return RTC_BOARD_EPOS;
+ else if (board_is_evm_14_or_later())
+ return RTC_BOARD_EVM14;
+ else if (board_is_evm_12_or_later())
+ return RTC_BOARD_EVM12;
+ else if (board_is_gpevm())
+ return RTC_BOARD_GPEVM;
+ else if (board_is_sk())
+ return RTC_BOARD_SK;
+
+ return 0;
+}
+
void sdram_init(void)
{
/*
@@ -852,10 +909,14 @@
}
#endif
-#ifdef CONFIG_SPL_LOAD_FIT
+#if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
int board_fit_config_name_match(const char *name)
{
- if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
+ bool eeprom_read = board_ti_was_eeprom_read();
+
+ if (!strcmp(name, "am4372-generic") && !eeprom_read)
+ return 0;
+ else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
return 0;
else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
return 0;
@@ -868,6 +929,16 @@
}
#endif
+#ifdef CONFIG_DTB_RESELECT
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig
index cead0f4..0c56682 100644
--- a/board/ti/am57xx/Kconfig
+++ b/board/ti/am57xx/Kconfig
@@ -9,15 +9,6 @@
config SYS_CONFIG_NAME
default "am57xx_evm"
-config CONS_INDEX
- int "UART used for console"
- range 1 6
- default 3
- help
- The AM57x (and DRA7xx) SoC has a total of 6 UARTs available to it.
- Depending on your specific board you may want something other than UART3
- here.
-
source "board/ti/common/Kconfig"
endif
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index d8402f2..1d55264 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -521,6 +521,14 @@
if (generate_fake_mac)
omap_die_id_usbethaddr();
+#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
+ if (strlen(CONFIG_MTDIDS_DEFAULT))
+ env_set("mtdids", CONFIG_MTDIDS_DEFAULT);
+
+ if (strlen(CONFIG_MTDPARTS_DEFAULT))
+ env_set("mtdparts", CONFIG_MTDPARTS_DEFAULT);
+#endif
+
return 0;
}
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
index b642113..f6a8e07 100644
--- a/board/ti/dra7xx/Kconfig
+++ b/board/ti/dra7xx/Kconfig
@@ -9,15 +9,6 @@
config SYS_CONFIG_NAME
default "dra7xx_evm"
-config CONS_INDEX
- int "UART used for console"
- range 1 6
- default 1
- help
- The DRA7xx (and AM57x) SoC has a total of 6 UARTs available to it.
- Depending on your specific board you may want something other than UART1
- here.
-
source "board/ti/common/Kconfig"
endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index b5dcaa5..32c9eca 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -372,13 +372,10 @@
};
const struct pad_conf_entry early_padconf[] = {
-#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
{UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
-#elif (CONFIG_CONS_INDEX == 3)
{UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
{UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
-#endif
{I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
{I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
};
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index cdde6a8..4a0f829 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <cpsw.h>
+#include <environment.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index cb40cc5..abc961a 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <spl.h>
#include <netdev.h>
#include <asm/cache.h>
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index 741b3ac..4bbbd81 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -18,6 +18,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <ns16550.h>
#include <twl4030.h>
#include <asm/io.h>
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index 6e12d27..d6d3671 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <g_dnl.h>
#include <linux/libfdt.h>
diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig
index bc1edcf..b721ed1 100644
--- a/board/vscom/baltos/Kconfig
+++ b/board/vscom/baltos/Kconfig
@@ -12,13 +12,4 @@
config SYS_CONFIG_NAME
default "baltos"
-config CONS_INDEX
- int "UART used for console"
- range 1 6
- default 1
- help
- The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
- in documentation, etc) available to it. Depending on your specific
- board you may want something other than UART0.
-
endif
diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
index e0dc4fe..fc6463a 100644
--- a/board/xilinx/zynq/MAINTAINERS
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -1,6 +1,7 @@
ZYNQ BOARD
M: Michal Simek <monstr@monstr.eu>
S: Maintained
+F: arch/arm/dts/zynq-*
F: board/xilinx/zynq/
F: include/configs/zynq*.h
F: configs/zynq_*_defconfig
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index fb8eab0..838ac0f 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -6,9 +6,11 @@
*/
#include <common.h>
+#include <dm/uclass.h>
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
+#include <wdt.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
@@ -33,6 +35,22 @@
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+static struct udevice *watchdog_dev;
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+# if defined(CONFIG_WDT)
+ /* bss is not cleared at time when watchdog_reset() is called */
+ watchdog_dev = NULL;
+# endif
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
@@ -75,6 +93,15 @@
}
#endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+ puts("Watchdog: Not found!\n");
+ } else {
+ wdt_start(watchdog_dev, 0, 0);
+ puts("Watchdog: Started\n");
+ }
+# endif
+
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init();
@@ -164,3 +191,25 @@
return 0;
}
#endif
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+# if !defined(CONFIG_SPL_BUILD)
+ static ulong next_reset;
+ ulong now;
+
+ if (!watchdog_dev)
+ return;
+
+ now = timer_get_us();
+
+ /* Do not reset the watchdog too often */
+ if (now > next_reset) {
+ wdt_reset(watchdog_dev);
+ next_reset = now + 1000;
+ }
+# endif
+}
+#endif
diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig
new file mode 100644
index 0000000..7d1f739
--- /dev/null
+++ b/board/xilinx/zynqmp/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQMP
+
+config CMD_ZYNQMP
+ bool "Enable ZynqMP specific commands"
+ default y
+ help
+ Enable ZynqMP specific commands like "zynqmp secure"
+ which is used for zynqmp secure image verification.
+ The secure image is a xilinx specific BOOT.BIN with
+ either authentication or encryption or both encryption
+ and authentication feature enabled while generating
+ BOOT.BIN using Xilinx bootgen tool.
+
+endif
diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 69edbf2..bb39f87 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -1,6 +1,7 @@
XILINX_ZYNQMP BOARDS
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
+F: arch/arm/dts/zynqmp-*
F: board/xilinx/zynqmp/
F: include/configs/xilinx_zynqmp*
F: configs/xilinx_zynqmp*
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 75aab92..3b7a10e 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -26,6 +26,10 @@
obj-y += $(init-objs)
endif
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
+endif
+
# Suppress "warning: function declaration isn't a prototype"
CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
new file mode 100644
index 0000000..6712d7b
--- /dev/null
+++ b/board/xilinx/zynqmp/cmds.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static int zynqmp_verify_secure(u8 *key_ptr, u8 *src_ptr, u32 len)
+{
+ int ret;
+ u32 src_lo, src_hi;
+ u32 key_lo = 0;
+ u32 key_hi = 0;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u64 addr;
+
+ if ((ulong)src_ptr != ALIGN((ulong)src_ptr,
+ CONFIG_SYS_CACHELINE_SIZE)) {
+ printf("Failed: source address not aligned:%p\n", src_ptr);
+ return -EINVAL;
+ }
+
+ src_lo = lower_32_bits((ulong)src_ptr);
+ src_hi = upper_32_bits((ulong)src_ptr);
+ flush_dcache_range((ulong)src_ptr, (ulong)(src_ptr + len));
+
+ if (key_ptr) {
+ key_lo = lower_32_bits((ulong)key_ptr);
+ key_hi = upper_32_bits((ulong)key_ptr);
+ flush_dcache_range((ulong)key_ptr,
+ (ulong)(key_ptr + KEY_PTR_LEN));
+ }
+
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD, src_lo, src_hi,
+ key_lo, key_hi, ret_payload);
+ if (ret) {
+ printf("Failed: secure op status:0x%x\n", ret);
+ } else {
+ addr = (u64)ret_payload[1] << 32 | ret_payload[2];
+ printf("Verified image at 0x%llx\n", addr);
+ env_set_hex("zynqmp_verified_img_addr", addr);
+ }
+
+ return ret;
+}
+
+/**
+ * do_zynqmp - Handle the "zynqmp" command-line command
+ * @cmdtp: Command data struct pointer
+ * @flag: Command flag
+ * @argc: Command-line argument count
+ * @argv: Array of command-line arguments
+ *
+ * Processes the zynqmp specific commands
+ *
+ * Return: return 0 on success and CMD_RET_USAGE incase of misuse and error
+ */
+static int do_zynqmp(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u64 src_addr;
+ u32 len;
+ u8 *key_ptr = NULL;
+ u8 *src_ptr;
+ int ret;
+
+ if (argc > 5 || argc < 4 || strncmp(argv[1], "secure", 6))
+ return CMD_RET_USAGE;
+
+ src_addr = simple_strtoull(argv[2], NULL, 16);
+
+ len = simple_strtoul(argv[3], NULL, 16);
+
+ if (argc > 4)
+ key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4],
+ NULL, 16);
+
+ src_ptr = (uint8_t *)(uintptr_t)src_addr;
+
+ ret = zynqmp_verify_secure(key_ptr, src_ptr, len);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+/***************************************************/
+#ifdef CONFIG_SYS_LONGHELP
+static char zynqmp_help_text[] =
+ "secure src len [key_addr] - verifies secure images of $len bytes\n"
+ " long at address $src. Optional key_addr\n"
+ " can be specified if user key needs to\n"
+ " be used for decryption\n";
+#endif
+
+U_BOOT_CMD(
+ zynqmp, 5, 1, do_zynqmp,
+ "Verify and load secure images",
+ zynqmp_help_text
+)
diff --git a/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
new file mode 100644
index 0000000..cb8ec25
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
@@ -0,0 +1,745 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F0E2412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D0419U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000802U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x281C0404U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070200U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320E08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+ psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0x0000003FU, 0x00000000U);
+ psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0000807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD402368, 0x000000FFU, 0x000000E0U);
+ psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x000000E0U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402370, 0x000000FFU, 0x000000C9U);
+ psu_mask_write(0xFD402374, 0x000000FFU, 0x000000D2U);
+ psu_mask_write(0xFD402378, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40237C, 0x000000B3U, 0x000000B0U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x000000C9U);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x000000D2U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40637C, 0x000000B3U, 0x000000B0U);
+ psu_mask_write(0xFD402360, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD406360, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40506C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD4040F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x0000009CU);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x00000039U);
+ psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD405990, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD405924, 0x000000FFU, 0x0000009CU);
+ psu_mask_write(0xFD405928, 0x000000FFU, 0x00000039U);
+ psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD405900, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000022U);
+ psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401C14, 0x000000FFU, 0x000000E6U);
+ psu_mask_write(0xFD401C40, 0x0000001FU, 0x0000000CU);
+ psu_mask_write(0xFD40194C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401950, 0x00000007U, 0x00000006U);
+ psu_mask_write(0xFD405C14, 0x000000FFU, 0x000000E6U);
+ psu_mask_write(0xFD405C40, 0x0000001FU, 0x0000000CU);
+ psu_mask_write(0xFD40594C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD405950, 0x00000007U, 0x00000006U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD400048, 0x000000FFU, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000001U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+ psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+ psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+ psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+ psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFF9B0000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFF9B0014, 0x00000003U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+ Xil_Out32(0xFD070180U, 0x00AB002BU);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 =
+ L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) | 0x20 | 0x4 |
+ ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 =
+ L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) | 0x40 | 0x8 |
+ ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ unsigned int tmp_regval;
+
+ tmp_regval = Xil_In32(0xFD690040);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690040, tmp_regval);
+
+ tmp_regval = Xil_In32(0xFD690030);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
new file mode 100644
index 0000000..2c84587
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
@@ -0,0 +1,467 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E60EC6CU);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013000U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000300U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010802U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020204U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x003800D4U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x0000003DU);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x64032010U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x38801C20U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0604U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00040200U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFD615000, 0x00000300U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+ Xil_Out32(0xFD070180U, 0x00800020U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zc1275-revA b/board/xilinx/zynqmp/zynqmp-zc1275-revA
new file mode 120000
index 0000000..7abf1dc
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1275-revA
@@ -0,0 +1 @@
+zynqmp-zc1254-revA
\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
new file mode 100644
index 0000000..ab106c6
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
@@ -0,0 +1,912 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0xFC7FE07FU, 0x54000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03004U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+ psu_mask_write(0xFF180320, 0x33803380U, 0x02801280U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000011U);
+ psu_mask_write(0xFD402860, 0x00000084U, 0x00000004U);
+ psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+ psu_mask_write(0xFD402868, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000018U);
+ psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000D3U);
+ psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000DAU);
+ psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000096U);
+ psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000096U);
+ psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+ psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+ psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000096U);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+ psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+ psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+ psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+ psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+ mask_poll(0xFD40E3E4, 0x00000010U);
+ psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184D1BU);
+ psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081906U);
+ psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+ psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EEFU);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+ int count = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
new file mode 100644
index 0000000..bcf3aedf
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
@@ -0,0 +1,900 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+ psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+ psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+ psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+ psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+ psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+ psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+ psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+ psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+ psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+ psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+ psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+ psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+ psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+ psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+ psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+ psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+ psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+ psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+ psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+ psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+ psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+ psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EEFU);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+ int count = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
new file mode 100644
index 0000000..bcf3aedf
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
@@ -0,0 +1,900 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+ psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+ psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+ psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+ psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+ psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+ psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+ psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+ psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+ psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+ psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+ psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+ psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+ psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+ psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+ psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+ psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+ psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+ psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+ psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+ psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+ psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+ psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EEFU);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+ int count = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
new file mode 100644
index 0000000..bcf3aedf
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
@@ -0,0 +1,900 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+ psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+ psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+ psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+ psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+ psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+ psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+ psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+ psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+ psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+ psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+ psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+ psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+ psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+ psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+ psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+ psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+ psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+ psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+ psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+ psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+ psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+ psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+ psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EEFU);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+ int count = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
new file mode 100644
index 0000000..8e62a9c
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
@@ -0,0 +1,926 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+ psu_mask_write(0xFF18030C, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x000000E0U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xAF000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x0003F000U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000240U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000020U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x00003380U, 0x00000080U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000800U);
+ psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000800U);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U);
+ mask_delay(1);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0000U);
+ mask_delay(5);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD40D924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD40D928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U);
+ psu_mask_write(0xFD410014, 0x00000077U, 0x00000011U);
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+ psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+ psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+ psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+ psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+ psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+ psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+ psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+ psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+ psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+ psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+ psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+ psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+ psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+ psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+ psu_mask_write(0xFD480094, 0x00004200U, 0x00004200U);
+ psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+ psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+ psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+ psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+ psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+ psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+ psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+ psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U);
+ psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+ psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+ psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+ psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EEFU);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+ int count = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
new file mode 100644
index 0000000..27e2ab6
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
@@ -0,0 +1,993 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000400U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC3081020U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000102U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x0028B090U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00404310U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00208030U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x0002020AU);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00360000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00001205U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00240012U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0E0B010CU);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00030412U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x04070F0DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00A05000U);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x05040306U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01020404U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000201U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030303U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x810B0008U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x00E32DCBU);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8206U);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00A00070U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000901U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x00000015U);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F060606U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F03D28U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x85642AD0U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xA0AA0580U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x05102000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A040A1U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06180C08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x2816050AU);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080064U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00602B08U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00231008U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x0000080EU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000024U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000012U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x810091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00030236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x00894C58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00BD0CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00BD0CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00BD0CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00BD0CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00BD0CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x05102000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x05102000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x05102000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x05102000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x05102000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x05102000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ psu_mask_write(0xFD090000, 0x0000FFFFU, 0x00000845U);
+ psu_mask_write(0xFD090004, 0x002DB5ADU, 0x002DB5ADU);
+ psu_mask_write(0xFD090800, 0xFFFFFFFFU, 0x00000001U);
+ psu_mask_write(0xFD09000C, 0x0000007FU, 0x00000010U);
+ psu_mask_write(0xFD090010, 0x0000007FU, 0x00000010U);
+ psu_mask_write(0xFD380008, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD38001C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD390008, 0x0000000FU, 0x00000003U);
+ psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000003U);
+ psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000003U);
+ psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000003U);
+ psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000003U);
+ psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000003U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x51000006U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B00000U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x039E1FFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0001007CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000FC0U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008001U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x33803380U, 0x00800080U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U);
+ psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40E094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40E374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40E37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD40D06C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD40C0F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD40D924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+ psu_mask_write(0xFD410014, 0x00000077U, 0x00000033U);
+ psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+ psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+ mask_poll(0xFD40E3E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+ >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+ Xil_Out32(0xFD090000U, 0x00000845U);
+ Xil_Out32(0xFD090004U, 0x003FFFFFU);
+ Xil_Out32(0xFD09000CU, 0x00000010U);
+ Xil_Out32(0xFD090010U, 0x00000010U);
+ Xil_Out32(0xFD090800U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+
+ Xil_Out32(0xFD070010U, 0x80000038U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000331U);
+ Xil_Out32(0xFD070010U, 0x80000038U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000B36U);
+ Xil_Out32(0xFD070010U, 0x80000038U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000C21U);
+ Xil_Out32(0xFD070010U, 0x80000038U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000E19U);
+ Xil_Out32(0xFD070010U, 0x80000038U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00001616U);
+ Xil_Out32(0xFD070010U, 0x80000038U);
+ Xil_Out32(0xFD070010U, 0x80000030U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0014FE01);
+
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x8000007E)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x010091C7U);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80008FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x810091C7U);
+ Xil_Out32(0xFD070180U, 0x010B0008U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD070020U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x0000001FU, 0x0000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
new file mode 100644
index 0000000..aa6496c
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
@@ -0,0 +1,826 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000820CU);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+ psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000600FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000600FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000600FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000600FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000600FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000600FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000600FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x008005F0U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04121U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28220708U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080200U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B08U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00340F09U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A2A58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080788, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0807C0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080888, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0808C0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080988, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0809C0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A88, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080AC0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B88, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080BC0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C88, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080CC0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D88, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080DC0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E88, 0xFFFFFFFFU, 0x0000000AU);
+ psu_mask_write(0xFD080EC0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F88, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080FC0, 0xFFFFFFFFU, 0x00020000U);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+ psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U);
+ psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0xC5ACCE55U);
+ psu_mask_write(0xFE980004, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+ psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+ psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+ psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+ psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+ psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+ psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+ psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+ psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+ psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00003FBFU, 0x00002417U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+ mask_poll(0xFD40E3E4, 0x00000010U);
+ psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+ psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+ psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+ psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ int dpll_divisor;
+
+ dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
+ prog_reg(0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
+ prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+ Xil_Out32(0xFD080004U, 0x00040003U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+ ;
+ prog_reg(0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg(0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg(0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg(0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg(0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
+ Xil_Out32(0xFD080004U, 0x40040071U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+ ;
+ Xil_Out32(0xFD080004U, 0x40040001U);
+ while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+ ;
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EF2U);
+ Xil_Out32(0xFD08001CU, 0x55AA5498U);
+ Xil_Out32(0xFD08142CU, 0x00041830U);
+ Xil_Out32(0xFD08146CU, 0x00041830U);
+ Xil_Out32(0xFD0814ACU, 0x00041830U);
+ Xil_Out32(0xFD0814ECU, 0x00041830U);
+ Xil_Out32(0xFD08152CU, 0x00041830U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F12302U);
+ Xil_Out32(0xFD08001CU, 0x55AA5480U);
+ Xil_Out32(0xFD08142CU, 0x00041800U);
+ Xil_Out32(0xFD08146CU, 0x00041800U);
+ Xil_Out32(0xFD0814ACU, 0x00041800U);
+ Xil_Out32(0xFD0814ECU, 0x00041800U);
+ Xil_Out32(0xFD08152CU, 0x00041800U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod;
+
+ Xil_Out32(0xFD40EC4C, 0x00000020);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+
+ if (maskstatus == 0) {
+ /* xil_printf("SERDES initialization timed out\n\r"); */
+ return maskstatus;
+ }
+
+ tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+
+ tmp_0_2 = tmp_0_1 & (0x7);
+ tmp_0_3 = tmp_0_1 & (0x38);
+
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ tmp_0_2_mod = (tmp_0_2 << 1) | (0x1);
+ tmp_0_2_mod = (tmp_0_2_mod << 4);
+
+ tmp_0_3 = tmp_0_3 >> 3;
+ Xil_Out32(0xFD40EC4C, tmp_0_3);
+
+ Xil_Out32(0xFD40EC48, tmp_0_2_mod);
+ return maskstatus;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ unsigned int regvalue;
+ unsigned int tmp_regval;
+
+ Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000);
+ Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000);
+ Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000);
+
+ regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU));
+ regvalue &= 0x7;
+ Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue);
+
+ Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000);
+
+ tmp_regval = Xil_In32(0xFD690040);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690040, tmp_regval);
+
+ tmp_regval = Xil_In32(0xFD690030);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+
+ status &= init_serdes();
+ init_peripheral();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
new file mode 100644
index 0000000..b7e0300
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
@@ -0,0 +1,878 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07240F08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0x7B3F003FU, 0x52240000U);
+ psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+ psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+ psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+ psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+ psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+ psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+ psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+ psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+ psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+ psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+ mask_poll(0xFD40E3E4, 0x00000010U);
+ psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+ psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+ psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+ psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EEFU);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revC b/board/xilinx/zynqmp/zynqmp-zcu104-revC
new file mode 120000
index 0000000..529e18f
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zcu104-revC
@@ -0,0 +1 @@
+zynqmp-zcu104-revA
\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
new file mode 100644
index 0000000..e6fa477
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
@@ -0,0 +1,802 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015900U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x80008E69U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010502U);
+ psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A02U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010A02U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010A02U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41980B06U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28210008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F09U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+ psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
+ psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+ psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+ psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+ psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+ psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+ psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD405978, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD409978, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D978, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+ psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+ psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+ psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+ psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00003FFFU, 0x00002457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000400U, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+ mask_poll(0xFD40E3E4, 0x00000010U);
+ psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+ psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+ psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+ psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EF2U);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F12302U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod;
+
+ Xil_Out32(0xFD40EC4C, 0x00000020);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+
+ if (maskstatus == 0) {
+ xil_printf("SERDES initialization timed out\n\r");
+ return maskstatus;
+ }
+
+ tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+
+ tmp_0_2 = tmp_0_1 & (0x7);
+ tmp_0_3 = tmp_0_1 & (0x38);
+
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ tmp_0_2_mod = (tmp_0_2 << 1) | (0x1);
+ tmp_0_2_mod = (tmp_0_2_mod << 4);
+
+ tmp_0_3 = tmp_0_3 >> 3;
+ Xil_Out32(0xFD40EC4C, tmp_0_3);
+
+ Xil_Out32(0xFD40EC48, tmp_0_2_mod);
+ return maskstatus;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ unsigned int regvalue;
+ unsigned int tmp_regval;
+
+ Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000);
+ Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000);
+ Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000);
+
+ regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU));
+ regvalue &= 0x7;
+ Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue);
+
+ Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000);
+
+ tmp_regval = Xil_In32(0xFD690040);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690040, tmp_regval);
+
+ tmp_regval = Xil_In32(0xFD690030);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+
+ status &= init_serdes();
+ init_peripheral();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ff0b3c7..0d1bd54 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -31,6 +31,7 @@
u32 id;
u32 ver;
char *name;
+ bool evexists;
} zynqmp_devices[] = {
{
.id = 0x10,
@@ -53,11 +54,13 @@
{
.id = 0x20,
.name = "5ev",
+ .evexists = 1,
},
{
.id = 0x20,
.ver = 0x100,
.name = "5eg",
+ .evexists = 1,
},
{
.id = 0x20,
@@ -67,11 +70,13 @@
{
.id = 0x21,
.name = "4ev",
+ .evexists = 1,
},
{
.id = 0x21,
.ver = 0x100,
.name = "4eg",
+ .evexists = 1,
},
{
.id = 0x21,
@@ -81,11 +86,13 @@
{
.id = 0x30,
.name = "7ev",
+ .evexists = 1,
},
{
.id = 0x30,
.ver = 0x100,
.name = "7eg",
+ .evexists = 1,
},
{
.id = 0x30,
@@ -219,20 +226,48 @@
return val;
}
+#define ZYNQMP_VERSION_SIZE 9
+#define ZYNQMP_PL_STATUS_BIT 9
+#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
+#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
+
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
u32 i, id, ver;
+ char *buf;
+ static char name[ZYNQMP_VERSION_SIZE];
id = chip_id(IDCODE);
ver = chip_id(IDCODE2);
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
- if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
- return zynqmp_devices[i].name;
+ if ((zynqmp_devices[i].id == id) &&
+ (zynqmp_devices[i].ver == (ver &
+ ZYNQMP_CSU_VERSION_MASK))) {
+ strncat(name, "zu", 2);
+ strncat(name, zynqmp_devices[i].name,
+ ZYNQMP_VERSION_SIZE - 3);
+ break;
+ }
}
- return "unknown";
+
+ if (i >= ARRAY_SIZE(zynqmp_devices))
+ return "unknown";
+
+ if (!zynqmp_devices[i].evexists)
+ return name;
+
+ if (ver & ZYNQMP_PL_STATUS_MASK)
+ return name;
+
+ if (strstr(name, "eg") || strstr(name, "ev")) {
+ buf = strstr(name, "e");
+ *buf = '\0';
+ }
+
+ return name;
}
#endif
@@ -250,8 +285,6 @@
return ret;
}
-#define ZYNQMP_VERSION_SIZE 9
-
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
@@ -260,12 +293,7 @@
!defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
defined(CONFIG_SPL_BUILD))
if (current_el() != 3) {
- static char version[ZYNQMP_VERSION_SIZE];
-
- strncat(version, "zu", 2);
- zynqmppl.name = strncat(version,
- zynqmp_get_silicon_idcode_name(),
- ZYNQMP_VERSION_SIZE - 3);
+ zynqmppl.name = zynqmp_get_silicon_idcode_name();
printf("Chip ID:\t%s\n", zynqmppl.name);
fpga_init();
fpga_add(fpga_xilinx, &zynqmppl);
@@ -316,6 +344,23 @@
return 0;
}
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+ char * const argv[])
+{
+ int ret = 0;
+
+ if (current_el() > 1) {
+ smp_kick_all_cpus();
+ dcache_disable();
+ armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
+ ES_TO_AARCH64);
+ } else {
+ printf("FAIL: current EL is not above EL1\n");
+ ret = EINVAL;
+ }
+ return ret;
+}
+
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 136836d..bc1d2f3 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -423,10 +423,15 @@
menu "Memory commands"
+config CMD_BINOP
+ bool "binop"
+ help
+ Compute binary operations (xor, or, and) of byte arrays of arbitrary
+ size from memory and store the result in memory or the environment.
+
config CMD_CRC32
bool "crc32"
select HASH
- default n if ARCH_SUNXI
default y
help
Compute CRC32.
@@ -528,6 +533,15 @@
help
Simple RAM read/write test.
+if CMD_MEMTEST
+
+config SYS_ALT_MEMTEST
+ bool "Alternative test"
+ help
+ Use a more complete alternative memory test.
+
+endif
+
config CMD_MX_CYCLIC
bool "mdc, mwc"
help
@@ -568,7 +582,6 @@
config CMD_UNZIP
bool "unzip"
- default n if ARCH_SUNXI
default y if CMD_BOOTI
help
Uncompress a zip-compressed memory region.
@@ -780,14 +793,12 @@
config CMD_LOADB
bool "loadb"
- default n if ARCH_SUNXI
default y
help
Load a binary file over serial line.
config CMD_LOADS
bool "loads"
- default n if ARCH_SUNXI
default y
help
Load an S-Record file over serial line
@@ -1010,46 +1021,127 @@
endmenu
-menu "Network commands"
-
if NET
-config CMD_NET
- bool "bootp, tftpboot"
+menuconfig CMD_NET
+ bool "Network commands"
+ default y
+
+if CMD_NET
+
+config CMD_BOOTP
+ bool "bootp"
default y
help
- Network commands.
bootp - boot image via network using BOOTP/TFTP protocol
+
+config CMD_DHCP
+ bool "dhcp"
+ depends on CMD_BOOTP
+ help
+ Boot image via network using DHCP/TFTP protocol
+
+config BOOTP_BOOTPATH
+ bool "Request & store 'rootpath' from BOOTP/DHCP server"
+ default y
+ depends on CMD_BOOTP
+ help
+ Even though the config is called BOOTP_BOOTPATH, it stores the
+ path in the variable 'rootpath'.
+
+config BOOTP_DNS
+ bool "Request & store 'dnsip' from BOOTP/DHCP server"
+ default y
+ depends on CMD_BOOTP
+ help
+ The primary DNS server is stored as 'dnsip'. If two servers are
+ returned, you must set BOOTP_DNS2 to store that second server IP
+ also.
+
+config BOOTP_DNS2
+ bool "Store 'dnsip2' from BOOTP/DHCP server"
+ depends on BOOTP_DNS
+ help
+ If a DHCP client requests the DNS server IP from a DHCP server,
+ it is possible that more than one DNS serverip is offered to the
+ client. If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
+ server IP will be stored in the additional environment
+ variable "dnsip2". The first DNS serverip is always
+ stored in the variable "dnsip", when BOOTP_DNS is defined.
+
+config BOOTP_GATEWAY
+ bool "Request & store 'gatewayip' from BOOTP/DHCP server"
+ default y
+ depends on CMD_BOOTP
+
+config BOOTP_HOSTNAME
+ bool "Request & store 'hostname' from BOOTP/DHCP server"
+ default y
+ depends on CMD_BOOTP
+ help
+ The name may or may not be qualified with the local domain name.
+
+config BOOTP_SUBNETMASK
+ bool "Request & store 'netmask' from BOOTP/DHCP server"
+ default y
+ depends on CMD_BOOTP
+
+config BOOTP_PXE
+ bool "Send PXE client arch to BOOTP/DHCP server"
+ default y
+ depends on CMD_BOOTP && CMD_PXE
+ help
+ Supported for ARM, ARM64, and x86 for now.
+
+config BOOTP_PXE_CLIENTARCH
+ hex
+ depends on BOOTP_PXE
+ default 0x16 if ARM64
+ default 0x15 if ARM
+ default 0 if X86
+
+config BOOTP_VCI_STRING
+ string
+ depends on CMD_BOOTP
+ default "U-Boot.armv7" if CPU_V7 || CPU_V7M
+ default "U-Boot.armv8" if ARM64
+ default "U-Boot.arm" if ARM
+ default "U-Boot"
+
+config CMD_TFTPBOOT
+ bool "tftpboot"
+ default y
+ help
tftpboot - boot image via network using TFTP protocol
config CMD_TFTPPUT
bool "tftp put"
+ depends on CMD_TFTPBOOT
help
TFTP put command, for uploading files to a server
config CMD_TFTPSRV
bool "tftpsrv"
+ depends on CMD_TFTPBOOT
help
Act as a TFTP server and boot the first received file
+config NET_TFTP_VARS
+ bool "Control TFTP timeout and count through environment"
+ depends on CMD_TFTPBOOT
+ default y
+ help
+ If set, allows controlling the TFTP timeout through the
+ environment variable tftptimeout, and the TFTP maximum
+ timeout count through the variable tftptimeoutcountmax.
+ If unset, timeout and maximum are hard-defined as 1 second
+ and 10 timouts per TFTP transfer.
+
config CMD_RARP
bool "rarpboot"
help
Boot image via network using RARP/TFTP protocol
-config CMD_DHCP
- bool "dhcp"
- depends on CMD_NET
- help
- Boot image via network using DHCP/TFTP protocol
-
-config CMD_PXE
- bool "pxe"
- depends on CMD_NET
- select MENU
- help
- Boot image via network using PXE protocol
-
config CMD_NFS
bool "nfs"
default y
@@ -1086,6 +1178,8 @@
help
Acquire a network IP address using the link-local protocol
+endif
+
config CMD_ETHSW
bool "ethsw"
help
@@ -1094,9 +1188,13 @@
operations such as enabling / disabling a port and
viewing/maintaining the filtering database (FDB)
-endif
+config CMD_PXE
+ bool "pxe"
+ select MENU
+ help
+ Boot image via network using PXE protocol
-endmenu
+endif
menu "Misc commands"
@@ -1187,7 +1285,6 @@
# TODO: rename to CMD_SLEEP
config CMD_MISC
bool "sleep"
- default n if ARCH_SUNXI
default y
help
Delay execution for some time
diff --git a/cmd/Makefile b/cmd/Makefile
index 9a358e4..c4269ac 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -20,6 +20,7 @@
obj-$(CONFIG_CMD_SOURCE) += source.o
obj-$(CONFIG_CMD_BDI) += bdinfo.o
obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
+obj-$(CONFIG_CMD_BINOP) += binop.o
obj-$(CONFIG_CMD_BLOCK_CACHE) += blkcache.o
obj-$(CONFIG_CMD_BMP) += bmp.o
obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index de6fc48..7bea9b7 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -180,7 +180,7 @@
print_bi_flash(bd);
print_num("sramstart", bd->bi_sramstart);
print_num("sramsize", bd->bi_sramsize);
-#if defined(CONFIG_8xx) || defined(CONFIG_E500)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
diff --git a/cmd/binop.c b/cmd/binop.c
new file mode 100644
index 0000000..0002c66
--- /dev/null
+++ b/cmd/binop.c
@@ -0,0 +1,176 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <linux/ctype.h>
+
+enum {
+ OP_ID_XOR,
+ OP_ID_AND,
+ OP_ID_OR,
+};
+
+void write_to_env_var(char *varname, u8 *result, ulong len)
+{
+ char *str_output;
+ char *str_ptr;
+ int i;
+
+ str_output = malloc(len * 2 + 1);
+ str_ptr = str_output;
+
+ for (i = 0; i < len; i++) {
+ sprintf(str_ptr, "%02x", result[i]);
+ str_ptr += 2;
+ }
+ *str_ptr = '\0';
+ setenv(varname, str_output);
+
+ free(str_output);
+}
+
+void decode_hexstring(char *hexstr, u8 *result)
+{
+ int i;
+ int acc = 0;
+
+ for (i = 0; i < strlen(hexstr); ++i) {
+ char d = hexstr[i];
+ int value;
+
+ if (isdigit(d))
+ value = (d - '0');
+ else
+ value = (islower(d) ? toupper(d) : d) - 'A' + 10;
+
+ if (i % 2 == 0) {
+ acc = value * 16;
+ } else {
+ result[i / 2] = acc + value;
+ acc = 0;
+ }
+ }
+}
+
+void read_from_env_var(char *varname, u8 *result)
+{
+ char *str_value;
+
+ str_value = getenv(varname);
+ if (str_value)
+ decode_hexstring(str_value, result);
+ else
+ decode_hexstring(varname, result);
+}
+
+void read_from_mem(ulong addr, u8 *result, ulong len)
+{
+ u8 *src;
+
+ src = map_sysmem(addr, len);
+ memcpy(result, src, len);
+ unmap_sysmem(src);
+}
+
+void write_to_mem(char *varname, u8 *result, ulong len)
+{
+ ulong addr;
+ u8 *buf;
+
+ addr = simple_strtoul(varname, NULL, 16);
+ buf = map_sysmem(addr, len);
+ memcpy(buf, result, len);
+ unmap_sysmem(buf);
+}
+
+static int do_binop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong len;
+ u8 *result, *src1, *src2;
+ char *oparg, *lenarg, *src1arg, *src2arg, *destarg;
+ int i, op;
+
+ if (argc < 5)
+ return CMD_RET_USAGE;
+
+ oparg = argv[1];
+ lenarg = argv[2];
+ src1arg = argv[3];
+ src2arg = argv[4];
+
+ if (!strcmp(oparg, "xor"))
+ op = OP_ID_XOR;
+ else if (!strcmp(oparg, "or"))
+ op = OP_ID_OR;
+ else if (!strcmp(oparg, "and"))
+ op = OP_ID_AND;
+ else
+ return CMD_RET_USAGE;
+
+ len = simple_strtoul(lenarg, NULL, 10);
+
+ src1 = malloc(len);
+ src2 = malloc(len);
+
+ if (*src1arg == '*')
+ read_from_mem(simple_strtoul(src1arg + 1, NULL, 16), src1, len);
+ else
+ read_from_env_var(src1arg, src1);
+
+ if (*src2arg == '*')
+ read_from_mem(simple_strtoul(src2arg + 1, NULL, 16), src2, len);
+ else
+ read_from_env_var(src2arg, src2);
+
+ result = malloc(len);
+
+ switch (op) {
+ case OP_ID_XOR:
+ for (i = 0; i < len; i++)
+ result[i] = src1[i] ^ src2[i];
+ break;
+ case OP_ID_OR:
+ for (i = 0; i < len; i++)
+ result[i] = src1[i] | src2[i];
+ break;
+ case OP_ID_AND:
+ for (i = 0; i < len; i++)
+ result[i] = src1[i] & src2[i];
+ break;
+ }
+
+ if (argc == 5) {
+ for (i = 0; i < len; i++) {
+ printf("%02x ", result[i]);
+ if (i % 16 == 15)
+ puts("\n");
+ }
+ puts("\n");
+
+ goto exit;
+ }
+
+ destarg = argv[5];
+
+ if (*destarg == '*')
+ write_to_mem(destarg + 1, result, len); /* Skip asterisk */
+ else
+ write_to_env_var(destarg, result, len);
+exit:
+ free(result);
+ free(src2);
+ free(src1);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ binop, 6, 1, do_binop,
+ "compute binary operation",
+ "op count [*]src1 [*]src2 [[*]dest]\n"
+ " - compute binary operation of data at/in src1 and\n src2 (either *memaddr, env var name or hex string)\n and store result in/at dest, where op is one of\n xor, or, and."
+);
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 6546272..5498a5f 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -22,37 +22,65 @@
DECLARE_GLOBAL_DATA_PTR;
-static uint8_t efi_obj_list_initalized;
+#define OBJ_LIST_NOT_INITIALIZED 1
+
+static efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
static struct efi_device_path *bootefi_image_path;
static struct efi_device_path *bootefi_device_path;
/* Initialize and populate EFI object list */
-static void efi_init_obj_list(void)
+efi_status_t efi_init_obj_list(void)
{
- efi_obj_list_initalized = 1;
+ efi_status_t ret = EFI_SUCCESS;
+
+ /* Initialize once only */
+ if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED)
+ return efi_obj_list_initialized;
/* Initialize EFI driver uclass */
- efi_driver_init();
+ ret = efi_driver_init();
+ if (ret != EFI_SUCCESS)
+ goto out;
- efi_console_register();
+ ret = efi_console_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
#ifdef CONFIG_PARTITIONS
- efi_disk_register();
+ ret = efi_disk_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
#endif
#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
- efi_gop_register();
+ ret = efi_gop_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
#endif
-#ifdef CONFIG_CMD_NET
- efi_net_register();
+#ifdef CONFIG_NET
+ ret = efi_net_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
#endif
#ifdef CONFIG_GENERATE_SMBIOS_TABLE
- efi_smbios_register();
+ ret = efi_smbios_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
#endif
- efi_watchdog_register();
+ ret = efi_watchdog_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
/* Initialize EFI runtime services */
- efi_reset_system_init();
- efi_get_time_init();
+ ret = efi_reset_system_init();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ ret = efi_get_time_init();
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+out:
+ efi_obj_list_initialized = ret;
+ return ret;
}
/*
@@ -150,24 +178,85 @@
}
#endif
+/* Carve out DT reserved memory ranges */
+static efi_status_t efi_carve_out_dt_rsv(void *fdt)
+{
+ int nr_rsv, i;
+ uint64_t addr, size, pages;
+
+ nr_rsv = fdt_num_mem_rsv(fdt);
+
+ /* Look for an existing entry and add it to the efi mem map. */
+ for (i = 0; i < nr_rsv; i++) {
+ if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0)
+ continue;
+
+ pages = ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT;
+ efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
+ false);
+ }
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t efi_install_fdt(void *fdt)
+{
+ bootm_headers_t img = { 0 };
+ ulong fdt_pages, fdt_size, fdt_start, fdt_end;
+ efi_status_t ret;
+
+ if (fdt_check_header(fdt)) {
+ printf("ERROR: invalid device tree\n");
+ return EFI_INVALID_PARAMETER;
+ }
+
+ /* Prepare fdt for payload */
+ fdt = copy_fdt(fdt);
+ if (!fdt)
+ return EFI_OUT_OF_RESOURCES;
+
+ if (image_setup_libfdt(&img, fdt, 0, NULL)) {
+ printf("ERROR: failed to process device tree\n");
+ return EFI_LOAD_ERROR;
+ }
+
+ if (efi_carve_out_dt_rsv(fdt) != EFI_SUCCESS) {
+ printf("ERROR: failed to carve out memory\n");
+ return EFI_LOAD_ERROR;
+ }
+
+ /* Link to it in the efi tables */
+ ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
+ if (ret != EFI_SUCCESS)
+ return EFI_OUT_OF_RESOURCES;
+
+ /* And reserve the space in the memory map */
+ fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK;
+ fdt_end = ((ulong)fdt) + fdt_totalsize(fdt);
+ fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK;
+ fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
+ /* Give a bootloader the chance to modify the device tree */
+ fdt_pages += 2;
+ ret = efi_add_memory_map(fdt_start, fdt_pages,
+ EFI_BOOT_SERVICES_DATA, true);
+ return ret;
+}
+
/*
* Load an EFI payload into a newly allocated piece of memory, register all
* EFI objects it would want to access and jump to it.
*/
-static efi_status_t do_bootefi_exec(void *efi, void *fdt,
+static efi_status_t do_bootefi_exec(void *efi,
struct efi_device_path *device_path,
struct efi_device_path *image_path)
{
struct efi_loaded_image loaded_image_info = {};
struct efi_object loaded_image_info_obj = {};
struct efi_device_path *memdp = NULL;
- ulong ret;
+ efi_status_t ret;
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
struct efi_system_table *st);
- ulong fdt_pages, fdt_size, fdt_start, fdt_end;
- const efi_guid_t fdt_guid = EFI_FDT_GUID;
- bootm_headers_t img = { 0 };
/*
* Special case for efi payload not loaded from disk, such as
@@ -183,10 +272,6 @@
assert(device_path && image_path);
}
- /* Initialize and populate EFI object list */
- if (!efi_obj_list_initalized)
- efi_init_obj_list();
-
efi_setup_loaded_image(&loaded_image_info, &loaded_image_info_obj,
device_path, image_path);
@@ -196,38 +281,12 @@
*/
efi_save_gd();
- if (fdt && !fdt_check_header(fdt)) {
- /* Prepare fdt for payload */
- fdt = copy_fdt(fdt);
-
- if (image_setup_libfdt(&img, fdt, 0, NULL)) {
- printf("ERROR: Failed to process device tree\n");
- return -EINVAL;
- }
-
- /* Link to it in the efi tables */
- efi_install_configuration_table(&fdt_guid, fdt);
-
- /* And reserve the space in the memory map */
- fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK;
- fdt_end = ((ulong)fdt) + fdt_totalsize(fdt);
- fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK;
- fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
- /* Give a bootloader the chance to modify the device tree */
- fdt_pages += 2;
- efi_add_memory_map(fdt_start, fdt_pages,
- EFI_BOOT_SERVICES_DATA, true);
- } else {
- printf("WARNING: Invalid device tree, expect boot to fail\n");
- efi_install_configuration_table(&fdt_guid, NULL);
- }
-
/* Transfer environment variable bootargs as load options */
set_load_options(&loaded_image_info, "bootargs");
/* Load the EFI payload */
entry = efi_load_pe(efi, &loaded_image_info);
if (!entry) {
- ret = -ENOENT;
+ ret = EFI_LOAD_ERROR;
goto exit;
}
@@ -277,16 +336,12 @@
return ret;
}
-static int do_bootefi_bootmgr_exec(unsigned long fdt_addr)
+static int do_bootefi_bootmgr_exec(void)
{
struct efi_device_path *device_path, *file_path;
void *addr;
efi_status_t r;
- /* Initialize and populate EFI object list */
- if (!efi_obj_list_initalized)
- efi_init_obj_list();
-
/*
* gd lives in a fixed register which may get clobbered while we execute
* the payload. So save it here and restore it on every callback entry
@@ -298,7 +353,7 @@
return 1;
printf("## Starting EFI application at %p ...\n", addr);
- r = do_bootefi_exec(addr, (void *)fdt_addr, device_path, file_path);
+ r = do_bootefi_exec(addr, device_path, file_path);
printf("## Application terminated, r = %lu\n",
r & ~EFI_ERROR_MASK);
@@ -311,12 +366,37 @@
/* Interpreter command to boot an arbitrary EFI image from memory */
static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *saddr, *sfdt;
- unsigned long addr, fdt_addr = 0;
+ unsigned long addr;
+ char *saddr;
efi_status_t r;
+ void *fdt_addr;
+
+ /* Initialize EFI drivers */
+ r = efi_init_obj_list();
+ if (r != EFI_SUCCESS) {
+ printf("Error: Cannot set up EFI drivers, r = %lu\n",
+ r & ~EFI_ERROR_MASK);
+ return CMD_RET_FAILURE;
+ }
if (argc < 2)
return CMD_RET_USAGE;
+
+ if (argc > 2) {
+ fdt_addr = (void *)simple_strtoul(argv[2], NULL, 16);
+ if (!fdt_addr && *argv[2] != '0')
+ return CMD_RET_USAGE;
+ /* Install device tree */
+ r = efi_install_fdt(fdt_addr);
+ if (r != EFI_SUCCESS) {
+ printf("ERROR: failed to install device tree\n");
+ return CMD_RET_FAILURE;
+ }
+ } else {
+ /* Remove device tree. EFI_NOT_FOUND can be ignored here */
+ efi_install_configuration_table(&efi_guid_fdt, NULL);
+ printf("WARNING: booting without device tree\n");
+ }
#ifdef CONFIG_CMD_BOOTEFI_HELLO
if (!strcmp(argv[1], "hello")) {
ulong size = __efi_helloworld_end - __efi_helloworld_begin;
@@ -350,8 +430,7 @@
*/
efi_save_gd();
/* Initialize and populate EFI object list */
- if (!efi_obj_list_initalized)
- efi_init_obj_list();
+ efi_init_obj_list();
/* Transfer environment variable efi_selftest as load options */
set_load_options(&loaded_image_info, "efi_selftest");
/* Execute the test */
@@ -363,12 +442,7 @@
} else
#endif
if (!strcmp(argv[1], "bootmgr")) {
- unsigned long fdt_addr = 0;
-
- if (argc > 2)
- fdt_addr = simple_strtoul(argv[2], NULL, 16);
-
- return do_bootefi_bootmgr_exec(fdt_addr);
+ return do_bootefi_bootmgr_exec();
} else {
saddr = argv[1];
@@ -377,15 +451,11 @@
if (!addr && *saddr != '0')
return CMD_RET_USAGE;
- if (argc > 2) {
- sfdt = argv[2];
- fdt_addr = simple_strtoul(sfdt, NULL, 16);
- }
}
printf("## Starting EFI application at %08lx ...\n", addr);
- r = do_bootefi_exec((void *)addr, (void *)fdt_addr,
- bootefi_device_path, bootefi_image_path);
+ r = do_bootefi_exec((void *)addr, bootefi_device_path,
+ bootefi_image_path);
printf("## Application terminated, r = %lu\n",
r & ~EFI_ERROR_MASK);
@@ -406,7 +476,7 @@
" - boot a sample Hello World application stored within U-Boot\n"
#endif
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
- "bootefi selftest\n"
+ "bootefi selftest [fdt address]\n"
" - boot an EFI selftest application stored within U-Boot\n"
" Use environment variable efi_selftest to select a single test.\n"
" Use 'setenv efi_selftest list' to enumerate all tests.\n"
@@ -424,16 +494,6 @@
bootefi_help_text
);
-static int parse_partnum(const char *devnr)
-{
- const char *str = strchr(devnr, ':');
- if (str) {
- str++;
- return simple_strtoul(str, NULL, 16);
- }
- return 0;
-}
-
void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
{
char filename[32] = { 0 }; /* dp->str is u16[32] long */
@@ -441,16 +501,17 @@
if (strcmp(dev, "Net")) {
struct blk_desc *desc;
+ disk_partition_t fs_partition;
int part;
- desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10));
- if (!desc)
+ part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition,
+ 1);
+ if (part < 0)
return;
- part = parse_partnum(devnr);
bootefi_device_path = efi_dp_from_part(desc, part);
} else {
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_NET
bootefi_device_path = efi_dp_from_eth();
#endif
}
diff --git a/cmd/cbfs.c b/cmd/cbfs.c
index 799ba01..736f8c4 100644
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -22,7 +22,7 @@
return 0;
}
if (argc == 2) {
- end_of_rom = (int)simple_strtoul(argv[1], &ep, 16);
+ end_of_rom = simple_strtoul(argv[1], &ep, 16);
if (*ep) {
puts("\n** Invalid end of ROM **\n");
return 1;
diff --git a/cmd/elf.c b/cmd/elf.c
index 5b59fc6..19479bb 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -16,6 +16,7 @@
#include <common.h>
#include <command.h>
#include <elf.h>
+#include <environment.h>
#include <net.h>
#include <vxworks.h>
#ifdef CONFIG_X86
@@ -361,13 +362,18 @@
* binary image.
*/
if (valid_elf_image(addr))
- addr = load_elf_image_shdr(addr);
+ addr = load_elf_image_phdr(addr);
else
puts("## Not an ELF image, assuming binary\n");
printf("## Starting vxWorks at 0x%08lx ...\n", addr);
dcache_disable();
+#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI)
+ armv8_setup_psci();
+ smp_kick_all_cpus();
+#endif
+
#ifdef CONFIG_X86
/* VxWorks on x86 uses stack to pass parameters */
((asmlinkage void (*)(int))addr)(0);
diff --git a/cmd/ethsw.c b/cmd/ethsw.c
index b600965..92a60b4 100644
--- a/cmd/ethsw.c
+++ b/cmd/ethsw.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <command.h>
+#include <environment.h>
#include <errno.h>
#include <env_flags.h>
#include <ethsw.h>
diff --git a/cmd/net.c b/cmd/net.c
index d7c776a..67888d4 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -14,6 +14,7 @@
static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []);
+#ifdef CONFIG_CMD_BOOTP
static int do_bootp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return netboot_common(BOOTP, cmdtp, argc, argv);
@@ -24,7 +25,9 @@
"boot image via network using BOOTP/TFTP protocol",
"[loadAddress] [[hostIPaddr:]bootfilename]"
);
+#endif
+#ifdef CONFIG_CMD_TFTPBOOT
int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret;
@@ -40,6 +43,7 @@
"boot image via network using TFTP protocol",
"[loadAddress] [[hostIPaddr:]bootfilename]"
);
+#endif
#ifdef CONFIG_CMD_TFTPPUT
static int do_tftpput(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 4cb25b8..9838678 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -341,6 +341,36 @@
return value;
}
+void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr)
+{
+ char *end;
+ int i;
+
+ for (i = 0; i < 6; ++i) {
+ enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0;
+ if (addr)
+ addr = (*end) ? end + 1 : end;
+ }
+}
+
+int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr)
+{
+ eth_parse_enetaddr(env_get(name), enetaddr);
+ return is_valid_ethaddr(enetaddr);
+}
+
+int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr)
+{
+ char buf[ARP_HLEN_ASCII + 1];
+
+ if (eth_env_get_enetaddr(name, (uint8_t *)buf))
+ return -EEXIST;
+
+ sprintf(buf, "%pM", enetaddr);
+
+ return env_set(name, buf);
+}
+
#ifndef CONFIG_SPL_BUILD
static int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/cmd/part.c b/cmd/part.c
index 746bf40..ec791fd 100644
--- a/cmd/part.c
+++ b/cmd/part.c
@@ -22,6 +22,11 @@
#include <part.h>
#include <vsprintf.h>
+enum cmd_part_info {
+ CMD_PART_INFO_START = 0,
+ CMD_PART_INFO_SIZE,
+};
+
static int do_part_uuid(int argc, char * const argv[])
{
int part;
@@ -108,11 +113,12 @@
return 0;
}
-static int do_part_start(int argc, char * const argv[])
+static int do_part_info(int argc, char * const argv[], enum cmd_part_info param)
{
struct blk_desc *desc;
disk_partition_t info;
char buf[512] = { 0 };
+ char *endp;
int part;
int err;
int ret;
@@ -122,17 +128,32 @@
if (argc > 4)
return CMD_RET_USAGE;
- part = simple_strtoul(argv[2], NULL, 0);
-
ret = blk_get_device_by_str(argv[0], argv[1], &desc);
if (ret < 0)
return 1;
- err = part_get_info(desc, part, &info);
- if (err)
- return 1;
+ part = simple_strtoul(argv[2], &endp, 0);
+ if (*endp == '\0') {
+ err = part_get_info(desc, part, &info);
+ if (err)
+ return 1;
+ } else {
+ part = part_get_info_by_name(desc, argv[2], &info);
+ if (part == -1)
+ return 1;
+ }
- snprintf(buf, sizeof(buf), LBAF, info.start);
+ switch (param) {
+ case CMD_PART_INFO_START:
+ snprintf(buf, sizeof(buf), LBAF, info.start);
+ break;
+ case CMD_PART_INFO_SIZE:
+ snprintf(buf, sizeof(buf), LBAF, info.size);
+ break;
+ default:
+ printf("** Unknown cmd_part_info value: %d\n", param);
+ return 1;
+ }
if (argc > 3)
env_set(argv[3], buf);
@@ -142,38 +163,14 @@
return 0;
}
+static int do_part_start(int argc, char * const argv[])
+{
+ return do_part_info(argc, argv, CMD_PART_INFO_START);
+}
+
static int do_part_size(int argc, char * const argv[])
{
- struct blk_desc *desc;
- disk_partition_t info;
- char buf[512] = { 0 };
- int part;
- int err;
- int ret;
-
- if (argc < 3)
- return CMD_RET_USAGE;
- if (argc > 4)
- return CMD_RET_USAGE;
-
- part = simple_strtoul(argv[2], NULL, 0);
-
- ret = blk_get_device_by_str(argv[0], argv[1], &desc);
- if (ret < 0)
- return 1;
-
- err = part_get_info(desc, part, &info);
- if (err)
- return 1;
-
- snprintf(buf, sizeof(buf), LBAF, info.size);
-
- if (argc > 3)
- env_set(argv[3], buf);
- else
- printf("%s\n", buf);
-
- return 0;
+ return do_part_info(argc, argv, CMD_PART_INFO_SIZE);
}
static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -207,6 +204,8 @@
" flags can be -bootable (list only bootable partitions)\n"
"part start <interface> <dev> <part> <varname>\n"
" - set environment variable to the start of the partition (in blocks)\n"
+ " part can be either partition number or partition name\n"
"part size <interface> <dev> <part> <varname>\n"
- " - set environment variable to the size of the partition (in blocks)"
+ " - set environment variable to the size of the partition (in blocks)\n"
+ " part can be either partition number or partition name"
);
diff --git a/cmd/sf.c b/cmd/sf.c
index f971eec..e7ff9a6 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -287,7 +287,7 @@
}
buf = map_physmem(addr, len, MAP_WRBACK);
- if (!buf) {
+ if (!buf && addr) {
puts("Failed to map physical memory\n");
return 1;
}
diff --git a/cmd/ximg.c b/cmd/ximg.c
index 21b5c37..069c6ad 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -249,7 +249,7 @@
puts("OK\n");
}
- flush_cache(dest, len);
+ flush_cache(dest, ALIGN(len, ARCH_DMA_MINALIGN));
env_set_hex("fileaddr", data);
env_set_hex("filesize", len);
diff --git a/common/Kconfig b/common/Kconfig
index b92d0e3..03eeeb2 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -561,13 +561,20 @@
to do this.
config DISPLAY_BOARDINFO
- bool "Display information about the board during start up"
+ bool "Display information about the board during early start up"
default y if ARM || M68K || MIPS || PPC || SANDBOX || XTENSA
help
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called
to do this.
+config DISPLAY_BOARDINFO_LATE
+ bool "Display information about the board during late start up"
+ help
+ Display information about the board that U-Boot is running on after
+ the relocation phase. The board function checkboard() is called to do
+ this.
+
menu "Start-up hooks"
config ARCH_EARLY_INIT_R
@@ -595,6 +602,22 @@
Note that the normal serial console is not yet set up, but the
debug UART will be available if enabled.
+config BOARD_EARLY_INIT_R
+ bool "Call board-specific init after relocation"
+ help
+ Some boards need to perform initialisation as directly after
+ relocation. With this option, U-Boot calls board_early_init_r()
+ in the post-relocation init sequence.
+
+config LAST_STAGE_INIT
+ bool "Call board-specific as last setup step"
+ help
+ Some boards need to perform initialisation immediately before control
+ is passed to the command-line interpreter (e.g. for initializations
+ that depend on later phases in the init sequence). With this option,
+ U-Boot calls last_stage_init() before the command-line interpreter is
+ started.
+
endmenu
menu "Security support"
diff --git a/common/board_f.c b/common/board_f.c
index c6bc53e..ae8bdb7 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -18,7 +18,6 @@
#include <fs.h>
#include <i2c.h>
#include <initcall.h>
-#include <init_helpers.h>
#include <malloc.h>
#include <mapmem.h>
#include <os.h>
@@ -489,7 +488,7 @@
return 0;
}
-int arch_reserve_stacks(void)
+__weak int arch_reserve_stacks(void)
{
return 0;
}
@@ -901,7 +900,8 @@
hang();
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
- !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
+ !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
+ !defined(CONFIG_ARC)
/* NOTREACHED - jump_to_copy() does not return */
hang();
#endif
diff --git a/common/board_r.c b/common/board_r.c
index 482f506..0f4479a 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -23,10 +23,6 @@
#include <fdtdec.h>
#include <ide.h>
#include <initcall.h>
-#include <init_helpers.h>
-#ifdef CONFIG_PS2KBD
-#include <keyboard.h>
-#endif
#if defined(CONFIG_CMD_KGDB)
#include <kgdb.h>
#endif
@@ -642,15 +638,6 @@
}
#endif
-#ifdef CONFIG_PS2KBD
-static int initr_kbd(void)
-{
- puts("PS/2: ");
- kbd_init();
- return 0;
-}
-#endif
-
static int run_main_loop(void)
{
#ifdef CONFIG_SANDBOX
@@ -859,9 +846,6 @@
#if defined(CONFIG_PRAM)
initr_mem,
#endif
-#ifdef CONFIG_PS2KBD
- initr_kbd,
-#endif
run_main_loop,
};
diff --git a/common/bootm_os.c b/common/bootm_os.c
index 5e6b177..b84a8e2 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -11,6 +11,7 @@
#include <linux/libfdt.h>
#include <malloc.h>
#include <vxworks.h>
+#include <tee/optee.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -433,6 +434,34 @@
}
#endif
+#ifdef CONFIG_BOOTM_OPTEE
+static int do_bootm_tee(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ int ret;
+
+ /* Verify OS type */
+ if (images->os.os != IH_OS_TEE) {
+ return 1;
+ };
+
+ /* Validate OPTEE header */
+ ret = optee_verify_bootm_image(images->os.image_start,
+ images->os.load,
+ images->os.image_len);
+ if (ret)
+ return ret;
+
+ /* Locate FDT etc */
+ ret = bootm_find_images(flag, argc, argv);
+ if (ret)
+ return ret;
+
+ /* From here we can run the regular linux boot path */
+ return do_bootm_linux(flag, argc, argv, images);
+}
+#endif
+
static boot_os_fn *boot_os[] = {
[IH_OS_U_BOOT] = do_bootm_standalone,
#ifdef CONFIG_BOOTM_LINUX
@@ -466,6 +495,9 @@
#ifdef CONFIG_BOOTM_OPENRTOS
[IH_OS_OPENRTOS] = do_bootm_openrtos,
#endif
+#ifdef CONFIG_BOOTM_OPTEE
+ [IH_OS_TEE] = do_bootm_tee,
+#endif
};
/* Allow for arch specific config before we boot */
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 25103ba..3dc02a1 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -21,6 +21,9 @@
#define CONFIG_SYS_FDT_PAD 0x3000
#endif
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD 0x80
+
DECLARE_GLOBAL_DATA_PTR;
static void fdt_error(const char *msg)
diff --git a/common/image-fit.c b/common/image-fit.c
index f6e956a..030a3e5 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -419,7 +419,8 @@
printf("%s Architecture: %s\n", p, genimg_get_arch_name(arch));
}
- if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_RAMDISK)) {
+ if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_RAMDISK) ||
+ (type == IH_TYPE_FIRMWARE)) {
fit_image_get_os(fit, image_noffset, &os);
printf("%s OS: %s\n", p, genimg_get_os_name(os));
}
@@ -1068,34 +1069,14 @@
return 0;
}
-/**
- * fit_image_verify - verify data integrity
- * @fit: pointer to the FIT format image header
- * @image_noffset: component image node offset
- *
- * fit_image_verify() goes over component image hash nodes,
- * re-calculates each data hash and compares with the value stored in hash
- * node.
- *
- * returns:
- * 1, if all hashes are valid
- * 0, otherwise (or on error)
- */
-int fit_image_verify(const void *fit, int image_noffset)
+int fit_image_verify_with_data(const void *fit, int image_noffset,
+ const void *data, size_t size)
{
- const void *data;
- size_t size;
int noffset = 0;
char *err_msg = "";
int verify_all = 1;
int ret;
- /* Get image data and data length */
- if (fit_image_get_data(fit, image_noffset, &data, &size)) {
- err_msg = "Can't get image data/size";
- goto error;
- }
-
/* Verify all required signatures */
if (IMAGE_ENABLE_VERIFY &&
fit_image_verify_required_sigs(fit, image_noffset, data, size,
@@ -1153,6 +1134,38 @@
}
/**
+ * fit_image_verify - verify data integrity
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: component image node offset
+ *
+ * fit_image_verify() goes over component image hash nodes,
+ * re-calculates each data hash and compares with the value stored in hash
+ * node.
+ *
+ * returns:
+ * 1, if all hashes are valid
+ * 0, otherwise (or on error)
+ */
+int fit_image_verify(const void *fit, int image_noffset)
+{
+ const void *data;
+ size_t size;
+ int noffset = 0;
+ char *err_msg = "";
+
+ /* Get image data and data length */
+ if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+ err_msg = "Can't get image data/size";
+ printf("error!\n%s for '%s' hash node in '%s' image node\n",
+ err_msg, fit_get_name(fit, noffset, NULL),
+ fit_get_name(fit, image_noffset, NULL));
+ return 0;
+ }
+
+ return fit_image_verify_with_data(fit, image_noffset, data, size);
+}
+
+/**
* fit_all_image_verify - verify data integrity for all images
* @fit: pointer to the FIT format image header
*
@@ -1598,6 +1611,10 @@
if (uname)
printf("%s Init Ramdisk: %s\n", p, uname);
+ uname = fdt_getprop(fit, noffset, FIT_FIRMWARE_PROP, NULL);
+ if (uname)
+ printf("%s Firmware: %s\n", p, uname);
+
for (fdt_index = 0;
uname = fdt_stringlist_get(fit, noffset, FIT_FDT_PROP,
fdt_index, NULL), uname;
diff --git a/common/image.c b/common/image.c
index 14be3ca..e1c50eb 100644
--- a/common/image.c
+++ b/common/image.c
@@ -86,6 +86,7 @@
{ IH_ARCH_ARC, "arc", "ARC", },
{ IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ IH_ARCH_XTENSA, "xtensa", "Xtensa", },
+ { IH_ARCH_RISCV, "riscv", "RISC-V", },
{ -1, "", "", },
};
@@ -100,6 +101,7 @@
{ IH_OS_OSE, "ose", "Enea OSE", },
{ IH_OS_PLAN9, "plan9", "Plan 9", },
{ IH_OS_RTEMS, "rtems", "RTEMS", },
+ { IH_OS_TEE, "tee", "Trusted Execution Environment" },
{ IH_OS_U_BOOT, "u-boot", "U-Boot", },
{ IH_OS_VXWORKS, "vxworks", "VxWorks", },
#if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
@@ -161,6 +163,7 @@
{ IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",},
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
{ IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",},
+ { IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
{ -1, "", "", },
};
diff --git a/common/log.c b/common/log.c
index 680a60f..66d5e3e 100644
--- a/common/log.c
+++ b/common/log.c
@@ -224,6 +224,7 @@
{
struct log_filter *filt;
struct log_device *ldev;
+ int ret;
int i;
ldev = log_device_find_by_name(drv_name);
@@ -236,8 +237,10 @@
if (cat_list) {
filt->flags |= LOGFF_HAS_CAT;
for (i = 0; ; i++) {
- if (i == ARRAY_SIZE(filt->cat_list))
- return -ENOSPC;
+ if (i == ARRAY_SIZE(filt->cat_list)) {
+ ret = -ENOSPC;
+ goto err;
+ }
filt->cat_list[i] = cat_list[i];
if (cat_list[i] == LOGC_END)
break;
@@ -246,17 +249,19 @@
filt->max_level = max_level;
if (file_list) {
filt->file_list = strdup(file_list);
- if (!filt->file_list)
- goto nomem;
+ if (!filt->file_list) {
+ ret = ENOMEM;
+ goto err;
+ }
}
filt->filter_num = ldev->next_filter_num++;
list_add_tail(&filt->sibling_node, &ldev->filter_head);
return filt->filter_num;
-nomem:
+err:
free(filt);
- return -ENOMEM;
+ return ret;
}
int log_remove_filter(const char *drv_name, int filter_num)
diff --git a/common/memsize.c b/common/memsize.c
index 0fb9ba5..c315275 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -27,7 +27,8 @@
long get_ram_size(long *base, long maxsize)
{
volatile long *addr;
- long save[32];
+ long save[31];
+ long save_base;
long cnt;
long val;
long size;
@@ -43,7 +44,7 @@
addr = base;
sync();
- save[i] = *addr;
+ save_base = *addr;
sync();
*addr = 0;
@@ -51,7 +52,7 @@
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function. */
sync();
- *addr = save[i];
+ *base = save_base;
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt;
sync();
@@ -76,9 +77,16 @@
addr = base + cnt;
*addr = save[--i];
}
+ /* warning: don't restore save_base in this case,
+ * it is already done in the loop because
+ * base and base+size share the same physical memory
+ * and *base is saved after *(base+size) modification
+ * in first loop
+ */
return (size);
}
}
+ *base = save_base;
return (maxsize);
}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 9609fce..4d27565 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -568,6 +568,15 @@
performed before booting. This enables the drivers in post/drivers
as part of an SPL build.
+config SPL_RESET_SUPPORT
+ bool "Support reset drivers"
+ depends on SPL
+ help
+ Enable support for reset control in SPL.
+ That can be useful in SPL to handle IP reset in driver, as in U-Boot,
+ by using the generic reset API provided by driver model.
+ This enables the drivers in drivers/reset as part of an SPL build.
+
config SPL_POWER_SUPPORT
bool "Support power drivers"
help
@@ -634,6 +643,13 @@
lines). This enables the drivers in drivers/mtd/spi as part of an
SPL build. This normally requires SPL_SPI_SUPPORT.
+config SPL_SPI_LOAD
+ bool "Support loading from SPI flash"
+ depends on SPL_SPI_FLASH_SUPPORT
+ help
+ Enable support for loading next stage, U-Boot or otherwise, from
+ SPI NOR in U-Boot SPL.
+
config SPL_SPI_SUPPORT
bool "Support SPI drivers"
help
@@ -763,6 +779,13 @@
If your ATF is affected, say Y.
+config SPL_AM33XX_ENABLE_RTC32K_OSC
+ bool "Enable the RTC32K OSC on AM33xx based platforms"
+ default y if AM33XX
+ help
+ Enable access to the AM33xx RTC and select the external 32kHz clock
+ source.
+
config TPL
bool
depends on SUPPORT_TPL
@@ -887,6 +910,20 @@
help
Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details.
+config TPL_RAM_SUPPORT
+ bool "Support booting from RAM"
+ help
+ Enable booting of an image in RAM. The image can be preloaded or
+ it can be loaded by TPL directly into RAM (e.g. using USB).
+
+config TPL_RAM_DEVICE
+ bool "Support booting from preloaded image in RAM"
+ depends on TPL_RAM_SUPPORT
+ help
+ Enable booting of an image already loaded in RAM. The image has to
+ be already in memory when TPL takes over, e.g. loaded by the boot
+ ROM.
+
config TPL_SERIAL_SUPPORT
bool "Support serial"
help
@@ -899,12 +936,27 @@
Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT
for details.
+config TPL_SPI_LOAD
+ bool "Support loading from SPI flash"
+ depends on TPL_SPI_FLASH_SUPPORT
+ help
+ Enable support for loading next stage, U-Boot or otherwise, from
+ SPI NOR in U-Boot TPL.
+
config TPL_SPI_SUPPORT
bool "Support SPI drivers"
help
Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for
details.
+config TPL_YMODEM_SUPPORT
+ bool "Support loading using Ymodem"
+ help
+ While loading from serial is slow it can be a useful backup when
+ there is no other option. The Ymodem protocol provides a reliable
+ means of transmitting U-Boot over a serial line for using in TPL,
+ with a checksum to ensure correctness.
+
endif # TPL
endif # SPL
diff --git a/common/spl/spl.c b/common/spl/spl.c
index b1ce56d..61d3071 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -127,8 +127,14 @@
ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
spl_image->size = CONFIG_SYS_MONITOR_LEN;
- if (u_boot_pos != BINMAN_SYM_MISSING) {
- /* biman does not support separate entry addresses at present */
+
+ /*
+ * Binman error cases: address of the end of the previous region or the
+ * start of the image's entry area (usually 0) if there is no previous
+ * region.
+ */
+ if (u_boot_pos && u_boot_pos != BINMAN_SYM_MISSING) {
+ /* Binman does not support separated entry addresses */
spl_image->entry_point = u_boot_pos;
spl_image->load_addr = u_boot_pos;
} else {
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index b705d03..9f03e26 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -174,6 +174,9 @@
uint8_t image_comp = -1, type = -1;
const void *data;
bool external_data = false;
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ int ret;
+#endif
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, &image_comp))
@@ -252,7 +255,16 @@
image_info->entry_point = fdt_getprop_u32(fit, node, "entry");
}
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ printf("## Checking hash(es) for Image %s ...\n",
+ fit_get_name(fit, node, NULL));
+ ret = fit_image_verify_with_data(fit, node,
+ (const void *)load_addr, length);
+ printf("\n");
+ return !ret;
+#else
return 0;
+#endif
}
static int spl_fit_append_fdt(struct spl_image_info *spl_image,
@@ -383,7 +395,8 @@
* - fall back to using the first 'loadables' entry
*/
if (node < 0)
- node = spl_fit_get_image_node(fit, images, "firmware", 0);
+ node = spl_fit_get_image_node(fit, images, FIT_FIRMWARE_PROP,
+ 0);
#ifdef CONFIG_SPL_OS_BOOT
if (node < 0)
node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 351f4ed..4aa0b2c 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -292,6 +292,14 @@
#endif
}
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+__weak
+int spl_boot_partition(const u32 boot_device)
+{
+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
+}
+#endif
+
int spl_mmc_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
@@ -347,8 +355,11 @@
return err;
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- err = mmc_load_image_raw_partition(spl_image, mmc,
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
+ err = spl_boot_partition(bootdev->boot_device);
+ if (!err)
+ return err;
+
+ err = mmc_load_image_raw_partition(spl_image, mmc, err);
if (!err)
return err;
#endif
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index d9db9f3..a15761e 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -36,7 +36,7 @@
header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
-#if defined(CONFIG_SPL_DFU_SUPPORT)
+#if CONFIG_IS_ENABLED(DFU_SUPPORT)
if (bootdev->boot_device == BOOT_DEVICE_DFU)
spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0");
#endif
@@ -74,10 +74,10 @@
return 0;
}
-#if defined(CONFIG_SPL_RAM_DEVICE)
+#if CONFIG_IS_ENABLED(RAM_DEVICE)
SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image);
#endif
-#if defined(CONFIG_SPL_DFU_SUPPORT)
+#if CONFIG_IS_ENABLED(DFU_SUPPORT)
SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
#endif
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index 21f58dc..aafaf45 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -4,6 +4,7 @@
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_CPU=y
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index e167646..990cb3e 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -4,6 +4,7 @@
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_CPU=y
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index d4f95f5..374d4e2 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index cf8e7d5..93ab4ec 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG1"
@@ -9,7 +9,6 @@
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
@@ -17,5 +16,6 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_AXP152_POWER=y
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index f32be68..fb680aa 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
@@ -13,11 +13,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUNXI_NO_PMIC=y
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index d054474..21fbc10 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
@@ -15,7 +15,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
@@ -25,6 +24,7 @@
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DFU_RAM=y
CONFIG_AXP_ALDO3_VOLT=3300
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index a9904f2..396ee0b 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -12,7 +12,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2-emmc"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 018a28f..b1243ea 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 8399e0b..cc03160 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -9,7 +9,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index e73410a..c2984cd 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 0f4046b..4c4048d 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -12,7 +12,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index a1a5e4c..f353ce9 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -13,7 +13,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
new file mode 100644
index 0000000..3f44104
--- /dev/null
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_I2C1_ENABLE=y
+CONFIG_SATAPWR="PC3"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_PHY_ADDR=3
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
new file mode 100644
index 0000000..99ab73c
--- /dev/null
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_I2C1_ENABLE=y
+CONFIG_SATAPWR="PC3"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_PHY_ADDR=3
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig
index b926b26..273e62e 100644
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
-CONFIG_CONS_INDEX=1
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
@@ -17,7 +16,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 45e39c6..d438ece 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=123
@@ -14,7 +14,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index ebfc7e0..fe8e6f6 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
@@ -15,11 +15,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index aefa98d..97b4bd9 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
@@ -8,12 +8,12 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 7ddc44d..2b24dab 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -1,17 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index c9d98cb..e12c8ea 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4420QDS=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 00360fa..fae510c 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index 4bcb1d4..9971bfb 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index 0df8562..bf56300 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index f1fb9b0..b275271 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index 9614ca3..a59e560 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index 7177ee2..ee0a054 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index 61dbe54..5e1528c 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index 43155ca..d44d8d0 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
@@ -11,7 +12,6 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
@@ -32,7 +32,8 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index 1ebda7e..9b8e964 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
@@ -10,7 +11,6 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
@@ -31,7 +31,8 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index b1b0ac7..7696681 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -27,7 +27,8 @@
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index b4cbbc5..1d85202 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -27,7 +27,8 @@
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index f3c5ed3..a0b81e4 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index 5b23a17..d3e579b 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_FIT=y
@@ -11,7 +12,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
@@ -29,14 +30,15 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index f1bb816..7abc5c5 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 0d5a5ef..9a2a1f1 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_FIT=y
@@ -11,7 +12,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
@@ -29,14 +30,15 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index 7cfd82c..f5e56e8 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index bb339fc..5137bbc 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 1acf9d4..06e46a7 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index 5459ff8..89e39f7 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 4da842f..2288900 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index 8499091..b1533a2 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 5dcd5fe..17fc7df 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index 6cf5b38..fef8b9c 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index 0063dfd..d19d748 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index acfb2c3..added1a 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 261c69b..a4d505c 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index 664b7ce..e84909d 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index cf75312..37cc2df 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_DRAM_ZQ=3881979
@@ -10,7 +10,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_SCSI_AHCI=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 7346116..7872cef 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
@@ -9,7 +9,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig
index 141fccb..8afc8d4 100644
--- a/configs/Bananapi_m2m_defconfig
+++ b/configs/Bananapi_m2m_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
-CONFIG_CONS_INDEX=1
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
@@ -11,7 +10,6 @@
CONFIG_USB0_ID_DET="PH8"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 0d7e4fb..faf3b50 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index c6d9cda..c2b016a 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -37,10 +38,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index 8e4d93a..75e993b 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_EEPROM=y
@@ -24,10 +25,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index ffb0bf7..87d544b 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_EEPROM=y
@@ -25,10 +26,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index b9b8562..cec758c 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_EEPROM=y
@@ -24,10 +25,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index 7e14708..9acd101 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_EEPROM=y
@@ -23,10 +24,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 5cd8aa0..c6f6230 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -1,12 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -17,6 +16,7 @@
# CONFIG_MMC is not set
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index a98bb40..5d63fad 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -1,13 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
-CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256"
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
@@ -17,9 +14,12 @@
CONFIG_ENV_UBI_VOLUME="uboot-env"
# CONFIG_MMC is not set
CONFIG_NAND=y
-CONFIG_NAND_SUNXI=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0x100
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index 86545bd..2a2bf42 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 937b6db..8835a0f 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
@@ -14,7 +14,6 @@
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index d60f92a..08bba86 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=240
CONFIG_DRAM_ZQ=251
@@ -17,7 +17,6 @@
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 648c8d3..c4ac610 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
@@ -8,7 +8,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index 42d9b4a..53d3f9b 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x2a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC0_CD_PIN="PH18"
@@ -12,7 +12,6 @@
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4"
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index f1ee623..72bf8bf 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
@@ -8,7 +8,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index c65f12d..107c613 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
@@ -13,7 +13,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 033e28f..5c0f67d 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=15355
@@ -16,7 +16,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index b82a756..32a280c 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -10,6 +10,7 @@
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -24,6 +25,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index ec561c2..9a6b2f2 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -10,6 +10,7 @@
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -24,6 +25,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 7db66f0..d7c2fbc 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig
index 5f2d551..84865e5 100644
--- a/configs/Empire_electronix_m712_defconfig
+++ b/configs/Empire_electronix_m712_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
@@ -15,11 +15,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 6f30461..d254e99 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_USB1_VBUS_PIN="PH24"
@@ -9,7 +9,6 @@
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 939bb80..a954e6f 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_EMR1=4
CONFIG_USB0_VBUS_PIN="PB09"
@@ -15,7 +15,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 6553a6f..54bfe4b 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
@@ -8,7 +8,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index 92e6821..1d5a686 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
@@ -10,7 +10,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
index 56e8ded..bf9bccb 100644
--- a/configs/LicheePi_Zero_defconfig
+++ b/configs/LicheePi_Zero_defconfig
@@ -1,11 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x42e00000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 70fc3ee..fdbe2c6 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
@@ -10,7 +10,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index cf05c54..7b4a806 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
@@ -8,7 +8,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index e0f11e1..750c80e 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -1,12 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index 108cf00..a75d68c 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x4000000
-CONFIG_8xx=y
+CONFIG_MPC8xx=y
CONFIG_TARGET_MCR3000=y
CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_CMD_IMMAP=y
@@ -39,8 +39,8 @@
CONFIG_SYS_IMMR=0xFF000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="ubi.mtd=4 root=ubi0:rootfs rw rootfstype=ubifs rootflags=sync console=ttyCPM0,115200N8 ip=${ipaddr}:::${netmask}:mcr3k:eth0:off"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run flashboot"
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="S3K> "
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index 402f8ef..ee8ba16 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -1,11 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index a82f51d..42e1214 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -22,7 +22,9 @@
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index cd4c474..ac0658d 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -6,6 +6,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
@@ -25,6 +26,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 9472b06..1ff3545 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -6,6 +6,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
@@ -25,6 +26,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 489be65..563a5f1 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -2,13 +2,14 @@
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_BOOTDELAY=6
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
@@ -32,6 +33,7 @@
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index f7c5e95..bf7b2a2 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -2,13 +2,14 @@
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_BOOTDELAY=6
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
@@ -32,6 +33,7 @@
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index e6f9224..c8a4b00 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -27,7 +27,8 @@
CONFIG_FSL_SATA=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index f334fda..92ca91d 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -6,6 +6,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 9d12171..f33d61f 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -6,6 +6,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 138c5bc..a35b3a3 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -6,6 +6,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index 38ca656..c1f307c 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -6,6 +6,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 67add9c..e6e09cb 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -5,6 +5,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index c72eaff..b858b8b 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -17,7 +17,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_MPC8XXX_SPI=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 83f2a39..364c6b7 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -23,6 +23,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index b7a0549..075b99d 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -30,7 +30,8 @@
CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index ed1ae06..57105c4 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -30,7 +30,8 @@
CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 300077f..8dcd04e 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -5,6 +5,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -21,8 +22,10 @@
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index 0d3ddd7..2d04d2d 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -5,6 +5,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -19,8 +20,10 @@
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 272a7d3..b4d6dac 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -22,8 +22,10 @@
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
CONFIG_FSL_SATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index cdef677..999d776 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -9,6 +9,7 @@
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -24,13 +25,14 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_FSL_DDR2=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index d4217dc..72d888c 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -9,6 +9,7 @@
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -23,13 +24,14 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_FSL_DDR2=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index 19258dd..66a3f57 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -23,13 +24,14 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_FSL_DDR2=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index d1eb20b..e55a776 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -8,6 +8,7 @@
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -23,13 +24,14 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_FSL_DDR2=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index 155c5d8..2885c6b 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -20,6 +20,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index 7f609be..7dac9ef 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -21,6 +21,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index 01381b0..0ed0f1b 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -25,11 +25,11 @@
CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_RTL8139=y
+CONFIG_TSEC_ENET=y
CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 24a5251..d87543e 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -20,9 +20,10 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 287639f..d674400 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -19,9 +19,10 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 9403d47..5fb058d 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -19,9 +19,10 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index ce7fa65..f3b62a0 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -20,6 +20,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index a4b964e..f46ab23 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -21,6 +21,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 370896a..767ad2c 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -22,6 +22,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index 10ea5d4..a818d2a 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -8,6 +8,7 @@
CONFIG_SYS_EXTRA_OPTIONS="ATM"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -24,6 +25,7 @@
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index 7c2f5a5..27a0f3a 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -23,6 +24,7 @@
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index 4b0f685..2967428 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -23,10 +24,10 @@
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_PCI=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index a184a5c..ee02cd3 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -22,10 +23,10 @@
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_PCI=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index f564fa1..f831988 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -23,7 +23,8 @@
CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index 1fb6fba..bb3ff52 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -23,7 +23,8 @@
CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index 13c2141..9ac7c48 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
@@ -10,7 +10,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 363fec1..18b7a7e 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=122
@@ -13,7 +13,6 @@
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index a77ac39..19fb196 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -1,11 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index cfb3792..013e511 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
CONFIG_INITIAL_USB_SCAN_DELAY=2000
@@ -8,7 +8,6 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index b482c18..2ed578e 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_MACPWR="PH15"
CONFIG_VIDEO_VGA=y
@@ -8,7 +8,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 1c9e418..3bde011 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index 0a99866..08a780c 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -9,7 +9,6 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 9df5b7c..1b802db 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=122
@@ -9,7 +9,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index bf696fc..13e9750 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 5e9f9ab..eb8f7c3 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x2a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC0_CD_PIN="PH18"
@@ -12,7 +12,6 @@
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 9c24dbd..ccc42a9 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -1,12 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index 2be7244..9893651 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
@@ -9,14 +9,18 @@
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_MMC is not set
+CONFIG_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_ELDO2_VOLT=1800
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index eb25504..c961e6a 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
@@ -12,7 +12,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 0b36944..33edf69 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
@@ -14,7 +14,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index 6f29507..ab7bc0e 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -13,6 +13,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -27,13 +28,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 3019174..4837928 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
@@ -15,7 +16,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
@@ -39,14 +40,15 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 45f531c..83e3788 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index c6baa73..16cecdb 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -10,6 +10,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index b519a97..9e1ffbb 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
@@ -16,7 +17,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,13 +37,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 8b49cd3..043af5d 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -13,6 +13,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -27,13 +28,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 802032a..0cba8c4 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
@@ -17,7 +18,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -37,13 +38,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index 82ff0bf..bac2a4c 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index c40b5aa..e65004f 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
@@ -38,14 +39,15 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index 1e6b2e9..32459c7 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -11,6 +11,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 8384f5b..7ee963f 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -9,6 +9,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -24,13 +25,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 54198a2..198839c 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
@@ -15,7 +16,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,13 +36,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index f011143..7b8c77b 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 888e177..9b3cf7f 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,13 +37,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index e46c277..e5d8c9a 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -13,6 +13,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -27,13 +28,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index b01342a..ddac227 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
@@ -15,7 +16,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
@@ -39,14 +40,15 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index 9be95be..fe47582 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 7841394..12b87a3 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -10,6 +10,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 8e05e8d..fe7203c 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
@@ -16,7 +17,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,13 +37,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 21a3a65..bb1adb7 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -13,6 +13,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -27,13 +28,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index d32c348..266fb8e 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
@@ -17,7 +18,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -37,13 +38,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 36f34a4..4687455 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 7c29aa6..30a91f2 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
@@ -38,14 +39,15 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index c72ca9e..ca7ea2b 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -11,6 +11,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -25,13 +26,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index eab387b..77e8e81 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -9,6 +9,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -24,13 +25,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 2b92050..d318cb2 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
@@ -15,7 +16,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,13 +36,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index d4c132f..7baa576 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index f70eaf9..3894be6 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,13 +37,14 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index e84004d..1330091 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -34,11 +35,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index 5f2bb82..af18212 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -24,11 +25,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index 4597a52..5368c29 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -33,11 +34,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 7b14e14..e10a189 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -23,11 +24,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index d30076a..66b3c70 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
@@ -14,7 +15,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -36,14 +37,15 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index d399b7b..d565cd6 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -34,13 +35,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 63188e1..ad6c6f0 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
@@ -16,7 +17,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,13 +36,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 7981efc..c46ff0e 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -24,13 +25,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 5d4eb54..f73e5a3 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -35,14 +36,15 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index b047fa6..62fcbab 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -33,13 +34,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index ef5a423..3acd28d 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -34,13 +35,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index c972a18..dd86d38 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -23,13 +24,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 5737076..56e8652 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -38,14 +39,15 @@
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 7e846b7..6d64329 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,13 +37,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 87af8e0..f6e4b41 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -37,13 +38,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index ee02c74..fda0ced 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index d4de315..c70e543 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -34,11 +35,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index d0edb8d..c831c61 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -24,11 +25,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index a8c4610..1f358bf 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -33,11 +34,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index c17c77e..613ad49 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -23,11 +24,12 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index 8ff9839..f57e4b0 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
@@ -14,7 +15,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -40,14 +41,15 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 3f5a7ec..8e6f811 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,13 +39,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index e77311d..320f043 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
@@ -16,7 +17,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -39,13 +40,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index d2c075a..2549370 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -28,13 +29,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index ae8dead..d26524c 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -39,14 +40,15 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 9c59d08..bab0e47 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -37,13 +38,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index f37e84a..95feedb 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,13 +39,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index fd3ae88..9008e31 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -27,13 +28,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index e7080ad..66d003c 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -39,14 +40,15 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 2f2c368..71107b4 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -37,13 +38,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index 4e886b4..4f0d58c 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,13 +39,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index 24c15d1..fd4bbae 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -27,13 +28,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index e2936ec..537d895 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_FIT=y
@@ -12,7 +13,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -38,14 +39,15 @@
CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index ab215be..db8897c 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,13 +37,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index 991c7a9..0e7b681 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -37,13 +38,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index a5549dd..7742a01 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -26,13 +27,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index 392dbc2..ff64d99 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=-1
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_REGINFO=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index 8307153..56c8fa5 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -24,13 +25,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index 8f871b3..fee335c 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -35,14 +36,15 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index 78cd55d..1beafe2 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -33,13 +34,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index 66ceef5..156d95b 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -34,13 +35,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index 8c9b756..a378a5f 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -23,13 +24,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index e2616ac..d1f29ca 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -26,13 +27,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index a5b5d55..ef26c95 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -37,14 +38,15 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index 893dbc4..4677d30 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,13 +36,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 013eb8f..f84ca86 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,13 +37,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index 2b1eb4b..3129805 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -25,13 +26,14 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index b3e140b..a8305c7 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
@@ -14,7 +15,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -40,14 +41,15 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 6a25a3e..6dba032 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,13 +39,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 9668178..4186192 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
@@ -16,7 +17,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -39,13 +40,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 2c3cc19..659a258 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -28,13 +29,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 0925e1b..f27d00c 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -39,14 +40,15 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index c3e2259..e625f9d 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -37,13 +38,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 2795be7..d811862 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,13 +39,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index fdd07a0..1aa38f0 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -27,13 +28,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 7a47277..f6d52a5 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index feb15d0..47fe40c 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 3bae568..be468bd 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 72d40c8..54996d0 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index 2c25994..256c68b 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 10cb402..da2d614 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -22,6 +23,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index b3ca192..d8ccd15 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 1d905f4..7862193 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 6e9b2e7..98e04d4 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index c3c8ad6..ce352ac 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 19be521..51a1ce9 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index 3fb2b73..a0fc3fa 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 7ab56d2..0ef284d 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -22,6 +23,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 8930394..88ac8b4 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index ffee42e..00d8e00 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 2fd145c..5833628 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index ec842cb..3528e23 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index afcfb3f..7842ac7 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -22,6 +23,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 81a6c8e..c8cfb2c 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -25,6 +26,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index e27b3d4..6c2f90c 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index 41bbeb4..ffc7b6c 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index f7ddd7b..f135aea 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index 2313ded..602fbd0 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index 4e53b19..11c525b 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -24,6 +25,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index 8229891..0821329 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index e5af3c5..504405d 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -25,6 +26,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index e4ff914..d4941b4 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 23fa5be..c077632 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index e2c1890..04a8b52 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 9b0d8f7..bf27112 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index fbde5dc..82b252f 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -23,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 102d672..ccf0bdc 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
@@ -11,7 +11,6 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index b0fe652..80fa863 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
-CONFIG_CONS_INDEX=1
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291
@@ -14,7 +13,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Sinovoip_BPI_M2_Plus_defconfig b/configs/Sinovoip_BPI_M2_Plus_defconfig
index a1eaf84..71d9e79 100644
--- a/configs/Sinovoip_BPI_M2_Plus_defconfig
+++ b/configs/Sinovoip_BPI_M2_Plus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -9,7 +9,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index aff76d9..da0f466 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 90875b1..dce310d 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_TYPE=7
CONFIG_DRAM_CLK=480
@@ -17,7 +17,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
index bb247ce..d7a6547 100644
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x2a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=3881915
@@ -12,7 +12,6 @@
CONFIG_USB3_VBUS_PIN="PL8"
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cx-a99"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index dc03af0..b48c2b7 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -22,6 +23,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -38,6 +40,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 9574b61..c621bff 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -22,6 +23,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -38,6 +40,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index e224ccb..4300095 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -10,10 +10,12 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,6 +30,7 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 66974a5..e3df263 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
@@ -15,7 +16,7 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -23,6 +24,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -39,6 +41,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index 27e4354..0813fac 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -8,10 +8,12 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,6 +29,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index 9d475d2..1e084f0 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -13,6 +13,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -30,6 +31,7 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index e7581a1..50b81ed 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -29,6 +30,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index e3612db..92757c6 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -41,6 +42,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 6f0eb95..1e98b22 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -41,6 +42,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index ecd0b03..e2cfcc5 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -13,6 +13,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -31,6 +32,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 9414ae4..804c5ff 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
@@ -18,7 +19,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -42,6 +43,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index d800162..d8c1159 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -30,6 +31,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 17b0e26..fce137a 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -25,6 +26,7 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -40,6 +42,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 66ebe20..62d1461 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -25,6 +26,7 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -40,6 +42,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 5d32498..76589e4 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -12,10 +12,12 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -30,6 +32,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index da5a488..0d3c4eb 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -26,6 +27,7 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -41,6 +43,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 568e256..7f9fb28 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -10,10 +10,12 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -29,6 +31,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index 5a5eee7..19c1c5f 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,6 +39,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index 91e3954..c986b58 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,6 +39,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 4a33062..6ff2860 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -28,6 +29,7 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index bb78e49..f79e700 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -39,6 +40,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index 27ea3c6..c7dd13c 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -10,6 +10,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -27,6 +28,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index 7d3c675..a523908 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -30,6 +31,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index 02efa86..2e3f028 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -13,6 +13,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -32,6 +33,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index 956cca8..b52a18e 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -31,6 +32,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 9c54a8c..4e62103 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -39,6 +40,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index 5a546f7..f1fddee 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
@@ -16,7 +17,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -39,6 +40,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index e7f169d..4b240c1 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -29,6 +30,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index 7b3a8da..8db1093 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -40,6 +41,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index 9fd7178..6ec8f85 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -10,6 +10,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -28,6 +29,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 779a5bb..7694551 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -39,6 +40,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 40e7a12..19b7961 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -39,6 +40,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 5e69872..12c686a 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -13,6 +13,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -29,6 +30,7 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 5aba98e..05fa81b 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
@@ -18,7 +19,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -40,6 +41,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index f1f4e03..8b9cfb2 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -28,6 +29,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
index 91aa951..f6ddc0a 100644
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
@@ -18,7 +19,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
@@ -44,6 +45,7 @@
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 69a7623..97c408b 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -41,6 +42,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index 64ef8bb..f02783b 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
@@ -17,7 +18,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -41,6 +42,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index 27ea5ba..16ae650 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
@@ -18,7 +19,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -42,6 +43,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index 2a24d2c..0899ee5 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -30,6 +31,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 1124661..a56f9da 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -28,6 +29,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index abbfefa..2a05527 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -10,6 +10,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -27,6 +28,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index f7fc6d0..7dcd52b 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,6 +36,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 1c99687..fb4dec1 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,6 +36,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index d353c96..a8532e5 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -25,6 +26,7 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 1e11764..7653ed0 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,6 +37,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index a4beec6..ae163ba 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -22,6 +23,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 99c88a1..0c6c62b 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index ba8762c..7f3091c 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -21,6 +22,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -36,6 +38,7 @@
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 604f81c..0d62c74 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -21,6 +22,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -36,6 +38,7 @@
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index f460981..a4f584c 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -9,9 +9,11 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -26,6 +28,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 8353313..cbff19c 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -22,6 +23,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -37,6 +39,7 @@
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index 658eb97..f6ac85d 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -8,8 +8,10 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -23,6 +25,7 @@
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 2eb4910..1be3419 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -7,9 +7,11 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -25,6 +27,7 @@
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 8cc6d8a..25f1241 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,6 +36,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index 2ef008c..d1500e6 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -35,6 +36,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 66edbaf..fb17bf9 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
@@ -14,7 +15,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -36,6 +37,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index af182c2..25ceffa 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -22,6 +23,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index c373f28..8f6b66e 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -24,6 +25,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index d2382da..eea656a 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4160QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index 4a31b97..13f0133 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4160QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 3f58ef8..57496bd 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -22,6 +23,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index a2ecafb..7304c07 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -21,6 +22,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index e9bde77..d780ef7 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -21,6 +22,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index 0f69ad5..73e15cf 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index ec1a812..8aaa90b 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index dd28b9e..228bdaa 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -22,6 +23,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index 79ee53f..d2c71e4 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -22,6 +23,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index 97a3a18..c1a66db 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -21,6 +22,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 22ca4a2..73328dd 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_FIT=y
@@ -13,7 +14,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 74029b6..8d1eb1c 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
@@ -21,6 +22,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 0032515..4fb0c19 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -5,6 +5,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
@@ -26,6 +27,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index fcbcc4d..edba6ef 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -10,6 +10,7 @@
CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -28,11 +29,12 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:256k(vsc7385-firmware),256k(dtb),5632k(kernel),57856k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SATA_SIL3114=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig
index 54fb6c9..d606067 100644
--- a/configs/UCP1020_SPIFLASH_defconfig
+++ b/configs/UCP1020_SPIFLASH_defconfig
@@ -8,6 +8,8 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_AUTOBOOT_KEYED=y
@@ -31,15 +33,16 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index c34f3f3..ffec2b0 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -7,6 +7,8 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="B$ "
@@ -31,15 +33,16 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index c0ca832..efbfe54 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
@@ -20,12 +20,12 @@
CONFIG_VIDEO_LCD_TL059WV5C0=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index 0312f27..8b30a00 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_USB0_VBUS_PIN="PB9"
@@ -13,7 +13,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index e570a43..98a4a53 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_VGA=y
@@ -12,7 +12,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index c2b152b..4d068a3 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PB3"
CONFIG_USB1_VBUS_PIN="PG12"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
@@ -15,5 +14,6 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index c7b6a50..9c2784e 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PH1"
@@ -19,7 +19,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 519b79b..770a39c 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=420
CONFIG_DRAM_ZQ=251
@@ -16,7 +16,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig
index cabbba7..6edefa4 100644
--- a/configs/a64-olinuxino_defconfig
+++ b/configs/a64-olinuxino_defconfig
@@ -1,12 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
index f3eabea..af17718 100644
--- a/configs/adp-ae3xx_defconfig
+++ b/configs/adp-ae3xx_defconfig
@@ -24,8 +24,8 @@
CONFIG_CLK=y
CONFIG_MMC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_NDS32=y
CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 742d904..481ef5b 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -21,8 +21,8 @@
CONFIG_DM=y
CONFIG_MMC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_NDS32=y
CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_ETH=y
CONFIG_FTMAC100=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index ab7d96d..d72228b 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -17,7 +18,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
@@ -38,11 +38,13 @@
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)"
CONFIG_CMD_UBI=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_OMAP24_I2C_SPEED=1000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index ed430e7..5688e44 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -3,13 +3,13 @@
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_AUTOBOOT_KEYED=y
@@ -17,10 +17,13 @@
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_MMC=y
@@ -28,7 +31,7 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index df73f65..b9726ed 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -3,6 +3,7 @@
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_SIGNATURE=y
@@ -12,7 +13,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_AUTOBOOT_KEYED=y
@@ -25,6 +25,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
@@ -34,8 +35,8 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 60120bf1..158ae0a 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -2,14 +2,15 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
@@ -26,6 +27,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
@@ -38,8 +40,8 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 6598879..af12695 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -3,12 +3,12 @@
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
CONFIG_NOR=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
@@ -20,6 +20,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
@@ -29,7 +30,7 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 22182f5..068c3f2 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -18,13 +18,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),4m(kernel),-(rootfs)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 079f69d..23ad679 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -5,6 +5,7 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_SPI_BOOT=y
@@ -12,8 +13,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
@@ -21,13 +22,14 @@
CONFIG_MTDIDS_DEFAULT="nor0=m25p80-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=m25p80-flash.0:128k(SPL),512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),3464k(kernel),-(rootfs)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index e4bf757..25d01bb 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -3,13 +3,15 @@
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
@@ -26,6 +28,8 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
@@ -34,7 +38,7 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index c903cc7..4eb5e27 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -7,8 +7,10 @@
CONFIG_AM33XX=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
@@ -17,7 +19,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_EXT_SUPPORT is not set
@@ -32,6 +33,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
@@ -45,8 +47,8 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index 6971e57..1321d52 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -7,6 +7,7 @@
# CONFIG_SPL_MMC_SUPPORT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_DISTRO_DEFAULTS=y
@@ -16,7 +17,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
@@ -30,6 +30,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
@@ -42,8 +43,8 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index d2026da..48dc3c9 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -17,7 +18,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
@@ -39,10 +39,11 @@
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index 58d7676..a9d0f8e 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -9,13 +9,13 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
CONFIG_LOCALVERSION="-EETS-1.0.0"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@@ -47,6 +47,7 @@
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_TPS65910=y
+CONFIG_CONS_INDEX=4
CONFIG_SYS_NS16550=y
# CONFIG_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index fb714da..42196dd 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -10,18 +10,19 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
@@ -34,8 +35,10 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 2568e3d..a32248e 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
@@ -17,12 +18,12 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
@@ -35,8 +36,10 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 16071fb..3474f51 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
@@ -17,13 +18,13 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
@@ -36,8 +37,10 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
index bbad6dd..de852cb 100644
--- a/configs/am335x_shc_prompt_defconfig
+++ b/configs/am335x_shc_prompt_defconfig
@@ -10,18 +10,19 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_AUTOBOOT_DELAY_STR="shc"
@@ -33,8 +34,10 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index 82a61a3..346efad 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
@@ -17,12 +18,12 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
@@ -35,8 +36,10 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
index 82a61a3..346efad 100644
--- a/configs/am335x_shc_sdboot_prompt_defconfig
+++ b/configs/am335x_shc_sdboot_prompt_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
@@ -17,12 +18,12 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
@@ -35,8 +36,10 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index cd1b78e..d51812e 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -10,12 +10,12 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -38,9 +38,10 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index 9d092ef..23b3441 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -5,8 +5,8 @@
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_AM3517_CRANE=y
CONFIG_EMIF4=y
-CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_BOOTDELAY=10
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
@@ -27,6 +27,7 @@
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HCD=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 4f9b161..26f3a96 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -7,12 +7,12 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
@@ -35,6 +35,7 @@
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 172b292..edb4119 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -3,6 +3,7 @@
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
@@ -10,7 +11,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
@@ -24,6 +24,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
@@ -35,7 +36,7 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 835a58d..fcb502c 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -1,12 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_AM43XX=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
@@ -34,6 +34,7 @@
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
@@ -41,7 +42,7 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 2bc302c..99daf5d 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x30000000
CONFIG_AM43XX=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
@@ -23,14 +24,23 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am4372-generic am437x-sk-evm am437x-idk-evm"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
@@ -48,4 +58,3 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
new file mode 100644
index 0000000..339a1c6
--- /dev/null
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_AM43XX=y
+CONFIG_SPL_RTC_DDR_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NAND_OFS=0x00100000
+CONFIG_CMD_SPL_WRITE_SIZE=0x40000
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_NAND=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_GIGE=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0403
+CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 7ca24d5..4e9a614 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
@@ -10,7 +11,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
@@ -38,6 +38,7 @@
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
@@ -49,7 +50,7 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index b69d855..d290af0 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -8,6 +8,7 @@
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
CONFIG_ISW_ENTRY_ADDR=0x403018e0
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
@@ -18,7 +19,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
@@ -35,6 +35,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
@@ -46,7 +47,7 @@
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 7ed010f..6b11b34 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -7,6 +7,7 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_DISTRO_DEFAULTS=y
@@ -18,11 +19,11 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
@@ -37,6 +38,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SCSI_AHCI=y
@@ -51,10 +53,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index d9fb6ec..ca9742f 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -11,6 +11,7 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
CONFIG_DISTRO_DEFAULTS=y
@@ -24,10 +25,10 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
@@ -40,6 +41,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SCSI_AHCI=y
@@ -54,10 +56,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index d88be90..2d418f6 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -18,6 +18,7 @@
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
index 7848b9d..4c39b34 100644
--- a/configs/ap143_defconfig
+++ b/configs/ap143_defconfig
@@ -19,6 +19,7 @@
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 7de517c..7718c29 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -12,6 +12,7 @@
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_PROMPT="Apalis TK1 # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 7b6adad..77a4008 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -7,15 +7,17 @@
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
@@ -30,6 +32,7 @@
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -46,7 +49,9 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig
index d6e3787..89af27f 100644
--- a/configs/apalis_imx6_nospl_com_defconfig
+++ b/configs/apalis_imx6_nospl_com_defconfig
@@ -9,7 +9,9 @@
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Apalis iMX6 # "
@@ -20,6 +22,7 @@
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -35,7 +38,9 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig
index 306f967..048d4f8 100644
--- a/configs/apalis_imx6_nospl_it_defconfig
+++ b/configs/apalis_imx6_nospl_it_defconfig
@@ -9,7 +9,9 @@
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Apalis iMX6 # "
@@ -20,6 +22,7 @@
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -35,7 +38,9 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index bc4b8c5..ddfdc2e 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -8,6 +8,7 @@
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_PROMPT="Apalis T30 # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index d77d2b5..8573528 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -4,13 +4,13 @@
CONFIG_SYS_TEXT_BASE=0xA0000800
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" apf27 patch 3.10"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySMX0,115200 mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs) ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="BIOS> "
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index ea4e18e..93718b4 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -6,12 +6,12 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_APX4DEVKIT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
@@ -31,6 +31,7 @@
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 8343846..d0e9829 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -32,6 +32,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index b49b1f2..617416e 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -32,6 +32,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index cc713e2..78e9352 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -32,6 +32,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 479f7d8..66d299b 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_ARNDALE=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ARNDALE"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_DISTRO_DEFAULTS=y
@@ -10,7 +11,6 @@
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="ARNDALE # "
CONFIG_CMD_GPIO=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index b41fe5b..ae2293d 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index a30a4f6..93f7612 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index 58a3431..f7585d0 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 575e217..bf06d32 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -49,7 +49,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index 7be7bec..ad7791a 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -49,7 +49,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 353dc0d..079c695 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -49,7 +49,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 418bbfc..06390dc 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -55,7 +55,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index 418bbfc..06390dc 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -55,7 +55,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index 1b3ef9b..5c3959e 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -55,7 +55,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 39abe2d..a26da00 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -54,7 +54,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 0426735..4f08450 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -54,7 +54,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 2382b25..c6cc752 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -49,7 +49,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 531dde8..81b291e 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -49,7 +49,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 4973519..9a53931 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -49,7 +49,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index c9ef79b..5f8824c 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -52,7 +52,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index 982ddfd..324f3ac 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -52,7 +52,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 36bb990..25bd456 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index de6d39d..c8cb0af 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index f8d9107..b4ddf9c 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index f1fc70b..a253d44 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -51,7 +51,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 966d544..dc95145 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -51,7 +51,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 634e3de..acd4a89 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -51,7 +51,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index e80d43c..7f3fd4d 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -48,7 +48,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index b18f2d4..84c9fa5 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -48,7 +48,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 5e8c97d..21b1958 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -48,7 +48,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index b4b2502..069cd2a 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -54,7 +54,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index c8c027e..b7e050f 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -54,7 +54,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 1fb3ff4..3ad4729 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -54,7 +54,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 6848bcc..fa400c8 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -54,7 +54,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index c935a0c..216ef83 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index db34a92..42ff46c 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index 179ab02..0e2b544 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -50,7 +50,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 911620a..69937a6 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
CONFIG_BOOTDELAY=3
@@ -19,7 +20,7 @@
CONFIG_BOOTARGS="\0addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}::off\0addtest=setenv bootargs ${bootargs} loglevel=4 test\0baudrate=115200\0boot_file=setenv bootfile /${project_dir}/kernel/uImage\0boot_retries=0\0bootcmd=run flash_self\0bootdelay=3\0ethact=macb0\0flash_nfs=run nand_kernel;run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0flash_self=run nand_kernel;run setbootargs;upgrade_available;bootm ${kernel_ram};reset\0flash_self_test=run nand_kernel;run setbootargs addtest; upgrade_available;bootm ${kernel_ram};reset\0hostname=systemone\0kernel_Off=0x00200000\0kernel_Off_fallback=0x03800000\0kernel_ram=0x21500000\0kernel_size=0x00400000\0kernel_size_fallback=0x00400000\0loads_echo=1\0nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} ${kernel_size}\0net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0netdev=eth0\0nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs rw nfsroot=${serverip}:${rootpath} at91sam9_wdt.wdt_timeout=16\0partitionset_active=A\0preboot=echo;echo Type 'run flash_self' to use kernel and root filesystem on memory;echo Type 'run flash_nfs' to use kernel from memory and root filesystem over NFS;echo Type 'run net_nfs' to get Kernel over TFTP and mount root filesystem over NFS;echo\0project_dir=systemone\0root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0rootfs=/dev/mtdblock5\0rootfs_fallback=/dev/mtdblock7\0setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops root=${rootfs} rootfstype=jffs2 panic=7 at91sam9_wdt.wdt_timeout=16\0stderr=serial\0stdin=serial\0stdout=serial\0upgrade_available=0\0"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index e612a87..afff94f 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_EMR1=4
@@ -9,7 +9,6 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
index db74254..fcdcbd0 100644
--- a/configs/bananapi_m1_plus_defconfig
+++ b/configs/bananapi_m1_plus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
@@ -9,7 +9,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig
index 8679ff5..60cbfd9 100644
--- a/configs/bananapi_m64_defconfig
+++ b/configs/bananapi_m64_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index c84356b..5f7a09d 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -17,6 +17,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index 948ac1c..4bf8a29 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -17,6 +17,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SHA1=y
CONFIG_SHA256=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index 60e9ad6..7608d37 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -17,6 +17,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SHA1=y
CONFIG_SHA256=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index d44555f..ac03934 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -17,6 +17,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SHA1=y
CONFIG_SHA256=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index 1e78d03..7af8104 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -17,6 +17,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SHA1=y
CONFIG_SHA256=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index d44555f..ac03934 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -17,6 +17,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SHA1=y
CONFIG_SHA256=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index d44555f..ac03934 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -17,6 +17,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SHA1=y
CONFIG_SHA256=y
diff --git a/configs/bcm958712k_defconfig b/configs/bcm958712k_defconfig
index 48c772e..b69ba5d 100644
--- a/configs/bcm958712k_defconfig
+++ b/configs/bcm958712k_defconfig
@@ -6,5 +6,6 @@
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="u-boot> "
+CONFIG_CONS_INDEX=4
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 797d113..8a53092 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_BG0900=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200"
@@ -13,7 +14,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -33,5 +33,6 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CONS_INDEX=0
CONFIG_MXS_SPI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 823fc74..edc24d6 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_BAV_VERSION=1
CONFIG_DISTRO_DEFAULTS=y
@@ -18,7 +19,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
@@ -42,13 +42,14 @@
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 6d12aba..4f814e4 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_BAV_VERSION=2
CONFIG_DISTRO_DEFAULTS=y
@@ -18,7 +19,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
@@ -42,13 +42,14 @@
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 2780e1e..441a156 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -29,6 +29,7 @@
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 6de9a78..e202bc3 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
CONFIG_BOOTDELAY=-2
@@ -20,7 +21,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@@ -54,7 +54,7 @@
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index a1a5590..8adbfa0 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -7,6 +7,7 @@
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=-2
@@ -18,7 +19,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@@ -56,7 +56,7 @@
CONFIG_BOOTCOUNT_LIMIT=y
# CONFIG_MMC is not set
CONFIG_NAND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 0052d16..67d125c 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
CONFIG_SPI_BOOT=y
@@ -23,9 +24,9 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -63,7 +64,7 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 3f37573..45f11d1 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=-2
# CONFIG_CONSOLE_MUX is not set
@@ -18,7 +19,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@@ -54,7 +54,7 @@
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index 70540fb..88f4848 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -2,12 +2,12 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_OMAP3_CAIRO=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=-2
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Cairo # "
@@ -29,6 +29,7 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 2ac0bac..e28c683 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
@@ -18,9 +19,9 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
CONFIG_FASTBOOT=y
@@ -46,9 +47,11 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DWC_AHSATA=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index 8ec24a4..a421504 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -7,6 +7,8 @@
CONFIG_SMP=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index b60ded6..344a3a0 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -8,13 +8,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_CMD_ASKENV=y
@@ -34,7 +34,7 @@
CONFIG_DM_GPIO=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index fbe0e5d..7bf9cdf 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -12,8 +12,10 @@
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index bced22e..23eeb92 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -13,9 +13,11 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index e84e571..cd3f910 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -21,6 +21,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 2f379cf..f402f8c 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -14,6 +14,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 913b32e..28f87d8 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -13,8 +13,10 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index b7bddf6..cdd1ae5 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -14,6 +14,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 226f474..841dce3 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -11,6 +11,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig
index 641c9b6..873f80d 100644
--- a/configs/cl-som-am57x_defconfig
+++ b/configs/cl-som-am57x_defconfig
@@ -3,11 +3,13 @@
CONFIG_OMAP54XX=y
CONFIG_TARGET_CL_SOM_AM57X=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
@@ -24,6 +26,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SCSI_AHCI=y
CONFIG_CMD_PCA953X=y
CONFIG_LED_STATUS=y
@@ -42,7 +45,8 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index aab2eb7..0861e62 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -9,17 +9,18 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CL-SOM-iMX7 # "
CONFIG_CMD_BOOTZ=y
@@ -44,6 +45,7 @@
CONFIG_CMD_FS_GENERIC=y
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MXC_SPI=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 2359ad2..3d5ff11 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -8,13 +8,14 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
@@ -30,6 +31,7 @@
CONFIG_CMD_TIME=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 183ad42..5926004 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
CONFIG_AHCI=y
@@ -18,9 +19,9 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="CM-FX6 # "
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GREPENV=y
@@ -45,9 +46,11 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DWC_AHSATA=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 46979b3..9b0eed8 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -9,16 +9,17 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="CM-T335 # "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
@@ -44,7 +45,7 @@
CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 3224c9d..97ed532 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -44,6 +44,7 @@
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2D000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index e0e7994..5640f22 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -3,10 +3,10 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_CM_T35=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3x # "
@@ -45,6 +45,7 @@
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 4e7978c..917bd6a 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -10,6 +10,7 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -17,12 +18,12 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
@@ -41,6 +42,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_MMC_OMAP_HS=y
@@ -55,7 +57,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index 07a52f6..20cb0fd 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -4,13 +4,13 @@
CONFIG_TARGET_CM_T54=y
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_SATA_SUPPORT=y
CONFIG_SYS_PROMPT="CM-T54 # "
@@ -28,9 +28,11 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SCSI_AHCI=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
+CONFIG_CONS_INDEX=4
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index b982a5e..c19e782 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -7,15 +7,17 @@
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
@@ -30,6 +32,7 @@
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -46,6 +49,8 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_USB=y
diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig
index c508821..aecc179 100644
--- a/configs/colibri_imx6_nospl_defconfig
+++ b/configs/colibri_imx6_nospl_defconfig
@@ -9,7 +9,9 @@
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX6 # "
@@ -20,6 +22,7 @@
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -35,6 +38,8 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_USB=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 5e013a5..b6139c0 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -12,6 +12,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
@@ -42,9 +43,11 @@
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_MTD_UBI_FASTMAP=y
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index e21068e..64e740c 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -5,6 +5,7 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
@@ -22,6 +23,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 7ddbd84..7e04549 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_PROMPT="Colibri T20 # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 6b15a08..73d1bb5 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -8,6 +8,7 @@
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_PROMPT="Colibri T30 # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index d30f3eb..77ad26e 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -10,6 +10,7 @@
CONFIG_LOGLEVEL=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
@@ -38,11 +39,13 @@
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
CONFIG_MTD_UBI_FASTMAP=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 0342d93..e6007b5 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
@@ -16,7 +16,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig
index 892977a..6b2c355 100644
--- a/configs/comtrend_ar5315u_ram_defconfig
+++ b/configs/comtrend_ar5315u_ram_defconfig
@@ -27,7 +27,9 @@
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
@@ -38,7 +40,8 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
-CONFIG_POWER_DOMAIN=y
+CONFIG_PHY=y
+CONFIG_BCM6318_USBH_PHY=y
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
@@ -47,3 +50,9 @@
CONFIG_BCM6345_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_BCM63XX_HSSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig
index 12dbf0b..efccf9a 100644
--- a/configs/comtrend_ar5387un_ram_defconfig
+++ b/configs/comtrend_ar5387un_ram_defconfig
@@ -27,7 +27,9 @@
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
@@ -38,6 +40,8 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
@@ -47,3 +51,9 @@
CONFIG_BCM6345_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_BCM63XX_HSSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig
index 108e8ea..708dcda 100644
--- a/configs/comtrend_ct5361_ram_defconfig
+++ b/configs/comtrend_ct5361_ram_defconfig
@@ -24,7 +24,9 @@
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
@@ -34,9 +36,15 @@
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6348_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
CONFIG_WDT_BCM6345=y
diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig
index 8149fab..3920f33 100644
--- a/configs/comtrend_vr3032u_ram_defconfig
+++ b/configs/comtrend_vr3032u_ram_defconfig
@@ -25,13 +25,17 @@
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
@@ -39,3 +43,9 @@
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig
index 6112725..a9c00e9 100644
--- a/configs/comtrend_wap5813n_ram_defconfig
+++ b/configs/comtrend_wap5813n_ram_defconfig
@@ -24,7 +24,9 @@
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
@@ -34,8 +36,16 @@
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 439a7dd..e2276a8 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -20,6 +20,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index afa0277..7329804 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -18,6 +18,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index 7136a4b..b009176 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -14,6 +14,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_EEPROM=y
@@ -34,9 +36,12 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_SATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index 6654968..472f363 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -14,6 +14,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_EEPROM=y
@@ -34,9 +36,12 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_SATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
index ef1c5e0..a57837a 100644
--- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
@@ -9,6 +9,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
@@ -22,7 +24,9 @@
# CONFIG_CMD_IRQ is not set
CONFIG_DOS_PARTITION=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
# CONFIG_PCI is not set
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig
index 879072a..c589507 100644
--- a/configs/controlcenterd_TRAILBLAZER_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_defconfig
@@ -9,6 +9,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
@@ -22,7 +24,9 @@
# CONFIG_CMD_IRQ is not set
CONFIG_DOS_PARTITION=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
# CONFIG_PCI is not set
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index 893dc68..5fe18c6 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -6,15 +6,18 @@
CONFIG_TARGET_CONTROLCENTERDC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index d8e8d17..ecedc8b 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -8,6 +8,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 7f385d6..c15a796 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -10,6 +10,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
@@ -17,7 +18,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -44,7 +44,6 @@
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
CONFIG_PHYLIB=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 4ec4eda..7ee7dfb 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -7,6 +7,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 00df2f6..d2e5290 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -12,6 +12,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index 93c833d..1bf959d 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
CONFIG_BOOTDELAY=3
@@ -16,8 +17,8 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index f1e0671..a72c94e 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
@@ -15,8 +16,8 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index b3d06ae..d9028a4 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -8,14 +8,16 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 29c9a39..e01d85b 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@@ -14,8 +15,9 @@
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 2beacdb..857b43c 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -8,14 +8,16 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index cfe852f..a9cb3e4 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -8,14 +8,16 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index fcc80b2..a88cf1c 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -5,13 +5,13 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_IMLS=y
@@ -36,6 +36,8 @@
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=31
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LPC32XX_SSP=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index c670ff4..defed2d 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -2,11 +2,11 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_DEVKIT8000=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
@@ -27,5 +27,6 @@
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index fa6ccc4..700662a 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -17,6 +17,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda1 ro quiet"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 2b4fe9c..de1016e 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -10,14 +10,15 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
CONFIG_CMD_DFU=y
@@ -36,6 +37,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 49bb62e..aa6c040 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
@@ -15,11 +15,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 4d67700..a5f1cf1 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -9,19 +9,20 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SAVEENV=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 > "
CONFIG_CMD_BOOTZ=y
@@ -51,6 +52,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -59,6 +61,5 @@
CONFIG_PHY_MARVELL=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_MXC_SPI=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index c968ca0..8c07f25 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
@@ -15,12 +16,12 @@
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run factory"
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@@ -58,6 +59,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -65,7 +67,6 @@
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index 8008916..8c1a55f 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index 7803052..578cd69 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -29,6 +29,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 1cc614f..e17135c 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -7,8 +7,10 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,11 +20,11 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
@@ -34,7 +36,10 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
@@ -52,15 +57,17 @@
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SPL_PHY=y
+CONFIG_PIPE3_PHY=y
CONFIG_PMIC_PALMAS=y
CONFIG_PMIC_LP873X=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 5a8129c..606f999 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -11,8 +11,10 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
@@ -24,10 +26,10 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
@@ -39,6 +41,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_REGMAP=y
@@ -59,10 +62,11 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_SPL_PHY=y
+CONFIG_PIPE3_PHY=y
CONFIG_PMIC_PALMAS=y
CONFIG_PMIC_LP873X=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 985e662..e562f1e 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -21,9 +22,10 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -64,7 +66,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 5d1d6ab..9071859 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -8,14 +8,16 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
@@ -39,6 +41,7 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index caf2229..9f5d22a 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PB9"
@@ -14,7 +14,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index a510294..23ca1b7 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -3,12 +3,12 @@
CONFIG_OMAP44XX=y
CONFIG_TARGET_DUOVERO=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SYS_PROMPT="duovero # "
CONFIG_CMD_ASKENV=y
@@ -23,11 +23,13 @@
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 38f1624..eea434c 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -4,8 +4,8 @@
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_ECO5PK=y
CONFIG_EMIF4=y
-CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_BOOTDELAY=10
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ECO5-PK # "
@@ -32,6 +32,7 @@
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
index d3ada21..b0e2622 100644
--- a/configs/edb9315a_defconfig
+++ b/configs/edb9315a_defconfig
@@ -37,5 +37,6 @@
CONFIG_LED_STATUS_GREEN=0
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index 7e095b9..54305fc 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -4,6 +4,7 @@
CONFIG_DEFAULT_DEVICE_TREE="edison"
CONFIG_TARGET_EDISON=y
CONFIG_SMP=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_CMD_CPU=y
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index 78dbd0a..1ad1fb7 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -5,11 +5,11 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_EDMINIV2=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" EDMiniV2"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index 7d162a8..1a22ef0 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -7,6 +7,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index dd862bb..ed7b6d5 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -21,9 +22,10 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -64,7 +66,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 888bed9..80ca4ac 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -61,6 +61,5 @@
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index e3abe41..c03682c 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -8,6 +8,7 @@
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index dd388a9..575fd10 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_ANDROID_BOOT_IMAGE is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_STACK_R=y
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index e7414c9..5407cba 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FASTBOOT_BUF_ADDR=0x60800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 5ec9788..549a166 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -11,6 +11,7 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 7ba7178..048c855 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -11,6 +11,7 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 266d699..a52e37a 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -7,6 +7,7 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index b5ae073..b36f232 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -12,6 +12,7 @@
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_CMD_BOOTZ=y
diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index bac4463..d72f0d4 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -7,6 +7,7 @@
CONFIG_DEBUG_UART=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FASTBOOT_BUF_ADDR=0x62000000
CONFIG_FASTBOOT_BUF_SIZE=0x08000000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 11112ca..fc038ae 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -12,6 +12,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index adb6b5d..b2fe19a 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -11,6 +11,7 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 03d0324..984c3f4 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_ATF=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 1d7cc16..24f3a83 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
@@ -17,12 +17,12 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index d516d40..233137b 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -10,6 +10,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 045380b..6f7424a 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -10,6 +10,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-b450v3.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -30,6 +31,7 @@
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index 9d4b8ae..7919b4c 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -10,6 +10,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-b650v3.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -30,6 +31,7 @@
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index 9478568..7df83cf 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -10,6 +10,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-b850v3.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -30,6 +31,7 @@
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index 83c1a4b..4644e8d 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig
@@ -7,6 +7,7 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index 2b94fe2..f11ba12 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=32767
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index a6db104..c77de88 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
@@ -19,8 +20,8 @@
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
@@ -55,6 +56,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 41b93c8..007b49a 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
@@ -19,8 +20,8 @@
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
@@ -55,6 +56,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=5
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index e513289..1de7081 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
@@ -20,8 +21,8 @@
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
@@ -57,6 +58,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig
index a07b37a..c381b00 100644
--- a/configs/h2200_defconfig
+++ b/configs/h2200_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
# CONFIG_MMC is not set
+CONFIG_CONS_INDEX=3
CONFIG_PXA_SERIAL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 398da03..b0eba06 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=15355
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 55f83ed..6375034 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -20,4 +20,5 @@
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
# CONFIG_MMC is not set
CONFIG_SCSI=y
+CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 84d7f37..58eb823 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -18,6 +18,7 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
+CONFIG_CONS_INDEX=4
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index 7f2fcf9..68b48b3 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -12,6 +12,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
@@ -25,7 +27,10 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 210c7f9..b569717 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -13,6 +13,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_FPGAD=y
@@ -23,7 +25,10 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index 11cb7e0..37f6190 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -7,13 +7,19 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="hsdk# "
+CONFIG_CMD_ENV_FLAGS=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -25,12 +31,20 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_CLK_HSDK=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig
index b9208ff..4a13de4 100644
--- a/configs/huawei_hg556a_ram_defconfig
+++ b/configs/huawei_hg556a_ram_defconfig
@@ -24,7 +24,9 @@
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
@@ -34,8 +36,16 @@
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6358_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 88cea82..3d89c4b 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index b785034..ff5f64a 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
@@ -14,7 +14,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 4a1e538..763222c 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=127
@@ -14,7 +14,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index d85b046..91cc85b 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_USB0_VBUS_PIN="PG12"
@@ -13,11 +13,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index 88e858c..e7e046c 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
@@ -17,12 +17,12 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-d978-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index adbd46a..b68147a 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
@@ -13,7 +13,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 44b411c..481a3c7 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -39,7 +39,8 @@
CONFIG_SYS_BOOTCOUNT_ADDR=0x9
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_MPC8XXX_SPI=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index b0daee1..5420dcb 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
@@ -9,7 +10,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
@@ -37,6 +37,7 @@
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
@@ -44,6 +45,7 @@
CONFIG_USB_OMAP3=y
CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
+CONFIG_UBIFS_SILENCE_MSG=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 22dbc70..d276ea5 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
@@ -9,7 +10,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
@@ -38,6 +38,7 @@
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
@@ -45,6 +46,7 @@
CONFIG_USB_OMAP3=y
CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
+CONFIG_UBIFS_SILENCE_MSG=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index d17f9cf..74a534c 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -7,6 +7,7 @@
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
CONFIG_FIT=y
@@ -14,7 +15,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
@@ -34,6 +34,7 @@
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index 2a86059..0caba80 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -7,6 +7,7 @@
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_FIT=y
@@ -15,7 +16,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
@@ -35,6 +35,7 @@
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index e6b3264..f0974bf 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -24,7 +24,9 @@
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig
index 6dc8d2f..4e1dad6 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
CONFIG_DEBUG_UART=y
@@ -19,7 +20,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-mipi> "
@@ -39,6 +39,7 @@
CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index a3f5e8f..308e11c 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_DEBUG_UART=y
@@ -19,7 +20,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
@@ -42,6 +42,7 @@
CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index 2a86059..0caba80 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -7,6 +7,7 @@
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_FIT=y
@@ -15,7 +16,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
@@ -35,6 +35,7 @@
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index 6c8fb85..fb7f260 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
CONFIG_FIT=y
@@ -18,7 +19,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
@@ -38,6 +38,7 @@
CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index b6d8680..b4aa1b2 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
CONFIG_FIT=y
@@ -17,7 +18,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_CRC32_VERIFY=y
@@ -35,6 +35,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
index a8eb08b..f836c18 100644
--- a/configs/imx6ul_geam_nand_defconfig
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -7,6 +7,7 @@
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
CONFIG_FIT=y
@@ -15,7 +16,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
@@ -36,6 +36,7 @@
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index a9bfbfd..2a5dbef 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_FIT=y
@@ -17,7 +18,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_CRC32_VERIFY=y
@@ -35,6 +35,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig
index ba898e6..2c84424 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -7,6 +7,7 @@
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
CONFIG_FIT=y
@@ -15,7 +16,6 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
@@ -36,6 +36,7 @@
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index cf3b557..24ca2dc 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
@@ -14,7 +14,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index b87dfb9..8de41e5 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index d7a34ab..635b763 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
@@ -13,7 +13,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index 1107cb1..32b8568 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
@@ -15,11 +15,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 96b315a..15889093 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
@@ -13,7 +13,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig
index 65fd456..4f9d750 100644
--- a/configs/inet_q972_defconfig
+++ b/configs/inet_q972_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_ZQ=251
@@ -15,7 +15,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
index f2d327a..13e0311 100644
--- a/configs/ipam390_defconfig
+++ b/configs/ipam390_defconfig
@@ -7,11 +7,11 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index adfc172..94c7cbe 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_MACPWR="PH19"
@@ -8,7 +8,6 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index c8bf8f2..b817a69 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,9 +16,9 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index a79ce60..6224222 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -11,6 +11,7 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -21,6 +22,8 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 2afb768..87b887c 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,9 +16,9 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -30,6 +31,7 @@
CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 5402cd3..86cb526 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -11,6 +11,7 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -20,6 +21,10 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 2252e45..feda22b 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,9 +16,9 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 09ac21e..1cca0ca 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -11,6 +11,7 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -21,6 +22,8 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 791bbae..4ff69fe 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,9 +16,9 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
new file mode 100644
index 0000000..cc002d3
--- /dev/null
+++ b/configs/k2l_hs_evm_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_TEXT_BASE=0xC000060
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_TARGET_K2L_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_GPT is not set
+# CONFIG_CMD_MMC is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_TI_AEMIF=y
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index ec5fb5e..534d604 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -4,10 +4,10 @@
CONFIG_OMAP44XX=y
CONFIG_TARGET_KC1=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
@@ -25,6 +25,7 @@
# CONFIG_CMD_NFS is not set
CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index a0b3f8d..0bfb594 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -20,6 +20,8 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index 9d22c21..1d92b2d 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -9,6 +9,8 @@
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 3426adf..1440849 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index e795ac4..1d9b982 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
index 12c06cc..9950617 100644
--- a/configs/kmlion1_defconfig
+++ b/configs/kmlion1_defconfig
@@ -9,6 +9,8 @@
CONFIG_SYS_EXTRA_OPTIONS="KMLION1"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index f3babb6..cd34d5d 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index ac3f336..eca1536 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index a5930ef..5e5ffc4 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 7441e4a..322e725 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index b415c9d..4a1b932 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index c7bd73f9..0dc493c 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_ANDROID_BOOT_IMAGE is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_STACK_R=y
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index a7177b9..931496c 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -20,6 +20,8 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig
index 3ed2889..1e2ce4b 100644
--- a/configs/libretech_all_h3_cc_h3_defconfig
+++ b/configs/libretech_all_h3_cc_h3_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -8,7 +8,6 @@
CONFIG_R_I2C_ENABLE=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 8a95ce3..0a5e5b3 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
@@ -25,8 +26,8 @@
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_SPL=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index 22872b3..16e488a 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -8,12 +8,12 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
@@ -29,6 +29,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 26dcb1a..6685a6f 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -15,7 +15,9 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -29,9 +31,11 @@
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
-CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1164361..3f26940 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -15,7 +15,9 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
@@ -29,7 +31,8 @@
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
-CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 9fdf333..86209c2 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -16,8 +16,10 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -34,9 +36,11 @@
CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
-CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 6b87c9e..bf94031 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -17,7 +17,9 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -31,6 +33,7 @@
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 4347263..30bab90 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -15,7 +15,9 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -30,9 +32,11 @@
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
-CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 3a53c5e..e93633a 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -14,13 +14,14 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index dc79938..59592db 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -1,10 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_CMD_BOOTZ=y
@@ -18,13 +18,14 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 7301ead..5b16236 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -32,15 +32,17 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 8bad35c..82da84b 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -33,11 +33,12 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index ddb53aa..39e6bc6 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
@@ -48,11 +48,12 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index e058969..63ab44f 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -33,11 +33,12 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index fb7c456..c8b76ae 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -33,15 +33,17 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index e30fba9..101421f 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -34,11 +34,12 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 379ff90..8ae176c 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -34,12 +34,13 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index da924aa..4265eea 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -16,7 +17,6 @@
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
@@ -46,11 +46,12 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 15d7876..2944723 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -16,7 +17,6 @@
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
@@ -45,12 +45,13 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 508abb8..17a202d 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -27,11 +27,12 @@
CONFIG_CMD_BMP=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 2a2c291..a18426e 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -27,15 +27,17 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 11091db..83ffa19 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -29,11 +29,12 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index d5c5711..d1457a6 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -30,13 +30,14 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 9154c72..705f227 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
@@ -21,7 +22,6 @@
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -42,11 +42,12 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 8acba2f..8e1959a 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
@@ -20,7 +21,6 @@
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
@@ -40,11 +40,12 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 1bfce52..d594250 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
@@ -20,7 +21,6 @@
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
@@ -40,13 +40,14 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index e8f9ba7..ce8a9f5 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -27,6 +27,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 4053d82..6f29647 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 908809b..305ac93 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
@@ -42,6 +42,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index d11eca6..4941db4 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -28,6 +28,7 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 9a45a09..0002412 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -27,6 +27,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index e06b2c9..20bf5f7 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
@@ -42,6 +42,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index da4cbf7..e57f2ff 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
@@ -40,6 +40,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 077185b..8e355c3 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 6f5204c..603bf46 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -22,6 +22,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index ec841e8..216a71e 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -19,7 +20,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -39,6 +39,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 8a5991d..7694268 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
@@ -39,6 +39,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 019d2e0..9de8476 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -38,6 +38,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 8620ad9..683983a 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
@@ -38,6 +38,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index b45a5c4..6015b2e 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -27,6 +27,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 5bec091..ca326b2 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index 76659e5..bb6897f 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -29,6 +29,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index f122108..1d40a14 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -12,7 +13,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
@@ -34,6 +34,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index 6985e95..379908a 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -27,6 +27,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 80bd715..4d0907c 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -12,7 +13,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
@@ -35,6 +35,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 0e46455..8467148 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -12,7 +13,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
@@ -33,6 +33,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 79a7676..3ca8f16 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -12,7 +13,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
@@ -30,6 +30,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 9bcbb73..e84bc0d 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -23,6 +23,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 97bd8e4..775f28c 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -24,6 +24,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index f0dc849..ee6320f 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -12,7 +13,6 @@
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -30,6 +30,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index a50d300..0fa6fa4 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -11,7 +12,6 @@
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
@@ -29,6 +29,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
new file mode 100644
index 0000000..946cad3
--- /dev/null
+++ b/configs/ls1088aqds_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+CONFIG_SYS_TEXT_BASE=0x30100000
+CONFIG_FSL_LS_PPA=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index cdf33e5..83b3ccd 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -13,6 +13,8 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -22,6 +24,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 455ecaa..8be7787 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -12,6 +12,8 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -22,6 +24,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
new file mode 100644
index 0000000..76ee120
--- /dev/null
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SD_BOOT=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 5baa7e9..ed7ffe4 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -16,12 +17,13 @@
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -32,6 +34,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index edfb029..8b6fbee 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -13,6 +13,8 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -22,6 +24,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index d568156..45fdfb8 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -12,6 +12,8 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -22,6 +24,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 6b4698d..5246471 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -17,7 +18,7 @@
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -25,6 +26,7 @@
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -34,6 +36,7 @@
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 94a7c80..94ea3d3 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -16,12 +17,13 @@
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -32,6 +34,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index 04bd65f..10b1821 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -30,6 +30,7 @@
# CONFIG_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 5c1422a..efda653 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -29,6 +29,7 @@
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 1fbeed1..8cd8107 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -30,6 +30,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index db3652d..dd3ad1f 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -16,7 +17,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -40,6 +40,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index e90158b..979d799 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -31,6 +31,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 1786e4f..94b3568 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -17,7 +18,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
@@ -38,6 +38,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 37e1da6..466b8b1 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -28,6 +28,7 @@
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
@@ -38,6 +39,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index de3ce13..8304411 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -29,6 +29,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
@@ -39,6 +40,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index ea0463e..49b9a32 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -16,7 +17,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -37,6 +37,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_PHYLIB=y
@@ -47,6 +48,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index 28fa200..3a61cb1 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -28,6 +28,7 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
@@ -38,6 +39,7 @@
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SCSI=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index b405a8e..a6e89b1 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -23,6 +23,7 @@
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
@@ -32,6 +33,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 4ea8a5c..f978be2 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -27,6 +27,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
@@ -36,6 +37,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index 7c53910..ce6cb0f 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_M28EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -16,7 +17,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -47,6 +47,7 @@
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CONS_INDEX=0
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index 52eb303..5dacd71 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -7,6 +7,7 @@
CONFIG_TARGET_M53EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aries/m53evk/imximage.cfg"
@@ -16,7 +17,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -41,6 +41,7 @@
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index 8322ed72..1dd8114 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -8,6 +8,8 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_ma5d4evk"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
@@ -16,7 +18,7 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -37,11 +39,14 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
+CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
@@ -56,5 +61,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 76b55df..e495b62 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -19,6 +19,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index b91c3ed..2848038 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -8,13 +8,15 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index da1d502..990944c 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -5,11 +5,11 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MCCMON6=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
@@ -24,7 +24,9 @@
CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index cbfd125..ff0a935 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -6,11 +6,11 @@
CONFIG_TARGET_MCCMON6=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
@@ -25,7 +25,9 @@
CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index f92bbac..90012f0 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -5,10 +5,10 @@
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_MCX=y
CONFIG_EMIF4=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mcx # "
@@ -38,6 +38,7 @@
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index f4b20fb..4aa9602 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -36,4 +36,3 @@
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index e1e5496..9d38247 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -37,4 +37,3 @@
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 699dc44..18bec1f 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -3,6 +3,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
@@ -15,7 +16,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=romfs"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index a198485..3547713 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -20,6 +20,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index a2e58a7..bc1f223 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -11,6 +11,7 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index a3f1dfd..963cb0d 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_MACPWR="PA21"
@@ -9,7 +9,6 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 8cd24f2..f8c7171 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -1,18 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index b54d6e6..3fd5ca6 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -1,11 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index dd788a0..c5caed5 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -1,10 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 54b126b..bdb5679 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -19,6 +19,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index 97bbd8e..6da1c93 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -4,10 +4,10 @@
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_EMIF4=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mt_ventoux => "
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 1d6233a..67a8077 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -11,12 +11,14 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@@ -44,6 +46,10 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_AARDVARK=y
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index da67aad..63f2103 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -12,6 +12,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 314d405..48dae2d 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -11,11 +11,14 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@@ -29,6 +32,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
+CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
@@ -42,7 +46,13 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_AARDVARK=y
CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_37XX=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index e16a56e..de682d1 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -12,6 +12,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index ebd95da..7ebdacf 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -6,11 +6,11 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX23_OLINUXINO=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
@@ -32,6 +32,7 @@
CONFIG_LED_STATUS_BOOT=0
CONFIG_LED_STATUS_CMD=y
CONFIG_MMC_MXS=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index ebdc108..84d1793 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -6,12 +6,12 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX23EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -27,6 +27,7 @@
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_NET is not set
CONFIG_MMC_MXS=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index a780733..8620ad2 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -18,6 +18,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index aa938a9..b1fe8ce 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -6,13 +6,13 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -42,6 +42,7 @@
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_CONS_INDEX=0
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 2c590ce..338c6e8 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -6,13 +6,13 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_FIT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -42,6 +42,7 @@
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_CONS_INDEX=0
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index fe8f151..2874fe0 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -6,12 +6,12 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -41,6 +41,7 @@
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_CONS_INDEX=0
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index ccc4c7a..9774719 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -6,12 +6,12 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -41,6 +41,7 @@
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_CONS_INDEX=0
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index 9f27c94..ef900ec 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -28,6 +28,7 @@
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_MXC_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 4eccf51..b7ed3ce 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -20,6 +20,7 @@
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index e772def..3bcd723 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -14,6 +14,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_NETDEVICES=y
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index c2e9411..351b8cd 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -23,6 +23,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
+CONFIG_FSL_ESDHC=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 8185eaa..cb86f56 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -13,4 +13,5 @@
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 7a68272..b938dcb 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -22,6 +22,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index f4a0b9b..0f5ce14 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -26,6 +26,7 @@
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
+CONFIG_FSL_ESDHC=y
CONFIG_NETDEVICES=y
CONFIG_RTC_S35392A=y
CONFIG_USB=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 0b41919..92cffb9 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -13,4 +13,5 @@
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 14f128a..6222ac6 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -9,13 +9,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
@@ -27,8 +27,10 @@
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index 1dc4e97..a2fe348 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -24,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index 8f07f8f..3b3169e 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -24,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index fdcef6b..d05c2cb 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -7,9 +7,9 @@
CONFIG_TARGET_MX6MEMCAL=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USB_ETHER=y
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index 925fc16..35f1d19 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -24,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index b907cb4..d707867 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -24,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 2b45dc1..7499704 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -13,6 +13,7 @@
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -35,6 +36,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index ee6ca57..2e4e0ff 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -9,13 +9,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_NXP_BOARD_REVISION=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -39,8 +39,10 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 83b8bed..c2d1cd4 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -9,12 +9,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
@@ -51,6 +51,8 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index a49e9cd..abc7788 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -32,6 +32,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 76fc584..a57e3b7 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -32,6 +32,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index c021b39..e9a40c8 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -9,12 +9,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -40,6 +40,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index 39c1cef..3c5da8c 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -28,6 +28,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 86f5195..3544897 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -29,6 +29,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 2ea2877..5ba3813 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -32,6 +32,7 @@
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 2856a7f..6ea92bb 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -31,9 +31,11 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 146c801..7b408e2 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
@@ -16,7 +17,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -40,9 +40,11 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index a992685..fd6962e 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -9,12 +9,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -35,6 +35,8 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index a36a872..86c942c 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -9,12 +9,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -35,6 +35,8 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 375db54..7a85397 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -23,10 +23,12 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index ce22715..0db69cd 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -24,10 +24,12 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index a7f08c5..da881d9 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -45,6 +45,7 @@
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PHYLIB=y
diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig
index a4cbf96..58e60ed 100644
--- a/configs/mx7dsabresd_secure_defconfig
+++ b/configs/mx7dsabresd_secure_defconfig
@@ -47,6 +47,7 @@
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PHYLIB=y
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index 57c5ebf..7949aa6 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -6,6 +6,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -18,6 +19,7 @@
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index ab782a0..dcac1ae 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -5,6 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -17,6 +18,7 @@
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig
index 76a8659..122fcc5 100644
--- a/configs/nanopi_a64_defconfig
+++ b/configs/nanopi_a64_defconfig
@@ -1,11 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig
index ab4d3e3..e0892c1 100644
--- a/configs/nanopi_m1_defconfig
+++ b/configs/nanopi_m1_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
index 22d515a..26483c6 100644
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
@@ -9,7 +9,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig
index 0d6926e..f27529d 100644
--- a/configs/nanopi_neo2_defconfig
+++ b/configs/nanopi_neo2_defconfig
@@ -1,12 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index ca9c2dd..b8860c1 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
@@ -9,7 +9,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
index 8a55885..87eb243 100644
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
@@ -9,7 +9,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
index 9753218..5f69799 100644
--- a/configs/nanopi_neo_plus2_defconfig
+++ b/configs/nanopi_neo_plus2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881977
@@ -8,7 +8,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig
index 595ad6c..f1ceb5c 100644
--- a/configs/netgear_cg3100d_ram_defconfig
+++ b/configs/netgear_cg3100d_ram_defconfig
@@ -27,6 +27,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig
new file mode 100644
index 0000000..4968336
--- /dev/null
+++ b/configs/netgear_dgnd3700v2_ram_defconfig
@@ -0,0 +1,55 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ARCH_BMIPS=y
+CONFIG_SOC_BMIPS_BCM6362=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="DGND3700v2 # "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BCM6328=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_BCM6345=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index c109aa3..5932e88 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -13,6 +13,7 @@
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 462229e..3414949 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -13,6 +13,7 @@
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 79c8de3..2e80523 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -13,6 +13,7 @@
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -34,6 +35,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 2895b6e..c0cd39a 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -13,6 +13,7 @@
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -34,6 +35,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index e7348af..bbd08cd 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -13,6 +13,7 @@
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index e9e9f73..1c916d0 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -13,6 +13,7 @@
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -32,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 2d28e0a..b7793d7 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -22,6 +22,7 @@
CONFIG_CMD_FAT=y
# CONFIG_NET is not set
CONFIG_MMC_OMAP_HS=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 75cc57b..1868305 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
@@ -20,7 +21,6 @@
CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_ASKENV=y
@@ -38,6 +38,7 @@
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/nx25-ae250_defconfig b/configs/nx25-ae250_defconfig
index 47b83db..4f9bd58 100644
--- a/configs/nx25-ae250_defconfig
+++ b/configs/nx25-ae250_defconfig
@@ -16,14 +16,15 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MMC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_NDS32=y
CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index caa60a4..3d593fa 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -13,6 +13,7 @@
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index bd3a7de..5943c19 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -25,6 +25,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 810874d..04a5e2c 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_DM_MMC=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index f0169a4..89f1df4 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -2,34 +2,43 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_PROMPT="BeagleBoard # "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
+CONFIG_CMD_SPL_NAND_OFS=0x280000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
+CONFIG_CMD_FS_UUID=y
+CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SPL_DM=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=1
@@ -45,11 +54,14 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
@@ -65,3 +77,5 @@
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
+CONFIG_SPL_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 3499877..4707d09 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -1,22 +1,22 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_MPUCLK=720
CONFIG_TARGET_OMAP3_EVM=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-evm"
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_ENV_SUPPORT=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
-# CONFIG_CMD_IMI is not set
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NAND_OFS=0x280000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -30,7 +30,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_UUID=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1792k(u-boot),128k(dtb),128k(u-boot-env),6m(kernel),-(rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
@@ -39,9 +39,10 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
@@ -54,14 +55,13 @@
CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x5678
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index e265164..d931343 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -3,9 +3,9 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_TAO3530=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
CONFIG_BOOTDELAY=3
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
@@ -28,6 +28,7 @@
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index c3e999e..144bdaa 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -3,12 +3,12 @@
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
@@ -46,7 +46,9 @@
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x08000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index 3e0aec2..f3b7343 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -2,11 +2,11 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_OVERO=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
@@ -38,6 +38,7 @@
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index a004f14..a0c8a36 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -28,6 +28,7 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index aa0c36e..7e01646 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -3,12 +3,12 @@
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_PANDA=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
@@ -26,7 +26,9 @@
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 0c7c80b..f5965da 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -6,12 +6,12 @@
CONFIG_TARGET_OMAP4_SDP4430=y
CONFIG_CMD_BAT=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -26,6 +26,7 @@
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 7e5fa82..abff63d 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -4,12 +4,12 @@
CONFIG_TARGET_OMAP5_UEVM=y
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_ARMV7_LPAE=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
@@ -24,12 +24,14 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SCSI_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_TCA642X=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index ccb308b..8adcf55 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
CONFIG_TARGET_OMAPL138_LCDK=y
+CONFIG_SYS_DA850_PLL0_POSTDIV=0
CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -9,13 +10,13 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_HUSH_PARSER=y
@@ -27,9 +28,13 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOOTP_DNS=y
+CONFIG_DM=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_COMPAT=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
@@ -38,6 +43,6 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DAVINCI_SPI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index d4c8db2..cff15a9 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
CONFIG_BOOTDELAY=5
@@ -18,7 +19,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -60,6 +60,7 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_PWRSEQ=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_NETDEVICES=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 9c26fea..ddd1acc 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -9,7 +9,6 @@
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index 8cbf5d4..770a4c2 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 672ac7e..575b305 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index a6777ac..893780a 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -1,18 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_MACPWR="PD6"
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_SPI_SUNXI=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 983e9be..c1e9aca 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -1,13 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
index 93f170c..f05e957 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
@@ -8,7 +8,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 0e36f12..8488a6c 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -9,7 +9,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index e62a074..1542519 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -11,7 +11,6 @@
CONFIG_SATAPWR="PG11"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig
index acff08c..759f825 100644
--- a/configs/orangepi_prime_defconfig
+++ b/configs/orangepi_prime_defconfig
@@ -1,12 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
index f21ea32..0fd2977 100644
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -1,16 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_SPI_SUNXI=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index 8263803..6afd4a3 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -1,17 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
# CONFIG_VIDEO_DE2 is not set
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
-CONFIG_SPL_SPI_SUNXI=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig
index f8b626e..b48f13e 100644
--- a/configs/orangepi_zero_plus2_defconfig
+++ b/configs/orangepi_zero_plus2_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
@@ -8,7 +8,6 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 884ee89..027be0d 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -3,13 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_ORIGEN=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ORIGEN"
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="ORIGEN # "
# CONFIG_CMD_XIMG is not set
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index e5baed1..f3ad096 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -28,6 +28,7 @@
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 29bbb9d..7aafee5 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -9,12 +9,13 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -36,6 +37,7 @@
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index d276e06..44221fc 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -20,6 +20,8 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index 6055501..fc3c407 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
@@ -12,11 +12,11 @@
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index a7094a6..3f06b6a 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
@@ -17,7 +18,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
@@ -39,10 +39,11 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index ee1165a..6a30fc0 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
@@ -17,7 +18,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
@@ -39,10 +39,11 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index a89e5d1..0b3d93e 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -28,6 +28,7 @@
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index b52499d..3ef7a8a 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -11,17 +11,19 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -37,6 +39,7 @@
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index b8c7abe..988e260 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -3,13 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_PEACH_PI=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pi"
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="Peach-Pi # "
CONFIG_CMD_GPIO=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index d62423a..165f895 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -3,13 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_PEACH_PIT=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pit"
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="Peach-Pit # "
CONFIG_CMD_GPIO=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 6218471..ab88d06 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -9,13 +9,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
@@ -44,9 +44,10 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),512k(SPL.backup1),512k(SPL.backup2),512k(SPL.backup3),1536k(u-boot),512k(u-boot-spl-os),512k(u-boot-env),5m(kernel),-(rootfs)"
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index a802e57..f3d048d 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -10,12 +10,12 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
@@ -28,10 +28,12 @@
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_NETDEVICES=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig
index c1ced48..eacd6b4 100644
--- a/configs/pfla02_defconfig
+++ b/configs/pfla02_defconfig
@@ -11,17 +11,19 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -36,6 +38,7 @@
CONFIG_CMD_UBI=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index bd698f5..09447b1 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -12,6 +12,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index c6fa11a..67b3eb1 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DFU_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_USB=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index b85486d..c355f06 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -22,6 +22,7 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_ESDHC=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_PHYLIB=y
CONFIG_USB=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index c53c656..19b96ba 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
@@ -18,7 +19,6 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 41ccff1..23365a5 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,16 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index c466d14..d265e8d 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -10,11 +10,11 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -42,6 +42,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index 298261d..a0df27b 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -10,11 +10,11 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -42,6 +42,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index 9570438..cd11aec 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -47,7 +47,6 @@
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index 38102dc..7d9b3d2 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -45,7 +45,6 @@
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index a9ec412..2759b72 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 7526aa1..175ef20 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 0d85349..4354c60 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -12,6 +12,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 736576c..1a92242 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -1,7 +1,9 @@
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
@@ -10,14 +12,19 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
@@ -39,21 +46,16 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
-CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas power-domains"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -65,7 +67,6 @@
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
-CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 9ad0bc1..7e1e6c7 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_USB0_VBUS_PIN="PB9"
@@ -14,7 +14,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index a8b4bac..4324a82 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -17,6 +17,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its"
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
@@ -25,6 +26,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
@@ -56,6 +58,7 @@
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 98edb88..b8b1f13d 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -23,8 +24,8 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
@@ -67,7 +68,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 2e09a5c..48e2623 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PG0"
@@ -15,11 +15,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 4262143..80e16e4 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63306
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index c6cf921..275fb19 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index c822175..569fb7e 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
@@ -16,11 +16,11 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 6fd5649..20003f8 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -10,6 +10,7 @@
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index d1ad802..10bbc76 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -23,6 +23,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index a26b40c..311fae3 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -13,6 +13,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
diff --git a/configs/qemu-x86_efi_payload32_defconfig b/configs/qemu-x86_efi_payload32_defconfig
index 2f3f6ce..d2fc546 100644
--- a/configs/qemu-x86_efi_payload32_defconfig
+++ b/configs/qemu-x86_efi_payload32_defconfig
@@ -9,6 +9,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/qemu-x86_efi_payload64_defconfig b/configs/qemu-x86_efi_payload64_defconfig
index 8666851..9fd563e 100644
--- a/configs/qemu-x86_efi_payload64_defconfig
+++ b/configs/qemu-x86_efi_payload64_defconfig
@@ -9,6 +9,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index f2ee229..2301e01 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -1,17 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_AXP152_POWER=y
+CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig
index 44921d9..6b5f109 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -37,7 +37,10 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index e85d0a4..4b2afb8 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -37,7 +37,10 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig
index 6420249..1bfd91f 100644
--- a/configs/r8a77965_salvator-x_defconfig
+++ b/configs/r8a77965_salvator-x_defconfig
@@ -38,7 +38,7 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig
index e0cf17a..3abd82c 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -38,7 +38,10 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index 5a65982..fedb82f 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -38,7 +38,10 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 3d421d2..eb8666a 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -37,7 +37,10 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 99a8089..ce92fba 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -38,7 +38,10 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index e561edc..4e684db 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -21,9 +22,10 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -64,7 +66,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index dd7df83..2842b54 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -19,6 +19,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 744a84a..d0d5dff 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -11,6 +11,7 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index f4882a8..c4a236c 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -11,6 +11,7 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_RANDOM_UUID=y
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index 04717d5..fcc2ae6 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -15,6 +15,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
@@ -22,6 +23,7 @@
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index f8203c9..204af74 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -15,6 +15,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
@@ -22,6 +23,7 @@
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 317fc28..9e142ca 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -16,10 +16,12 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
@@ -30,6 +32,7 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 0f3a54e..f46e504 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -16,10 +16,12 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
@@ -30,6 +32,7 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index d13d3d3..82c90d4 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -15,6 +15,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
@@ -22,6 +23,7 @@
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index e09f4c5..49d6258 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -24,8 +25,8 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
@@ -68,7 +69,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
index a28d24c..19b31db 100644
--- a/configs/s32v234evb_defconfig
+++ b/configs/s32v234evb_defconfig
@@ -8,5 +8,7 @@
CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 237b590..a54dd5f 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -26,6 +26,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 5014216..62b585d 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -25,6 +25,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=samsung-onenand:128k(s-boot),896k(bootloader),256k(params),2816k(config),8m(csa),7m(kernel),1m(log),12m(modem),60m(qboot),-(UBI)"
CONFIG_OF_CONTROL=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_DM_MMC=y
diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig
index 886e367..7b049fc 100644
--- a/configs/sagem_f@st1704_ram_defconfig
+++ b/configs/sagem_f@st1704_ram_defconfig
@@ -28,6 +28,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index b90a10c..3cd6e98 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
CONFIG_DEBUG_UART=y
@@ -19,7 +20,6 @@
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -77,7 +77,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index e112c31..cd53ac5 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_DEBUG_UART=y
@@ -21,7 +22,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -75,7 +75,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 232b6bf..5265a3d 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -19,7 +20,7 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -72,7 +73,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index 5377f6d..1c9148d 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -28,6 +28,7 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
@@ -54,7 +55,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DM_VIDEO=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index be75fb3..a39e230 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -28,6 +28,7 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
@@ -54,7 +55,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DM_VIDEO=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index fd9bf0c..d0be9fe 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -28,6 +28,7 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
@@ -54,7 +55,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DM_VIDEO=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 2d6793a..1e1d92e 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_DEBUG_UART=y
@@ -20,7 +21,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 3891539..9ff7651 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -18,7 +19,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index f9aff19..4beedb6 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_DEBUG_UART=y
@@ -22,7 +23,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -44,6 +44,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
@@ -76,7 +77,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 49b229c..53346ed 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -20,7 +21,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -39,6 +39,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
@@ -71,7 +72,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 607e997..72b88c7 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -19,7 +20,7 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -38,6 +39,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
@@ -70,7 +72,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index e850a2d..59edbd0 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_DEBUG_UART=y
@@ -20,7 +21,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -71,7 +71,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 9c8eedf..ce78111 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -18,7 +19,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -68,7 +68,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index a2411ab..abc71f2 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -19,7 +20,7 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -70,7 +71,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 12b7313..81812a6 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_DEBUG_UART=y
@@ -22,7 +23,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -71,7 +71,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index ed24e17..dc84cff 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -20,7 +21,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -68,7 +68,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 9e63c4f..d1f552f 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -19,7 +20,7 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -67,7 +68,6 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 8f96c16..ff60508 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -20,6 +20,7 @@
CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=6
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 0638283..fd39519 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -20,6 +20,7 @@
CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=6
CONFIG_LOG_ERROR_RETURN=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index d5f2379..9b8d033 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -15,6 +15,7 @@
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index b01a9fd..8bdd4ed 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -16,6 +16,7 @@
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 802dc30..c308628 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -4,6 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DISTRO_DEFAULTS=y
@@ -21,7 +22,7 @@
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_CPU=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index d35798f..8697dca 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_SANSA_FUZE_PLUS=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 "
@@ -15,7 +16,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
@@ -29,6 +29,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MMC_MXS=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index c71eacf..866c440 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -18,6 +18,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 3910a3f..5752fce 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -18,6 +18,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index cf5cae0..4bd0603 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -16,7 +16,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index 97689ae..6c0ff6b 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -23,6 +23,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index 71940d2..ff4065f 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -23,6 +23,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index b3bb691..067201e 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -23,6 +23,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index 620f3e8..b7ef609 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -23,6 +23,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index 8bdbdce..a82ad0c 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -21,7 +21,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index 715773f..5524685 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -16,6 +16,7 @@
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 8d700d6..56a4a2f 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_SC_SPS_1=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200"
@@ -13,7 +14,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
@@ -29,6 +29,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_MMC_MXS=y
CONFIG_PHYLIB=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index f113660..9c3d65a 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -24,6 +24,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig
index 57ca22c..f2031df 100644
--- a/configs/sfr_nb4-ser_ram_defconfig
+++ b/configs/sfr_nb4-ser_ram_defconfig
@@ -25,7 +25,9 @@
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
@@ -36,8 +38,16 @@
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6358_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index c16de7e..8ada682 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig
@@ -8,6 +8,7 @@
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
index c5cb713..01c9386 100644
--- a/configs/sksimx6_defconfig
+++ b/configs/sksimx6_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +22,6 @@
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_GPIO=y
@@ -30,6 +30,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 1b17399..4e1ef5f 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_FIT=y
@@ -17,7 +18,6 @@
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 080ff97..fbca175 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -5,6 +5,7 @@
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SMDK5250=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5250"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_DISTRO_DEFAULTS=y
@@ -12,7 +13,6 @@
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="SMDK5250 # "
CONFIG_CMD_GPIO=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index f1b72b6..6b39098 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SMDK5420=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5420"
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_DISTRO_DEFAULTS=y
@@ -10,7 +11,6 @@
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="SMDK5420 # "
CONFIG_CMD_GPIO=y
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index ea4c8eb..43da3fd 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -2,11 +2,11 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDKC210/V310"
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="SMDKV310 # "
# CONFIG_CMD_XIMG is not set
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 72dea46..ad22a1c 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -4,10 +4,10 @@
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_SNIPER=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
@@ -26,6 +26,7 @@
# CONFIG_CMD_NFS is not set
CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 2473f89..9d14eb8 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -5,6 +5,7 @@
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SNOW=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for snow"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_DEBUG_UART=y
@@ -12,7 +13,6 @@
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="snow # "
CONFIG_CMD_GPIO=y
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 1bf3731..e5984f2 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_DISTRO_DEFAULTS=y
@@ -10,8 +11,9 @@
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 5f80232..742473f 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_DISTRO_DEFAULTS=y
@@ -14,9 +15,10 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 5202f47..a687074 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_DISTRO_DEFAULTS=y
@@ -14,9 +15,10 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index d14fceb..6cf8220 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_FIT=y
@@ -13,9 +14,10 @@
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 4736def..93e43d2 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_DISTRO_DEFAULTS=y
@@ -14,10 +15,11 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 5a876dd..240216b 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_DISTRO_DEFAULTS=y
@@ -14,9 +15,10 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_nano.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 33381da..1e6eb86 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -4,6 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
# CONFIG_SPL_SPI_SUPPORT is not set
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_DISTRO_DEFAULTS=y
@@ -15,7 +16,7 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 53b5c34..37d2821 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_IS1=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_DISTRO_DEFAULTS=y
@@ -15,8 +16,9 @@
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index c97dcd0..12e2293 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_DISTRO_DEFAULTS=y
@@ -15,9 +16,10 @@
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index f421740..077d5c9 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_DISTRO_DEFAULTS=y
@@ -14,9 +15,10 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 3873c2b..a4289e3 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_DISTRO_DEFAULTS=y
@@ -14,9 +15,10 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index d7df688..05c903a 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_DISTRO_DEFAULTS=y
@@ -15,10 +16,11 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index a245c54..7ba289f 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_DISTRO_DEFAULTS=y
@@ -16,9 +17,10 @@
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 4f0946f..96c35de 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -9,6 +9,7 @@
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -34,7 +35,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
# CONFIG_USB_EHCI_HCD is not set
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index 7189634..5516291 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -17,6 +17,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig
index 8ca43a6..503e390 100644
--- a/configs/sopine_baseboard_defconfig
+++ b/configs/sopine_baseboard_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
@@ -9,14 +9,13 @@
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_SPI_SUNXI=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index a347f19..94620a8 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index 0fa4bb6..c28633a 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index f5ad5fc..5dd0ad7 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index b14008a..f1a1ec6 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index a6476e7..283d729 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index 1389a68..4737bb5 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 83ccd5a..4a79746 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index 3313633..aa039da 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index a4be617..071ac55 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index 1e1ccc0..432ed43 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index 33d2bef..001828d 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index ec6cbf0..3667bf8 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index a3acdb2..2dbd092 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index 4395647..fb1eade 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index a5fd760..b39339a 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index 6aff317..de99577 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index ac16b40..65693d7 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -26,3 +26,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index e781ba0..a279ec2 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index c77229a..7505ac0 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -23,3 +23,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index dbf4d32..fef9abe 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -24,3 +24,4 @@
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index c1a5dda..821d32e 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -5,6 +5,7 @@
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SPRING=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" for spring"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
CONFIG_DEBUG_UART=y
@@ -12,7 +13,6 @@
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="spring # "
CONFIG_CMD_GPIO=y
diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig
index b0f3af0..1b14a49 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -24,7 +24,6 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
# CONFIG_BLK is not set
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
index f457501..4de03ed 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -24,7 +24,6 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
# CONFIG_BLK is not set
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 918e972..8139ab1 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -29,12 +29,13 @@
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
@@ -53,5 +54,10 @@
# CONFIG_PINCTRL_FULL is not set
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=640
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
new file mode 100644
index 0000000..0f5950f
--- /dev/null
+++ b/configs/stm32mp15_basic_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_TARGET_STM32MP1=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ed1"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_DM_MMC=y
+CONFIG_STM32_SDMMC2=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMU1=y
+CONFIG_STM32_SERIAL=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index fd7e2dc..c933fbf 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -1,17 +1,37 @@
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE8080000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7790=y
CONFIG_TARGET_STOUT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
@@ -19,21 +39,42 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 4c460ef..29d12de 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -13,11 +13,14 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -27,7 +30,10 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index b7cd1d8..b185e0f 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -13,11 +13,14 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -27,7 +30,10 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index b28e405..0014cfc 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -13,11 +13,14 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -27,7 +30,10 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index f250ea3..b0b7269 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -13,11 +13,14 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -27,7 +30,10 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig
index b77a8b9..e5c5b42 100644
--- a/configs/sun8i_a23_evb_defconfig
+++ b/configs/sun8i_a23_evb_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
@@ -9,10 +9,10 @@
CONFIG_USB1_VBUS_PIN="PH7"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 9c9e54a..c971aa4 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
@@ -11,7 +11,6 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index 0213101..2fa97e2 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 67d1f54..005cb9c 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
CONFIG_DEBUG_UART=y
@@ -12,7 +13,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index ad08060..fc2c0d9 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -3,8 +3,8 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_TAO3530=y
-CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="TAO-3530 # "
@@ -28,6 +28,7 @@
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 344207c..81b95b2 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
CONFIG_BOOTDELAY=3
@@ -21,7 +22,7 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 567f80b..a30ff22 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -38,6 +38,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_DM_THERMAL=y
diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig
index 78881a3..2162544 100644
--- a/configs/tbs_a711_defconfig
+++ b/configs/tbs_a711_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL=y
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_TYPE=7
CONFIG_DRAM_CLK=648
@@ -13,7 +13,6 @@
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index 6503af9..fa96b93 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
@@ -18,6 +18,8 @@
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index f9ac967..dc756ba 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig
@@ -17,6 +17,8 @@
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index 52da3b1..aa14da3 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -16,6 +16,8 @@
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 918447a..5d28791 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -16,8 +17,9 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index eb7e285..ebeed59 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
@@ -21,9 +22,10 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -64,7 +66,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index 61c3a7a..fa77800 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=1
@@ -15,7 +16,6 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_YMODEM_SUPPORT=y
@@ -32,10 +32,11 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_DNS=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_PHYLIB=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 77038db..2061efb 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm"
CONFIG_DISTRO_DEFAULTS=y
@@ -19,7 +20,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_CMD_FLASH is not set
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index f8ff916..cc43508 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -12,6 +12,7 @@
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index 2267039..0f658ff 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -30,6 +30,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 8b02599..cfe7e92 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
@@ -11,10 +12,11 @@
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 572b2f5..b95cde1 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
@@ -11,10 +12,11 @@
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 3e8504d..39cdb22 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
@@ -11,10 +12,11 @@
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index ed86488..c07b64d 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -13,6 +13,7 @@
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index 3a6a9f0..8ef6ac1 100644
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index 35f58a2..d82081e 100644
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -31,6 +31,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index 4a4803d..ef980b3 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -29,6 +29,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index a37ab54..cadba31 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index dec79e0..6054226 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index ba257b8..579e65f 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -31,6 +31,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index 995a1ce..898d334 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -56,6 +56,7 @@
CONFIG_LED_STATUS_STATE5=2
CONFIG_LED_STATUS_CMD=y
CONFIG_PCA9551_LED=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 3ca154b..0ee5670 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -27,6 +27,7 @@
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_S3C24X0=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 019dca3..fde2b13 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -26,6 +26,7 @@
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_S3C24X0=y
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index 480b0aa..f8a87a8 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -2,9 +2,9 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_TRICORDER=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
# CONFIG_CMD_IMI is not set
@@ -36,6 +36,7 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_PANIC_HANG=y
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index aeedbb2..408814e 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -2,10 +2,10 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_TRICORDER=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_EEPROM=y
@@ -35,6 +35,7 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_PANIC_HANG=y
diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig
index fac1439..91af6ce 100644
--- a/configs/ts4600_defconfig
+++ b/configs/ts4600_defconfig
@@ -4,12 +4,12 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_TS4600=y
+CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -21,4 +21,5 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_MMC_MXS=y
+CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index 7260149..d91d9c1 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -14,6 +14,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 278d35a..28712f7 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 1c2eef0..a118395 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -8,14 +8,16 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 6414ac2..602e1dd 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -6,6 +6,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 3f07756..b5d4838 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -4,8 +4,8 @@
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_TWISTER=y
CONFIG_EMIF4=y
-CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_BOOTDELAY=10
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 0e88f2b..2d8cedf 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -9,11 +9,11 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -31,8 +31,10 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index dff2896..fb02fc5 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -9,12 +9,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
# CONFIG_CMD_FLASH is not set
@@ -24,6 +24,8 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 1ae9f96..d0d9122 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -5,12 +5,12 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_LOGLEVEL=6
-CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 6c6d284..076ee19 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -5,11 +5,11 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_LOGLEVEL=6
-CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index fc0ed31..ac3f3e2 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -42,4 +42,3 @@
CONFIG_DM_SERIAL=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
-CONFIG_ATMEL_SPI=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 1e92678..2e5bdad 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -12,6 +12,7 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 6d52b18..78aab9f 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -19,6 +19,7 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 23aeabb..6850074 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -25,4 +25,5 @@
CONFIG_SMC911X_BASE=0x1a000000
CONFIG_SMC911X_32_BIT=y
CONFIG_BAUDRATE=38400
+CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index c66a8a8..9ef660e 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -24,4 +24,5 @@
CONFIG_SMC911X_BASE=0x1a000000
CONFIG_SMC911X_32_BIT=y
CONFIG_BAUDRATE=38400
+CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 063febd..cd22552 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -24,4 +24,5 @@
CONFIG_SMC911X_BASE=0x4e000000
CONFIG_SMC911X_32_BIT=y
CONFIG_BAUDRATE=38400
+CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index 803489a..833fcdf 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -29,6 +29,7 @@
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPI_FLASH=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index b94f11f..7544624 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -29,6 +29,7 @@
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPI_FLASH=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 0d87441..e8dad44 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x20f00000
CONFIG_TARGET_VINCO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
@@ -23,6 +24,7 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 844809d..1d28b2f 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -29,6 +29,8 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_USB=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 5bbb3e2..a22d55f 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -19,7 +19,8 @@
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_BAUDRATE=9600
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 4c76041..7644d73 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -11,6 +11,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_CMD_GPIO=y
@@ -45,6 +46,9 @@
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 2c739fa..0333529 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -17,8 +18,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
@@ -30,8 +31,10 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 29c4512..3901a27 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -28,6 +28,7 @@
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DFU_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/warp7_secure_defconfig b/configs/warp7_secure_defconfig
index 7310855..915f218 100644
--- a/configs/warp7_secure_defconfig
+++ b/configs/warp7_secure_defconfig
@@ -27,6 +27,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_DFU_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index bddf4bc..db268f0 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -27,6 +27,7 @@
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_NET is not set
CONFIG_DFU_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig
index ed08f69..7018516 100644
--- a/configs/wb45n_defconfig
+++ b/configs/wb45n_defconfig
@@ -7,11 +7,11 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig
index 432257c..5b2daae 100644
--- a/configs/wb50n_defconfig
+++ b/configs/wb50n_defconfig
@@ -7,13 +7,14 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
-CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_NAND=y
@@ -22,6 +23,7 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index d6c7689..4c2d280 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -29,6 +29,7 @@
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_MXC_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 60873a1..7726472 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -7,10 +7,10 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
@@ -40,6 +40,7 @@
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_MXC_GPIO=y
+CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 2451b56..677672d 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL=y
CONFIG_CMD_HD44760=y
CONFIG_CMD_MAX6957=y
CONFIG_BOOTDELAY=3
@@ -13,7 +14,7 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
@@ -35,6 +36,7 @@
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LPC32XX_SSP=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 0aef5b6..77f2b03 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -7,11 +7,11 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="X600> "
@@ -44,10 +44,12 @@
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index acdb677..7f6a8d0 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_XFI3=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 "
@@ -15,7 +16,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
@@ -28,6 +28,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MMC_MXS=y
+CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
diff --git a/configs/xilinx_zynqmp_mini_emmc_defconfig b/configs/xilinx_zynqmp_mini_emmc_defconfig
index b15120e..a1ab39e 100644
--- a/configs/xilinx_zynqmp_mini_emmc_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc_defconfig
@@ -2,12 +2,14 @@
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=-1
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="ZynqMP> "
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index 55200bc..4c8c2fc 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -2,12 +2,14 @@
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=-1
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig
new file mode 100644
index 0000000..9757546
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1232 revA"
+# CONFIG_SPL_FAT_SUPPORT is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig
new file mode 100644
index 0000000..44640fb
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1254 revA"
+# CONFIG_SPL_FAT_SUPPORT is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig
new file mode 100644
index 0000000..ea14a60
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1275 revA"
+# CONFIG_SPL_FAT_SUPPORT is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7da0ca8..0faed06 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
@@ -14,16 +15,18 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
@@ -45,6 +48,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
@@ -67,6 +71,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 3e53166..be922b6 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -4,6 +4,7 @@
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_ZYNQMP_USB=y
@@ -15,15 +16,17 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
@@ -44,6 +47,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
@@ -63,6 +67,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
new file mode 100644
index 0000000..5de7541
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
@@ -0,0 +1,86 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm017_dc3"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm017 dc3"
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_NAND=y
+CONFIG_NAND_ARASAN=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 9bc0b77..8219de0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
CONFIG_DEBUG_UART=y
@@ -11,12 +12,14 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
@@ -34,6 +37,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
@@ -55,6 +59,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index ac565ec..99ca366 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
CONFIG_DEBUG_UART=y
@@ -12,12 +13,14 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
@@ -32,8 +35,10 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
@@ -43,7 +48,15 @@
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig
new file mode 100644
index 0000000..4024017
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevC"
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 1df5b0b..2147e18 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
@@ -14,10 +15,11 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
@@ -25,6 +27,7 @@
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
@@ -48,6 +51,7 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
@@ -73,6 +77,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index c8a8362..4f52c8c 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
@@ -14,10 +15,11 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
@@ -25,6 +27,7 @@
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
@@ -48,6 +51,7 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
@@ -73,6 +77,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 8f85b5f..17a5986 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
@@ -14,10 +15,11 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
@@ -25,6 +27,7 @@
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
@@ -48,6 +51,7 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
@@ -73,6 +77,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig
similarity index 64%
copy from configs/xilinx_zynqmp_ep_defconfig
copy to configs/xilinx_zynqmp_zcu104_revA_defconfig
index a0c8f28..ce11139 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig
@@ -1,11 +1,12 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revA"
CONFIG_ZYNQMP_USB=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA"
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
@@ -14,32 +15,24 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_THOR_DOWNLOAD=y
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
@@ -52,21 +45,22 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
+CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
-CONFIG_NAND=y
-CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -76,6 +70,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
@@ -83,7 +78,7 @@
CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
@@ -92,11 +87,9 @@
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig
similarity index 64%
copy from configs/xilinx_zynqmp_ep_defconfig
copy to configs/xilinx_zynqmp_zcu104_revC_defconfig
index a0c8f28..e87cc15 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig
@@ -1,11 +1,12 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revC"
CONFIG_ZYNQMP_USB=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revC"
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
@@ -14,32 +15,24 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_THOR_DOWNLOAD=y
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
@@ -52,21 +45,22 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
+CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
-CONFIG_NAND=y
-CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -76,6 +70,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
@@ -83,7 +78,7 @@
CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
@@ -92,11 +87,9 @@
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig
similarity index 73%
rename from configs/xilinx_zynqmp_ep_defconfig
rename to configs/xilinx_zynqmp_zcu106_revA_defconfig
index a0c8f28..e0d22dc 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig
@@ -1,11 +1,12 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu106"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106 revA"
CONFIG_ZYNQMP_USB=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA"
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
@@ -14,32 +15,28 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
@@ -52,21 +49,24 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
+CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
CONFIG_MISC=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
-CONFIG_NAND=y
-CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -76,6 +76,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
@@ -83,7 +84,7 @@
CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
@@ -92,11 +93,12 @@
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig
similarity index 64%
copy from configs/xilinx_zynqmp_ep_defconfig
copy to configs/xilinx_zynqmp_zcu111_revA_defconfig
index a0c8f28..5c88429 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig
@@ -1,11 +1,12 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu111"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000
+CONFIG_SPL=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU111"
CONFIG_ZYNQMP_USB=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA"
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
@@ -14,32 +15,23 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_THOR_DOWNLOAD=y
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
@@ -52,21 +44,23 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
+CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
CONFIG_MISC=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
-CONFIG_NAND=y
-CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -76,6 +70,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
@@ -83,7 +78,7 @@
CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
@@ -92,11 +87,9 @@
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index 5edf429..8353d1e 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -7,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
@@ -27,7 +28,8 @@
CONFIG_DS4510=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_PANIC_HANG=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index d13959e..b006dea 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
@@ -29,7 +30,8 @@
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_PANIC_HANG=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index d473ad0..42d959e 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
@@ -29,7 +30,8 @@
CONFIG_DS4510=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_PANIC_HANG=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index 6118d1d..6285387 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
@@ -27,7 +28,8 @@
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index 4a3ddcc..5c50470 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -23,6 +23,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index 3425d53..5e265d4 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -9,12 +9,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -33,6 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index 82e8fc3..c1fec76 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -11,15 +11,17 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -28,6 +30,8 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index cd2f521..415664f 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -11,15 +11,17 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -27,6 +29,8 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
index 9f78de3..935058a 100644
--- a/configs/zipitz2_defconfig
+++ b/configs/zipitz2_defconfig
@@ -19,6 +19,7 @@
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_CONS_INDEX=2
CONFIG_PXA_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 3a4de92..170cfbd 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
CONFIG_DEBUG_UART=y
@@ -10,8 +11,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 80bb26c..2a3d8b2 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_ZYNQ_DDRC_INIT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
@@ -11,8 +12,8 @@
CONFIG_BOOTDELAY=-1
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 94a1a40..967c037 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
CONFIG_DISTRO_DEFAULTS=y
@@ -9,9 +10,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index f9ee904..6a841f8 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,12 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index 7a51b85..5b13edb 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -1,8 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
-CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
@@ -10,9 +11,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 8e8b800..2c9210f 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC702"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
@@ -12,9 +13,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 8f83d17..dd1b1af 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC706"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
@@ -12,9 +13,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
@@ -73,3 +74,5 @@
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 8db30d0..fe23dc1 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
@@ -11,9 +12,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index b6ddf98..9613b8a 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011"
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
@@ -12,7 +13,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index bd0ec7b..884186a 100644
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011 x16"
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
@@ -10,9 +11,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
@@ -29,7 +29,6 @@
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 8dbba65..0b3db39 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012"
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
@@ -11,7 +12,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index f9eabb1..9930d52 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
@@ -11,9 +12,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 7ed0128..769c531 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,17 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
+CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
@@ -47,6 +49,9 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 92f3e1e..fbe22c5 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_CONFIG_NAME="zynq_zybo"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_DEBUG_UART=y
@@ -11,9 +12,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
diff --git a/disk/part.c b/disk/part.c
index e9e18a0..44ef14d 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -26,23 +26,35 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_HAVE_BLOCK_DEVICE
-static struct part_driver *part_driver_lookup_type(int part_type)
+static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
{
struct part_driver *drv =
ll_entry_start(struct part_driver, part_driver);
const int n_ents = ll_entry_count(struct part_driver, part_driver);
struct part_driver *entry;
- for (entry = drv; entry != drv + n_ents; entry++) {
- if (part_type == entry->part_type)
- return entry;
+ if (dev_desc->part_type == PART_TYPE_UNKNOWN) {
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ int ret;
+
+ ret = entry->test(dev_desc);
+ if (!ret) {
+ dev_desc->part_type = entry->part_type;
+ return entry;
+ }
+ }
+ } else {
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (dev_desc->part_type == entry->part_type)
+ return entry;
+ }
}
/* Not found */
return NULL;
}
+#ifdef CONFIG_HAVE_BLOCK_DEVICE
static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
struct blk_desc *dev_desc;
@@ -285,7 +297,7 @@
{
struct part_driver *drv;
- drv = part_driver_lookup_type(dev_desc->part_type);
+ drv = part_driver_lookup_type(dev_desc);
if (!drv) {
printf("## Unknown partition table type %x\n",
dev_desc->part_type);
@@ -314,7 +326,7 @@
info->type_guid[0] = 0;
#endif
- drv = part_driver_lookup_type(dev_desc->part_type);
+ drv = part_driver_lookup_type(dev_desc);
if (!drv) {
debug("## Unknown partition table type %x\n",
dev_desc->part_type);
@@ -632,28 +644,25 @@
int part_get_info_by_name_type(struct blk_desc *dev_desc, const char *name,
disk_partition_t *info, int part_type)
{
- struct part_driver *first_drv =
- ll_entry_start(struct part_driver, part_driver);
- const int n_drvs = ll_entry_count(struct part_driver, part_driver);
struct part_driver *part_drv;
+ int ret;
+ int i;
- for (part_drv = first_drv; part_drv != first_drv + n_drvs; part_drv++) {
- int ret;
- int i;
- for (i = 1; i < part_drv->max_entries; i++) {
- if (part_type >= 0 && part_type != part_drv->part_type)
- break;
- ret = part_drv->get_info(dev_desc, i, info);
- if (ret != 0) {
- /* no more entries in table */
- break;
- }
- if (strcmp(name, (const char *)info->name) == 0) {
- /* matched */
- return i;
- }
+ part_drv = part_driver_lookup_type(dev_desc);
+ if (!part_drv)
+ return -1;
+ for (i = 1; i < part_drv->max_entries; i++) {
+ ret = part_drv->get_info(dev_desc, i, info);
+ if (ret != 0) {
+ /* no more entries in table */
+ break;
+ }
+ if (strcmp(name, (const char *)info->name) == 0) {
+ /* matched */
+ return i;
}
}
+
return -1;
}
diff --git a/doc/README.POST b/doc/README.POST
index a9335f4..43f424f 100644
--- a/doc/README.POST
+++ b/doc/README.POST
@@ -159,17 +159,6 @@
Also, the following board-specific routines will be called from the
U-Boot common code:
- o) int board_power_mode(void)
-
- This routine will return the mode the system is running in
- (POST_POWERON, POST_NORMAL or POST_SHUTDOWN).
-
- o) void board_poweroff(void)
-
- This routine will turn off the power supply of the board. It
- will be called on power-fail booting after running all POST
- tests.
-
o) int post_hotkeys_pressed(gd_t *gd)
This routine will scan the keyboard to detect if a magic key
diff --git a/doc/README.ae250 b/doc/README.ae250
index a80bb39..77c168a 100644
--- a/doc/README.ae250
+++ b/doc/README.ae250
@@ -49,8 +49,8 @@
5. Burn this u-boot image to spi rom by spi driver
6. Re-boot u-boot from spi flash with power off and power on.
-Messages
-====================
+Messages of U-Boot boot on AE250 board
+======================================
U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
DRAM: 1 GiB
@@ -131,7 +131,145 @@
eth0: mac@e0100000
RISC-V #
-TODO
-====================
-Boot bbl and riscv-linux
+Boot bbl and riscv-linux via U-Boot on QEMU
+===========================================
+1. Build riscv-linux
+2. Build bbl and riscv-linux with --with-payload
+3. Prepare ae250.dtb
+4. Creating OS-kernel images
+ ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
+ Image Name:
+ Created: Tue Mar 13 10:06:42 2018
+ Image Type: RISC-V Linux Kernel Image (uncompressed)
+ Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB
+ Load Address: 00000000
+ Entry Point: 00000000
+
+4. Copy bootmImage-bbl.bin and ae250.dtb to qemu sd card image
+5. Message of booting riscv-linux from bbl via u-boot on qemu
+
+U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
+
+DRAM: 1 GiB
+main-loop: WARNING: I/O thread spun for 1000 iterations
+MMC: mmc@f0e00000: 0
+Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
+
+Failed (-22)
+In: serial@f0300000
+Out: serial@f0300000
+Err: serial@f0300000
+Net:
+Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
+eth0: mac@e0100000
+RISC-V # mmc rescan
+RISC-V # mmc part
+
+Partition Map for MMC device 0 -- Partition Type: DOS
+
+Part Start Sector Num Sectors UUID Type
+RISC-V # fatls mmc 0:0
+ 17901268 bootmImage-bbl.bin
+ 1954 ae2xx.dtb
+
+2 file(s), 0 dir(s)
+
+RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
+17901268 bytes read in 4642 ms (3.7 MiB/s)
+RISC-V # fatload mmc 0:0 0x2000000 ae250.dtb
+1954 bytes read in 1 ms (1.9 MiB/s)
+RISC-V # setenv bootm_size 0x2000000
+RISC-V # setenv fdt_high 0x1f00000
+RISC-V # bootm 0x00600000 - 0x2000000
+## Booting kernel from Legacy Image at 00600000 ...
+ Image Name:
+ Image Type: RISC-V Linux Kernel Image (uncompressed)
+ Data Size: 17901204 Bytes = 17.1 MiB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+## Flattened Device Tree blob at 02000000
+ Booting using the fdt blob at 0x2000000
+ Loading Kernel Image ... OK
+ Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
+[ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
+[ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
+[ 0.000000] bootconsole [early0] enabled
+[ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
+[ 0.000000] Zone ranges:
+[ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff]
+[ 0.000000] Normal empty
+[ 0.000000] Movable zone start for each node
+[ 0.000000] Early memory node ranges
+[ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff]
+[ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
+[ 0.000000] elf_hwcap is 0x112d
+[ 0.000000] random: fast init done
+[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615
+[ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
+[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
+[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
+[ 0.000000] Sorting __ex_table...
+[ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
+[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+[ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
+[ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
+[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
+[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
+[ 0.000000] pid_max: default: 32768 minimum: 301
+[ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.056000] devtmpfs: initialized
+[ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+[ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
+[ 0.068000] NET: Registered protocol family 16
+[ 0.080000] vgaarb: loaded
+[ 0.084000] clocksource: Switched to clocksource riscv_clocksource
+[ 0.088000] NET: Registered protocol family 2
+[ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.096000] TCP: Hash tables configured (established 16384 bind 16384)
+[ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
+[ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
+[ 0.104000] NET: Registered protocol family 1
+[ 0.616000] Unpacking initramfs...
+[ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
+[ 1.244000] io scheduler noop registered
+[ 1.244000] io scheduler cfq registered (default)
+[ 1.244000] io scheduler mq-deadline registered
+[ 1.248000] io scheduler kyber registered
+[ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 1.368000] console [ttyS0] disabled
+[ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
+[ 1.392000] console [ttyS0] enabled
+[ 1.392000] ftmac100: Loading version 0.2 ...
+[ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
+[ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
+[ 1.404000] IR NEC protocol handler initialized
+[ 1.404000] IR RC5(x/sz) protocol handler initialized
+[ 1.404000] IR RC6 protocol handler initialized
+[ 1.404000] IR JVC protocol handler initialized
+[ 1.408000] IR Sony protocol handler initialized
+[ 1.408000] IR SANYO protocol handler initialized
+[ 1.408000] IR Sharp protocol handler initialized
+[ 1.408000] IR MCE Keyboard/mouse protocol handler initialized
+[ 1.412000] IR XMP protocol handler initialized
+[ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
+[ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
+[ 1.464000] bootconsole [early0] disabled
+[ 1.508000] Freeing unused kernel memory: 12076K
+[ 1.512000] This architecture does not have kernel memory protection.
+[ 1.520000] mmc0: new SD card at address 4567
+[ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
+[ 1.844000] mmcblk0:
+Wed Dec 1 10:00:00 CST 2010
+/ #
+
+
+
+TODO
+==================================================
+Boot bbl and riscv-linux via U-Boot on AE250 board
diff --git a/doc/README.efi b/doc/README.efi
deleted file mode 100644
index 956f5bf..0000000
--- a/doc/README.efi
+++ /dev/null
@@ -1,86 +0,0 @@
-#
-# Copyright (C) 2015 Google, Inc
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-EFI on U-Boot
-=============
-This document provides information about the implementation of the UEFI API [1]
-in U-Boot.
-
-
-=========== Table of Contents ===========
-
-Motivation
-How do I get it?
-Status
-Future work
-
-
-Motivation
-----------
-
-With this API support in place, you can run any UEFI payload (such as the Linux
-kernel, grub2 or gummiboot) on U-Boot. This dramatically simplifies boot loader
-configuration, as U-Boot based systems now look and feel (almost) the same way
-as TianoCore based systems.
-
-How do I get it?
-----------------
-
-EFI support for 32bit ARM and AArch64 is already included in U-Boot. All you
-need to do is enable
-
- CONFIG_CMD_BOOTEFI=y
- CONFIG_EFI_LOADER=y
-
-in your .config file and you will automatically get a bootefi command to run
-an efi application as well as snippet in the default distro boot script that
-scans for removable media efi binaries as fallback.
-
-Status
-------
-
-I am successfully able to run grub2 and Linux EFI binaries with this code on
-ARMv7 as well as AArch64 systems.
-
-When enabled, the resulting U-Boot binary only grows by ~10KB, so it's very
-light weight.
-
-All storage devices are directly accessible from the uEFI payload
-
-Removable media booting (search for /efi/boot/boota{a64,arm}.efi) is supported.
-
-Simple use cases like "Plug this SD card into my ARM device and it just
-boots into grub which boots into Linux", work very well.
-
-
-Running HelloWord.efi
----------------------
-
-You can run a simple 'hello world' EFI program in U-Boot.
-Enable the option CONFIG_CMD_BOOTEFI_HELLO.
-
-Then you can boot into U-Boot and type:
-
- > bootefi hello
-
-The 'hello world EFI' program will then run, print a message and exit.
-
-
-Future work
------------
-
-Of course, there are still a few things one could do on top:
-
- - Improve disk media detection (don't scan, use what information we
-have)
- - Add EFI variable support using NVRAM
- - Add GFX support
- - Make EFI Shell work
- - Network device support
- - Support for payload exit
- - Payload Watchdog support
-
-[1] http://uefi.org/
diff --git a/doc/README.log b/doc/README.log
index dc9e2de..2ee1b75 100644
--- a/doc/README.log
+++ b/doc/README.log
@@ -162,7 +162,8 @@
---------
Code size impact depends largely on what is enabled. The following numbers are
-for snow, which is a Thumb-2 board:
+generated by 'buildman -S' for snow, which is a Thumb-2 board (all units in
+bytes):
This series: adds bss +20.0 data +4.0 rodata +4.0 text +44.0
CONFIG_LOG: bss -52.0 data +92.0 rodata -635.0 text +1048.0
diff --git a/doc/README.uefi b/doc/README.uefi
new file mode 100644
index 0000000..7403be3
--- /dev/null
+++ b/doc/README.uefi
@@ -0,0 +1,332 @@
+<!--
+ Copyright (c) 2018 Heinrich Schuchardt
+
+ SPDX-License-Identifier: GPL-2.0+
+-->
+
+# UEFI on U-Boot
+
+The Unified Extensible Firmware Interface Specification (UEFI) [1] has become
+the default for booting on AArch64 and x86 systems. It provides a stable API for
+the interaction of drivers and applications with the firmware. The API comprises
+access to block storage, network, and console to name a few. The Linux kernel
+and boot loaders like GRUB or the FreeBSD loader can be executed.
+
+## Building for UEFI
+
+The UEFI standard supports only little endian systems. The UEFI support can be
+activated for ARM and x86 by specifying
+
+ CONFIG_CMD_BOOTEFI=y
+ CONFIG_EFI_LOADER=y
+
+in the .config file.
+
+Support for attaching virtual block devices, e.g. iSCSI drives connected by the
+loaded UEFI application [3], requires
+
+ CONFIG_BLK=y
+ CONFIG_PARTITIONS=y
+
+### Executing a UEFI binary
+
+The bootefi command is used to start UEFI applications or to install UEFI
+drivers. It takes two parameters
+
+ bootefi <image address> [fdt address]
+
+* image address - the memory address of the UEFI binary
+* fdt address - the memory address of the flattened device tree
+
+Below you find the output of an example session starting GRUB.
+
+ => load mmc 0:2 ${fdt_addr_r} boot/dtb
+ 29830 bytes read in 14 ms (2 MiB/s)
+ => load mmc 0:1 ${kernel_addr_r} efi/debian/grubaa64.efi
+ reading efi/debian/grubaa64.efi
+ 120832 bytes read in 7 ms (16.5 MiB/s)
+ => bootefi ${kernel_addr_r} ${fdt_addr_r}
+
+The environment variable 'bootargs' is passed as load options in the UEFI system
+table. The Linux kernel EFI stub uses the load options as command line
+arguments.
+
+### Executing the boot manager
+
+The UEFI specfication foresees to define boot entries and boot sequence via UEFI
+variables. Booting according to these variables is possible via
+
+ bootefi bootmgr [fdt address]
+
+As of U-Boot v2018.03 UEFI variables are not persisted and cannot be set at
+runtime.
+
+### Executing the built in hello world application
+
+A hello world UEFI application can be built with
+
+ CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
+
+It can be embedded into the U-Boot binary with
+
+ CONFIG_CMD_BOOTEFI_HELLO=y
+
+The bootefi command is used to start the embedded hello world application.
+
+ bootefi hello [fdt address]
+
+Below you find the output of an example session.
+
+ => bootefi hello ${fdtcontroladdr}
+ ## Starting EFI application at 01000000 ...
+ WARNING: using memory device/image path, this may confuse some payloads!
+ Hello, world!
+ Running on UEFI 2.7
+ Have SMBIOS table
+ Have device tree
+ Load options: root=/dev/sdb3 init=/sbin/init rootwait ro
+ ## Application terminated, r = 0
+
+The environment variable fdtcontroladdr points to U-Boot's internal device tree
+(if available).
+
+### Executing the built-in selftest
+
+An UEFI selftest suite can be embedded in U-Boot by building with
+
+ CONFIG_CMD_BOOTEFI_SELFTEST=y
+
+For testing the UEFI implementation the bootefi command can be used to start the
+selftest.
+
+ bootefi selftest [fdt address]
+
+The environment variable 'efi_selftest' can be used to select a single test. If
+it is not provided all tests are executed except those marked as 'on request'.
+If the environment variable is set to 'list' a list of all tests is shown.
+
+Below you can find the output of an example session.
+
+ => setenv efi_selftest simple network protocol
+ => bootefi selftest
+ Testing EFI API implementation
+ Selected test: 'simple network protocol'
+ Setting up 'simple network protocol'
+ Setting up 'simple network protocol' succeeded
+ Executing 'simple network protocol'
+ DHCP Discover
+ DHCP reply received from 192.168.76.2 (52:55:c0:a8:4c:02)
+ as broadcast message.
+ Executing 'simple network protocol' succeeded
+ Tearing down 'simple network protocol'
+ Tearing down 'simple network protocol' succeeded
+ Boot services terminated
+ Summary: 0 failures
+ Preparing for reset. Press any key.
+
+## The UEFI life cycle
+
+After the U-Boot platform has been initialized the UEFI API provides two kinds
+of services
+
+* boot services and
+* runtime services.
+
+The API can be extended by loading UEFI drivers which come in two variants
+
+* boot drivers and
+* runtime drivers.
+
+UEFI drivers are installed with U-Boot's bootefi command. With the same command
+UEFI applications can be executed.
+
+Loaded images of UEFI drivers stay in memory after returning to U-Boot while
+loaded images of applications are removed from memory.
+
+An UEFI application (e.g. an operating system) that wants to take full control
+of the system calls ExitBootServices. After a UEFI application calls
+ExitBootServices
+
+* boot services are not available anymore
+* timer events are stopped
+* the memory used by U-Boot except for runtime services is released
+* the memory used by boot time drivers is released
+
+So this is a point of no return. Afterwards the UEFI application can only return
+to U-Boot by rebooting.
+
+## The UEFI object model
+
+UEFI offers a flexible and expandable object model. The objects in the UEFI API
+are devices, drivers, and loaded images. These objects are referenced by
+handles.
+
+The interfaces implemented by the objects are referred to as protocols. These
+are identified by GUIDs. They can be installed and uninstalled by calling the
+appropriate boot services.
+
+Handles are created by the InstallProtocolInterface or the
+InstallMultipleProtocolinterfaces service if NULL is passed as handle.
+
+Handles are deleted when the last protocol has been removed with the
+UninstallProtocolInterface or the UninstallMultipleProtocolInterfaces service.
+
+Devices offer the EFI_DEVICE_PATH_PROTOCOL. A device path is the concatenation
+of device nodes. By their device paths all devices of a system are arranged in a
+tree.
+
+Drivers offer the EFI_DRIVER_BINDING_PROTOCOL. This protocol is used to connect
+a driver to devices (which are referenced as controllers in this context).
+
+Loaded images offer the EFI_LOADED_IMAGE_PROTOCOL. This protocol provides meta
+information about the image and a pointer to the unload callback function.
+
+## The UEFI events
+
+In the UEFI terminology an event is a data object referencing a notification
+function which is queued for calling when the event is signaled. The following
+types of events exist:
+
+* periodic and single shot timer events
+* exit boot services events, triggered by calling the ExitBootServices() service
+* virtual address change events
+* memory map change events
+* read to boot events
+* reset system events
+* system table events
+* events that are only triggered programmatically
+
+Events can be created with the CreateEvent service and deleted with CloseEvent
+service.
+
+Events can be assigned to an event group. If any of the events in a group is
+signaled, all other events in the group are also set to the signaled state.
+
+## The UEFI driver model
+
+A driver is specific for a single protocol installed on a device. To install a
+driver on a device the ConnectController service is called. In this context
+controller refers to the device for which the driver is installed.
+
+The relevant drivers are identified using the EFI_DRIVER_BINDING_PROTOCOL. This
+protocol has has three functions:
+
+* supported - determines if the driver is compatible with the device
+* start - installs the driver by opening the relevant protocol with
+ attribute EFI_OPEN_PROTOCOL_BY_DRIVER
+* stop - uninstalls the driver
+
+The driver may create child controllers (child devices). E.g. a driver for block
+IO devices will create the device handles for the partitions. The child
+controllers will open the supported protocol with the attribute
+EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+A driver can be detached from a device using the DisconnectController service.
+
+## U-Boot devices mapped as UEFI devices
+
+Some of the U-Boot devices are mapped as UEFI devices
+
+* block IO devices
+* console
+* graphical output
+* network adapter
+
+As of U-Boot 2018.03 the logic for doing this is hard coded.
+
+The development target is to integrate the setup of these UEFI devices with the
+U-Boot driver model. So when a U-Boot device is discovered a handle should be
+created and the device path protocol and the relevant IO protocol should be
+installed. The UEFI driver then would be attached by calling ConnectController.
+When a U-Boot device is removed DisconnectController should be called.
+
+## UEFI devices mapped as U-Boot devices
+
+UEFI drivers binaries and applications may create new (virtual) devices, install
+a protocol and call the ConnectController service. Now the matching UEFI driver
+is determined by iterating over the implementations of the
+EFI_DRIVER_BINDING_PROTOCOL.
+
+It is the task of the UEFI driver to create a corresponding U-Boot device and to
+proxy calls for this U-Boot device to the controller.
+
+In U-Boot 2018.03 this has only been implemented for block IO devices.
+
+### UEFI uclass
+
+An UEFI uclass driver (lib/efi_driver/efi_uclass.c) has been created that
+takes care of initializing the UEFI drivers and providing the
+EFI_DRIVER_BINDING_PROTOCOL implementation for the UEFI drivers.
+
+A linker created list is used to keep track of the UEFI drivers. To create an
+entry in the list the UEFI driver uses the U_BOOT_DRIVER macro specifying
+UCLASS_EFI as the ID of its uclass, e.g.
+
+ /* Identify as UEFI driver */
+ U_BOOT_DRIVER(efi_block) = {
+ .name = "EFI block driver",
+ .id = UCLASS_EFI,
+ .ops = &driver_ops,
+ };
+
+The available operations are defined via the structure struct efi_driver_ops.
+
+ struct efi_driver_ops {
+ const efi_guid_t *protocol;
+ const efi_guid_t *child_protocol;
+ int (*bind)(efi_handle_t handle, void *interface);
+ };
+
+When the supported() function of the EFI_DRIVER_BINDING_PROTOCOL is called the
+uclass checks if the protocol GUID matches the protocol GUID of the UEFI driver.
+In the start() function the bind() function of the UEFI driver is called after
+checking the GUID.
+The stop() function of the EFI_DRIVER_BINDING_PROTOCOL disconnects the child
+controllers created by the UEFI driver and the UEFI driver. (In U-Boot v2013.03
+this is not yet completely implemented.)
+
+### UEFI block IO driver
+
+The UEFI block IO driver supports devices exposing the EFI_BLOCK_IO_PROTOCOL.
+
+When connected it creates a new U-Boot block IO device with interface type
+IF_TYPE_EFI, adds child controllers mapping the partitions, and installs the
+EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the
+software iPXE to boot from iSCSI network drives [3].
+
+This driver is only available if U-Boot is configured with
+
+ CONFIG_BLK=y
+ CONFIG_PARTITIONS=y
+
+## TODOs as of U-Boot 2018.03
+
+* unimplemented or incompletely implemented boot services
+ * Exit - call unload function, unload applications only
+ * ReinstallProtocolInterface
+ * UnloadImage
+
+* unimplemented events
+ * EVT_RUNTIME
+ * EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
+ * event groups
+
+* data model
+ * manage events in a linked list
+ * manage configuration tables in a linked list
+
+* UEFI drivers
+ * support DisconnectController for UEFI block devices.
+
+* support for CONFIG_EFI_LOADER in the sandbox (CONFIG_SANDBOX=y)
+
+* UEFI variables
+ * persistence
+ * runtime support
+
+## Links
+
+* [1](http://uefi.org/specifications)
+ http://uefi.org/specifications - UEFI specifications
+* [2](./driver-model/README.txt) doc/driver-model/README.txt - Driver model
+* [3](./README.iscsi) doc/README.iscsi - iSCSI booting with U-Boot and iPXE
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
new file mode 100644
index 0000000..c29d90f
--- /dev/null
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -0,0 +1,226 @@
+STMicroelectronics STM32MP1 clock tree initialization
+=====================================================
+
+The STM32MP clock tree initialization is based on device tree information
+for RCC IP and on fixed clocks.
+
+-------------------------------
+RCC CLOCK = st,stm32mp1-rcc-clk
+-------------------------------
+
+The RCC IP is both a reset and a clock controller but this documentation only
+describes the fields added for clock tree initialization which are not present
+in Linux binding.
+
+Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
+with Linux.
+
+Required properties:
+
+- compatible: Should be "st,stm32mp1-rcc-clk"
+
+- st,clksrc : The clock source in this order
+
+ for STM32MP15x: 9 clock sources are requested
+ MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
+
+ with value equals to RCC clock specifier as defined in
+ dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
+
+- st,clkdiv : The div parameters in this order
+ for STM32MP15x: 11 dividers value are requested
+ MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
+
+ with DIV coding defined in RCC associated register RCC_xxxDIVR
+
+ most the case, it is:
+ 0x0: not divided
+ 0x1: division by 2
+ 0x2: division by 4
+ 0x3: division by 8
+ ...
+
+ but for RTC MCO1 MCO2, the coding is different:
+ 0x0: not divided
+ 0x1: division by 2
+ 0x2: division by 3
+ 0x3: division by 4
+ ...
+
+Optional Properties:
+- st,pll
+ PLL children node for PLL1 to PLL4 : (see ref manual for details)
+ with associated index 0 to 3 (st,pll@0 to st,pll@4)
+ PLLx is off when the associated node is absent
+
+ - Sub-nodes:
+
+ - cfg: The parameters for PLL configuration in this order:
+ DIVM DIVN DIVP DIVQ DIVR Output
+
+ with DIV value as defined in RCC spec:
+ 0x0: bypass (division by 1)
+ 0x1: division by 2
+ 0x2: division by 3
+ 0x3: division by 4
+ ...
+
+ and Output = bitfield for each output value = 1:ON/0:OFF
+ BIT(0) => output P : DIVPEN
+ BIT(1) => output Q : DIVQEN
+ BIT(2) => output R : DIVREN
+ NB : macro PQR(p,q,r) can be used to build this value
+ with p,p,r = 0 or 1
+
+ - frac : Fractional part of the multiplication factor
+ (optional, PLL is in integer mode when absent)
+
+ - csg : Clock Spreading Generator (optional)
+ with parameters in this order:
+ MOD_PER INC_STEP SSCG_MODE
+
+ * MOD_PER: Modulation Period Adjustment
+ * INC_STEP: Modulation Depth Adjustment
+ * SSCG_MODE: Spread spectrum clock generator mode
+ you can use associated defines from stm32mp1-clksrc.h
+ * SSCG_MODE_CENTER_SPREAD = 0
+ * SSCG_MODE_DOWN_SPREAD = 1
+
+
+- st,pkcs : used to configure the peripherals kernel clock selection
+ containing a list of peripheral kernel clock source identifier as defined
+ in the file dt-bindings/clock/stm32mp1-clksrc.h
+
+ Example:
+
+ rcc: rcc@50000000 {
+ compatible = "syscon", "simple-mfd";
+
+ reg = <0x50000000 0x1000>;
+
+ rcc_clk: rcc-clk@50000000 {
+ #clock-cells = <1>;
+ compatible = "st,stm32mp1-rcc-clk";
+
+ st,clksrc = < CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_HSI
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_HSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 5 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pll@0 {
+ cfg = < 1 53 0 0 0 1 >;
+ frac = < 0x810 >;
+ };
+ st,pll@1 {
+ cfg = < 1 43 1 0 0 PQR(0,1,1)>;
+ csg = <10 20 1>;
+ };
+ st,pll@2 {
+ cfg = < 2 85 3 13 3 0>;
+ csg = <10 20 SSCG_MODE_CENTER_SPREAD>;
+ };
+ st,pll@3 {
+ cfg = < 2 78 4 7 9 3>;
+ };
+ st,pkcs = <
+ CLK_STGEN_HSE
+ CLK_CKPER_HSI
+ CLK_USBPHY_PLL2P
+ CLK_DSI_PLL2Q
+ >;
+ };
+ };
+
+--------------------------
+other clocks = fixed-clock
+--------------------------
+The clock tree is also based on 5 fixed-clock in clocks node
+used to define the state of associated ST32MP1 oscillators:
+- clk-lsi
+- clk-lse
+- clk-hsi
+- clk-hse
+- clk-csi
+
+At boot the clock tree initialization will
+- enable the oscillator present in device tree
+- disable HSI oscillator if the node is absent (always activated by bootrom)
+
+Optional properties :
+
+a) for external oscillator: "clk-lse", "clk-hse"
+
+ 3 optional fields are managed
+ - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
+ - "st,css" Activate the clock security system (HSECSSON, LSECSSON)
+ - "st,drive" (only for LSE) value of the drive for the oscillator
+ (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
+
+ Example board file:
+
+ / {
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ st,bypass;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ st,css;
+ st,drive = <LSEDRV_LOWEST>;
+ };
+ };
+
+b) for internal oscillator: "clk-hsi"
+
+ internally HSI clock is fixed to 64MHz for STM32MP157 soc
+ in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
+ So this clock frequency is used to compute the expected HSI_DIV
+ for the clock tree initialisation
+
+ ex: for HSIDIV = /1
+
+ / {
+ clocks {
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+ };
+
+ ex: for HSIDIV = /2
+
+ / {
+ clocks {
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000000>;
+ };
+ };
diff --git a/doc/device-tree-bindings/i2c/i2c.txt b/doc/device-tree-bindings/i2c/i2c.txt
index ea918dd..de818d4 100644
--- a/doc/device-tree-bindings/i2c/i2c.txt
+++ b/doc/device-tree-bindings/i2c/i2c.txt
@@ -12,6 +12,11 @@
Optional properties:
- u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the
default value of 1 is used.
+- gpios = <sda ...>, <scl ...>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c_xfer>;
+ pinctrl-1 = <&i2c_gpio>;
+ Pin description for I2C bus software deblocking.
Example
@@ -26,3 +31,11 @@
ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
};
};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-1 = <&i2c1_gpio>;
+ gpios = <&gpio1 26 GPIO_ACTIVE_LOW>, /* SDA */
+ <&gpio1 27 GPIO_ACTIVE_LOW>; /* SCL */
+};
diff --git a/doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
new file mode 100644
index 0000000..86ec113
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
@@ -0,0 +1,186 @@
+* Marvell Armada 37xx SoC pin and GPIO controller
+
+Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
+South Bridge and the other for the North Bridge.
+
+GPIO and pin controller:
+------------------------
+
+Main node:
+
+Refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning
+of the phrase "pin configuration node".
+
+Required properties for pinctrl driver:
+
+- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
+ for the South Bridge
+ "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
+ for the North Bridge
+- reg: The first set of registers is for pinctrl/GPIO and the second
+ set is for the interrupt controller
+- interrupts: list of interrupts used by the GPIO
+
+Available groups and functions for the North Bridge:
+
+group: jtag
+ - pins 20-24
+ - functions jtag, gpio
+
+group sdio0
+ - pins 8-10
+ - functions sdio, gpio
+
+group emmc_nb
+ - pins 27-35
+ - functions emmc, gpio
+
+group pwm0
+ - pin 11 (GPIO1-11)
+ - functions pwm, gpio
+
+group pwm1
+ - pin 12
+ - functions pwm, gpio
+
+group pwm2
+ - pin 13
+ - functions pwm, gpio
+
+group pwm3
+ - pin 14
+ - functions pwm, gpio
+
+group pmic1
+ - pin 7
+ - functions pmic, gpio
+
+group pmic0
+ - pin 6
+ - functions pmic, gpio
+
+group i2c2
+ - pins 2-3
+ - functions i2c, gpio
+
+group i2c1
+ - pins 0-1
+ - functions i2c, gpio
+
+group spi_cs1
+ - pin 17
+ - functions spi, gpio
+
+group spi_cs2
+ - pin 18
+ - functions spi, gpio
+
+group spi_cs3
+ - pin 19
+ - functions spi, gpio
+
+group onewire
+ - pin 4
+ - functions onewire, gpio
+
+group uart1
+ - pins 25-26
+ - functions uart, gpio
+
+group spi_quad
+ - pins 15-16
+ - functions spi, gpio
+
+group uart_2
+ - pins 9-10
+ - functions uart, gpio
+
+Available groups and functions for the South Bridge:
+
+group usb32_drvvbus0
+ - pin 36
+ - functions drvbus, gpio
+
+group usb2_drvvbus1
+ - pin 37
+ - functions drvbus, gpio
+
+group sdio_sb
+ - pins 60-65
+ - functions sdio, gpio
+
+group rgmii
+ - pins 42-53
+ - functions mii, gpio
+
+group pcie1
+ - pins 39-41
+ - functions pcie, gpio
+
+group smi
+ - pins 54-55
+ - functions smi, gpio
+
+group ptp
+ - pins 56-58
+ - functions ptp, gpio
+
+group ptp_clk
+ - pin 57
+ - functions ptp, mii
+
+group ptp_trig
+ - pin 58
+ - functions ptp, mii
+
+group mii_col
+ - pin 59
+ - functions mii, mii_err
+
+GPIO subnode:
+
+Please refer to gpio.txt in "gpio" directory for details of gpio-ranges property
+and the common GPIO bindings used by client devices.
+
+Required properties for the GPIO driver under the gpio subnode:
+- interrupts: List of interrupt specifiers for the controllers interrupt.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be 2. The first cell is the GPIO number and the
+ second cell specifies GPIO flags, as defined in
+ <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
+ GPIO_ACTIVE_LOW flags are supported.
+- gpio-ranges: Range of pins managed by the GPIO controller.
+
+Example:
+pinctrl_sb: pinctrl-sb@18800 {
+ compatible = "marvell,armada3710-sb-pinctrl",
+ "syscon", "simple-mfd";
+ reg = <0x18800 0x100>, <0x18C00 0x20>;
+ gpiosb: gpiosb {
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sb 0 0 30>;
+ gpio-controller;
+ interrupts =
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ rgmii_pins: mii-pins {
+ groups = "rgmii";
+ function = "mii";
+ };
+
+ sdio_pins: sdio-pins {
+ groups = "sdio_sb";
+ function = "sdio";
+ };
+
+ pcie_pins: pcie-pins {
+ groups = "pcie1";
+ function = "pcie";
+ };
+};
\ No newline at end of file
diff --git a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
new file mode 100644
index 0000000..3028636
--- /dev/null
+++ b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
@@ -0,0 +1,299 @@
+ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
+
+--------------------
+Required properties:
+--------------------
+- compatible : Should be "st,stm32mp1-ddr"
+- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
+- clocks : controller clocks handle
+- clock-names : associated controller clock names
+ the "ddrphyc" clock is used to check the DDR frequency
+ at phy level according the expected value in "mem-speed" field
+
+the next attributes are DDR parameters, they are generated by DDR tools
+included in STM32 Cube tool
+
+info attributes:
+----------------
+- st,mem-name : name for DDR configuration, simple string for information
+- st,mem-speed : DDR expected speed for the setting in MHz
+- st,mem-size : DDR mem size in byte
+
+
+controlleur attributes:
+-----------------------
+- st,ctl-reg : controleur values depending of the DDR type
+ (DDR3/LPDDR2/LPDDR3)
+ for STM32MP15x: 25 values are requested in this order
+ MSTR
+ MRCTRL0
+ MRCTRL1
+ DERATEEN
+ DERATEINT
+ PWRCTL
+ PWRTMG
+ HWLPCTL
+ RFSHCTL0
+ RFSHCTL3
+ CRCPARCTL0
+ ZQCTL0
+ DFITMG0
+ DFITMG1
+ DFILPCFG0
+ DFIUPD0
+ DFIUPD1
+ DFIUPD2
+ DFIPHYMSTR
+ ODTMAP
+ DBG0
+ DBG1
+ DBGCMD
+ POISONCFG
+ PCCFG
+
+- st,ctl-timing : controleur values depending of frequency and timing parameter
+ of DDR
+ for STM32MP15x: 12 values are requested in this order
+ RFSHTMG
+ DRAMTMG0
+ DRAMTMG1
+ DRAMTMG2
+ DRAMTMG3
+ DRAMTMG4
+ DRAMTMG5
+ DRAMTMG6
+ DRAMTMG7
+ DRAMTMG8
+ DRAMTMG14
+ ODTCFG
+
+- st,ctl-map : controleur values depending of address mapping
+ for STM32MP15x: 9 values are requested in this order
+ ADDRMAP1
+ ADDRMAP2
+ ADDRMAP3
+ ADDRMAP4
+ ADDRMAP5
+ ADDRMAP6
+ ADDRMAP9
+ ADDRMAP10
+ ADDRMAP11
+
+- st,ctl-perf : controleur values depending of performance and scheduling
+ for STM32MP15x: 17 values are requested in this order
+ SCHED
+ SCHED1
+ PERFHPR1
+ PERFLPR1
+ PERFWR1
+ PCFGR_0
+ PCFGW_0
+ PCFGQOS0_0
+ PCFGQOS1_0
+ PCFGWQOS0_0
+ PCFGWQOS1_0
+ PCFGR_1
+ PCFGW_1
+ PCFGQOS0_1
+ PCFGQOS1_1
+ PCFGWQOS0_1
+ PCFGWQOS1_1
+
+phyc attributes:
+----------------
+- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
+ for STM32MP15x: 10 values are requested in this order
+ PGCR
+ ACIOCR
+ DXCCR
+ DSGCR
+ DCR
+ ODTCR
+ ZQ0CR1
+ DX0GCR
+ DX1GCR
+ DX2GCR
+ DX3GCR
+
+- st,phy-timing : phy values depending of frequency and timing parameter of DDR
+ for STM32MP15x: 10 values are requested in this order
+ PTR0
+ PTR1
+ PTR2
+ DTPR0
+ DTPR1
+ DTPR2
+ MR0
+ MR1
+ MR2
+ MR3
+
+- st,phy-cal : phy cal depending of calibration or tuning of DDR
+ for STM32MP15x: 12 values are requested in this order
+ DX0DLLCR
+ DX0DQTR
+ DX0DQSTR
+ DX1DLLCR
+ DX1DQTR
+ DX1DQSTR
+ DX2DLLCR
+ DX2DQTR
+ DX2DQSTR
+ DX3DLLCR
+ DX3DQTR
+ DX3DQSTR
+
+Example:
+
+/ {
+ soc {
+ u-boot,dm-spl;
+
+ ddr: ddr@0x5A003000{
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp1-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ clocks = <&rcc_clk AXIDCG>,
+ <&rcc_clk DDRC1>,
+ <&rcc_clk DDRC2>,
+ <&rcc_clk DDRPHYC>,
+ <&rcc_clk DDRCAPB>,
+ <&rcc_clk DDRPHYCAPB>;
+
+ clock-names = "axidcg",
+ "ddrc1",
+ "ddrc2",
+ "ddrphyc",
+ "ddrcapb",
+ "ddrphycapb";
+
+ st,mem-name = "DDR3 2x4Gb 533MHz";
+ st,mem-speed = <533>;
+ st,mem-size = <0x40000000>;
+
+ st,ctl-reg = <
+ 0x00040401 /*MSTR*/
+ 0x00000010 /*MRCTRL0*/
+ 0x00000000 /*MRCTRL1*/
+ 0x00000000 /*DERATEEN*/
+ 0x00800000 /*DERATEINT*/
+ 0x00000000 /*PWRCTL*/
+ 0x00400010 /*PWRTMG*/
+ 0x00000000 /*HWLPCTL*/
+ 0x00210000 /*RFSHCTL0*/
+ 0x00000000 /*RFSHCTL3*/
+ 0x00000000 /*CRCPARCTL0*/
+ 0xC2000040 /*ZQCTL0*/
+ 0x02050105 /*DFITMG0*/
+ 0x00000202 /*DFITMG1*/
+ 0x07000000 /*DFILPCFG0*/
+ 0xC0400003 /*DFIUPD0*/
+ 0x00000000 /*DFIUPD1*/
+ 0x00000000 /*DFIUPD2*/
+ 0x00000000 /*DFIPHYMSTR*/
+ 0x00000001 /*ODTMAP*/
+ 0x00000000 /*DBG0*/
+ 0x00000000 /*DBG1*/
+ 0x00000000 /*DBGCMD*/
+ 0x00000000 /*POISONCFG*/
+ 0x00000010 /*PCCFG*/
+ >;
+
+ st,ctl-timing = <
+ 0x0080008A /*RFSHTMG*/
+ 0x121B2414 /*DRAMTMG0*/
+ 0x000D041B /*DRAMTMG1*/
+ 0x0607080E /*DRAMTMG2*/
+ 0x0050400C /*DRAMTMG3*/
+ 0x07040407 /*DRAMTMG4*/
+ 0x06060303 /*DRAMTMG5*/
+ 0x02020002 /*DRAMTMG6*/
+ 0x00000202 /*DRAMTMG7*/
+ 0x00001005 /*DRAMTMG8*/
+ 0x000D041B /*DRAMTMG1*/4
+ 0x06000600 /*ODTCFG*/
+ >;
+
+ st,ctl-map = <
+ 0x00080808 /*ADDRMAP1*/
+ 0x00000000 /*ADDRMAP2*/
+ 0x00000000 /*ADDRMAP3*/
+ 0x00001F1F /*ADDRMAP4*/
+ 0x07070707 /*ADDRMAP5*/
+ 0x0F070707 /*ADDRMAP6*/
+ 0x00000000 /*ADDRMAP9*/
+ 0x00000000 /*ADDRMAP10*/
+ 0x00000000 /*ADDRMAP11*/
+ >;
+
+ st,ctl-perf = <
+ 0x00001201 /*SCHED*/
+ 0x00001201 /*SCHED*/1
+ 0x01000001 /*PERFHPR1*/
+ 0x08000200 /*PERFLPR1*/
+ 0x08000400 /*PERFWR1*/
+ 0x00010000 /*PCFGR_0*/
+ 0x00000000 /*PCFGW_0*/
+ 0x02100B03 /*PCFGQOS0_0*/
+ 0x00800100 /*PCFGQOS1_0*/
+ 0x01100B03 /*PCFGWQOS0_0*/
+ 0x01000200 /*PCFGWQOS1_0*/
+ 0x00010000 /*PCFGR_1*/
+ 0x00000000 /*PCFGW_1*/
+ 0x02100B03 /*PCFGQOS0_1*/
+ 0x00800000 /*PCFGQOS1_1*/
+ 0x01100B03 /*PCFGWQOS0_1*/
+ 0x01000200 /*PCFGWQOS1_1*/
+ >;
+
+ st,phy-reg = <
+ 0x01442E02 /*PGCR*/
+ 0x10400812 /*ACIOCR*/
+ 0x00000C40 /*DXCCR*/
+ 0xF200001F /*DSGCR*/
+ 0x0000000B /*DCR*/
+ 0x00010000 /*ODTCR*/
+ 0x0000007B /*ZQ0CR1*/
+ 0x0000CE81 /*DX0GCR*/
+ 0x0000CE81 /*DX1GCR*/
+ 0x0000CE81 /*DX2GCR*/
+ 0x0000CE81 /*DX3GCR*/
+ >;
+
+ st,phy-timing = <
+ 0x0022A41B /*PTR0*/
+ 0x047C0740 /*PTR1*/
+ 0x042D9C80 /*PTR2*/
+ 0x369477D0 /*DTPR0*/
+ 0x098A00D8 /*DTPR1*/
+ 0x10023600 /*DTPR2*/
+ 0x00000830 /*MR0*/
+ 0x00000000 /*MR1*/
+ 0x00000208 /*MR2*/
+ 0x00000000 /*MR3*/
+ >;
+
+ st,phy-cal = <
+ 0x40000000 /*DX0DLLCR*/
+ 0xFFFFFFFF /*DX0DQTR*/
+ 0x3DB02000 /*DX0DQSTR*/
+ 0x40000000 /*DX1DLLCR*/
+ 0xFFFFFFFF /*DX1DQTR*/
+ 0x3DB02000 /*DX1DQSTR*/
+ 0x40000000 /*DX2DLLCR*/
+ 0xFFFFFFFF /*DX2DQTR*/
+ 0x3DB02000 /*DX2DQSTR*/
+ 0x40000000 /*DX3DLLCR*/
+ 0xFFFFFFFF /*DX3DQTR*/
+ 0x3DB02000 /*DX3DQSTR*/
+ >;
+
+ status = "okay";
+ };
+ };
+};
diff --git a/doc/driver-model/MIGRATION.txt b/doc/driver-model/MIGRATION.txt
index d2fe027..5ebefd6 100644
--- a/doc/driver-model/MIGRATION.txt
+++ b/doc/driver-model/MIGRATION.txt
@@ -18,3 +18,38 @@
Note that this implies use of driver model for all block devices (e.g.
MMC, USB, SCSI, SATA).
+
+CONFIG_DM_SPI
+CONFIG_DM_SPI_FLASH
+-------------------
+
+Board Maintainers should submit the patches for enabling DM_SPI and DM_SPI_FLASH
+to move the migration with in the deadline.
+
+Status: In progress
+Deadline: 2018.09
+
+No dm conversion yet:
+ drivers/spi/cf_spi.c
+ drivers/spi/fsl_espi.c
+ drivers/spi/lpc32xx_ssp.c
+ drivers/spi/mpc8xx_spi.c
+ drivers/spi/mpc8xxx_spi.c
+ drivers/spi/mxs_spi.c
+ drivers/spi/sh_qspi.c
+ drivers/spi/sh_spi.c
+ drivers/spi/soft_spi_legacy.c
+
+Partially converted:
+ drivers/spi/atcspi200_spi.c
+ drivers/spi/davinci_spi.c
+ drivers/spi/fsl_dspi.c
+ drivers/spi/fsl_qspi.c
+ drivers/spi/kirkwood_spi.c
+ drivers/spi/mxc_spi.c
+ drivers/spi/omap3_spi.c
+ drivers/spi/ti_qspi.c
+
+--
+Jagan Teki <jagan@openedev.com>
+03/14/2018
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 5a365cd..d5e3097 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -15,6 +15,7 @@
alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com>
alias afleming Andy Fleming <afleming@gmail.com>
alias ag Anatolij Gustschin <agust@denx.de>
+alias agraf Alexander Graf <agraf@suse.de>
alias alisonwang Alison Wang <alison.wang@freescale.com>
alias angelo_ts Angelo Dureghello <angelo@sysam.it>
alias bmeng Bin Meng <bmeng.cn@gmail.com>
@@ -120,6 +121,7 @@
alias dm uboot, sjg
alias cfi uboot, stroese
alias dfu uboot, lukma
+alias efi uboot, agraf
alias eth uboot, jhersh
alias kerneldoc uboot, marex
alias fdt uboot, sjg
diff --git a/drivers/Makefile b/drivers/Makefile
index 2673428..6846d18 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -29,6 +29,7 @@
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
+obj-$(CONFIG_SPL_RESET_SUPPORT) += reset/
obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c
index 029b778..6c7371e 100644
--- a/drivers/ata/dwc_ahci.c
+++ b/drivers/ata/dwc_ahci.c
@@ -25,17 +25,18 @@
void *wrapper_base;
};
+static int dwc_ahci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ahci_bind_scsi(dev, &scsi_dev);
+}
+
static int dwc_ahci_ofdata_to_platdata(struct udevice *dev)
{
struct dwc_ahci_priv *priv = dev_get_priv(dev);
- struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
fdt_addr_t addr;
- plat->max_id = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "max-id", CONFIG_SYS_SCSI_MAX_SCSI_ID);
- plat->max_lun = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "max-lun", CONFIG_SYS_SCSI_MAX_LUN);
-
priv->base = map_physmem(devfdt_get_addr(dev), sizeof(void *),
MAP_NOCACHE);
@@ -81,11 +82,7 @@
writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG);
}
- ret = ahci_init_dm(dev, priv->base);
- if (ret)
- return ret;
-
- return ahci_start_ports_dm(dev);
+ return ahci_probe_scsi(dev, (ulong)priv->base);
}
static const struct udevice_id dwc_ahci_ids[] = {
@@ -95,11 +92,11 @@
U_BOOT_DRIVER(dwc_ahci) = {
.name = "dwc_ahci",
- .id = UCLASS_SCSI,
+ .id = UCLASS_AHCI,
.of_match = dwc_ahci_ids,
+ .bind = dwc_ahci_bind,
.ofdata_to_platdata = dwc_ahci_ofdata_to_platdata,
.ops = &scsi_ops,
.probe = dwc_ahci_probe,
.priv_auto_alloc_size = sizeof(struct dwc_ahci_priv),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
};
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 73972b7..d335ed1 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -34,6 +34,7 @@
config BOOTCOUNT_AM33XX
bool "Boot counter in AM33XX RTC IP block"
depends on AM33XX || SOC_DA8XX
+ select SPL_AM33XX_ENABLE_RTC32K_OSC if AM33XX
help
A bootcount driver for the RTC IP block found on many TI platforms.
This requires the RTC clocks, etc, to be enabled prior to use and
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cdfa052..c382e88 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -75,6 +75,14 @@
This clock driver adds support for clock realted settings for
ZynqMP platform.
+config CLK_STM32MP1
+ bool "Enable RCC clock driver for STM32MP1"
+ depends on ARCH_STM32MP && CLK
+ default y
+ help
+ Enable the STM32 clock (RCC) driver. Enable support for
+ manipulating STM32MP1's on-SoC clocks.
+
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dab106a..e05c607 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -17,6 +17,7 @@
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
+obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
index fd56f20..8d482a2 100644
--- a/drivers/clk/at91/Kconfig
+++ b/drivers/clk/at91/Kconfig
@@ -27,6 +27,14 @@
fast crystal oscillator to meet the frequency accuracy
required by USB.
+config AT91_USB_CLK
+ bool "Support USB OHCI Input Clock"
+ depends on CLK_AT91
+ help
+ This option is used to enable the USB Input Clock, from
+ the device tree, configure the USBS bit (PLLA or UTMI PLL)
+ and USBDIV field of the PMC_USB register.
+
config AT91_H32MX
bool "Support H32MX 32-bit Matrix Clock"
depends on CLK_AT91
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index fbe3cb6..8c197ff 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,9 +3,10 @@
#
obj-y += pmc.o sckc.o
-obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o
+obj-y += clk-slow.o clk-main.o clk-plla.o clk-plladiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_UTMI) += clk-utmi.o
+obj-$(CONFIG_AT91_USB_CLK) += clk-usb.o
obj-$(CONFIG_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generated.o
diff --git a/drivers/clk/at91/clk-plladiv.c b/drivers/clk/at91/clk-plladiv.c
new file mode 100644
index 0000000..0599d28
--- /dev/null
+++ b/drivers/clk/at91/clk-plladiv.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2018 Microhip / Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/io.h>
+#include <mach/at91_pmc.h>
+#include "pmc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int at91_plladiv_clk_enable(struct clk *clk)
+{
+ return 0;
+}
+
+static ulong at91_plladiv_clk_get_rate(struct clk *clk)
+{
+ struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct at91_pmc *pmc = plat->reg_base;
+ struct clk source;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(clk->dev, 0, &source);
+ if (ret)
+ return -EINVAL;
+
+ clk_rate = clk_get_rate(&source);
+ if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
+ clk_rate /= 2;
+
+ return clk_rate;
+}
+
+static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct at91_pmc *pmc = plat->reg_base;
+ struct clk source;
+ ulong parent_rate;
+ int ret;
+
+ ret = clk_get_by_index(clk->dev, 0, &source);
+ if (ret)
+ return -EINVAL;
+
+ parent_rate = clk_get_rate(&source);
+ if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
+ return -EINVAL;
+
+ if (parent_rate != rate) {
+ writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
+ &pmc->mckr);
+ }
+
+ return 0;
+}
+
+static struct clk_ops at91_plladiv_clk_ops = {
+ .enable = at91_plladiv_clk_enable,
+ .get_rate = at91_plladiv_clk_get_rate,
+ .set_rate = at91_plladiv_clk_set_rate,
+};
+
+static int at91_plladiv_clk_probe(struct udevice *dev)
+{
+ return at91_pmc_core_probe(dev);
+}
+
+static const struct udevice_id at91_plladiv_clk_match[] = {
+ { .compatible = "atmel,at91sam9x5-clk-plldiv" },
+ {}
+};
+
+U_BOOT_DRIVER(at91_plladiv_clk) = {
+ .name = "at91-plladiv-clk",
+ .id = UCLASS_CLK,
+ .of_match = at91_plladiv_clk_match,
+ .probe = at91_plladiv_clk_probe,
+ .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .ops = &at91_plladiv_clk_ops,
+};
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
index 24b271a..81fe47a 100644
--- a/drivers/clk/at91/clk-system.c
+++ b/drivers/clk/at91/clk-system.c
@@ -44,6 +44,30 @@
return (id >= 8) && (id <= 15);
}
+static ulong system_clk_get_rate(struct clk *clk)
+{
+ struct clk clk_dev;
+ int ret;
+
+ ret = clk_get_by_index(clk->dev, 0, &clk_dev);
+ if (ret)
+ return -EINVAL;
+
+ return clk_get_rate(&clk_dev);
+}
+
+static ulong system_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk clk_dev;
+ int ret;
+
+ ret = clk_get_by_index(clk->dev, 0, &clk_dev);
+ if (ret)
+ return -EINVAL;
+
+ return clk_set_rate(&clk_dev, rate);
+}
+
static int system_clk_enable(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
@@ -73,6 +97,8 @@
static struct clk_ops system_clk_ops = {
.of_xlate = at91_clk_of_xlate,
+ .get_rate = system_clk_get_rate,
+ .set_rate = system_clk_set_rate,
.enable = system_clk_enable,
};
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 0000000..36622c0
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2018 Microhip / Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/io.h>
+#include <mach/at91_pmc.h>
+#include "pmc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AT91_USB_CLK_SOURCE_MAX 2
+#define AT91_USB_CLK_MAX_DIV 15
+
+struct at91_usb_clk_priv {
+ u32 num_clksource;
+};
+
+static ulong at91_usb_clk_get_rate(struct clk *clk)
+{
+ struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct at91_pmc *pmc = plat->reg_base;
+ struct clk source;
+ u32 tmp, usbdiv;
+ u8 source_index;
+ int ret;
+
+ tmp = readl(&pmc->pcr);
+ source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
+ AT91_PMC_USB_USBS_MASK;
+ usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
+
+ ret = clk_get_by_index(clk->dev, source_index, &source);
+ if (ret)
+ return 0;
+
+ return clk_get_rate(&source) / (usbdiv + 1);
+}
+
+static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct at91_pmc *pmc = plat->reg_base;
+ struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
+ struct clk source, best_source;
+ ulong tmp_rate, best_rate = rate, source_rate;
+ int tmp_diff, best_diff = -1;
+ u32 div, best_div = 0;
+ u8 best_source_index = 0;
+ u8 i;
+ u32 tmp;
+ int ret;
+
+ for (i = 0; i < priv->num_clksource; i++) {
+ ret = clk_get_by_index(clk->dev, i, &source);
+ if (ret)
+ return ret;
+
+ source_rate = clk_get_rate(&source);
+ if (IS_ERR_VALUE(source_rate))
+ return source_rate;
+
+ for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
+ tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
+ tmp_diff = abs(rate - tmp_rate);
+
+ if (best_diff < 0 || best_diff > tmp_diff) {
+ best_rate = tmp_rate;
+ best_diff = tmp_diff;
+
+ best_div = div - 1;
+ best_source = source;
+ best_source_index = i;
+ }
+
+ if (!best_diff || tmp_rate < rate)
+ break;
+ }
+
+ if (!best_diff)
+ break;
+ }
+
+ debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
+ best_source.dev->name, best_rate, best_div);
+
+ ret = clk_enable(&best_source);
+ if (ret)
+ return ret;
+
+ tmp = AT91_PMC_USB_USBS_(best_source_index) |
+ AT91_PMC_USB_DIV_(best_div);
+ writel(tmp, &pmc->usb);
+
+ return 0;
+}
+
+static struct clk_ops at91_usb_clk_ops = {
+ .get_rate = at91_usb_clk_get_rate,
+ .set_rate = at91_usb_clk_set_rate,
+};
+
+static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct at91_usb_clk_priv *priv = dev_get_priv(dev);
+ u32 cells[AT91_USB_CLK_SOURCE_MAX];
+ u32 num_clksource;
+
+ num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
+ dev_of_offset(dev),
+ "clocks", cells,
+ AT91_USB_CLK_SOURCE_MAX);
+
+ if (!num_clksource)
+ return -1;
+
+ priv->num_clksource = num_clksource;
+
+ return 0;
+}
+
+static int at91_usb_clk_probe(struct udevice *dev)
+{
+ return at91_pmc_core_probe(dev);
+}
+
+static const struct udevice_id at91_usb_clk_match[] = {
+ { .compatible = "atmel,at91sam9x5-clk-usb" },
+ {}
+};
+
+U_BOOT_DRIVER(at91_usb_clk) = {
+ .name = "at91-usb-clk",
+ .id = UCLASS_CLK,
+ .of_match = at91_usb_clk_match,
+ .probe = at91_usb_clk_probe,
+ .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv),
+ .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .ops = &at91_usb_clk_ops,
+};
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ad76379..6e99b3b 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -104,6 +104,39 @@
return clk_get_by_indexed_prop(dev, "clocks", index, clk);
}
+int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+ int i, ret, err, count;
+
+ bulk->count = 0;
+
+ count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+ if (!count)
+ return 0;
+
+ bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
+ if (!bulk->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ ret = clk_get_by_index(dev, i, &bulk->clks[i]);
+ if (ret < 0)
+ goto bulk_get_err;
+
+ ++bulk->count;
+ }
+
+ return 0;
+
+bulk_get_err:
+ err = clk_release_all(bulk->clks, bulk->count);
+ if (err)
+ debug("%s: could release all clocks for %p\n",
+ __func__, dev);
+
+ return ret;
+}
+
static int clk_set_default_parents(struct udevice *dev)
{
struct clk clk, parent_clk;
@@ -336,6 +369,19 @@
return ops->enable(clk);
}
+int clk_enable_bulk(struct clk_bulk *bulk)
+{
+ int i, ret;
+
+ for (i = 0; i < bulk->count; i++) {
+ ret = clk_enable(&bulk->clks[i]);
+ if (ret < 0 && ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
int clk_disable(struct clk *clk)
{
const struct clk_ops *ops = clk_dev_ops(clk->dev);
@@ -348,6 +394,19 @@
return ops->disable(clk);
}
+int clk_disable_bulk(struct clk_bulk *bulk)
+{
+ int i, ret;
+
+ for (i = 0; i < bulk->count; i++) {
+ ret = clk_disable(&bulk->clks[i]);
+ if (ret < 0 && ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
index 999100d..d089881 100644
--- a/drivers/clk/clk_sandbox_test.c
+++ b/drivers/clk/clk_sandbox_test.c
@@ -11,6 +11,7 @@
struct sandbox_clk_test {
struct clk clks[SANDBOX_CLK_TEST_ID_COUNT];
+ struct clk_bulk bulk;
};
static const char * const sandbox_clk_test_names[] = {
@@ -34,6 +35,13 @@
return 0;
}
+int sandbox_clk_test_get_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_get_bulk(dev, &sbct->bulk);
+}
+
ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -64,6 +72,13 @@
return clk_enable(&sbct->clks[id]);
}
+int sandbox_clk_test_enable_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_enable_bulk(&sbct->bulk);
+}
+
int sandbox_clk_test_disable(struct udevice *dev, int id)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -74,6 +89,13 @@
return clk_disable(&sbct->clks[id]);
}
+int sandbox_clk_test_disable_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_disable_bulk(&sbct->bulk);
+}
+
int sandbox_clk_test_free(struct udevice *dev)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -88,6 +110,13 @@
return 0;
}
+int sandbox_clk_test_release_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_release_bulk(&sbct->bulk);
+}
+
static const struct udevice_id sandbox_clk_test_ids[] = {
{ .compatible = "sandbox,clk-test" },
{ }
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 926b249..d8eab1a 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -55,18 +55,27 @@
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
-#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
-#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
+#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
+#define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
+#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
+#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
-#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
+#define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
+#define RCC_DCKCFGRX_TIMPRE BIT(24)
#define RCC_DCKCFGRX_CK48MSEL BIT(27)
#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
+#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
+#define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
+#define RCC_DCKCFGR_PLLSAIDIVR_2 0
+
/*
* RCC AHB1ENR specific definitions
*/
@@ -86,8 +95,10 @@
#define RCC_APB2ENR_SYSCFGEN BIT(14)
#define RCC_APB2ENR_SAI1EN BIT(22)
-enum periph_clock {
- TIMER2_CLOCK_CFG,
+enum pllsai_div {
+ PLLSAIP,
+ PLLSAIQ,
+ PLLSAIR,
};
static const struct stm32_clk_info stm32f4_clk_info = {
@@ -125,13 +136,17 @@
unsigned long hse_rate;
};
+#ifdef CONFIG_VIDEO_STM32
+static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
+#endif
+static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
+
static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
struct stm32_pwr_regs *pwr = priv->pwr_regs;
struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
- u32 pllsaicfgr = 0;
/* Reset RCC configuration */
setbits_le32(®s->cr, RCC_CR_HSION);
@@ -163,20 +178,10 @@
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
- /* Configure the SAI PLL to get a 48 MHz source */
- pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
- RCC_PLLSAICFGR_PLLSAIP_4;
- pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
- writel(pllsaicfgr, ®s->pllsaicfgr);
-
- /* Enable the main PLL */
- setbits_le32(®s->cr, RCC_CR_PLLON);
- while (!(readl(®s->cr) & RCC_CR_PLLRDY))
- ;
-
+ /* configure SDMMC clock */
if (priv->info.v2) { /*stm32f7 case */
- /* select PLLSAI as 48MHz clock source */
- setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
+ /* select PLLQ as 48MHz clock source */
+ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
/* select 48MHz as SDMMC1 clock source */
clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
@@ -184,18 +189,36 @@
/* select 48MHz as SDMMC2 clock source */
clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
} else { /* stm32f4 case */
- /* select PLLSAI as 48MHz clock source */
- setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
+ /* select PLLQ as 48MHz clock source */
+ clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
/* select 48MHz as SDMMC1 clock source */
clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
}
- /* Enable the SAI PLL */
+#ifdef CONFIG_VIDEO_STM32
+ /*
+ * Configure the SAI PLL to generate LTDC pixel clock
+ */
+ clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
+ RCC_PLLSAICFGR_PLLSAIR_3);
+ clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
+ 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
+
+ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
+#endif
+ /* Enable the main PLL */
+ setbits_le32(®s->cr, RCC_CR_PLLON);
+ while (!(readl(®s->cr) & RCC_CR_PLLRDY))
+ ;
+
+#ifdef CONFIG_VIDEO_STM32
+/* Enable the SAI PLL */
setbits_le32(®s->cr, RCC_CR_PLLSAION);
while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
;
-
+#endif
setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
if (priv->info.has_overdrive) {
@@ -221,8 +244,6 @@
while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
- /* gate the SAI clock, needed for MMC 1&2 clocks */
- setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN);
#ifdef CONFIG_ETH_DESIGNWARE
/* gate the SYSCFG clock, needed to set RMII ethernet interface */
@@ -232,49 +253,145 @@
return 0;
}
-static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
- u32 sysclk)
+static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
{
struct stm32_rcc_regs *regs = priv->base;
- u16 pllq, pllm, pllsain, pllsaip;
- bool pllsai;
-
- pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
- >> RCC_PLLCFGR_PLLQ_SHIFT;
if (priv->info.v2) /*stm32f7 case */
- pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
+ return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
else
- pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
- if (pllsai) {
- /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
- pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
- pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
- >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
- pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
- >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
- return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
- }
- /* PLL48CLK is selected from PLLQ */
- return sysclk / pllq;
+ return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
}
-static unsigned long stm32_clk_get_rate(struct clk *clk)
+static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
{
- struct stm32_clk *priv = dev_get_priv(clk->dev);
struct stm32_rcc_regs *regs = priv->base;
- u32 sysclk = 0;
- u32 shift = 0;
- u16 pllm, plln, pllp;
+ u16 pllm, pllsain;
+
+ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+ pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
+
+ return ((priv->hse_rate / pllm) * pllsain);
+}
+
+static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
+ enum pllsai_div output)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u16 pll_div_output;
+
+ switch (output) {
+ case PLLSAIP:
+ pll_div_output = ((((readl(®s->pllsaicfgr)
+ & RCC_PLLSAICFGR_PLLSAIP_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
+ break;
+ case PLLSAIQ:
+ pll_div_output = (readl(®s->pllsaicfgr)
+ & RCC_PLLSAICFGR_PLLSAIQ_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
+ break;
+ case PLLSAIR:
+ pll_div_output = (readl(®s->pllsaicfgr)
+ & RCC_PLLSAICFGR_PLLSAIR_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
+ break;
+ default:
+ pr_err("incorrect PLLSAI output %d\n", output);
+ return -EINVAL;
+ }
+
+ return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
+}
+
+static bool stm32_get_timpre(struct stm32_clk *priv)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u32 val;
+
+ if (priv->info.v2) /*stm32f7 case */
+ val = readl(®s->dckcfgr2);
+ else
+ val = readl(®s->dckcfgr);
+ /* get timer prescaler */
+ return !!(val & RCC_DCKCFGRX_TIMPRE);
+}
+
+static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
+{
+ u8 shift;
/* Prescaler table lookups for clock computation */
u8 ahb_psc_table[16] = {
0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
};
+
+ shift = ahb_psc_table[(
+ (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
+ >> RCC_CFGR_HPRE_SHIFT)];
+
+ return sysclk >> shift;
+};
+
+static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
+{
+ /* Prescaler table lookups for clock computation */
u8 apb_psc_table[8] = {
0, 0, 0, 0, 1, 2, 3, 4
};
+ if (apb == APB1)
+ return apb_psc_table[(
+ (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
+ >> RCC_CFGR_PPRE1_SHIFT)];
+ else /* APB2 */
+ return apb_psc_table[(
+ (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
+ >> RCC_CFGR_PPRE2_SHIFT)];
+};
+
+static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
+ enum apb apb)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u8 shift = stm32_get_apb_shift(regs, apb);
+
+ if (stm32_get_timpre(priv))
+ /*
+ * if APB prescaler is configured to a
+ * division factor of 1, 2 or 4
+ */
+ switch (shift) {
+ case 0:
+ case 1:
+ case 2:
+ return stm32_get_hclk_rate(regs, sysclk);
+ default:
+ return (sysclk >> shift) * 4;
+ }
+ else
+ /*
+ * if APB prescaler is configured to a
+ * division factor of 1
+ */
+ if (shift == 0)
+ return sysclk;
+ else
+ return (sysclk >> shift) * 2;
+};
+
+static ulong stm32_clk_get_rate(struct clk *clk)
+{
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
+ u32 sysclk = 0;
+ u32 vco;
+ u32 sdmmcxsel_bit;
+ u32 saidivr;
+ u32 pllsai_rate;
+ u16 pllm, plln, pllp, pllq;
+
if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
@@ -282,7 +399,10 @@
>> RCC_PLLCFGR_PLLN_SHIFT);
pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
- sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
+ pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
+ >> RCC_PLLCFGR_PLLQ_SHIFT);
+ vco = (priv->hse_rate / pllm) * plln;
+ sysclk = vco / pllp;
} else {
return -EINVAL;
}
@@ -293,44 +413,72 @@
* AHB1, AHB2 and AHB3
*/
case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
- shift = ahb_psc_table[(
- (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
- >> RCC_CFGR_HPRE_SHIFT)];
- return sysclk >>= shift;
+ return stm32_get_hclk_rate(regs, sysclk);
/* APB1 CLOCK */
case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
- shift = apb_psc_table[(
- (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
- >> RCC_CFGR_PPRE1_SHIFT)];
- return sysclk >>= shift;
+ /* For timer clock, an additionnal prescaler is used*/
+ switch (clk->id) {
+ case STM32F7_APB1_CLOCK(TIM2):
+ case STM32F7_APB1_CLOCK(TIM3):
+ case STM32F7_APB1_CLOCK(TIM4):
+ case STM32F7_APB1_CLOCK(TIM5):
+ case STM32F7_APB1_CLOCK(TIM6):
+ case STM32F7_APB1_CLOCK(TIM7):
+ case STM32F7_APB1_CLOCK(TIM12):
+ case STM32F7_APB1_CLOCK(TIM13):
+ case STM32F7_APB1_CLOCK(TIM14):
+ return stm32_get_timer_rate(priv, sysclk, APB1);
+ }
+ return (sysclk >> stm32_get_apb_shift(regs, APB1));
+
/* APB2 CLOCK */
- case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
+ case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
+ switch (clk->id) {
/*
* particular case for SDMMC1 and SDMMC2 :
* 48Mhz source clock can be from main PLL or from
- * SAI PLL
+ * PLLSAIP
*/
- switch (clk->id) {
case STM32F7_APB2_CLOCK(SDMMC1):
- if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
+ case STM32F7_APB2_CLOCK(SDMMC2):
+ if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
+ sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
+ else
+ sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
+
+ if (readl(®s->dckcfgr2) & sdmmcxsel_bit)
/* System clock is selected as SDMMC1 clock */
return sysclk;
+ /*
+ * 48 MHz can be generated by either PLLSAIP
+ * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
+ */
+ if (stm32_clk_get_ck48msel(priv))
+ return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
else
- return stm32_clk_pll48clk_rate(priv, sysclk);
+ return (vco / pllq);
break;
- case STM32F7_APB2_CLOCK(SDMMC2):
- if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
- /* System clock is selected as SDMMC2 clock */
- return sysclk;
- else
- return stm32_clk_pll48clk_rate(priv, sysclk);
- break;
- }
- shift = apb_psc_table[(
- (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
- >> RCC_CFGR_PPRE2_SHIFT)];
- return sysclk >>= shift;
+ /* For timer clock, an additionnal prescaler is used*/
+ case STM32F7_APB2_CLOCK(TIM1):
+ case STM32F7_APB2_CLOCK(TIM8):
+ case STM32F7_APB2_CLOCK(TIM9):
+ case STM32F7_APB2_CLOCK(TIM10):
+ case STM32F7_APB2_CLOCK(TIM11):
+ return stm32_get_timer_rate(priv, sysclk, APB2);
+ break;
+
+ /* particular case for LTDC clock */
+ case STM32F7_APB2_CLOCK(LTDC):
+ saidivr = readl(®s->dckcfgr);
+ saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
+ >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
+ pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
+
+ return pllsai_rate / pllsaidivr_table[saidivr];
+ }
+ return (sysclk >> stm32_get_apb_shift(regs, APB2));
+
default:
pr_err("clock index %ld out of range\n", clk->id);
return -EINVAL;
@@ -339,7 +487,104 @@
static ulong stm32_set_rate(struct clk *clk, ulong rate)
{
+#ifdef CONFIG_VIDEO_STM32
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
+ u32 pllsair_rate, pllsai_vco_rate, current_rate;
+ u32 best_div, best_diff, diff;
+ u16 div;
+ u8 best_plldivr, best_pllsaidivr;
+ u8 i, j;
+ bool found = false;
+
+ /* Only set_rate for LTDC clock is implemented */
+ if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
+ pr_err("set_rate not implemented for clock index %ld\n",
+ clk->id);
+ return 0;
+ }
+
+ if (rate == stm32_clk_get_rate(clk))
+ /* already set to requested rate */
+ return rate;
+
+ /* get the current PLLSAIR output freq */
+ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
+ best_div = pllsair_rate / rate;
+
+ /* look into pllsaidivr_table if this divider is available*/
+ for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
+ if (best_div == pllsaidivr_table[i]) {
+ /* set pll_saidivr with found value */
+ clrsetbits_le32(®s->dckcfgr,
+ RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ pllsaidivr_table[i]);
+ return rate;
+ }
+
+ /*
+ * As no pllsaidivr value is suitable to obtain requested freq,
+ * test all combination of pllsaidivr * pllsair and find the one
+ * which give freq closest to requested rate.
+ */
+
+ pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
+ best_diff = ULONG_MAX;
+ best_pllsaidivr = 0;
+ best_plldivr = 0;
+ /*
+ * start at index 2 of plldivr_table as divider value at index 0
+ * and 1 are 0)
+ */
+ for (i = 2; i < sizeof(plldivr_table); i++) {
+ for (j = 0; j < sizeof(pllsaidivr_table); j++) {
+ div = plldivr_table[i] * pllsaidivr_table[j];
+ current_rate = pllsai_vco_rate / div;
+ /* perfect combination is found ? */
+ if (current_rate == rate) {
+ best_pllsaidivr = j;
+ best_plldivr = i;
+ found = true;
+ break;
+ }
+
+ diff = (current_rate > rate) ?
+ current_rate - rate : rate - current_rate;
+
+ /* found a better combination ? */
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_pllsaidivr = j;
+ best_plldivr = i;
+ }
+ }
+
+ if (found)
+ break;
+ }
+
+ /* Disable the SAI PLL */
+ clrbits_le32(®s->cr, RCC_CR_PLLSAION);
+
+ /* set pll_saidivr with found value */
+ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
+
+ /* set pllsair with found value */
+ clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
+ plldivr_table[best_plldivr]
+ << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
+
+ /* Enable the SAI PLL */
+ setbits_le32(®s->cr, RCC_CR_PLLSAION);
+ while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
+ ;
+
+ div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
+ return pllsai_vco_rate / div;
+#else
return 0;
+#endif
}
static int stm32_clk_enable(struct clk *clk)
@@ -356,17 +601,6 @@
return 0;
}
-void clock_setup(int peripheral)
-{
- switch (peripheral) {
- case TIMER2_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
- break;
- default:
- break;
- }
-}
-
static int stm32_clk_probe(struct udevice *dev)
{
struct ofnode_phandle_args args;
diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index c9594d4..9ee2e2e 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -35,6 +35,7 @@
#define RCC_CFGR_SW_CSI 1
#define RCC_CFGR_SW_HSE 2
#define RCC_CFGR_SW_PLL1 3
+#define RCC_CFGR_TIMPRE BIT(15)
#define RCC_PLLCKSELR_PLLSRC_HSI 0
#define RCC_PLLCKSELR_PLLSRC_CSI 1
@@ -339,6 +340,11 @@
.divr = 2,
};
+enum apb {
+ APB1,
+ APB2,
+};
+
int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
@@ -562,13 +568,74 @@
return -EINVAL;
}
+static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb)
+{
+ u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
+ u32 d2cfgr = readl(®s->d2cfgr);
+
+ if (apb == APB1) {
+ if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED)
+ /* get D2 domain APB1 prescaler */
+ return prescaler_table[
+ ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER)
+ >> RCC_D2CFGR_D2PPRE1_SHIFT)];
+ } else { /* APB2 */
+ if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED)
+ /* get D2 domain APB2 prescaler */
+ return prescaler_table[
+ ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER)
+ >> RCC_D2CFGR_D2PPRE2_SHIFT)];
+ }
+
+ return 1;
+};
+
+static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
+ enum apb apb)
+{
+ struct stm32_rcc_regs *regs = priv->rcc_base;
+u32 psc = stm32_get_apb_psc(regs, apb);
+
+ if (readl(®s->cfgr) & RCC_CFGR_TIMPRE)
+ /*
+ * if APB prescaler is configured to a
+ * division factor of 1, 2 or 4
+ */
+ switch (psc) {
+ case 1:
+ case 2:
+ case 4:
+ return sysclk;
+ case 8:
+ return sysclk / 2;
+ case 16:
+ return sysclk / 4;
+ default:
+ pr_err("unexpected prescaler value (%d)\n", psc);
+ return 0;
+ }
+ else
+ switch (psc) {
+ case 1:
+ return sysclk;
+ case 2:
+ case 4:
+ case 8:
+ case 16:
+ return sysclk / psc;
+ default:
+ pr_err("unexpected prescaler value (%d)\n", psc);
+ return 0;
+ }
+};
+
static ulong stm32_clk_get_rate(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);
struct stm32_rcc_regs *regs = priv->rcc_base;
ulong sysclk = 0;
u32 gate_offset;
- u32 d1cfgr;
+ u32 d1cfgr, d3cfgr;
/* prescaler table lookups for clock computation */
u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
u8 source, idx;
@@ -645,9 +712,10 @@
break;
case RCC_APB4ENR:
- if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
+ d3cfgr = readl(®s->d3cfgr);
+ if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
/* get D3 domain APB4 prescaler */
- idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
+ idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
RCC_D3CFGR_D3PPRE_SHIFT;
sysclk = sysclk / prescaler_table[idx];
}
@@ -660,31 +728,42 @@
case RCC_APB1LENR:
case RCC_APB1HENR:
- if (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) {
- /* get D2 domain APB1 prescaler */
- idx = (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) >>
- RCC_D2CFGR_D2PPRE1_SHIFT;
- sysclk = sysclk / prescaler_table[idx];
+ /* special case for GPT timers */
+ switch (clk->id) {
+ case TIM14_CK:
+ case TIM13_CK:
+ case TIM12_CK:
+ case TIM7_CK:
+ case TIM6_CK:
+ case TIM5_CK:
+ case TIM4_CK:
+ case TIM3_CK:
+ case TIM2_CK:
+ return stm32_get_timer_rate(priv, sysclk, APB1);
}
debug("%s system clock: freq after APB1 prescaler = %ld\n",
__func__, sysclk);
- return sysclk;
+ return (sysclk / stm32_get_apb_psc(regs, APB1));
break;
case RCC_APB2ENR:
- if (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) {
- /* get D2 domain APB1 prescaler */
- idx = (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) >>
- RCC_D2CFGR_D2PPRE2_SHIFT;
- sysclk = sysclk / prescaler_table[idx];
+ /* special case for timers */
+ switch (clk->id) {
+ case TIM17_CK:
+ case TIM16_CK:
+ case TIM15_CK:
+ case TIM8_CK:
+ case TIM1_CK:
+ return stm32_get_timer_rate(priv, sysclk, APB2);
}
debug("%s system clock: freq after APB2 prescaler = %ld\n",
__func__, sysclk);
- return sysclk;
+ return (sysclk / stm32_get_apb_psc(regs, APB2));
+
break;
default:
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
new file mode 100644
index 0000000..c67aa44
--- /dev/null
+++ b/drivers/clk/clk_stm32mp1.c
@@ -0,0 +1,1777 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <regmap.h>
+#include <spl.h>
+#include <syscon.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+/* activate clock tree initialization in the driver */
+#define STM32MP1_CLOCK_TREE_INIT
+#endif
+
+#define MAX_HSI_HZ 64000000
+
+/* TIMEOUT */
+#define TIMEOUT_200MS 200000
+#define TIMEOUT_1S 1000000
+
+/* STGEN registers */
+#define STGENC_CNTCR 0x00
+#define STGENC_CNTSR 0x04
+#define STGENC_CNTCVL 0x08
+#define STGENC_CNTCVU 0x0C
+#define STGENC_CNTFID0 0x20
+
+#define STGENC_CNTCR_EN BIT(0)
+
+/* RCC registers */
+#define RCC_OCENSETR 0x0C
+#define RCC_OCENCLRR 0x10
+#define RCC_HSICFGR 0x18
+#define RCC_MPCKSELR 0x20
+#define RCC_ASSCKSELR 0x24
+#define RCC_RCK12SELR 0x28
+#define RCC_MPCKDIVR 0x2C
+#define RCC_AXIDIVR 0x30
+#define RCC_APB4DIVR 0x3C
+#define RCC_APB5DIVR 0x40
+#define RCC_RTCDIVR 0x44
+#define RCC_MSSCKSELR 0x48
+#define RCC_PLL1CR 0x80
+#define RCC_PLL1CFGR1 0x84
+#define RCC_PLL1CFGR2 0x88
+#define RCC_PLL1FRACR 0x8C
+#define RCC_PLL1CSGR 0x90
+#define RCC_PLL2CR 0x94
+#define RCC_PLL2CFGR1 0x98
+#define RCC_PLL2CFGR2 0x9C
+#define RCC_PLL2FRACR 0xA0
+#define RCC_PLL2CSGR 0xA4
+#define RCC_I2C46CKSELR 0xC0
+#define RCC_CPERCKSELR 0xD0
+#define RCC_STGENCKSELR 0xD4
+#define RCC_DDRITFCR 0xD8
+#define RCC_BDCR 0x140
+#define RCC_RDLSICR 0x144
+#define RCC_MP_APB4ENSETR 0x200
+#define RCC_MP_APB5ENSETR 0x208
+#define RCC_MP_AHB5ENSETR 0x210
+#define RCC_MP_AHB6ENSETR 0x218
+#define RCC_OCRDYR 0x808
+#define RCC_DBGCFGR 0x80C
+#define RCC_RCK3SELR 0x820
+#define RCC_RCK4SELR 0x824
+#define RCC_MCUDIVR 0x830
+#define RCC_APB1DIVR 0x834
+#define RCC_APB2DIVR 0x838
+#define RCC_APB3DIVR 0x83C
+#define RCC_PLL3CR 0x880
+#define RCC_PLL3CFGR1 0x884
+#define RCC_PLL3CFGR2 0x888
+#define RCC_PLL3FRACR 0x88C
+#define RCC_PLL3CSGR 0x890
+#define RCC_PLL4CR 0x894
+#define RCC_PLL4CFGR1 0x898
+#define RCC_PLL4CFGR2 0x89C
+#define RCC_PLL4FRACR 0x8A0
+#define RCC_PLL4CSGR 0x8A4
+#define RCC_I2C12CKSELR 0x8C0
+#define RCC_I2C35CKSELR 0x8C4
+#define RCC_UART6CKSELR 0x8E4
+#define RCC_UART24CKSELR 0x8E8
+#define RCC_UART35CKSELR 0x8EC
+#define RCC_UART78CKSELR 0x8F0
+#define RCC_SDMMC12CKSELR 0x8F4
+#define RCC_SDMMC3CKSELR 0x8F8
+#define RCC_ETHCKSELR 0x8FC
+#define RCC_QSPICKSELR 0x900
+#define RCC_FMCCKSELR 0x904
+#define RCC_USBCKSELR 0x91C
+#define RCC_MP_APB1ENSETR 0xA00
+#define RCC_MP_APB2ENSETR 0XA08
+#define RCC_MP_AHB2ENSETR 0xA18
+#define RCC_MP_AHB4ENSETR 0xA28
+
+/* used for most of SELR register */
+#define RCC_SELR_SRC_MASK GENMASK(2, 0)
+#define RCC_SELR_SRCRDY BIT(31)
+
+/* Values of RCC_MPCKSELR register */
+#define RCC_MPCKSELR_HSI 0
+#define RCC_MPCKSELR_HSE 1
+#define RCC_MPCKSELR_PLL 2
+#define RCC_MPCKSELR_PLL_MPUDIV 3
+
+/* Values of RCC_ASSCKSELR register */
+#define RCC_ASSCKSELR_HSI 0
+#define RCC_ASSCKSELR_HSE 1
+#define RCC_ASSCKSELR_PLL 2
+
+/* Values of RCC_MSSCKSELR register */
+#define RCC_MSSCKSELR_HSI 0
+#define RCC_MSSCKSELR_HSE 1
+#define RCC_MSSCKSELR_CSI 2
+#define RCC_MSSCKSELR_PLL 3
+
+/* Values of RCC_CPERCKSELR register */
+#define RCC_CPERCKSELR_HSI 0
+#define RCC_CPERCKSELR_CSI 1
+#define RCC_CPERCKSELR_HSE 2
+
+/* used for most of DIVR register : max div for RTC */
+#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
+#define RCC_DIVR_DIVRDY BIT(31)
+
+/* Masks for specific DIVR registers */
+#define RCC_APBXDIV_MASK GENMASK(2, 0)
+#define RCC_MPUDIV_MASK GENMASK(2, 0)
+#define RCC_AXIDIV_MASK GENMASK(2, 0)
+#define RCC_MCUDIV_MASK GENMASK(3, 0)
+
+/* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET 4
+
+/* Fields of RCC_BDCR register */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(8)
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+
+/* Fields of RCC_RDLSICR register */
+#define RCC_RDLSICR_LSION BIT(0)
+#define RCC_RDLSICR_LSIRDY BIT(1)
+
+/* used for ALL PLLNCR registers */
+#define RCC_PLLNCR_PLLON BIT(0)
+#define RCC_PLLNCR_PLLRDY BIT(1)
+#define RCC_PLLNCR_DIVPEN BIT(4)
+#define RCC_PLLNCR_DIVQEN BIT(5)
+#define RCC_PLLNCR_DIVREN BIT(6)
+#define RCC_PLLNCR_DIVEN_SHIFT 4
+
+/* used for ALL PLLNCFGR1 registers */
+#define RCC_PLLNCFGR1_DIVM_SHIFT 16
+#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
+#define RCC_PLLNCFGR1_DIVN_SHIFT 0
+#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
+/* only for PLL3 and PLL4 */
+#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
+#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
+
+/* used for ALL PLLNCFGR2 registers */
+#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVP_SHIFT 0
+#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
+#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLLNCFGR2_DIVR_SHIFT 16
+#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
+
+/* used for ALL PLLNFRACR registers */
+#define RCC_PLLNFRACR_FRACV_SHIFT 3
+#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLLNFRACR_FRACLE BIT(16)
+
+/* used for ALL PLLNCSGR registers */
+#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
+#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
+#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
+#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
+
+/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
+#define RCC_OCENR_HSION BIT(0)
+#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_HSEON BIT(8)
+#define RCC_OCENR_HSEBYP BIT(10)
+#define RCC_OCENR_HSECSSON BIT(11)
+
+/* Fields of RCC_OCRDYR register */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_HSIDIVRDY BIT(2)
+#define RCC_OCRDYR_CSIRDY BIT(4)
+#define RCC_OCRDYR_HSERDY BIT(8)
+
+/* Fields of DDRITFCR register */
+#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
+#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
+#define RCC_DDRITFCR_DDRCKMOD_SSR 0
+
+/* Fields of RCC_HSICFGR register */
+#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
+
+/* used for MCO related operations */
+#define RCC_MCOCFG_MCOON BIT(12)
+#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
+#define RCC_MCOCFG_MCODIV_SHIFT 4
+#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
+
+enum stm32mp1_parent_id {
+/*
+ * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
+ * they are used as index in osc[] as entry point
+ */
+ _HSI,
+ _HSE,
+ _CSI,
+ _LSI,
+ _LSE,
+ _I2S_CKIN,
+ _USB_PHY_48,
+ NB_OSC,
+
+/* other parent source */
+ _HSI_KER = NB_OSC,
+ _HSE_KER,
+ _HSE_KER_DIV2,
+ _CSI_KER,
+ _PLL1_P,
+ _PLL1_Q,
+ _PLL1_R,
+ _PLL2_P,
+ _PLL2_Q,
+ _PLL2_R,
+ _PLL3_P,
+ _PLL3_Q,
+ _PLL3_R,
+ _PLL4_P,
+ _PLL4_Q,
+ _PLL4_R,
+ _ACLK,
+ _PCLK1,
+ _PCLK2,
+ _PCLK3,
+ _PCLK4,
+ _PCLK5,
+ _HCLK6,
+ _HCLK2,
+ _CK_PER,
+ _CK_MPU,
+ _CK_MCU,
+ _PARENT_NB,
+ _UNKNOWN_ID = 0xff,
+};
+
+enum stm32mp1_parent_sel {
+ _I2C12_SEL,
+ _I2C35_SEL,
+ _I2C46_SEL,
+ _UART6_SEL,
+ _UART24_SEL,
+ _UART35_SEL,
+ _UART78_SEL,
+ _SDMMC12_SEL,
+ _SDMMC3_SEL,
+ _ETH_SEL,
+ _QSPI_SEL,
+ _FMC_SEL,
+ _USBPHY_SEL,
+ _USBO_SEL,
+ _STGEN_SEL,
+ _PARENT_SEL_NB,
+ _UNKNOWN_SEL = 0xff,
+};
+
+enum stm32mp1_pll_id {
+ _PLL1,
+ _PLL2,
+ _PLL3,
+ _PLL4,
+ _PLL_NB
+};
+
+enum stm32mp1_div_id {
+ _DIV_P,
+ _DIV_Q,
+ _DIV_R,
+ _DIV_NB,
+};
+
+enum stm32mp1_clksrc_id {
+ CLKSRC_MPU,
+ CLKSRC_AXI,
+ CLKSRC_MCU,
+ CLKSRC_PLL12,
+ CLKSRC_PLL3,
+ CLKSRC_PLL4,
+ CLKSRC_RTC,
+ CLKSRC_MCO1,
+ CLKSRC_MCO2,
+ CLKSRC_NB
+};
+
+enum stm32mp1_clkdiv_id {
+ CLKDIV_MPU,
+ CLKDIV_AXI,
+ CLKDIV_MCU,
+ CLKDIV_APB1,
+ CLKDIV_APB2,
+ CLKDIV_APB3,
+ CLKDIV_APB4,
+ CLKDIV_APB5,
+ CLKDIV_RTC,
+ CLKDIV_MCO1,
+ CLKDIV_MCO2,
+ CLKDIV_NB
+};
+
+enum stm32mp1_pllcfg {
+ PLLCFG_M,
+ PLLCFG_N,
+ PLLCFG_P,
+ PLLCFG_Q,
+ PLLCFG_R,
+ PLLCFG_O,
+ PLLCFG_NB
+};
+
+enum stm32mp1_pllcsg {
+ PLLCSG_MOD_PER,
+ PLLCSG_INC_STEP,
+ PLLCSG_SSCG_MODE,
+ PLLCSG_NB
+};
+
+enum stm32mp1_plltype {
+ PLL_800,
+ PLL_1600,
+ PLL_TYPE_NB
+};
+
+struct stm32mp1_pll {
+ u8 refclk_min;
+ u8 refclk_max;
+ u8 divn_max;
+};
+
+struct stm32mp1_clk_gate {
+ u16 offset;
+ u8 bit;
+ u8 index;
+ u8 set_clr;
+ u8 sel;
+ u8 fixed;
+};
+
+struct stm32mp1_clk_sel {
+ u16 offset;
+ u8 src;
+ u8 msk;
+ u8 nb_parent;
+ const u8 *parent;
+};
+
+#define REFCLK_SIZE 4
+struct stm32mp1_clk_pll {
+ enum stm32mp1_plltype plltype;
+ u16 rckxselr;
+ u16 pllxcfgr1;
+ u16 pllxcfgr2;
+ u16 pllxfracr;
+ u16 pllxcr;
+ u16 pllxcsgr;
+ u8 refclk[REFCLK_SIZE];
+};
+
+struct stm32mp1_clk_data {
+ const struct stm32mp1_clk_gate *gate;
+ const struct stm32mp1_clk_sel *sel;
+ const struct stm32mp1_clk_pll *pll;
+ const int nb_gate;
+};
+
+struct stm32mp1_clk_priv {
+ fdt_addr_t base;
+ const struct stm32mp1_clk_data *data;
+ ulong osc[NB_OSC];
+ struct udevice *osc_dev[NB_OSC];
+};
+
+#define STM32MP1_CLK(off, b, idx, s) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 0, \
+ .sel = (s), \
+ .fixed = _UNKNOWN_ID, \
+ }
+
+#define STM32MP1_CLK_F(off, b, idx, f) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 0, \
+ .sel = _UNKNOWN_SEL, \
+ .fixed = (f), \
+ }
+
+#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 1, \
+ .sel = (s), \
+ .fixed = _UNKNOWN_ID, \
+ }
+
+#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 1, \
+ .sel = _UNKNOWN_SEL, \
+ .fixed = (f), \
+ }
+
+#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
+ [(idx)] = { \
+ .offset = (off), \
+ .src = (s), \
+ .msk = (m), \
+ .parent = (p), \
+ .nb_parent = ARRAY_SIZE((p)) \
+ }
+
+#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
+ p1, p2, p3, p4) \
+ [(idx)] = { \
+ .plltype = (type), \
+ .rckxselr = (off1), \
+ .pllxcfgr1 = (off2), \
+ .pllxcfgr2 = (off3), \
+ .pllxfracr = (off4), \
+ .pllxcr = (off5), \
+ .pllxcsgr = (off6), \
+ .refclk[0] = (p1), \
+ .refclk[1] = (p2), \
+ .refclk[2] = (p3), \
+ .refclk[3] = (p4), \
+ }
+
+static const u8 stm32mp1_clks[][2] = {
+ {CK_PER, _CK_PER},
+ {CK_MPU, _CK_MPU},
+ {CK_AXI, _ACLK},
+ {CK_MCU, _CK_MCU},
+ {CK_HSE, _HSE},
+ {CK_CSI, _CSI},
+ {CK_LSI, _LSI},
+ {CK_LSE, _LSE},
+ {CK_HSI, _HSI},
+ {CK_HSE_DIV2, _HSE_KER_DIV2},
+};
+
+static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
+ STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
+ STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
+ STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
+
+ STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
+};
+
+static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
+static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
+static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
+static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
+static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
+static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
+static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
+static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
+static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
+static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
+static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
+
+static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
+ STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
+ STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
+ STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
+ STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
+ STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
+ uart24_parents),
+ STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
+ uart35_parents),
+ STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
+ uart78_parents),
+ STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
+ sdmmc12_parents),
+ STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
+ sdmmc3_parents),
+ STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
+ STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
+ STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
+ STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
+ STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
+ STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
+};
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+/* define characteristic of PLL according type */
+#define DIVN_MIN 24
+static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
+ [PLL_800] = {
+ .refclk_min = 4,
+ .refclk_max = 16,
+ .divn_max = 99,
+ },
+ [PLL_1600] = {
+ .refclk_min = 8,
+ .refclk_max = 16,
+ .divn_max = 199,
+ },
+};
+#endif /* STM32MP1_CLOCK_TREE_INIT */
+
+static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
+ STM32MP1_CLK_PLL(_PLL1, PLL_1600,
+ RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
+ RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
+ _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
+ STM32MP1_CLK_PLL(_PLL2, PLL_1600,
+ RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
+ RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
+ _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
+ STM32MP1_CLK_PLL(_PLL3, PLL_800,
+ RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
+ RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
+ _HSI, _HSE, _CSI, _UNKNOWN_ID),
+ STM32MP1_CLK_PLL(_PLL4, PLL_800,
+ RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
+ RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
+ _HSI, _HSE, _CSI, _I2S_CKIN),
+};
+
+/* Prescaler table lookups for clock computation */
+/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
+static const u8 stm32mp1_mcu_div[16] = {
+ 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
+};
+
+/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
+#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
+#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
+static const u8 stm32mp1_mpu_apbx_div[8] = {
+ 0, 1, 2, 3, 4, 4, 4, 4
+};
+
+/* div = /1 /2 /3 /4 */
+static const u8 stm32mp1_axi_div[8] = {
+ 1, 2, 3, 4, 4, 4, 4, 4
+};
+
+#ifdef DEBUG
+static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
+ [_HSI] = "HSI",
+ [_HSE] = "HSE",
+ [_CSI] = "CSI",
+ [_LSI] = "LSI",
+ [_LSE] = "LSE",
+ [_I2S_CKIN] = "I2S_CKIN",
+ [_HSI_KER] = "HSI_KER",
+ [_HSE_KER] = "HSE_KER",
+ [_HSE_KER_DIV2] = "HSE_KER_DIV2",
+ [_CSI_KER] = "CSI_KER",
+ [_PLL1_P] = "PLL1_P",
+ [_PLL1_Q] = "PLL1_Q",
+ [_PLL1_R] = "PLL1_R",
+ [_PLL2_P] = "PLL2_P",
+ [_PLL2_Q] = "PLL2_Q",
+ [_PLL2_R] = "PLL2_R",
+ [_PLL3_P] = "PLL3_P",
+ [_PLL3_Q] = "PLL3_Q",
+ [_PLL3_R] = "PLL3_R",
+ [_PLL4_P] = "PLL4_P",
+ [_PLL4_Q] = "PLL4_Q",
+ [_PLL4_R] = "PLL4_R",
+ [_ACLK] = "ACLK",
+ [_PCLK1] = "PCLK1",
+ [_PCLK2] = "PCLK2",
+ [_PCLK3] = "PCLK3",
+ [_PCLK4] = "PCLK4",
+ [_PCLK5] = "PCLK5",
+ [_HCLK6] = "KCLK6",
+ [_HCLK2] = "HCLK2",
+ [_CK_PER] = "CK_PER",
+ [_CK_MPU] = "CK_MPU",
+ [_CK_MCU] = "CK_MCU",
+ [_USB_PHY_48] = "USB_PHY_48"
+};
+
+static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
+ [_I2C12_SEL] = "I2C12",
+ [_I2C35_SEL] = "I2C35",
+ [_I2C46_SEL] = "I2C46",
+ [_UART6_SEL] = "UART6",
+ [_UART24_SEL] = "UART24",
+ [_UART35_SEL] = "UART35",
+ [_UART78_SEL] = "UART78",
+ [_SDMMC12_SEL] = "SDMMC12",
+ [_SDMMC3_SEL] = "SDMMC3",
+ [_ETH_SEL] = "ETH",
+ [_QSPI_SEL] = "QSPI",
+ [_FMC_SEL] = "FMC",
+ [_USBPHY_SEL] = "USBPHY",
+ [_USBO_SEL] = "USBO",
+ [_STGEN_SEL] = "STGEN"
+};
+#endif
+
+static const struct stm32mp1_clk_data stm32mp1_data = {
+ .gate = stm32mp1_clk_gate,
+ .sel = stm32mp1_clk_sel,
+ .pll = stm32mp1_clk_pll,
+ .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
+};
+
+static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
+{
+ if (idx >= NB_OSC) {
+ debug("%s: clk id %d not found\n", __func__, idx);
+ return 0;
+ }
+
+ debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
+ (u32)priv->osc[idx], priv->osc[idx] / 1000);
+
+ return priv->osc[idx];
+}
+
+static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
+{
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+ int i, nb_clks = priv->data->nb_gate;
+
+ for (i = 0; i < nb_clks; i++) {
+ if (gate[i].index == id)
+ break;
+ }
+
+ if (i == nb_clks) {
+ printf("%s: clk id %d not found\n", __func__, (u32)id);
+ return -EINVAL;
+ }
+
+ return i;
+}
+
+static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
+ int i)
+{
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+
+ if (gate[i].sel > _PARENT_SEL_NB) {
+ printf("%s: parents for clk id %d not found\n",
+ __func__, i);
+ return -EINVAL;
+ }
+
+ return gate[i].sel;
+}
+
+static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
+ int i)
+{
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+
+ if (gate[i].fixed == _UNKNOWN_ID)
+ return -ENOENT;
+
+ return gate[i].fixed;
+}
+
+static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
+ unsigned long id)
+{
+ const struct stm32mp1_clk_sel *sel = priv->data->sel;
+ int i;
+ int s, p;
+
+ for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
+ if (stm32mp1_clks[i][0] == id)
+ return stm32mp1_clks[i][1];
+
+ i = stm32mp1_clk_get_id(priv, id);
+ if (i < 0)
+ return i;
+
+ p = stm32mp1_clk_get_fixed_parent(priv, i);
+ if (p >= 0 && p < _PARENT_NB)
+ return p;
+
+ s = stm32mp1_clk_get_sel(priv, i);
+ if (s < 0)
+ return s;
+
+ p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
+
+ if (p < sel[s].nb_parent) {
+#ifdef DEBUG
+ debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
+ stm32mp1_clk_parent_name[sel[s].parent[p]],
+ stm32mp1_clk_parent_sel_name[s],
+ (u32)id);
+#endif
+ return sel[s].parent[p];
+ }
+
+ pr_err("%s: no parents defined for clk id %d\n",
+ __func__, (u32)id);
+
+ return -EINVAL;
+}
+
+static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
+ int pll_id, int div_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divm, divn, divy, src;
+ ulong refclk, dfout;
+ u32 selr, cfgr1, cfgr2, fracr;
+ const u8 shift[_DIV_NB] = {
+ [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
+ [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
+ [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
+
+ debug("%s(%d, %d)\n", __func__, pll_id, div_id);
+ if (div_id > _DIV_NB)
+ return 0;
+
+ selr = readl(priv->base + pll[pll_id].rckxselr);
+ cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
+ cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
+ fracr = readl(priv->base + pll[pll_id].pllxfracr);
+
+ debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
+ pll_id, selr, cfgr1, cfgr2, fracr);
+
+ divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
+ divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
+ divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
+
+ debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
+
+ src = selr & RCC_SELR_SRC_MASK;
+ refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+
+ debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
+
+ /*
+ * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
+ * So same final result than PLL2 et 4
+ * with FRACV :
+ * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
+ * / (DIVM + 1) * (DIVy + 1)
+ * without FRACV
+ * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
+ */
+ if (fracr & RCC_PLLNFRACR_FRACLE) {
+ u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
+ >> RCC_PLLNFRACR_FRACV_SHIFT;
+ dfout = (ulong)lldiv((unsigned long long)refclk *
+ (((divn + 1) << 13) + fracv),
+ ((unsigned long long)(divm + 1) *
+ (divy + 1)) << 13);
+ } else {
+ dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
+ }
+ debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
+
+ return dfout;
+}
+
+static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
+{
+ u32 reg;
+ ulong clock = 0;
+
+ switch (p) {
+ case _CK_MPU:
+ /* MPU sub system */
+ reg = readl(priv->base + RCC_MPCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_MPCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_MPCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_MPCKSELR_PLL:
+ case RCC_MPCKSELR_PLL_MPUDIV:
+ clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
+ if (p == RCC_MPCKSELR_PLL_MPUDIV) {
+ reg = readl(priv->base + RCC_MPCKDIVR);
+ clock /= stm32mp1_mpu_div[reg &
+ RCC_MPUDIV_MASK];
+ }
+ break;
+ }
+ break;
+ /* AXI sub system */
+ case _ACLK:
+ case _HCLK2:
+ case _HCLK6:
+ case _PCLK4:
+ case _PCLK5:
+ reg = readl(priv->base + RCC_ASSCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_ASSCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_ASSCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_ASSCKSELR_PLL:
+ clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
+ break;
+ }
+
+ /* System clock divider */
+ reg = readl(priv->base + RCC_AXIDIVR);
+ clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
+
+ switch (p) {
+ case _PCLK4:
+ reg = readl(priv->base + RCC_APB4DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _PCLK5:
+ reg = readl(priv->base + RCC_APB5DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ default:
+ break;
+ }
+ break;
+ /* MCU sub system */
+ case _CK_MCU:
+ case _PCLK1:
+ case _PCLK2:
+ case _PCLK3:
+ reg = readl(priv->base + RCC_MSSCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_MSSCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_MSSCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_MSSCKSELR_CSI:
+ clock = stm32mp1_clk_get_fixed(priv, _CSI);
+ break;
+ case RCC_MSSCKSELR_PLL:
+ clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
+ break;
+ }
+
+ /* MCU clock divider */
+ reg = readl(priv->base + RCC_MCUDIVR);
+ clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
+
+ switch (p) {
+ case _PCLK1:
+ reg = readl(priv->base + RCC_APB1DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _PCLK2:
+ reg = readl(priv->base + RCC_APB2DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _PCLK3:
+ reg = readl(priv->base + RCC_APB3DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _CK_MCU:
+ default:
+ break;
+ }
+ break;
+ case _CK_PER:
+ reg = readl(priv->base + RCC_CPERCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_CPERCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_CPERCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_CPERCKSELR_CSI:
+ clock = stm32mp1_clk_get_fixed(priv, _CSI);
+ break;
+ }
+ break;
+ case _HSI:
+ case _HSI_KER:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case _CSI:
+ case _CSI_KER:
+ clock = stm32mp1_clk_get_fixed(priv, _CSI);
+ break;
+ case _HSE:
+ case _HSE_KER:
+ case _HSE_KER_DIV2:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ if (p == _HSE_KER_DIV2)
+ clock >>= 1;
+ break;
+ case _LSI:
+ clock = stm32mp1_clk_get_fixed(priv, _LSI);
+ break;
+ case _LSE:
+ clock = stm32mp1_clk_get_fixed(priv, _LSE);
+ break;
+ /* PLL */
+ case _PLL1_P:
+ case _PLL1_Q:
+ case _PLL1_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
+ break;
+ case _PLL2_P:
+ case _PLL2_Q:
+ case _PLL2_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
+ break;
+ case _PLL3_P:
+ case _PLL3_Q:
+ case _PLL3_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
+ break;
+ case _PLL4_P:
+ case _PLL4_Q:
+ case _PLL4_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
+ break;
+ /* other */
+ case _USB_PHY_48:
+ clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
+ break;
+
+ default:
+ break;
+ }
+
+ debug("%s(%d) clock = %lx : %ld kHz\n",
+ __func__, p, clock, clock / 1000);
+
+ return clock;
+}
+
+static int stm32mp1_clk_enable(struct clk *clk)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+ int i = stm32mp1_clk_get_id(priv, clk->id);
+
+ if (i < 0)
+ return i;
+
+ if (gate[i].set_clr)
+ writel(BIT(gate[i].bit), priv->base + gate[i].offset);
+ else
+ setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
+
+ debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
+
+ return 0;
+}
+
+static int stm32mp1_clk_disable(struct clk *clk)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+ int i = stm32mp1_clk_get_id(priv, clk->id);
+
+ if (i < 0)
+ return i;
+
+ if (gate[i].set_clr)
+ writel(BIT(gate[i].bit),
+ priv->base + gate[i].offset
+ + RCC_MP_ENCLRR_OFFSET);
+ else
+ clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
+
+ debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
+
+ return 0;
+}
+
+static ulong stm32mp1_clk_get_rate(struct clk *clk)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ int p = stm32mp1_clk_get_parent(priv, clk->id);
+ ulong rate;
+
+ if (p < 0)
+ return 0;
+
+ rate = stm32mp1_clk_get(priv, p);
+
+#ifdef DEBUG
+ debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
+ __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
+#endif
+ return rate;
+}
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
+ u32 mask_on)
+{
+ u32 address = rcc + offset;
+
+ if (enable)
+ setbits_le32(address, mask_on);
+ else
+ clrbits_le32(address, mask_on);
+}
+
+static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
+{
+ if (enable)
+ setbits_le32(rcc + RCC_OCENSETR, mask_on);
+ else
+ setbits_le32(rcc + RCC_OCENCLRR, mask_on);
+}
+
+static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
+ u32 mask_rdy)
+{
+ u32 mask_test = 0;
+ u32 address = rcc + offset;
+ u32 val;
+ int ret;
+
+ if (enable)
+ mask_test = mask_rdy;
+
+ ret = readl_poll_timeout(address, val,
+ (val & mask_rdy) == mask_test,
+ TIMEOUT_1S);
+
+ if (ret)
+ pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
+ mask_rdy, address, enable, readl(address));
+
+ return ret;
+}
+
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+{
+ u32 value;
+
+ if (bypass)
+ setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
+
+ /*
+ * warning: not recommended to switch directly from "high drive"
+ * to "medium low drive", and vice-versa.
+ */
+ value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
+ >> RCC_BDCR_LSEDRV_SHIFT;
+
+ while (value != lsedrv) {
+ if (value > lsedrv)
+ value--;
+ else
+ value++;
+
+ clrsetbits_le32(rcc + RCC_BDCR,
+ RCC_BDCR_LSEDRV_MASK,
+ value << RCC_BDCR_LSEDRV_SHIFT);
+ }
+
+ stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
+}
+
+static void stm32mp1_lse_wait(fdt_addr_t rcc)
+{
+ stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
+}
+
+static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
+{
+ stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
+ stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
+}
+
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+{
+ if (bypass)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
+
+ stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
+ stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
+
+ if (css)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
+}
+
+static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
+{
+ stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
+ stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
+}
+
+static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
+{
+ stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
+ stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
+}
+
+static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
+{
+ u32 address = rcc + RCC_OCRDYR;
+ u32 val;
+ int ret;
+
+ clrsetbits_le32(rcc + RCC_HSICFGR,
+ RCC_HSICFGR_HSIDIV_MASK,
+ RCC_HSICFGR_HSIDIV_MASK & hsidiv);
+
+ ret = readl_poll_timeout(address, val,
+ val & RCC_OCRDYR_HSIDIVRDY,
+ TIMEOUT_200MS);
+ if (ret)
+ pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
+ address, readl(address));
+
+ return ret;
+}
+
+static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
+{
+ u8 hsidiv;
+ u32 hsidivfreq = MAX_HSI_HZ;
+
+ for (hsidiv = 0; hsidiv < 4; hsidiv++,
+ hsidivfreq = hsidivfreq / 2)
+ if (hsidivfreq == hsifreq)
+ break;
+
+ if (hsidiv == 4) {
+ pr_err("clk-hsi frequency invalid");
+ return -1;
+ }
+
+ if (hsidiv > 0)
+ return stm32mp1_set_hsidiv(rcc, hsidiv);
+
+ return 0;
+}
+
+static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+
+ writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
+}
+
+static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+ u32 val;
+ int ret;
+
+ ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
+ TIMEOUT_200MS);
+
+ if (ret) {
+ pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
+ pll_id, pllxcr, readl(pllxcr));
+ return ret;
+ }
+
+ /* start the requested output */
+ setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
+
+ return 0;
+}
+
+static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+ u32 val;
+
+ /* stop all output */
+ clrbits_le32(pllxcr,
+ RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
+
+ /* stop PLL */
+ clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
+
+ /* wait PLL stopped */
+ return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
+ TIMEOUT_200MS);
+}
+
+static void pll_config_output(struct stm32mp1_clk_priv *priv,
+ int pll_id, u32 *pllcfg)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ fdt_addr_t rcc = priv->base;
+ u32 value;
+
+ value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
+ & RCC_PLLNCFGR2_DIVP_MASK;
+ value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
+ & RCC_PLLNCFGR2_DIVQ_MASK;
+ value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
+ & RCC_PLLNCFGR2_DIVR_MASK;
+ writel(value, rcc + pll[pll_id].pllxcfgr2);
+}
+
+static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
+ u32 *pllcfg, u32 fracv)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ fdt_addr_t rcc = priv->base;
+ enum stm32mp1_plltype type = pll[pll_id].plltype;
+ int src;
+ ulong refclk;
+ u8 ifrge = 0;
+ u32 value;
+
+ src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
+
+ refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
+ (pllcfg[PLLCFG_M] + 1);
+
+ if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
+ refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
+ debug("invalid refclk = %x\n", (u32)refclk);
+ return -EINVAL;
+ }
+ if (type == PLL_800 && refclk >= 8000000)
+ ifrge = 1;
+
+ value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
+ & RCC_PLLNCFGR1_DIVN_MASK;
+ value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
+ & RCC_PLLNCFGR1_DIVM_MASK;
+ value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
+ & RCC_PLLNCFGR1_IFRGE_MASK;
+ writel(value, rcc + pll[pll_id].pllxcfgr1);
+
+ /* fractional configuration: load sigma-delta modulator (SDM) */
+
+ /* Write into FRACV the new fractional value , and FRACLE to 0 */
+ writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
+ rcc + pll[pll_id].pllxfracr);
+
+ /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
+ setbits_le32(rcc + pll[pll_id].pllxfracr,
+ RCC_PLLNFRACR_FRACLE);
+
+ pll_config_output(priv, pll_id, pllcfg);
+
+ return 0;
+}
+
+static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcsg;
+
+ pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
+ RCC_PLLNCSGR_MOD_PER_MASK) |
+ ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
+ RCC_PLLNCSGR_INC_STEP_MASK) |
+ ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
+ RCC_PLLNCSGR_SSCG_MODE_MASK);
+
+ writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
+}
+
+static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
+{
+ u32 address = priv->base + (clksrc >> 4);
+ u32 val;
+ int ret;
+
+ clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
+ ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
+ TIMEOUT_200MS);
+ if (ret)
+ pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
+ clksrc, address, readl(address));
+
+ return ret;
+}
+
+static void stgen_config(struct stm32mp1_clk_priv *priv)
+{
+ int p;
+ u32 stgenc, cntfid0;
+ ulong rate;
+
+ stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
+
+ cntfid0 = readl(stgenc + STGENC_CNTFID0);
+ p = stm32mp1_clk_get_parent(priv, STGEN_K);
+ rate = stm32mp1_clk_get(priv, p);
+
+ if (cntfid0 != rate) {
+ pr_debug("System Generic Counter (STGEN) update\n");
+ clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
+ writel(0x0, stgenc + STGENC_CNTCVL);
+ writel(0x0, stgenc + STGENC_CNTCVU);
+ writel(rate, stgenc + STGENC_CNTFID0);
+ setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
+
+ __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
+
+ /* need to update gd->arch.timer_rate_hz with new frequency */
+ timer_init();
+ pr_debug("gd->arch.timer_rate_hz = %x\n",
+ (u32)gd->arch.timer_rate_hz);
+ pr_debug("Tick = %x\n", (u32)(get_ticks()));
+ }
+}
+
+static int set_clkdiv(unsigned int clkdiv, u32 address)
+{
+ u32 val;
+ int ret;
+
+ clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
+ ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
+ TIMEOUT_200MS);
+ if (ret)
+ pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
+ clkdiv, address, readl(address));
+
+ return ret;
+}
+
+static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
+ u32 clksrc, u32 clkdiv)
+{
+ u32 address = priv->base + (clksrc >> 4);
+
+ /*
+ * binding clksrc : bit15-4 offset
+ * bit3: disable
+ * bit2-0: MCOSEL[2:0]
+ */
+ if (clksrc & 0x8) {
+ clrbits_le32(address, RCC_MCOCFG_MCOON);
+ } else {
+ clrsetbits_le32(address,
+ RCC_MCOCFG_MCOSRC_MASK,
+ clksrc & RCC_MCOCFG_MCOSRC_MASK);
+ clrsetbits_le32(address,
+ RCC_MCOCFG_MCODIV_MASK,
+ clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
+ setbits_le32(address, RCC_MCOCFG_MCOON);
+ }
+}
+
+static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
+ unsigned int clksrc,
+ int lse_css)
+{
+ u32 address = priv->base + RCC_BDCR;
+
+ if (readl(address) & RCC_BDCR_RTCCKEN)
+ goto skip_rtc;
+
+ if (clksrc == CLK_RTC_DISABLED)
+ goto skip_rtc;
+
+ clrsetbits_le32(address,
+ RCC_BDCR_RTCSRC_MASK,
+ clksrc << RCC_BDCR_RTCSRC_SHIFT);
+
+ setbits_le32(address, RCC_BDCR_RTCCKEN);
+
+skip_rtc:
+ if (lse_css)
+ setbits_le32(address, RCC_BDCR_LSECSSON);
+}
+
+static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
+{
+ u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
+ u32 value = pkcs & 0xF;
+ u32 mask = 0xF;
+
+ if (pkcs & BIT(31)) {
+ mask <<= 4;
+ value <<= 4;
+ }
+ clrsetbits_le32(address, mask, value);
+}
+
+static int stm32mp1_clktree(struct udevice *dev)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ fdt_addr_t rcc = priv->base;
+ unsigned int clksrc[CLKSRC_NB];
+ unsigned int clkdiv[CLKDIV_NB];
+ unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
+ ofnode plloff[_PLL_NB];
+ int ret;
+ int i, len;
+ int lse_css = 0;
+ const u32 *pkcs_cell;
+
+ /* check mandatory field */
+ ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
+ if (ret < 0) {
+ debug("field st,clksrc invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
+ if (ret < 0) {
+ debug("field st,clkdiv invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ /* check mandatory field in each pll */
+ for (i = 0; i < _PLL_NB; i++) {
+ char name[12];
+
+ sprintf(name, "st,pll@%d", i);
+ plloff[i] = dev_read_subnode(dev, name);
+ if (!ofnode_valid(plloff[i]))
+ continue;
+ ret = ofnode_read_u32_array(plloff[i], "cfg",
+ pllcfg[i], PLLCFG_NB);
+ if (ret < 0) {
+ debug("field cfg invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+ }
+
+ debug("configuration MCO\n");
+ stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
+ stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
+
+ debug("switch ON osillator\n");
+ /*
+ * switch ON oscillator found in device-tree,
+ * HSI already ON after bootrom
+ */
+ if (priv->osc[_LSI])
+ stm32mp1_lsi_set(rcc, 1);
+
+ if (priv->osc[_LSE]) {
+ int bypass;
+ int lsedrv;
+ struct udevice *dev = priv->osc_dev[_LSE];
+
+ bypass = dev_read_bool(dev, "st,bypass");
+ lse_css = dev_read_bool(dev, "st,css");
+ lsedrv = dev_read_u32_default(dev, "st,drive",
+ LSEDRV_MEDIUM_HIGH);
+
+ stm32mp1_lse_enable(rcc, bypass, lsedrv);
+ }
+
+ if (priv->osc[_HSE]) {
+ int bypass, css;
+ struct udevice *dev = priv->osc_dev[_HSE];
+
+ bypass = dev_read_bool(dev, "st,bypass");
+ css = dev_read_bool(dev, "st,css");
+
+ stm32mp1_hse_enable(rcc, bypass, css);
+ }
+ /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
+ * => switch on CSI even if node is not present in device tree
+ */
+ stm32mp1_csi_set(rcc, 1);
+
+ /* come back to HSI */
+ debug("come back to HSI\n");
+ set_clksrc(priv, CLK_MPU_HSI);
+ set_clksrc(priv, CLK_AXI_HSI);
+ set_clksrc(priv, CLK_MCU_HSI);
+
+ debug("pll stop\n");
+ for (i = 0; i < _PLL_NB; i++)
+ pll_stop(priv, i);
+
+ /* configure HSIDIV */
+ debug("configure HSIDIV\n");
+ if (priv->osc[_HSI]) {
+ stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
+ stgen_config(priv);
+ }
+
+ /* select DIV */
+ debug("select DIV\n");
+ /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
+ writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
+ set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
+ set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
+
+ /* no ready bit for RTC */
+ writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
+
+ /* configure PLLs source */
+ debug("configure PLLs source\n");
+ set_clksrc(priv, clksrc[CLKSRC_PLL12]);
+ set_clksrc(priv, clksrc[CLKSRC_PLL3]);
+ set_clksrc(priv, clksrc[CLKSRC_PLL4]);
+
+ /* configure and start PLLs */
+ debug("configure PLLs\n");
+ for (i = 0; i < _PLL_NB; i++) {
+ u32 fracv;
+ u32 csg[PLLCSG_NB];
+
+ debug("configure PLL %d @ %d\n", i,
+ ofnode_to_offset(plloff[i]));
+ if (!ofnode_valid(plloff[i]))
+ continue;
+
+ fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
+ pll_config(priv, i, pllcfg[i], fracv);
+ ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
+ if (!ret) {
+ pll_csg(priv, i, csg);
+ } else if (ret != -FDT_ERR_NOTFOUND) {
+ debug("invalid csg node for pll@%d res=%d\n", i, ret);
+ return ret;
+ }
+ pll_start(priv, i);
+ }
+
+ /* wait and start PLLs ouptut when ready */
+ for (i = 0; i < _PLL_NB; i++) {
+ if (!ofnode_valid(plloff[i]))
+ continue;
+ debug("output PLL %d\n", i);
+ pll_output(priv, i, pllcfg[i][PLLCFG_O]);
+ }
+
+ /* wait LSE ready before to use it */
+ if (priv->osc[_LSE])
+ stm32mp1_lse_wait(rcc);
+
+ /* configure with expected clock source */
+ debug("CLKSRC\n");
+ set_clksrc(priv, clksrc[CLKSRC_MPU]);
+ set_clksrc(priv, clksrc[CLKSRC_AXI]);
+ set_clksrc(priv, clksrc[CLKSRC_MCU]);
+ set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
+
+ /* configure PKCK */
+ debug("PKCK\n");
+ pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
+ if (pkcs_cell) {
+ bool ckper_disabled = false;
+
+ for (i = 0; i < len / sizeof(u32); i++) {
+ u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
+
+ if (pkcs == CLK_CKPER_DISABLED) {
+ ckper_disabled = true;
+ continue;
+ }
+ pkcs_config(priv, pkcs);
+ }
+ /* CKPER is source for some peripheral clock
+ * (FMC-NAND / QPSI-NOR) and switching source is allowed
+ * only if previous clock is still ON
+ * => deactivated CKPER only after switching clock
+ */
+ if (ckper_disabled)
+ pkcs_config(priv, CLK_CKPER_DISABLED);
+ }
+
+ /* STGEN clock source can change with CLK_STGEN_XXX */
+ stgen_config(priv);
+
+ debug("oscillator off\n");
+ /* switch OFF HSI if not found in device-tree */
+ if (!priv->osc[_HSI])
+ stm32mp1_hsi_set(rcc, 0);
+
+ /* Software Self-Refresh mode (SSR) during DDR initilialization */
+ clrsetbits_le32(priv->base + RCC_DDRITFCR,
+ RCC_DDRITFCR_DDRCKMOD_MASK,
+ RCC_DDRITFCR_DDRCKMOD_SSR <<
+ RCC_DDRITFCR_DDRCKMOD_SHIFT);
+
+ return 0;
+}
+#endif /* STM32MP1_CLOCK_TREE_INIT */
+
+static void stm32mp1_osc_clk_init(const char *name,
+ struct stm32mp1_clk_priv *priv,
+ int index)
+{
+ struct clk clk;
+ struct udevice *dev = NULL;
+
+ priv->osc[index] = 0;
+ clk.id = 0;
+ if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
+ if (clk_request(dev, &clk))
+ pr_err("%s request", name);
+ else
+ priv->osc[index] = clk_get_rate(&clk);
+ }
+ priv->osc_dev[index] = dev;
+}
+
+static void stm32mp1_osc_init(struct udevice *dev)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ int i;
+ const char *name[NB_OSC] = {
+ [_LSI] = "clk-lsi",
+ [_LSE] = "clk-lse",
+ [_HSI] = "clk-hsi",
+ [_HSE] = "clk-hse",
+ [_CSI] = "clk-csi",
+ [_I2S_CKIN] = "i2s_ckin",
+ [_USB_PHY_48] = "ck_usbo_48m"};
+
+ for (i = 0; i < NB_OSC; i++) {
+ stm32mp1_osc_clk_init(name[i], priv, i);
+ debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
+ }
+}
+
+static int stm32mp1_clk_probe(struct udevice *dev)
+{
+ int result = 0;
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev->parent);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->data = (void *)&stm32mp1_data;
+
+ if (!priv->data->gate || !priv->data->sel ||
+ !priv->data->pll)
+ return -EINVAL;
+
+ stm32mp1_osc_init(dev);
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+ /* clock tree init is done only one time, before relocation */
+ if (!(gd->flags & GD_FLG_RELOC))
+ result = stm32mp1_clktree(dev);
+#endif
+
+ return result;
+}
+
+static const struct clk_ops stm32mp1_clk_ops = {
+ .enable = stm32mp1_clk_enable,
+ .disable = stm32mp1_clk_disable,
+ .get_rate = stm32mp1_clk_get_rate,
+};
+
+static const struct udevice_id stm32mp1_clk_ids[] = {
+ { .compatible = "st,stm32mp1-rcc-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(stm32mp1_clock) = {
+ .name = "stm32mp1_clk",
+ .id = UCLASS_CLK,
+ .of_match = stm32mp1_clk_ids,
+ .ops = &stm32mp1_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
+ .probe = stm32mp1_clk_probe,
+};
diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index 50f2a65..3845e07 100644
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -394,7 +394,7 @@
return zynq_clk_get_peripheral_rate(priv, id, two_divs);
case dma_clk:
return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
- case usb0_aper_clk ... smc_aper_clk:
+ case usb0_aper_clk ... swdt_clk:
return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
default:
return -ENXIO;
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index bcc6290..d0d6c89 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -226,6 +226,18 @@
return CRL_APB_CAN0_REF_CTRL;
case can1_ref:
return CRL_APB_CAN1_REF_CTRL;
+ case pl0:
+ return CRL_APB_PL0_REF_CTRL;
+ case pl1:
+ return CRL_APB_PL1_REF_CTRL;
+ case pl2:
+ return CRL_APB_PL2_REF_CTRL;
+ case pl3:
+ return CRL_APB_PL3_REF_CTRL;
+ case wdt:
+ return CRF_APB_TOPSW_LSBUS_CTRL;
+ case iopll_to_fpd:
+ return CRL_APB_IOPLL_TO_FPD_CTRL;
default:
debug("Invalid clk id%d\n", id);
}
@@ -278,6 +290,22 @@
}
}
+static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
+{
+ u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
+ CLK_CTRL_SRCSEL_SHIFT;
+
+ switch (srcsel) {
+ case 2:
+ return iopll_to_fpd;
+ case 3:
+ return dpll;
+ case 0 ... 1:
+ default:
+ return apll;
+ }
+}
+
static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
struct zynqmp_clk_priv *priv,
bool is_pre_src)
@@ -420,6 +448,49 @@
DIV_ROUND_CLOSEST(pllrate, div0), div1);
}
+static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
+ enum zynqmp_clk id, bool two_divs)
+{
+ enum zynqmp_clk pll;
+ u32 clk_ctrl, div0;
+ u32 div1 = 1;
+ int ret;
+ ulong pllrate;
+
+ ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
+ if (ret) {
+ printf("%d %s mio read fail\n", __LINE__, __func__);
+ return -EIO;
+ }
+
+ div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ if (!div0)
+ div0 = 1;
+
+ pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
+ if (two_divs) {
+ ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
+ if (ret) {
+ printf("%d %s mio read fail\n", __LINE__, __func__);
+ return -EIO;
+ }
+ div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ if (!div1)
+ div1 = 1;
+ }
+
+ if (pll == iopll_to_fpd)
+ pll = iopll;
+
+ pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+ if (IS_ERR_VALUE(pllrate))
+ return pllrate;
+
+ return
+ DIV_ROUND_CLOSEST(
+ DIV_ROUND_CLOSEST(pllrate, div0), div1);
+}
+
static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
ulong pll_rate,
u32 *div0, u32 *div1)
@@ -510,8 +581,12 @@
return zynqmp_clk_get_ddr_rate(priv);
case gem0_ref ... gem3_ref:
case qspi_ref ... can1_ref:
+ case pl0 ... pl3:
two_divs = true;
return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
+ case wdt:
+ two_divs = true;
+ return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
default:
return -ENXIO;
}
@@ -627,6 +702,7 @@
};
static const struct udevice_id zynqmp_clk_ids[] = {
+ { .compatible = "xlnx,zynqmp-clk" },
{ .compatible = "xlnx,zynqmp-clkc" },
{ }
};
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 33ab9ad..360c02c 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -40,7 +40,7 @@
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7790_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -90,7 +90,7 @@
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
-static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7790_mod_clks[] = {
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
@@ -209,10 +209,6 @@
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
-static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
- MOD_CLK_ID(408), /* INTC-SYS (GIC) */
-};
-
/*
* CPG Clock Data
*/
@@ -235,7 +231,7 @@
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 510a00a..560222b 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -321,7 +321,7 @@
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3036_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
rkclk_init(priv->cru);
return 0;
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index 6451c95..cfe6abe 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -123,7 +123,7 @@
unsigned int hz, bool has_bwadj)
{
static const struct pll_div dpll_cfg[] = {
- {.nf = 25, .nr = 2, .no = 1},
+ {.nf = 75, .nr = 1, .no = 6},
{.nf = 400, .nr = 9, .no = 2},
{.nf = 500, .nr = 9, .no = 2},
{.nf = 100, .nr = 3, .no = 1},
@@ -541,7 +541,7 @@
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3188_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3188_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 4e6d2f0..ebcab73 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -475,7 +475,7 @@
{
struct rk322x_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
return 0;
}
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 552a71a..3a36d04 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -906,7 +906,7 @@
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 2ccc798..046b4e4 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -767,7 +767,7 @@
{
struct rk3328_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3328_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
return 0;
}
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 224c813..958fc78 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -213,7 +213,7 @@
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
rkclk_init(priv->cru);
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 3847dd8..9a3b4c3 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -49,12 +49,17 @@
reg += index * (na + ns);
- /*
- * Use the full-fledged translate function for complex
- * bus setups.
- */
- addr = fdt_translate_address((void *)gd->fdt_blob,
- dev_of_offset(dev), reg);
+ if (ns) {
+ /*
+ * Use the full-fledged translate function for complex
+ * bus setups.
+ */
+ addr = fdt_translate_address((void *)gd->fdt_blob,
+ dev_of_offset(dev), reg);
+ } else {
+ /* Non translatable if #size-cells == 0 */
+ addr = fdt_read_number(reg, na);
+ }
} else {
/*
* Use the "simple" translate function for less complex
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 4e45326..5909a25 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -227,13 +227,16 @@
uint flags;
u64 size;
int na;
+ int ns;
prop_val = of_get_address(ofnode_to_np(node), index, &size,
&flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
- if (IS_ENABLED(CONFIG_OF_TRANSLATE)) {
+ ns = of_n_size_cells(ofnode_to_np(node));
+
+ if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) {
return of_translate_address(ofnode_to_np(node), prop_val);
} else {
na = of_n_addr_cells(ofnode_to_np(node));
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 3a426ab..9000ed5 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -333,7 +333,8 @@
int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only)
{
- int node, ret;
+ int ret;
+ ofnode node;
ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
if (ret) {
@@ -342,13 +343,18 @@
}
/* bind fixed-clock */
- node = ofnode_to_offset(ofnode_path("/clocks"));
+ node = ofnode_path("/clocks");
/* if no DT "clocks" node, no need to go further */
- if (node < 0)
+ if (!ofnode_valid(node))
return ret;
- ret = dm_scan_fdt_node(gd->dm_root, gd->fdt_blob, node,
- pre_reloc_only);
+#if CONFIG_IS_ENABLED(OF_LIVE)
+ if (of_live_active())
+ ret = dm_scan_fdt_live(gd->dm_root, node.np, pre_reloc_only);
+ else
+#endif
+ ret = dm_scan_fdt_node(gd->dm_root, gd->fdt_blob, node.of_offset,
+ pre_reloc_only);
if (ret)
debug("dm_scan_fdt_node() failed: %d\n", ret);
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 1aedaa0..628e2e1 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -457,6 +457,32 @@
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
+int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_get(id, &uc);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+ uint phandle;
+
+ phandle = dev_read_phandle(dev);
+
+ if (phandle == phandle_id) {
+ *devp = dev;
+ return uclass_get_device_tail(dev, ret, devp);
+ }
+ }
+
+ return -ENODEV;
+}
+
int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent,
const char *name, struct udevice **devp)
{
diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 4ad291a..6c612ba 100644
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -50,6 +50,10 @@
#define DMIPSPLLCFG_6358_N2_SHIFT 29
#define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
+#define REG_BCM6362_MISC_STRAPBUS 0x1814
+#define STRAPBUS_6362_FCVO_SHIFT 1
+#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
+
#define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0
#define DMIPSPLLCFG_6368_P1_SHIFT 0
#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
@@ -194,6 +198,44 @@
return (16 * 1000000 * n1 * n2) / m1;
}
+static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int mips_pll_fcvo;
+
+ mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
+ mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
+ >> STRAPBUS_6362_FCVO_SHIFT;
+
+ switch (mips_pll_fcvo) {
+ case 0x03:
+ case 0x0b:
+ case 0x13:
+ case 0x1b:
+ return 240000000;
+ case 0x04:
+ case 0x0c:
+ case 0x14:
+ case 0x1c:
+ return 160000000;
+ case 0x05:
+ case 0x0e:
+ case 0x16:
+ case 0x1e:
+ case 0x1f:
+ return 400000000;
+ case 0x06:
+ return 440000000;
+ case 0x07:
+ case 0x17:
+ return 384000000;
+ case 0x15:
+ case 0x1d:
+ return 200000000;
+ default:
+ return 320000000;
+ }
+}
+
static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
{
unsigned int tmp, p1, p2, ndiv, m1;
@@ -289,6 +331,12 @@
.get_cpu_count = bcm6358_get_cpu_count,
};
+static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
+ .get_cpu_desc = bmips_short_cpu_desc,
+ .get_cpu_freq = bcm6362_get_cpu_freq,
+ .get_cpu_count = bcm6358_get_cpu_count,
+};
+
static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
.get_cpu_desc = bmips_short_cpu_desc,
.get_cpu_freq = bcm6368_get_cpu_freq,
@@ -395,6 +443,9 @@
.compatible = "brcm,bcm6358-cpu",
.data = (ulong)&bmips_cpu_bcm6358,
}, {
+ .compatible = "brcm,bcm6362-cpu",
+ .data = (ulong)&bmips_cpu_bcm6362,
+ }, {
.compatible = "brcm,bcm6368-cpu",
.data = (ulong)&bmips_cpu_bcm6368,
}, {
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 6aead27..ac01612 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -148,20 +148,21 @@
{
int devnum = FPGA_INVALID_DEVICE;
+ if (!desc) {
+ printf("%s: NULL device descriptor\n", __func__);
+ return devnum;
+ }
+
if (next_desc < 0) {
printf("%s: FPGA support not initialized!\n", __func__);
} else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
- if (desc) {
- if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
- devnum = next_desc;
- desc_table[next_desc].devtype = devtype;
- desc_table[next_desc++].devdesc = desc;
- } else {
- printf("%s: Exceeded Max FPGA device count\n",
- __func__);
- }
+ if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
+ devnum = next_desc;
+ desc_table[next_desc].devtype = devtype;
+ desc_table[next_desc++].devdesc = desc;
} else {
- printf("%s: NULL device descriptor\n", __func__);
+ printf("%s: Exceeded Max FPGA device count\n",
+ __func__);
}
} else {
printf("%s: Unsupported FPGA type %d\n", __func__, devtype);
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 57a4e6c..43e8b252 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -11,6 +11,7 @@
#include <zynqmppl.h>
#include <linux/sizes.h>
#include <asm/arch/sys_proto.h>
+#include <memalign.h>
#define DUMMY_WORD 0xffffffff
@@ -195,6 +196,7 @@
static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
{
+ ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
u32 swap;
ulong bin_buf;
int ret;
@@ -205,25 +207,37 @@
return FPGA_FAIL;
bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+ bsizeptr = (u32 *)&bsize;
debug("%s called!\n", __func__);
flush_dcache_range(bin_buf, bin_buf + bsize);
-
- if (bsize % 4)
- bsize = bsize / 4 + 1;
- else
- bsize = bsize / 4;
+ flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
buf_lo = (u32)bin_buf;
buf_hi = upper_32_bits(bin_buf);
- ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
- bstype, ret_payload);
+ bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+ (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
if (ret)
debug("PL FPGA LOAD fail\n");
return ret;
}
+static int zynqmp_pcap_info(xilinx_desc *desc)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
+ 0, ret_payload);
+ if (!ret)
+ printf("PCAP status\t0x%x\n", ret_payload[1]);
+
+ return ret;
+}
+
struct xilinx_fpga_op zynqmp_op = {
.load = zynqmp_load,
+ .info = zynqmp_pcap_info,
};
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 2ff716c..db9bd12 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -17,6 +17,7 @@
#include <asm/arch/sys_proto.h>
#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
+#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
@@ -205,9 +206,24 @@
/* Setting PCFG_PROG_B signal to high */
control = readl(&devcfg_base->ctrl);
writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+ /*
+ * Delay is required if AES efuse is selected as
+ * key source.
+ */
+ if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+ mdelay(5);
+
/* Setting PCFG_PROG_B signal to low */
writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+ /*
+ * Delay is required if AES efuse is selected as
+ * key source.
+ */
+ if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+ mdelay(5);
+
/* Polling the PCAP_INIT status for Reset */
ts = get_timer(0);
while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index cc75aec..b7e4ffb 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -234,7 +234,7 @@
config STM32F7_GPIO
bool "ST STM32 GPIO driver"
- depends on DM_GPIO && STM32
+ depends on DM_GPIO && (STM32 || ARCH_STM32MP)
default y
help
Device model driver support for STM32 GPIO controller. It should be
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 9faf335..1fbfdef 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -655,7 +655,7 @@
ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
&desc->dev);
if (ret) {
- debug("%s: uclass_get_device_by_of_offset failed\n", __func__);
+ debug("%s: uclass_get_device_by_ofnode failed\n", __func__);
goto err;
}
ret = gpio_find_and_xlate(desc, args);
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index 7243100..559f29b 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -345,6 +345,7 @@
.bind = omap_gpio_bind,
.probe = omap_gpio_probe,
.priv_auto_alloc_size = sizeof(struct gpio_bank),
+ .flags = DM_FLAG_PRE_RELOC,
};
#endif /* CONFIG_DM_GPIO */
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
index a7cfb8c..376e86c 100644
--- a/drivers/gpio/stm32f7_gpio.c
+++ b/drivers/gpio/stm32f7_gpio.c
@@ -16,14 +16,11 @@
#include <linux/errno.h>
#include <linux/io.h>
-#define MAX_SIZE_BANK_NAME 5
#define STM32_GPIOS_PER_BANK 16
#define MODE_BITS(gpio_pin) (gpio_pin * 2)
#define MODE_BITS_MASK 3
#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin))
-DECLARE_GLOBAL_DATA_PTR;
-
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
@@ -82,21 +79,19 @@
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_gpio_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- char *name;
+ const char *name;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (struct stm32_gpio_regs *)addr;
- name = (char *)fdtdec_locate_byte_array(gd->fdt_blob,
- dev_of_offset(dev),
- "st,bank-name",
- MAX_SIZE_BANK_NAME);
+ name = dev_read_string(dev, "st,bank-name");
if (!name)
return -EINVAL;
uc_priv->bank_name = name;
- uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
+ uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
+ STM32_GPIOS_PER_BANK);
debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
uc_priv->bank_name);
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 3cf01b6..ea6f359 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -354,12 +354,15 @@
ID("allwinner,sun8i-a83t-pinctrl", a_all),
ID("allwinner,sun8i-h3-pinctrl", a_all),
ID("allwinner,sun8i-r40-pinctrl", a_all),
+ ID("allwinner,sun8i-v3s-pinctrl", a_all),
ID("allwinner,sun9i-a80-pinctrl", a_all),
+ ID("allwinner,sun50i-a64-pinctrl", a_all),
ID("allwinner,sun6i-a31-r-pinctrl", l_2),
ID("allwinner,sun8i-a23-r-pinctrl", l_1),
ID("allwinner,sun8i-a83t-r-pinctrl", l_1),
ID("allwinner,sun8i-h3-r-pinctrl", l_1),
ID("allwinner,sun9i-a80-r-pinctrl", l_3),
+ ID("allwinner,sun50i-a64-r-pinctrl", l_1),
{ }
};
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 286ae48..7fb201d 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -370,7 +370,7 @@
config SYS_I2C_STM32F7
bool "STMicroelectronics STM32F7 I2C support"
- depends on (STM32F7 || STM32H7) && DM_I2C
+ depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
help
Enable this option to add support for STM32 I2C controller
introduced with STM32F7/H7 SoCs. This I2C controller supports :
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index cb0f5ea..450a91d 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -12,6 +12,7 @@
#include <i2c.h> /* Functional interface */
#include <asm/io.h>
#include <asm/fsl_i2c.h> /* HW definitions */
+#include <clk.h>
#include <dm.h>
#include <mapmem.h>
@@ -573,11 +574,9 @@
static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
{
struct fsl_i2c_dev *dev = dev_get_priv(bus);
- fdt_addr_t addr;
+ struct clk clock;
- addr = dev_read_u32_default(bus, "reg", -1);
-
- dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, sizeof(struct fsl_i2c_base));
+ dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
if (!dev->base)
return -ENOMEM;
@@ -587,7 +586,11 @@
0x7f);
dev->speed = dev_read_u32_default(bus, "clock-frequency", 400000);
- dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
+ if (!clk_get_by_index(bus, 0, &clock))
+ dev->i2c_clk = clk_get_rate(&clock);
+ else
+ dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
+ gd->arch.i2c1_clk;
return 0;
}
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 920811a..4ac6ef8 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -11,9 +11,19 @@
#include <malloc.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#ifdef CONFIG_DM_GPIO
+#include <asm/gpio.h>
+#endif
#define I2C_MAX_OFFSET_LEN 4
+enum {
+ PIN_SDA = 0,
+ PIN_SCL,
+ PIN_COUNT,
+};
+
/* Useful debugging function */
void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs)
{
@@ -445,20 +455,110 @@
return chip->offset_len;
}
+#ifdef CONFIG_DM_GPIO
+static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit)
+{
+ if (bit)
+ dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
+ else
+ dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW |
+ GPIOD_IS_OUT_ACTIVE);
+}
+
+static int i2c_gpio_get_pin(struct gpio_desc *pin)
+{
+ return dm_gpio_get_value(pin);
+}
+
+static int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,
+ struct gpio_desc *scl_pin)
+{
+ int counter = 9;
+ int ret = 0;
+
+ i2c_gpio_set_pin(sda_pin, 1);
+ i2c_gpio_set_pin(scl_pin, 1);
+ udelay(5);
+
+ /* Toggle SCL until slave release SDA */
+ while (counter-- >= 0) {
+ i2c_gpio_set_pin(scl_pin, 1);
+ udelay(5);
+ i2c_gpio_set_pin(scl_pin, 0);
+ udelay(5);
+ if (i2c_gpio_get_pin(sda_pin))
+ break;
+ }
+
+ /* Then, send I2C stop */
+ i2c_gpio_set_pin(sda_pin, 0);
+ udelay(5);
+
+ i2c_gpio_set_pin(scl_pin, 1);
+ udelay(5);
+
+ i2c_gpio_set_pin(sda_pin, 1);
+ udelay(5);
+
+ if (!i2c_gpio_get_pin(sda_pin) || !i2c_gpio_get_pin(scl_pin))
+ ret = -EREMOTEIO;
+
+ return ret;
+}
+
+static int i2c_deblock_gpio(struct udevice *bus)
+{
+ struct gpio_desc gpios[PIN_COUNT];
+ int ret, ret0;
+
+ ret = gpio_request_list_by_name(bus, "gpios", gpios,
+ ARRAY_SIZE(gpios), GPIOD_IS_IN);
+ if (ret != ARRAY_SIZE(gpios)) {
+ debug("%s: I2C Node '%s' has no 'gpios' property %s\n",
+ __func__, dev_read_name(bus), bus->name);
+ if (ret >= 0) {
+ gpio_free_list(bus, gpios, ret);
+ ret = -ENOENT;
+ }
+ goto out;
+ }
+
+ ret = pinctrl_select_state(bus, "gpio");
+ if (ret) {
+ debug("%s: I2C Node '%s' has no 'gpio' pinctrl state. %s\n",
+ __func__, dev_read_name(bus), bus->name);
+ goto out_no_pinctrl;
+ }
+
+ ret0 = i2c_deblock_gpio_loop(&gpios[PIN_SDA], &gpios[PIN_SCL]);
+
+ ret = pinctrl_select_state(bus, "default");
+ if (ret) {
+ debug("%s: I2C Node '%s' has no 'default' pinctrl state. %s\n",
+ __func__, dev_read_name(bus), bus->name);
+ }
+
+ ret = !ret ? ret0 : ret;
+
+out_no_pinctrl:
+ gpio_free_list(bus, gpios, ARRAY_SIZE(gpios));
+out:
+ return ret;
+}
+#else
+static int i2c_deblock_gpio(struct udevice *bus)
+{
+ return -ENOSYS;
+}
+#endif // CONFIG_DM_GPIO
+
int i2c_deblock(struct udevice *bus)
{
struct dm_i2c_ops *ops = i2c_get_ops(bus);
- /*
- * We could implement a software deblocking here if we could get
- * access to the GPIOs used by I2C, and switch them to GPIO mode
- * and then back to I2C. This is somewhat beyond our powers in
- * driver model at present, so for now just fail.
- *
- * See https://patchwork.ozlabs.org/patch/399040/
- */
if (!ops->deblock)
- return -ENOSYS;
+ return i2c_deblock_gpio(bus);
return ops->deblock(bus);
}
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
index 9298521..82abb43 100644
--- a/drivers/i2c/ihs_i2c.c
+++ b/drivers/i2c/ihs_i2c.c
@@ -99,7 +99,8 @@
#endif
#ifdef CONFIG_DM_I2C
- fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val);
+ fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
+ FPGAMAP_SIZE_16);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
@@ -110,7 +111,8 @@
if (ctr++ > 5000)
return 1;
#ifdef CONFIG_DM_I2C
- fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val);
+ fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
+ FPGAMAP_SIZE_16);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
@@ -128,6 +130,7 @@
#endif
{
u16 val;
+ u16 data;
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv *priv = dev_get_priv(dev);
struct udevice *fpga;
@@ -136,13 +139,14 @@
#endif
/* Clear interrupt status */
+ data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
#ifdef CONFIG_DM_I2C
- fpgamap_write16(fpga, priv->addr + REG_INTERRUPT_STATUS,
- I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
- fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val);
+ fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
+ FPGAMAP_SIZE_16);
+ fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
+ FPGAMAP_SIZE_16);
#else
- I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV
- | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
+ I2C_SET_REG(interrupt_status, data);
I2C_GET_REG(interrupt_status, &val);
#endif
@@ -153,26 +157,24 @@
if (len > 1)
val |= buffer[1] << 8;
#ifdef CONFIG_DM_I2C
- fpgamap_write16(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, val);
+ fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
+ FPGAMAP_SIZE_16);
#else
I2C_SET_REG(write_mailbox_ext, val);
#endif
}
+ data = I2CMB_NATIVE
+ | (read ? 0 : I2CMB_WRITE)
+ | (chip << 1)
+ | ((len > 1) ? I2CMB_2BYTE : 0)
+ | (is_last ? 0 : I2CMB_HOLD_BUS);
+
#ifdef CONFIG_DM_I2C
- fpgamap_write16(fpga, priv->addr + REG_WRITE_MAILBOX,
- I2CMB_NATIVE
- | (read ? I2CMB_READ : I2CMB_WRITE)
- | (chip << 1)
- | ((len > 1) ? I2CMB_2BYTE : I2CMB_1BYTE)
- | (!is_last ? I2CMB_HOLD_BUS : I2CMB_DONT_HOLD_BUS));
+ fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
+ FPGAMAP_SIZE_16);
#else
- I2C_SET_REG(write_mailbox,
- I2CMB_NATIVE
- | (read ? 0 : I2CMB_WRITE)
- | (chip << 1)
- | ((len > 1) ? I2CMB_2BYTE : 0)
- | (is_last ? 0 : I2CMB_HOLD_BUS));
+ I2C_SET_REG(write_mailbox, data);
#endif
#ifdef CONFIG_DM_I2C
@@ -185,7 +187,8 @@
/* If we want to read, get the bytes from the mailbox */
if (read) {
#ifdef CONFIG_DM_I2C
- fpgamap_read16(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val);
+ fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
+ FPGAMAP_SIZE_16);
#else
I2C_GET_REG(read_mailbox_ext, &val);
#endif
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index de74e89..32d7809 100644
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -156,7 +156,7 @@
static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir)
{
- lpi2c_status_t result = LPI2C_SUCESS;
+ lpi2c_status_t result;
u32 val;
result = imx_lpci2c_check_busy_bus(regs);
@@ -184,7 +184,7 @@
static int bus_i2c_stop(struct imx_lpi2c_reg *regs)
{
- lpi2c_status_t result = LPI2C_SUCESS;
+ lpi2c_status_t result;
u32 status;
result = bus_i2c_wait_for_tx_ready(regs);
@@ -213,7 +213,7 @@
static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
{
- lpi2c_status_t result = LPI2C_SUCESS;
+ lpi2c_status_t result;
result = bus_i2c_start(regs, chip, 1);
if (result)
@@ -230,7 +230,7 @@
static int bus_i2c_write(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
{
- lpi2c_status_t result = LPI2C_SUCESS;
+ lpi2c_status_t result;
result = bus_i2c_start(regs, chip, 0);
if (result)
@@ -354,7 +354,7 @@
u32 chip_flags)
{
struct imx_lpi2c_reg *regs;
- lpi2c_status_t result = LPI2C_SUCESS;
+ lpi2c_status_t result;
regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
result = bus_i2c_start(regs, chip, 0);
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 4fd5551..cc9c5ef 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -25,9 +25,6 @@
#include <asm/arch/gpio.h>
#endif
#endif
-#if defined(CONFIG_8xx)
-#include <asm/io.h>
-#endif
#include <i2c.h>
#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 8662487..81f061a 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -533,7 +533,7 @@
if (((sdadel >= sdadel_min) &&
(sdadel <= sdadel_max)) &&
(p != p_prev)) {
- v = kmalloc(sizeof(*v), GFP_KERNEL);
+ v = calloc(1, sizeof(*v));
if (!v)
return -ENOMEM;
@@ -689,7 +689,7 @@
/* Release list and memory */
list_for_each_entry_safe(v, _v, &solutions, node) {
list_del(&v->node);
- kfree(v);
+ free(v);
}
return ret;
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 9109ac6..ee7bfc4 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -12,9 +12,5 @@
obj-$(CONFIG_TWL4030_INPUT) += twl4030.o
obj-$(CONFIG_TWL6030_INPUT) += twl6030.o
obj-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o
-ifdef CONFIG_PS2KBD
-obj-y += keyboard.o pc_keyb.o
-obj-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
-endif
obj-y += input.o
obj-$(CONFIG_$(SPL_)OF_CONTROL) += key_matrix.o
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
deleted file mode 100644
index 84ee015..0000000
--- a/drivers/input/keyboard.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/***********************************************************************
- *
- * (C) Copyright 2004
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * Keyboard driver
- *
- ***********************************************************************/
-
-#include <common.h>
-#include <console.h>
-#include <input.h>
-
-#include <stdio_dev.h>
-#include <keyboard.h>
-#include <stdio_dev.h>
-
-static struct input_config config;
-
-static int kbd_read_keys(struct input_config *config)
-{
-#if defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
- /* no ISR is used, so received chars must be polled */
- ps2ser_check();
-#endif
-
- return 1;
-}
-
-static int check_leds(int ret)
-{
- int leds;
-
- leds = input_leds_changed(&config);
- if (leds >= 0)
- pckbd_leds(leds);
-
- return ret;
-}
-
-/* test if a character is in the queue */
-static int kbd_testc(struct stdio_dev *dev)
-{
- return check_leds(input_tstc(&config));
-}
-
-/* gets the character from the queue */
-static int kbd_getc(struct stdio_dev *dev)
-{
- return check_leds(input_getc(&config));
-}
-
-void handle_scancode(unsigned char scan_code)
-{
- bool release = false;
-
- /* Compare with i8042_kbd_check() in i8042.c if some logic is missing */
- if (scan_code & 0x80) {
- scan_code &= 0x7f;
- release = true;
- }
-
- input_add_keycode(&config, scan_code, release);
-}
-
-/* TODO: convert to driver model */
-int kbd_init (void)
-{
- struct stdio_dev kbddev;
- struct input_config *input = &config;
-
- if(kbd_init_hw()==-1)
- return -1;
- memset (&kbddev, 0, sizeof(kbddev));
- strcpy(kbddev.name, "kbd");
- kbddev.flags = DEV_FLAGS_INPUT;
- kbddev.getc = kbd_getc;
- kbddev.tstc = kbd_testc;
-
- input_init(input, 0);
- input->read_keys = kbd_read_keys;
- input_add_tables(input, true);
-
- return input_stdio_register(&kbddev);
-}
diff --git a/drivers/input/pc_keyb.c b/drivers/input/pc_keyb.c
deleted file mode 100644
index 1606ab3..0000000
--- a/drivers/input/pc_keyb.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/***********************************************************************
- *
- * (C) Copyright 2004
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * PS/2 keyboard driver
- *
- * Originally from linux source (drivers/char/pc_keyb.c)
- *
- ***********************************************************************/
-
-#include <common.h>
-
-#include <keyboard.h>
-#include <pc_keyb.h>
-
-#undef KBG_DEBUG
-
-#ifdef KBG_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-
-/*
- * This reads the keyboard status port, and does the
- * appropriate action.
- *
- */
-static unsigned char handle_kbd_event(void)
-{
- unsigned char status = kbd_read_status();
- unsigned int work = 10000;
-
- while ((--work > 0) && (status & KBD_STAT_OBF)) {
- unsigned char scancode;
-
- scancode = kbd_read_input();
-
- /* Error bytes must be ignored to make the
- Synaptics touchpads compaq use work */
- /* Ignore error bytes */
- if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) {
- if (status & KBD_STAT_MOUSE_OBF)
- ; /* not supported: handle_mouse_event(scancode); */
- else
- handle_scancode(scancode);
- }
- status = kbd_read_status();
- }
- if (!work)
- PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
- return status;
-}
-
-
-static int kbd_read_data(void)
-{
- int val;
- unsigned char status;
-
- val = -1;
- status = kbd_read_status();
- if (status & KBD_STAT_OBF) {
- val = kbd_read_input();
- if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
- val = -2;
- }
- return val;
-}
-
-static int kbd_wait_for_input(void)
-{
- unsigned long timeout;
- int val;
-
- timeout = KBD_TIMEOUT;
- val=kbd_read_data();
- while(val < 0) {
- if(timeout--==0)
- return -1;
- udelay(1000);
- val=kbd_read_data();
- }
- return val;
-}
-
-
-static int kb_wait(void)
-{
- unsigned long timeout = KBC_TIMEOUT * 10;
-
- do {
- unsigned char status = handle_kbd_event();
- if (!(status & KBD_STAT_IBF))
- return 0; /* ok */
- udelay(1000);
- timeout--;
- } while (timeout);
- return 1;
-}
-
-static void kbd_write_command_w(int data)
-{
- if(kb_wait())
- PRINTF("timeout in kbd_write_command_w\n");
- kbd_write_command(data);
-}
-
-static void kbd_write_output_w(int data)
-{
- if(kb_wait())
- PRINTF("timeout in kbd_write_output_w\n");
- kbd_write_output(data);
-}
-
-static void kbd_send_data(unsigned char data)
-{
- kbd_write_output_w(data);
- kbd_wait_for_input();
-}
-
-
-static char * kbd_initialize(void)
-{
- int status;
-
- /*
- * Test the keyboard interface.
- * This seems to be the only way to get it going.
- * If the test is successful a x55 is placed in the input buffer.
- */
- kbd_write_command_w(KBD_CCMD_SELF_TEST);
- if (kbd_wait_for_input() != 0x55)
- return "Kbd: failed self test";
- /*
- * Perform a keyboard interface test. This causes the controller
- * to test the keyboard clock and data lines. The results of the
- * test are placed in the input buffer.
- */
- kbd_write_command_w(KBD_CCMD_KBD_TEST);
- if (kbd_wait_for_input() != 0x00)
- return "Kbd: interface failed self test";
- /*
- * Enable the keyboard by allowing the keyboard clock to run.
- */
- kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
-
- /*
- * Reset keyboard. If the read times out
- * then the assumption is that no keyboard is
- * plugged into the machine.
- * This defaults the keyboard to scan-code set 2.
- *
- * Set up to try again if the keyboard asks for RESEND.
- */
- do {
- kbd_write_output_w(KBD_CMD_RESET);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- break;
- if (status != KBD_REPLY_RESEND) {
- PRINTF("status: %X\n",status);
- return "Kbd: reset failed, no ACK";
- }
- } while (1);
- if (kbd_wait_for_input() != KBD_REPLY_POR)
- return "Kbd: reset failed, no POR";
-
- /*
- * Set keyboard controller mode. During this, the keyboard should be
- * in the disabled state.
- *
- * Set up to try again if the keyboard asks for RESEND.
- */
- do {
- kbd_write_output_w(KBD_CMD_DISABLE);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- break;
- if (status != KBD_REPLY_RESEND)
- return "Kbd: disable keyboard: no ACK";
- } while (1);
-
- kbd_write_command_w(KBD_CCMD_WRITE_MODE);
- kbd_write_output_w(KBD_MODE_KBD_INT
- | KBD_MODE_SYS
- | KBD_MODE_DISABLE_MOUSE
- | KBD_MODE_KCC);
-
- /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
- kbd_write_command_w(KBD_CCMD_READ_MODE);
- if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
- /*
- * If the controller does not support conversion,
- * Set the keyboard to scan-code set 1.
- */
- kbd_write_output_w(0xF0);
- kbd_wait_for_input();
- kbd_write_output_w(0x01);
- kbd_wait_for_input();
- }
- kbd_write_output_w(KBD_CMD_ENABLE);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: enable keyboard: no ACK";
-
- /*
- * Finally, set the typematic rate to maximum.
- */
- kbd_write_output_w(KBD_CMD_SET_RATE);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: Set rate: no ACK";
- kbd_write_output_w(0x00);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: Set rate: no ACK";
- return NULL;
-}
-
-static void kbd_interrupt(void *dev_id)
-{
- handle_kbd_event();
-}
-
-/******************************************************************
- * Init
- ******************************************************************/
-
-int kbd_init_hw(void)
-{
- char* result;
-
- kbd_request_region();
-
- result=kbd_initialize();
- if (result==NULL) {
- PRINTF("AT Keyboard initialized\n");
- kbd_request_irq(kbd_interrupt);
- return (1);
- } else {
- printf("%s\n",result);
- return (-1);
- }
-}
-
-void pckbd_leds(unsigned char leds)
-{
- kbd_send_data(KBD_CMD_SET_LEDS);
- kbd_send_data(leds);
-}
diff --git a/drivers/input/ps2mult.c b/drivers/input/ps2mult.c
deleted file mode 100644
index ab74933..0000000
--- a/drivers/input/ps2mult.c
+++ /dev/null
@@ -1,461 +0,0 @@
-/***********************************************************************
- *
- * (C) Copyright 2004
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * PS/2 multiplexer driver
- *
- * Originally from linux source (drivers/char/ps2mult.c)
- *
- * Uses simple serial driver (ps2ser.c) to access the multiplexer
- * Used by PS/2 keyboard driver (pc_keyb.c)
- *
- ***********************************************************************/
-
-#include <common.h>
-
-#include <pc_keyb.h>
-#include <asm/atomic.h>
-#include <ps2mult.h>
-
-/* #define DEBUG_MULT */
-/* #define DEBUG_KEYB */
-
-#define KBD_STAT_DEFAULT (KBD_STAT_SELFTEST | KBD_STAT_UNLOCKED)
-
-#define PRINTF(format, args...) printf("ps2mult.c: " format, ## args)
-
-#ifdef DEBUG_MULT
-#define PRINTF_MULT(format, args...) printf("PS2MULT: " format, ## args)
-#else
-#define PRINTF_MULT(format, args...)
-#endif
-
-#ifdef DEBUG_KEYB
-#define PRINTF_KEYB(format, args...) printf("KEYB: " format, ## args)
-#else
-#define PRINTF_KEYB(format, args...)
-#endif
-
-
-static ulong start_time;
-static int init_done = 0;
-
-static int received_escape = 0;
-static int received_bsync = 0;
-static int received_selector = 0;
-
-static int kbd_command_active = 0;
-static int mouse_command_active = 0;
-static int ctl_command_active = 0;
-
-static u_char command_byte = 0;
-
-static void (*keyb_handler)(void *dev_id);
-
-static u_char ps2mult_buf [PS2BUF_SIZE];
-static atomic_t ps2mult_buf_cnt;
-static int ps2mult_buf_in_idx;
-static int ps2mult_buf_out_idx;
-
-static u_char ps2mult_buf_status [PS2BUF_SIZE];
-
-#ifndef CONFIG_BOARD_EARLY_INIT_R
-#error #define CONFIG_BOARD_EARLY_INIT_R and call ps2mult_early_init() in board_early_init_r()
-#endif
-void ps2mult_early_init (void)
-{
- start_time = get_timer(0);
-}
-
-static void ps2mult_send_byte(u_char byte, u_char sel)
-{
- ps2ser_putc(sel);
-
- if (sel == PS2MULT_KB_SELECTOR) {
- PRINTF_MULT("0x%02x send KEYBOARD\n", byte);
- kbd_command_active = 1;
- } else {
- PRINTF_MULT("0x%02x send MOUSE\n", byte);
- mouse_command_active = 1;
- }
-
- switch (byte) {
- case PS2MULT_ESCAPE:
- case PS2MULT_BSYNC:
- case PS2MULT_KB_SELECTOR:
- case PS2MULT_MS_SELECTOR:
- case PS2MULT_SESSION_START:
- case PS2MULT_SESSION_END:
- ps2ser_putc(PS2MULT_ESCAPE);
- break;
- default:
- break;
- }
-
- ps2ser_putc(byte);
-}
-
-static void ps2mult_receive_byte(u_char byte, u_char sel)
-{
- u_char status = KBD_STAT_DEFAULT;
-
-#if 1 /* Ignore mouse in U-Boot */
- if (sel == PS2MULT_MS_SELECTOR) return;
-#endif
-
- if (sel == PS2MULT_KB_SELECTOR) {
- if (kbd_command_active) {
- if (!received_bsync) {
- PRINTF_MULT("0x%02x lost KEYBOARD !!!\n", byte);
- return;
- } else {
- kbd_command_active = 0;
- received_bsync = 0;
- }
- }
- PRINTF_MULT("0x%02x receive KEYBOARD\n", byte);
- status |= KBD_STAT_IBF | KBD_STAT_OBF;
- } else {
- if (mouse_command_active) {
- if (!received_bsync) {
- PRINTF_MULT("0x%02x lost MOUSE !!!\n", byte);
- return;
- } else {
- mouse_command_active = 0;
- received_bsync = 0;
- }
- }
- PRINTF_MULT("0x%02x receive MOUSE\n", byte);
- status |= KBD_STAT_IBF | KBD_STAT_OBF | KBD_STAT_MOUSE_OBF;
- }
-
- if (atomic_read(&ps2mult_buf_cnt) < PS2BUF_SIZE) {
- ps2mult_buf_status[ps2mult_buf_in_idx] = status;
- ps2mult_buf[ps2mult_buf_in_idx++] = byte;
- ps2mult_buf_in_idx &= (PS2BUF_SIZE - 1);
- atomic_inc(&ps2mult_buf_cnt);
- } else {
- PRINTF("buffer overflow\n");
- }
-
- if (received_bsync) {
- PRINTF("unexpected BSYNC\n");
- received_bsync = 0;
- }
-}
-
-void ps2mult_callback (int in_cnt)
-{
- int i;
- u_char byte;
- static int keyb_handler_active = 0;
-
- if (!init_done) {
- return;
- }
-
- for (i = 0; i < in_cnt; i ++) {
- byte = ps2ser_getc();
-
- if (received_escape) {
- ps2mult_receive_byte(byte, received_selector);
- received_escape = 0;
- } else switch (byte) {
- case PS2MULT_ESCAPE:
- PRINTF_MULT("ESCAPE receive\n");
- received_escape = 1;
- break;
-
- case PS2MULT_BSYNC:
- PRINTF_MULT("BSYNC receive\n");
- received_bsync = 1;
- break;
-
- case PS2MULT_KB_SELECTOR:
- case PS2MULT_MS_SELECTOR:
- PRINTF_MULT("%s receive\n",
- byte == PS2MULT_KB_SELECTOR ? "KB_SEL" : "MS_SEL");
- received_selector = byte;
- break;
-
- case PS2MULT_SESSION_START:
- case PS2MULT_SESSION_END:
- PRINTF_MULT("%s receive\n",
- byte == PS2MULT_SESSION_START ?
- "SESSION_START" : "SESSION_END");
- break;
-
- default:
- ps2mult_receive_byte(byte, received_selector);
- }
- }
-
- if (keyb_handler && !keyb_handler_active &&
- atomic_read(&ps2mult_buf_cnt)) {
- keyb_handler_active = 1;
- keyb_handler(NULL);
- keyb_handler_active = 0;
- }
-}
-
-u_char ps2mult_read_status(void)
-{
- u_char byte;
-
- if (atomic_read(&ps2mult_buf_cnt) == 0) {
- ps2ser_check();
- }
-
- if (atomic_read(&ps2mult_buf_cnt)) {
- byte = ps2mult_buf_status[ps2mult_buf_out_idx];
- } else {
- byte = KBD_STAT_DEFAULT;
- }
- PRINTF_KEYB("read_status()=0x%02x\n", byte);
- return byte;
-}
-
-u_char ps2mult_read_input(void)
-{
- u_char byte = 0;
-
- if (atomic_read(&ps2mult_buf_cnt) == 0) {
- ps2ser_check();
- }
-
- if (atomic_read(&ps2mult_buf_cnt)) {
- byte = ps2mult_buf[ps2mult_buf_out_idx++];
- ps2mult_buf_out_idx &= (PS2BUF_SIZE - 1);
- atomic_dec(&ps2mult_buf_cnt);
- }
- PRINTF_KEYB("read_input()=0x%02x\n", byte);
- return byte;
-}
-
-void ps2mult_write_output(u_char val)
-{
- int i;
-
- PRINTF_KEYB("write_output(0x%02x)\n", val);
-
- for (i = 0; i < KBD_TIMEOUT; i++) {
- if (!kbd_command_active && !mouse_command_active) {
- break;
- }
- udelay(1000);
- ps2ser_check();
- }
-
- if (kbd_command_active) {
- PRINTF("keyboard command not acknoledged\n");
- kbd_command_active = 0;
- }
-
- if (mouse_command_active) {
- PRINTF("mouse command not acknoledged\n");
- mouse_command_active = 0;
- }
-
- if (ctl_command_active) {
- switch (ctl_command_active) {
- case KBD_CCMD_WRITE_MODE:
- /* Scan code conversion not supported */
- command_byte = val & ~KBD_MODE_KCC;
- break;
-
- case KBD_CCMD_WRITE_AUX_OBUF:
- ps2mult_receive_byte(val, PS2MULT_MS_SELECTOR);
- break;
-
- case KBD_CCMD_WRITE_MOUSE:
- ps2mult_send_byte(val, PS2MULT_MS_SELECTOR);
- break;
-
- default:
- PRINTF("invalid controller command\n");
- break;
- }
-
- ctl_command_active = 0;
- return;
- }
-
- ps2mult_send_byte(val, PS2MULT_KB_SELECTOR);
-}
-
-void ps2mult_write_command(u_char val)
-{
- ctl_command_active = 0;
-
- PRINTF_KEYB("write_command(0x%02x)\n", val);
-
- switch (val) {
- case KBD_CCMD_READ_MODE:
- ps2mult_receive_byte(command_byte, PS2MULT_KB_SELECTOR);
- break;
-
- case KBD_CCMD_WRITE_MODE:
- ctl_command_active = val;
- break;
-
- case KBD_CCMD_MOUSE_DISABLE:
- break;
-
- case KBD_CCMD_MOUSE_ENABLE:
- break;
-
- case KBD_CCMD_SELF_TEST:
- ps2mult_receive_byte(0x55, PS2MULT_KB_SELECTOR);
- break;
-
- case KBD_CCMD_KBD_TEST:
- ps2mult_receive_byte(0x00, PS2MULT_KB_SELECTOR);
- break;
-
- case KBD_CCMD_KBD_DISABLE:
- break;
-
- case KBD_CCMD_KBD_ENABLE:
- break;
-
- case KBD_CCMD_WRITE_AUX_OBUF:
- ctl_command_active = val;
- break;
-
- case KBD_CCMD_WRITE_MOUSE:
- ctl_command_active = val;
- break;
-
- default:
- PRINTF("invalid controller command\n");
- break;
- }
-}
-
-static int ps2mult_getc_w (void)
-{
- int res = -1;
- int i;
-
- for (i = 0; i < KBD_TIMEOUT; i++) {
- if (ps2ser_check()) {
- res = ps2ser_getc();
- break;
- }
- udelay(1000);
- }
-
- switch (res) {
- case PS2MULT_KB_SELECTOR:
- case PS2MULT_MS_SELECTOR:
- received_selector = res;
- break;
- default:
- break;
- }
-
- return res;
-}
-
-int ps2mult_init (void)
-{
- int byte;
- int kbd_found = 0;
- int mouse_found = 0;
-
- while (get_timer(start_time) < CONFIG_PS2MULT_DELAY);
-
- ps2ser_init();
-
- ps2ser_putc(PS2MULT_SESSION_START);
-
- ps2ser_putc(PS2MULT_KB_SELECTOR);
- ps2ser_putc(KBD_CMD_RESET);
-
- do {
- byte = ps2mult_getc_w();
- } while (byte >= 0 && byte != KBD_REPLY_ACK);
-
- if (byte == KBD_REPLY_ACK) {
- byte = ps2mult_getc_w();
- if (byte == 0xaa) {
- kbd_found = 1;
- puts("keyboard");
- }
- }
-
- if (!kbd_found) {
- while (byte >= 0) {
- byte = ps2mult_getc_w();
- }
- }
-
-#if 1 /* detect mouse */
- ps2ser_putc(PS2MULT_MS_SELECTOR);
- ps2ser_putc(AUX_RESET);
-
- do {
- byte = ps2mult_getc_w();
- } while (byte >= 0 && byte != AUX_ACK);
-
- if (byte == AUX_ACK) {
- byte = ps2mult_getc_w();
- if (byte == 0xaa) {
- byte = ps2mult_getc_w();
- if (byte == 0x00) {
- mouse_found = 1;
- puts(", mouse");
- }
- }
- }
-
- if (!mouse_found) {
- while (byte >= 0) {
- byte = ps2mult_getc_w();
- }
- }
-#endif
-
- if (mouse_found || kbd_found) {
- if (!received_selector) {
- if (mouse_found) {
- received_selector = PS2MULT_MS_SELECTOR;
- } else {
- received_selector = PS2MULT_KB_SELECTOR;
- }
- }
-
- init_done = 1;
- } else {
- puts("No device found");
- }
-
- puts("\n");
-
-#if 0 /* for testing */
- {
- int i;
- u_char key[] = {
- 0x1f, 0x12, 0x14, 0x12, 0x31, 0x2f, 0x39, /* setenv */
- 0x1f, 0x14, 0x20, 0x17, 0x31, 0x39, /* stdin */
- 0x1f, 0x12, 0x13, 0x17, 0x1e, 0x26, 0x1c, /* serial */
- };
-
- for (i = 0; i < sizeof (key); i++) {
- ps2mult_receive_byte (key[i], PS2MULT_KB_SELECTOR);
- ps2mult_receive_byte (key[i] | 0x80, PS2MULT_KB_SELECTOR);
- }
- }
-#endif
-
- return init_done ? 0 : -1;
-}
-
-int ps2mult_request_irq(void (*handler)(void *))
-{
- keyb_handler = handler;
-
- return 0;
-}
diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
deleted file mode 100644
index 0b5ce06..0000000
--- a/drivers/input/ps2ser.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/***********************************************************************
- *
- * (C) Copyright 2004-2009
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * Simple 16550A serial driver
- *
- * Originally from linux source (drivers/char/ps2ser.c)
- *
- * Used by the PS/2 multiplexer driver (ps2mult.c)
- *
- ***********************************************************************/
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/atomic.h>
-#include <ps2mult.h>
-/* This is needed for ns16550.h */
-#ifndef CONFIG_SYS_NS16550_REG_SIZE
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#endif
-#include <ns16550.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* #define DEBUG */
-
-#define PS2SER_BAUD 57600
-
-#if CONFIG_PS2SERIAL == 1
-#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
-#elif CONFIG_PS2SERIAL == 2
-#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4600)
-#else
-#error CONFIG_PS2SERIAL must be in 1 ... 2
-#endif
-
-static int ps2ser_getc_hw(void);
-static void ps2ser_interrupt(void *dev_id);
-
-extern struct serial_state rs_table[]; /* in serial.c */
-
-static u_char ps2buf[PS2BUF_SIZE];
-static atomic_t ps2buf_cnt;
-static int ps2buf_in_idx;
-static int ps2buf_out_idx;
-
-int ps2ser_init(void)
-{
- NS16550_t com_port = (NS16550_t)COM_BASE;
-
- com_port->ier = 0x00;
- com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
- com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
- com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
- com_port->lcr = UART_LCR_8N1;
- com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS);
- com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);
-
- return (0);
-}
-
-void ps2ser_putc(int chr)
-{
- NS16550_t com_port = (NS16550_t)COM_BASE;
- debug(">>>> 0x%02x\n", chr);
-
- while ((com_port->lsr & UART_LSR_THRE) == 0);
- com_port->thr = chr;
-}
-
-static int ps2ser_getc_hw(void)
-{
- NS16550_t com_port = (NS16550_t)COM_BASE;
- int res = -1;
-
- if (com_port->lsr & UART_LSR_DR) {
- res = com_port->rbr;
- }
-
- return res;
-}
-
-int ps2ser_getc(void)
-{
- volatile int chr;
- int flags;
-
- debug("<< ");
-
- flags = disable_interrupts();
-
- do {
- if (atomic_read(&ps2buf_cnt) != 0) {
- chr = ps2buf[ps2buf_out_idx++];
- ps2buf_out_idx &= (PS2BUF_SIZE - 1);
- atomic_dec(&ps2buf_cnt);
- } else {
- chr = ps2ser_getc_hw();
- }
- }
- while (chr < 0);
-
- if (flags)
- enable_interrupts();
-
- debug("0x%02x\n", chr);
-
- return chr;
-}
-
-int ps2ser_check(void)
-{
- int flags;
-
- flags = disable_interrupts();
- ps2ser_interrupt(NULL);
- if (flags) enable_interrupts();
-
- return atomic_read(&ps2buf_cnt);
-}
-
-static void ps2ser_interrupt(void *dev_id)
-{
- NS16550_t com_port = (NS16550_t)COM_BASE;
- int chr;
- int status;
-
- do {
- chr = ps2ser_getc_hw();
- status = com_port->lsr;
- if (chr < 0) continue;
-
- if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
- ps2buf[ps2buf_in_idx++] = chr;
- ps2buf_in_idx &= (PS2BUF_SIZE - 1);
- atomic_inc(&ps2buf_cnt);
- } else {
- printf ("ps2ser.c: buffer overflow\n");
- }
- } while (status & UART_LSR_DR);
- if (atomic_read(&ps2buf_cnt)) {
- ps2mult_callback(atomic_read(&ps2buf_cnt));
- }
-}
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5f67e33..6935da2 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -267,13 +267,22 @@
Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
config MMC_UNIPHIER
- bool "UniPhier/RCar SD/MMC Host Controller support"
- depends on ARCH_UNIPHIER || ARCH_RMOBILE
+ bool "UniPhier SD/MMC Host Controller support"
+ depends on ARCH_UNIPHIER
depends on BLK && DM_MMC
depends on OF_CONTROL
help
This selects support for the Matsushita SD/MMC Host Controller on
- SocioNext UniPhier and Renesas RCar SoCs.
+ SocioNext UniPhier SoCs.
+
+config RENESAS_SDHI
+ bool "Renesas R-Car SD/MMC Host Controller support"
+ depends on ARCH_RMOBILE
+ depends on BLK && DM_MMC
+ depends on OF_CONTROL
+ help
+ This selects support for the Matsushita SD/MMC Host Controller on
+ Renesas R-Car SoCs.
config MMC_BCM2835
bool "BCM2835 family custom SD/MMC Host Controller support"
@@ -523,18 +532,18 @@
If you have a board based on such a SoC and with a SD/MMC slot,
say Y or M here.
-config MMC_NDS32
- bool "Andestech SD/MMC controller support"
- depends on DM_MMC && OF_CONTROL && BLK && FTSDC010
- help
- This enables support for the Andestech SD/MMM controller, which is
- based on Faraday IP.
-
config FTSDC010
bool "Ftsdc010 SD/MMC controller Support"
help
This SD/MMC controller is present in Andestech SoCs which is based on Faraday IP.
+config FTSDC010_SDIO
+ bool "Support ftsdc010 sdio"
+ default n
+ depends on FTSDC010
+ help
+ This can enable ftsdc010 sdio function.
+
endif
config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
@@ -548,6 +557,12 @@
TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
approach once proper kernel integration made it mainline.
+config FSL_ESDHC
+ bool "Freescale/NXP eSDHC controller support"
+ help
+ This selects support for the eSDHC (enhanced secure digital host
+ controller) found on numerous Freescale/NXP SoCs.
+
endmenu
config SYS_FSL_ERRATUM_ESDHC111
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 42113e2..cf46c33 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -42,7 +42,6 @@
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
-obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o
# SDHCI
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
@@ -63,5 +62,6 @@
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
-obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
+obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
+obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 3157354..08bddd4 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -183,7 +183,7 @@
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
- ret = bcm2835_get_mmc_clock();
+ ret = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_EMMC);
if (ret < 0) {
debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
return ret;
diff --git a/drivers/mmc/bcm2835_sdhost.c b/drivers/mmc/bcm2835_sdhost.c
index 1bf52a3..bccd182 100644
--- a/drivers/mmc/bcm2835_sdhost.c
+++ b/drivers/mmc/bcm2835_sdhost.c
@@ -35,6 +35,7 @@
#include <dm.h>
#include <mmc.h>
#include <asm/arch/msg.h>
+#include <asm/arch/mbox.h>
#include <asm/unaligned.h>
#include <linux/compat.h>
#include <linux/io.h>
@@ -941,7 +942,7 @@
if (!host->ioaddr)
return -ENOMEM;
- host->max_clk = bcm2835_get_mmc_clock();
+ host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
bcm2835_add_host(host);
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
index 6ac4f83..9de3a15 100644
--- a/drivers/mmc/ftsdc010_mci.c
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -4,23 +4,63 @@
* (C) Copyright 2010 Faraday Technology
* Dante Su <dantesu@faraday-tech.com>
*
+ * Copyright 2018 Andes Technology, Inc.
+ * Author: Rick Chen (rick@andestech.com)
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <clk.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>
-
#include <linux/io.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
#include <faraday/ftsdc010.h>
#include "ftsdc010_mci.h"
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <mapmem.h>
+#include <pwrseq.h>
+#include <syscon.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct ftsdc010 {
+ fdt32_t bus_width;
+ bool cap_mmc_highspeed;
+ bool cap_sd_highspeed;
+ fdt32_t clock_freq_min_max[2];
+ struct phandle_2_cell clocks[4];
+ fdt32_t fifo_depth;
+ fdt32_t reg[2];
+};
+#endif
+
+struct ftsdc010_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct ftsdc010 dtplat;
+#endif
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct ftsdc_priv {
+ struct clk clk;
+ struct ftsdc010_chip chip;
+ int fifo_depth;
+ bool fifo_mode;
+ u32 minmax[2];
+};
+
static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
struct ftsdc010_chip *chip = mmc->priv;
@@ -138,16 +178,10 @@
/*
* u-boot mmc api
*/
-#ifdef CONFIG_DM_MMC
static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
-#endif
int ret = -EOPNOTSUPP;
uint32_t len = 0;
struct ftsdc010_chip *chip = mmc->priv;
@@ -248,14 +282,9 @@
return ret;
}
-#ifdef CONFIG_DM_MMC
static int ftsdc010_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_set_ios(struct mmc *mmc)
-{
-#endif
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
@@ -277,27 +306,17 @@
return 0;
}
-#ifdef CONFIG_DM_MMC
static int ftsdc010_get_cd(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_get_cd(struct mmc *mmc)
-{
-#endif
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
return !(readl(®s->status) & FTSDC010_STATUS_CARD_DETECT);
}
-#ifdef CONFIG_DM_MMC
static int ftsdc010_get_wp(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_get_wp(struct mmc *mmc)
-{
-#endif
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) {
@@ -337,31 +356,20 @@
return 0;
}
-#ifdef CONFIG_DM_MMC
-int ftsdc010_probe(struct udevice *dev)
+static int ftsdc010_probe(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
return ftsdc010_init(mmc);
}
-const struct dm_mmc_ops dm_ftsdc010_ops = {
+const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
.send_cmd = ftsdc010_request,
.set_ios = ftsdc010_set_ios,
.get_cd = ftsdc010_get_cd,
.get_wp = ftsdc010_get_wp,
};
-#else
-static const struct mmc_ops ftsdc010_ops = {
- .send_cmd = ftsdc010_request,
- .set_ios = ftsdc010_set_ios,
- .getcd = ftsdc010_get_cd,
- .getwp = ftsdc010_get_wp,
- .init = ftsdc010_init,
-};
-#endif
-
-void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
uint caps, u32 max_clk, u32 min_clk)
{
cfg->name = name;
@@ -380,73 +388,94 @@
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}
-void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg)
+static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
{
- switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) {
- case FTSDC010_BWR_CAPS_4BIT:
- cfg->host_caps |= MMC_MODE_4BIT;
- break;
- case FTSDC010_BWR_CAPS_8BIT:
- cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
- break;
- default:
- break;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct ftsdc_priv *priv = dev_get_priv(dev);
+ struct ftsdc010_chip *chip = &priv->chip;
+ chip->name = dev->name;
+ chip->ioaddr = (void *)devfdt_get_addr(dev);
+ chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 4);
+ chip->priv = dev;
+ priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-depth", 0);
+ priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-mode");
+ if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
+ "clock-freq-min-max", priv->minmax, 2)) {
+ int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "max-frequency", -EINVAL);
+ if (val < 0)
+ return val;
+
+ priv->minmax[0] = 400000; /* 400 kHz */
+ priv->minmax[1] = val;
+ } else {
+ debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+ __func__);
}
-}
-
-#ifdef CONFIG_BLK
-int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
-{
- return mmc_bind(dev, mmc, cfg);
-}
-#else
-
-int ftsdc010_mmc_init(int devid)
-{
- struct mmc *mmc;
- struct ftsdc010_chip *chip;
- struct ftsdc010_mmc __iomem *regs;
-#ifdef CONFIG_FTSDC010_BASE_LIST
- uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST;
-
- if (devid < 0 || devid >= ARRAY_SIZE(base_list))
- return -1;
- regs = (void __iomem *)base_list[devid];
-#else
- regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
#endif
-
- chip = malloc(sizeof(struct ftsdc010_chip));
- if (!chip)
- return -ENOMEM;
- memset(chip, 0, sizeof(struct ftsdc010_chip));
-
- chip->regs = regs;
-#ifdef CONFIG_SYS_CLK_FREQ
- chip->sclk = CONFIG_SYS_CLK_FREQ;
-#else
- chip->sclk = clk_get_rate("SDC");
-#endif
-
- chip->cfg.name = "ftsdc010";
-#ifndef CONFIG_DM_MMC
- chip->cfg.ops = &ftsdc010_ops;
-#endif
- chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
- set_bus_width(regs , &chip->cfg);
- chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
- chip->cfg.f_max = chip->sclk / 2;
- chip->cfg.f_min = chip->sclk / 0x100;
-
- chip->cfg.part_type = PART_TYPE_DOS;
- chip->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
-
- mmc = mmc_create(&chip->cfg, chip);
- if (mmc == NULL) {
- free(chip);
- return -ENOMEM;
- }
-
+ chip->sclk = priv->minmax[1];
+ chip->regs = chip->ioaddr;
return 0;
}
+
+static int ftsdc010_mmc_probe(struct udevice *dev)
+{
+ struct ftsdc010_plat *plat = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct ftsdc_priv *priv = dev_get_priv(dev);
+ struct ftsdc010_chip *chip = &priv->chip;
+ struct udevice *pwr_dev __maybe_unused;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ int ret;
+ struct ftsdc010 *dtplat = &plat->dtplat;
+ chip->name = dev->name;
+ chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+ chip->buswidth = dtplat->bus_width;
+ chip->priv = dev;
+ chip->dev_index = 1;
+ memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
+ ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
+ if (ret < 0)
+ return ret;
#endif
+
+ if (dev_read_bool(dev, "cap-mmc-highspeed") || \
+ dev_read_bool(dev, "cap-sd-highspeed"))
+ chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+ ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
+ priv->minmax[1] , priv->minmax[0]);
+ chip->mmc = &plat->mmc;
+ chip->mmc->priv = &priv->chip;
+ chip->mmc->dev = dev;
+ upriv->mmc = chip->mmc;
+ return ftsdc010_probe(dev);
+}
+
+int ftsdc010_mmc_bind(struct udevice *dev)
+{
+ struct ftsdc010_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id ftsdc010_mmc_ids[] = {
+ { .compatible = "andestech,atsdc010" },
+ { }
+};
+
+U_BOOT_DRIVER(ftsdc010_mmc) = {
+ .name = "ftsdc010_mmc",
+ .id = UCLASS_MMC,
+ .of_match = ftsdc010_mmc_ids,
+ .ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata,
+ .ops = &dm_ftsdc010_mmc_ops,
+ .bind = ftsdc010_mmc_bind,
+ .probe = ftsdc010_mmc_probe,
+ .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
+ .platdata_auto_alloc_size = sizeof(struct ftsdc010_plat),
+};
diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h
index 31a27fd..e417360 100644
--- a/drivers/mmc/ftsdc010_mci.h
+++ b/drivers/mmc/ftsdc010_mci.h
@@ -35,19 +35,4 @@
bool fifo_mode;
};
-
-#ifdef CONFIG_DM_MMC
-/* Export the operations to drivers */
-int ftsdc010_probe(struct udevice *dev);
-extern const struct dm_mmc_ops dm_ftsdc010_ops;
-#endif
-void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
- uint caps, u32 max_clk, u32 min_clk);
-void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg);
-
-#ifdef CONFIG_BLK
-int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
-#endif
-
-
#endif /* __FTSDC010_MCI_H */
diff --git a/drivers/mmc/nds32_mmc.c b/drivers/mmc/nds32_mmc.c
deleted file mode 100644
index 6d3c857..0000000
--- a/drivers/mmc/nds32_mmc.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Andestech ATFSDC010 SD/MMC driver
- *
- * (C) Copyright 2017
- * Rick Chen, NDS32 Software Engineering, rick@andestech.com
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <dt-structs.h>
-#include <errno.h>
-#include <mapmem.h>
-#include <mmc.h>
-#include <pwrseq.h>
-#include <syscon.h>
-#include <linux/err.h>
-#include <faraday/ftsdc010.h>
-#include "ftsdc010_mci.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-struct nds_mmc {
- fdt32_t bus_width;
- bool cap_mmc_highspeed;
- bool cap_sd_highspeed;
- fdt32_t clock_freq_min_max[2];
- struct phandle_2_cell clocks[4];
- fdt32_t fifo_depth;
- fdt32_t reg[2];
-};
-#endif
-
-struct nds_mmc_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct nds_mmc dtplat;
-#endif
- struct mmc_config cfg;
- struct mmc mmc;
-};
-
-struct ftsdc_priv {
- struct clk clk;
- struct ftsdc010_chip chip;
- int fifo_depth;
- bool fifo_mode;
- u32 minmax[2];
-};
-
-static int nds32_mmc_ofdata_to_platdata(struct udevice *dev)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct ftsdc_priv *priv = dev_get_priv(dev);
- struct ftsdc010_chip *chip = &priv->chip;
- chip->name = dev->name;
- chip->ioaddr = (void *)devfdt_get_addr(dev);
- chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "bus-width", 4);
- chip->priv = dev;
- priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "fifo-depth", 0);
- priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
- "fifo-mode");
- if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
- "clock-freq-min-max", priv->minmax, 2)) {
- int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "max-frequency", -EINVAL);
- if (val < 0)
- return val;
-
- priv->minmax[0] = 400000; /* 400 kHz */
- priv->minmax[1] = val;
- } else {
- debug("%s: 'clock-freq-min-max' property was deprecated.\n",
- __func__);
- }
-#endif
- chip->sclk = priv->minmax[1];
- chip->regs = chip->ioaddr;
- return 0;
-}
-
-static int nds32_mmc_probe(struct udevice *dev)
-{
- struct nds_mmc_plat *plat = dev_get_platdata(dev);
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct ftsdc_priv *priv = dev_get_priv(dev);
- struct ftsdc010_chip *chip = &priv->chip;
- struct udevice *pwr_dev __maybe_unused;
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- int ret;
- struct nds_mmc *dtplat = &plat->dtplat;
- chip->name = dev->name;
- chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
- chip->buswidth = dtplat->bus_width;
- chip->priv = dev;
- chip->dev_index = 1;
- memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
- ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
- if (ret < 0)
- return ret;
-#endif
- ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
- priv->minmax[1] , priv->minmax[0]);
- chip->mmc = &plat->mmc;
- chip->mmc->priv = &priv->chip;
- chip->mmc->dev = dev;
- upriv->mmc = chip->mmc;
- return ftsdc010_probe(dev);
-}
-
-static int nds32_mmc_bind(struct udevice *dev)
-{
- struct nds_mmc_plat *plat = dev_get_platdata(dev);
- return ftsdc010_bind(dev, &plat->mmc, &plat->cfg);
-}
-
-static const struct udevice_id nds32_mmc_ids[] = {
- { .compatible = "andestech,atsdc010" },
- { }
-};
-
-U_BOOT_DRIVER(nds32_mmc_drv) = {
- .name = "nds32_mmc",
- .id = UCLASS_MMC,
- .of_match = nds32_mmc_ids,
- .ofdata_to_platdata = nds32_mmc_ofdata_to_platdata,
- .ops = &dm_ftsdc010_ops,
- .bind = nds32_mmc_bind,
- .probe = nds32_mmc_probe,
- .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
- .platdata_auto_alloc_size = sizeof(struct nds_mmc_plat),
-};
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 05c0044..b7a2ebf 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -29,11 +29,10 @@
struct pci_mmc_plat *plat = dev_get_platdata(dev);
struct pci_mmc_priv *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
- u32 ioaddr;
int ret;
- dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &ioaddr);
- host->ioaddr = map_sysmem(ioaddr, 0);
+ host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
+ PCI_REGION_MEM);
host->name = dev->name;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
new file mode 100644
index 0000000..56a43ca
--- /dev/null
+++ b/drivers/mmc/renesas-sdhi.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <fdtdec.h>
+#include <mmc.h>
+#include <dm.h>
+#include <linux/compat.h>
+#include <linux/dma-direction.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <power/regulator.h>
+#include <asm/unaligned.h>
+
+#include "tmio-common.h"
+
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+
+/* SCC registers */
+#define RENESAS_SDHI_SCC_DTCNTL 0x800
+#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
+#define RENESAS_SDHI_SCC_TAPSET 0x804
+#define RENESAS_SDHI_SCC_DT2FF 0x808
+#define RENESAS_SDHI_SCC_CKSEL 0x80c
+#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
+#define RENESAS_SDHI_SCC_RVSCNTL 0x810
+#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
+#define RENESAS_SDHI_SCC_RVSREQ 0x814
+#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
+#define RENESAS_SDHI_SCC_SMPCMP 0x818
+#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
+
+#define RENESAS_SDHI_MAX_TAP 3
+
+static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
+{
+ u32 reg;
+
+ /* Initialize SCC */
+ tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
+
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg &= ~TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
+
+ /* Set sampling clock selection range */
+ tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
+ RENESAS_SDHI_SCC_DTCNTL);
+
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
+ reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
+
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
+ reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
+
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+
+ tmio_sd_writel(priv, 0x300 /* scc_tappos */,
+ RENESAS_SDHI_SCC_DT2FF);
+
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg |= TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
+
+ /* Read TAPNUM */
+ return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
+ RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
+ RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
+}
+
+static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
+{
+ u32 reg;
+
+ /* Reset SCC */
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg &= ~TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
+
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
+ reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
+
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg |= TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
+
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+}
+
+static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
+ unsigned long tap)
+{
+ /* Set sampling clock position */
+ tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
+}
+
+static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
+{
+ /* Get comparison of sampling data */
+ return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
+}
+
+static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
+ unsigned int tap_num, unsigned int taps,
+ unsigned int smpcmp)
+{
+ unsigned long tap_cnt; /* counter of tuning success */
+ unsigned long tap_set; /* tap position */
+ unsigned long tap_start;/* start position of tuning success */
+ unsigned long tap_end; /* end position of tuning success */
+ unsigned long ntap; /* temporary counter of tuning success */
+ unsigned long match_cnt;/* counter of matching data */
+ unsigned long i;
+ bool select = false;
+ u32 reg;
+
+ /* Clear SCC_RVSREQ */
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
+
+ /* Merge the results */
+ for (i = 0; i < tap_num * 2; i++) {
+ if (!(taps & BIT(i))) {
+ taps &= ~BIT(i % tap_num);
+ taps &= ~BIT((i % tap_num) + tap_num);
+ }
+ if (!(smpcmp & BIT(i))) {
+ smpcmp &= ~BIT(i % tap_num);
+ smpcmp &= ~BIT((i % tap_num) + tap_num);
+ }
+ }
+
+ /*
+ * Find the longest consecutive run of successful probes. If that
+ * is more than RENESAS_SDHI_MAX_TAP probes long then use the
+ * center index as the tap.
+ */
+ tap_cnt = 0;
+ ntap = 0;
+ tap_start = 0;
+ tap_end = 0;
+ for (i = 0; i < tap_num * 2; i++) {
+ if (taps & BIT(i))
+ ntap++;
+ else {
+ if (ntap > tap_cnt) {
+ tap_start = i - ntap;
+ tap_end = i - 1;
+ tap_cnt = ntap;
+ }
+ ntap = 0;
+ }
+ }
+
+ if (ntap > tap_cnt) {
+ tap_start = i - ntap;
+ tap_end = i - 1;
+ tap_cnt = ntap;
+ }
+
+ /*
+ * If all of the TAP is OK, the sampling clock position is selected by
+ * identifying the change point of data.
+ */
+ if (tap_cnt == tap_num * 2) {
+ match_cnt = 0;
+ ntap = 0;
+ tap_start = 0;
+ tap_end = 0;
+ for (i = 0; i < tap_num * 2; i++) {
+ if (smpcmp & BIT(i))
+ ntap++;
+ else {
+ if (ntap > match_cnt) {
+ tap_start = i - ntap;
+ tap_end = i - 1;
+ match_cnt = ntap;
+ }
+ ntap = 0;
+ }
+ }
+ if (ntap > match_cnt) {
+ tap_start = i - ntap;
+ tap_end = i - 1;
+ match_cnt = ntap;
+ }
+ if (match_cnt)
+ select = true;
+ } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
+ select = true;
+
+ if (select)
+ tap_set = ((tap_start + tap_end) / 2) % tap_num;
+ else
+ return -EIO;
+
+ /* Set SCC */
+ tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
+
+ /* Enable auto re-tuning */
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+
+ return 0;
+}
+
+int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct mmc *mmc = upriv->mmc;
+ unsigned int tap_num;
+ unsigned int taps = 0, smpcmp = 0;
+ int i, ret = 0;
+ u32 caps;
+
+ /* Only supported on Renesas RCar */
+ if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
+ return -EINVAL;
+
+ /* clock tuning is not needed for upto 52MHz */
+ if (!((mmc->selected_mode == MMC_HS_200) ||
+ (mmc->selected_mode == UHS_SDR104) ||
+ (mmc->selected_mode == UHS_SDR50)))
+ return 0;
+
+ tap_num = renesas_sdhi_init_tuning(priv);
+ if (!tap_num)
+ /* Tuning is not supported */
+ goto out;
+
+ if (tap_num * 2 >= sizeof(taps) * 8) {
+ dev_err(dev,
+ "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
+ goto out;
+ }
+
+ /* Issue CMD19 twice for each tap */
+ for (i = 0; i < 2 * tap_num; i++) {
+ renesas_sdhi_prepare_tuning(priv, i % tap_num);
+
+ /* Force PIO for the tuning */
+ caps = priv->caps;
+ priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
+
+ ret = mmc_send_tuning(mmc, opcode, NULL);
+
+ priv->caps = caps;
+
+ if (ret == 0)
+ taps |= BIT(i);
+
+ ret = renesas_sdhi_compare_scc_data(priv);
+ if (ret == 0)
+ smpcmp |= BIT(i);
+
+ mdelay(1);
+ }
+
+ ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
+
+out:
+ if (ret < 0) {
+ dev_warn(dev, "Tuning procedure failed\n");
+ renesas_sdhi_reset_tuning(priv);
+ }
+
+ return ret;
+}
+#endif
+
+static int renesas_sdhi_set_ios(struct udevice *dev)
+{
+ int ret = tmio_sd_set_ios(dev);
+
+ mdelay(10);
+
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+
+ renesas_sdhi_reset_tuning(priv);
+#endif
+
+ return ret;
+}
+
+static const struct dm_mmc_ops renesas_sdhi_ops = {
+ .send_cmd = tmio_sd_send_cmd,
+ .set_ios = renesas_sdhi_set_ios,
+ .get_cd = tmio_sd_get_cd,
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ .execute_tuning = renesas_sdhi_execute_tuning,
+#endif
+};
+
+#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
+#define RENESAS_GEN3_QUIRKS \
+ TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
+
+static const struct udevice_id renesas_sdhi_match[] = {
+ { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
+ { /* sentinel */ }
+};
+
+static int renesas_sdhi_probe(struct udevice *dev)
+{
+ u32 quirks = dev_get_driver_data(dev);
+ struct fdt_resource reg_res;
+ DECLARE_GLOBAL_DATA_PTR;
+ int ret;
+
+ if (quirks == RENESAS_GEN2_QUIRKS) {
+ ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
+ "reg", 0, ®_res);
+ if (ret < 0) {
+ dev_err(dev, "\"reg\" resource not found, ret=%i\n",
+ ret);
+ return ret;
+ }
+
+ if (fdt_resource_size(®_res) == 0x100)
+ quirks |= TMIO_SD_CAP_16BIT;
+ }
+
+ ret = tmio_sd_probe(dev, quirks);
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ if (!ret)
+ renesas_sdhi_reset_tuning(dev_get_priv(dev));
+#endif
+ return ret;
+}
+
+U_BOOT_DRIVER(renesas_sdhi) = {
+ .name = "renesas-sdhi",
+ .id = UCLASS_MMC,
+ .of_match = renesas_sdhi_match,
+ .bind = tmio_sd_bind,
+ .probe = renesas_sdhi_probe,
+ .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
+ .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
+ .ops = &renesas_sdhi_ops,
+};
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index be6edb2..ab89be4 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -62,6 +62,13 @@
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
host->max_clk = max_frequency;
+ /*
+ * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
+ * doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't
+ * check for other bus-width values.
+ */
+ if (host->bus_width == 8)
+ host->host_caps |= MMC_MODE_8BIT;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
@@ -82,6 +89,7 @@
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
#endif
return 0;
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index bd2200a..f5b21dd 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -72,7 +72,10 @@
#define SDMMC_CLKCR_HWFC_EN BIT(17)
#define SDMMC_CLKCR_DDR BIT(18)
#define SDMMC_CLKCR_BUSSPEED BIT(19)
-#define SDMMC_CLKCR_SELCLKRX GENMASK(21, 20)
+#define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
+#define SDMMC_CLKCR_SELCLKRX_CK 0
+#define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
+#define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
/* SDMMC_CMD register */
#define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
@@ -495,7 +498,8 @@
if (mmc->bus_width == 8)
clk |= SDMMC_CLKCR_WIDBUS_8;
- writel(clk | priv->clk_reg_msk, priv->base + SDMMC_CLKCR);
+ writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
+ priv->base + SDMMC_CLKCR);
return 0;
}
@@ -534,6 +538,8 @@
priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
if (dev_read_bool(dev, "st,dirpol"))
priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
+ if (dev_read_bool(dev, "st,pin-ckin"))
+ priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4edb4be..df6f328 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -30,6 +30,7 @@
uint32_t *mclkreg;
unsigned fatal_err;
struct gpio_desc cd_gpio; /* Change Detect GPIO */
+ int cd_inverted; /* Inverted Card Detect */
struct sunxi_mmc *reg;
struct mmc_config cfg;
};
@@ -544,9 +545,11 @@
{
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
- if (dm_gpio_is_valid(&priv->cd_gpio))
- return dm_gpio_get_value(&priv->cd_gpio);
+ if (dm_gpio_is_valid(&priv->cd_gpio)) {
+ int cd_state = dm_gpio_get_value(&priv->cd_gpio);
+ return cd_state ^ priv->cd_inverted;
+ }
return 1;
}
@@ -610,6 +613,9 @@
sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
}
+ /* Check if card detect is inverted */
+ priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
+
upriv->mmc = &plat->mmc;
/* Reset controller */
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
new file mode 100644
index 0000000..5f1c9c0
--- /dev/null
+++ b/drivers/mmc/tmio-common.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <fdtdec.h>
+#include <mmc.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <linux/compat.h>
+#include <linux/dma-direction.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <power/regulator.h>
+#include <asm/unaligned.h>
+
+#include "tmio-common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
+{
+ return readq(priv->regbase + (reg << 1));
+}
+
+static void tmio_sd_writeq(struct tmio_sd_priv *priv,
+ u64 val, unsigned int reg)
+{
+ writeq(val, priv->regbase + (reg << 1));
+}
+
+static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
+{
+ return readw(priv->regbase + (reg >> 1));
+}
+
+static void tmio_sd_writew(struct tmio_sd_priv *priv,
+ u16 val, unsigned int reg)
+{
+ writew(val, priv->regbase + (reg >> 1));
+}
+
+u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
+{
+ u32 val;
+
+ if (priv->caps & TMIO_SD_CAP_64BIT)
+ return readl(priv->regbase + (reg << 1));
+ else if (priv->caps & TMIO_SD_CAP_16BIT) {
+ val = readw(priv->regbase + (reg >> 1)) & 0xffff;
+ if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
+ (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
+ val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
+ }
+ return val;
+ } else
+ return readl(priv->regbase + reg);
+}
+
+void tmio_sd_writel(struct tmio_sd_priv *priv,
+ u32 val, unsigned int reg)
+{
+ if (priv->caps & TMIO_SD_CAP_64BIT)
+ writel(val, priv->regbase + (reg << 1));
+ else if (priv->caps & TMIO_SD_CAP_16BIT) {
+ writew(val & 0xffff, priv->regbase + (reg >> 1));
+ if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
+ reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
+ reg == TMIO_SD_ARG)
+ writew(val >> 16, priv->regbase + (reg >> 1) + 2);
+ } else
+ writel(val, priv->regbase + reg);
+}
+
+static dma_addr_t __dma_map_single(void *ptr, size_t size,
+ enum dma_data_direction dir)
+{
+ unsigned long addr = (unsigned long)ptr;
+
+ if (dir == DMA_FROM_DEVICE)
+ invalidate_dcache_range(addr, addr + size);
+ else
+ flush_dcache_range(addr, addr + size);
+
+ return addr;
+}
+
+static void __dma_unmap_single(dma_addr_t addr, size_t size,
+ enum dma_data_direction dir)
+{
+ if (dir != DMA_TO_DEVICE)
+ invalidate_dcache_range(addr, addr + size);
+}
+
+static int tmio_sd_check_error(struct udevice *dev)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
+
+ if (info2 & TMIO_SD_INFO2_ERR_RTO) {
+ /*
+ * TIMEOUT must be returned for unsupported command. Do not
+ * display error log since this might be a part of sequence to
+ * distinguish between SD and MMC.
+ */
+ return -ETIMEDOUT;
+ }
+
+ if (info2 & TMIO_SD_INFO2_ERR_TO) {
+ dev_err(dev, "timeout error\n");
+ return -ETIMEDOUT;
+ }
+
+ if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
+ TMIO_SD_INFO2_ERR_IDX)) {
+ dev_err(dev, "communication out of sync\n");
+ return -EILSEQ;
+ }
+
+ if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
+ TMIO_SD_INFO2_ERR_ILW)) {
+ dev_err(dev, "illegal access\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
+ u32 flag)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ long wait = 1000000;
+ int ret;
+
+ while (!(tmio_sd_readl(priv, reg) & flag)) {
+ if (wait-- < 0) {
+ dev_err(dev, "timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ ret = tmio_sd_check_error(dev);
+ if (ret)
+ return ret;
+
+ udelay(1);
+ }
+
+ return 0;
+}
+
+#define tmio_pio_read_fifo(__width, __suffix) \
+static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
+ char *pbuf, uint blksz) \
+{ \
+ u##__width *buf = (u##__width *)pbuf; \
+ int i; \
+ \
+ if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
+ for (i = 0; i < blksz / ((__width) / 8); i++) { \
+ *buf++ = tmio_sd_read##__suffix(priv, \
+ TMIO_SD_BUF); \
+ } \
+ } else { \
+ for (i = 0; i < blksz / ((__width) / 8); i++) { \
+ u##__width data; \
+ data = tmio_sd_read##__suffix(priv, \
+ TMIO_SD_BUF); \
+ put_unaligned(data, buf++); \
+ } \
+ } \
+}
+
+tmio_pio_read_fifo(64, q)
+tmio_pio_read_fifo(32, l)
+tmio_pio_read_fifo(16, w)
+
+static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
+ uint blocksize)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* wait until the buffer is filled with data */
+ ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
+ TMIO_SD_INFO2_BRE);
+ if (ret)
+ return ret;
+
+ /*
+ * Clear the status flag _before_ read the buffer out because
+ * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
+ */
+ tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
+
+ if (priv->caps & TMIO_SD_CAP_64BIT)
+ tmio_pio_read_fifo_64(priv, pbuf, blocksize);
+ else if (priv->caps & TMIO_SD_CAP_16BIT)
+ tmio_pio_read_fifo_16(priv, pbuf, blocksize);
+ else
+ tmio_pio_read_fifo_32(priv, pbuf, blocksize);
+
+ return 0;
+}
+
+#define tmio_pio_write_fifo(__width, __suffix) \
+static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
+ const char *pbuf, uint blksz)\
+{ \
+ const u##__width *buf = (const u##__width *)pbuf; \
+ int i; \
+ \
+ if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
+ for (i = 0; i < blksz / ((__width) / 8); i++) { \
+ tmio_sd_write##__suffix(priv, *buf++, \
+ TMIO_SD_BUF); \
+ } \
+ } else { \
+ for (i = 0; i < blksz / ((__width) / 8); i++) { \
+ u##__width data = get_unaligned(buf++); \
+ tmio_sd_write##__suffix(priv, data, \
+ TMIO_SD_BUF); \
+ } \
+ } \
+}
+
+tmio_pio_write_fifo(64, q)
+tmio_pio_write_fifo(32, l)
+tmio_pio_write_fifo(16, w)
+
+static int tmio_sd_pio_write_one_block(struct udevice *dev,
+ const char *pbuf, uint blocksize)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* wait until the buffer becomes empty */
+ ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
+ TMIO_SD_INFO2_BWE);
+ if (ret)
+ return ret;
+
+ tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
+
+ if (priv->caps & TMIO_SD_CAP_64BIT)
+ tmio_pio_write_fifo_64(priv, pbuf, blocksize);
+ else if (priv->caps & TMIO_SD_CAP_16BIT)
+ tmio_pio_write_fifo_16(priv, pbuf, blocksize);
+ else
+ tmio_pio_write_fifo_32(priv, pbuf, blocksize);
+
+ return 0;
+}
+
+static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
+{
+ const char *src = data->src;
+ char *dest = data->dest;
+ int i, ret;
+
+ for (i = 0; i < data->blocks; i++) {
+ if (data->flags & MMC_DATA_READ)
+ ret = tmio_sd_pio_read_one_block(dev, dest,
+ data->blocksize);
+ else
+ ret = tmio_sd_pio_write_one_block(dev, src,
+ data->blocksize);
+ if (ret)
+ return ret;
+
+ if (data->flags & MMC_DATA_READ)
+ dest += data->blocksize;
+ else
+ src += data->blocksize;
+ }
+
+ return 0;
+}
+
+static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
+ dma_addr_t dma_addr)
+{
+ u32 tmp;
+
+ tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
+ tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
+
+ /* enable DMA */
+ tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
+ tmp |= TMIO_SD_EXTMODE_DMA_EN;
+ tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
+
+ tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
+
+ /* suppress the warning "right shift count >= width of type" */
+ dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
+
+ tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
+
+ tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
+}
+
+static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
+ unsigned int blocks)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ long wait = 1000000 + 10 * blocks;
+
+ while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
+ if (wait-- < 0) {
+ dev_err(dev, "timeout during DMA\n");
+ return -ETIMEDOUT;
+ }
+
+ udelay(10);
+ }
+
+ if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
+ dev_err(dev, "error during DMA\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ size_t len = data->blocks * data->blocksize;
+ void *buf;
+ enum dma_data_direction dir;
+ dma_addr_t dma_addr;
+ u32 poll_flag, tmp;
+ int ret;
+
+ tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
+
+ if (data->flags & MMC_DATA_READ) {
+ buf = data->dest;
+ dir = DMA_FROM_DEVICE;
+ /*
+ * The DMA READ completion flag position differs on Socionext
+ * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
+ * bit 17 is a hardware bug and forbidden. It is bit 17 on
+ * Renesas SoCs and bit 20 does not work on them.
+ */
+ poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ?
+ TMIO_SD_DMA_INFO1_END_RD :
+ TMIO_SD_DMA_INFO1_END_RD2;
+ tmp |= TMIO_SD_DMA_MODE_DIR_RD;
+ } else {
+ buf = (void *)data->src;
+ dir = DMA_TO_DEVICE;
+ poll_flag = TMIO_SD_DMA_INFO1_END_WR;
+ tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
+ }
+
+ tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
+
+ dma_addr = __dma_map_single(buf, len, dir);
+
+ tmio_sd_dma_start(priv, dma_addr);
+
+ ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
+
+ __dma_unmap_single(dma_addr, len, dir);
+
+ return ret;
+}
+
+/* check if the address is DMA'able */
+static bool tmio_sd_addr_is_dmaable(unsigned long addr)
+{
+ if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
+ return false;
+
+#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
+ defined(CONFIG_SPL_BUILD)
+ /*
+ * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
+ * of L2, which is unreachable from the DMA engine.
+ */
+ if (addr < CONFIG_SPL_STACK)
+ return false;
+#endif
+
+ return true;
+}
+
+int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ int ret;
+ u32 tmp;
+
+ if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
+ dev_err(dev, "command busy\n");
+ return -EBUSY;
+ }
+
+ /* clear all status flags */
+ tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
+ tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
+
+ /* disable DMA once */
+ tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
+ tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
+ tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
+
+ tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
+
+ tmp = cmd->cmdidx;
+
+ if (data) {
+ tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
+ tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
+
+ /* Do not send CMD12 automatically */
+ tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
+
+ if (data->blocks > 1)
+ tmp |= TMIO_SD_CMD_MULTI;
+
+ if (data->flags & MMC_DATA_READ)
+ tmp |= TMIO_SD_CMD_RD;
+ }
+
+ /*
+ * Do not use the response type auto-detection on this hardware.
+ * CMD8, for example, has different response types on SD and eMMC,
+ * while this controller always assumes the response type for SD.
+ * Set the response type manually.
+ */
+ switch (cmd->resp_type) {
+ case MMC_RSP_NONE:
+ tmp |= TMIO_SD_CMD_RSP_NONE;
+ break;
+ case MMC_RSP_R1:
+ tmp |= TMIO_SD_CMD_RSP_R1;
+ break;
+ case MMC_RSP_R1b:
+ tmp |= TMIO_SD_CMD_RSP_R1B;
+ break;
+ case MMC_RSP_R2:
+ tmp |= TMIO_SD_CMD_RSP_R2;
+ break;
+ case MMC_RSP_R3:
+ tmp |= TMIO_SD_CMD_RSP_R3;
+ break;
+ default:
+ dev_err(dev, "unknown response type\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
+ cmd->cmdidx, tmp, cmd->cmdarg);
+ tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
+
+ ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
+ TMIO_SD_INFO1_RSP);
+ if (ret)
+ return ret;
+
+ if (cmd->resp_type & MMC_RSP_136) {
+ u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
+ u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
+ u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
+ u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
+
+ cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
+ ((rsp_103_72 & 0xff000000) >> 24);
+ cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
+ ((rsp_71_40 & 0xff000000) >> 24);
+ cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
+ ((rsp_39_8 & 0xff000000) >> 24);
+ cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
+ } else {
+ /* bit 39-8 */
+ cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
+ }
+
+ if (data) {
+ /* use DMA if the HW supports it and the buffer is aligned */
+ if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
+ tmio_sd_addr_is_dmaable((long)data->src))
+ ret = tmio_sd_dma_xfer(dev, data);
+ else
+ ret = tmio_sd_pio_xfer(dev, data);
+
+ ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
+ TMIO_SD_INFO1_CMP);
+ if (ret)
+ return ret;
+ }
+
+ tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN);
+
+ return ret;
+}
+
+static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
+ struct mmc *mmc)
+{
+ u32 val, tmp;
+
+ switch (mmc->bus_width) {
+ case 0:
+ case 1:
+ val = TMIO_SD_OPTION_WIDTH_1;
+ break;
+ case 4:
+ val = TMIO_SD_OPTION_WIDTH_4;
+ break;
+ case 8:
+ val = TMIO_SD_OPTION_WIDTH_8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
+ tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
+ tmp |= val;
+ tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
+
+ return 0;
+}
+
+static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
+ struct mmc *mmc)
+{
+ u32 tmp;
+
+ tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
+ if (mmc->ddr_mode)
+ tmp |= TMIO_SD_IF_MODE_DDR;
+ else
+ tmp &= ~TMIO_SD_IF_MODE_DDR;
+ tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
+}
+
+static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
+ struct mmc *mmc)
+{
+ unsigned int divisor;
+ u32 val, tmp;
+
+ if (!mmc->clock)
+ return;
+
+ divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
+
+ if (divisor <= 1)
+ val = (priv->caps & TMIO_SD_CAP_RCAR) ?
+ TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
+ else if (divisor <= 2)
+ val = TMIO_SD_CLKCTL_DIV2;
+ else if (divisor <= 4)
+ val = TMIO_SD_CLKCTL_DIV4;
+ else if (divisor <= 8)
+ val = TMIO_SD_CLKCTL_DIV8;
+ else if (divisor <= 16)
+ val = TMIO_SD_CLKCTL_DIV16;
+ else if (divisor <= 32)
+ val = TMIO_SD_CLKCTL_DIV32;
+ else if (divisor <= 64)
+ val = TMIO_SD_CLKCTL_DIV64;
+ else if (divisor <= 128)
+ val = TMIO_SD_CLKCTL_DIV128;
+ else if (divisor <= 256)
+ val = TMIO_SD_CLKCTL_DIV256;
+ else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
+ val = TMIO_SD_CLKCTL_DIV512;
+ else
+ val = TMIO_SD_CLKCTL_DIV1024;
+
+ tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ if (tmp & TMIO_SD_CLKCTL_SCLKEN &&
+ (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val)
+ return;
+
+ /* stop the clock before changing its rate to avoid a glitch signal */
+ tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
+
+ tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
+ tmp |= val | TMIO_SD_CLKCTL_OFFEN;
+ tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
+
+ tmp |= TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
+
+ udelay(1000);
+}
+
+static void tmio_sd_set_pins(struct udevice *dev)
+{
+ __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+#ifdef CONFIG_DM_REGULATOR
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+
+ if (priv->vqmmc_dev) {
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+ regulator_set_value(priv->vqmmc_dev, 1800000);
+ else
+ regulator_set_value(priv->vqmmc_dev, 3300000);
+ regulator_set_enable(priv->vqmmc_dev, true);
+ }
+#endif
+
+#ifdef CONFIG_PINCTRL
+ switch (mmc->selected_mode) {
+ case MMC_LEGACY:
+ case SD_LEGACY:
+ case MMC_HS:
+ case SD_HS:
+ case MMC_HS_52:
+ case MMC_DDR_52:
+ pinctrl_select_state(dev, "default");
+ break;
+ case UHS_SDR12:
+ case UHS_SDR25:
+ case UHS_SDR50:
+ case UHS_DDR50:
+ case UHS_SDR104:
+ case MMC_HS_200:
+ pinctrl_select_state(dev, "state_uhs");
+ break;
+ default:
+ break;
+ }
+#endif
+}
+
+int tmio_sd_set_ios(struct udevice *dev)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ int ret;
+
+ dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
+ mmc->clock, mmc->ddr_mode, mmc->bus_width);
+
+ ret = tmio_sd_set_bus_width(priv, mmc);
+ if (ret)
+ return ret;
+ tmio_sd_set_ddr_mode(priv, mmc);
+ tmio_sd_set_clk_rate(priv, mmc);
+ tmio_sd_set_pins(dev);
+
+ return 0;
+}
+
+int tmio_sd_get_cd(struct udevice *dev)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+
+ if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
+ return 1;
+
+ return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
+ TMIO_SD_INFO1_CD);
+}
+
+static void tmio_sd_host_init(struct tmio_sd_priv *priv)
+{
+ u32 tmp;
+
+ /* soft reset of the host */
+ tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
+ tmp &= ~TMIO_SD_SOFT_RST_RSTX;
+ tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
+ tmp |= TMIO_SD_SOFT_RST_RSTX;
+ tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
+
+ /* FIXME: implement eMMC hw_reset */
+
+ tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
+
+ /*
+ * Connected to 32bit AXI.
+ * This register dropped backward compatibility at version 0x10.
+ * Write an appropriate value depending on the IP version.
+ */
+ if (priv->version >= 0x10)
+ tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
+ else
+ tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
+
+ if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
+ tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
+ tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
+ tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
+ }
+}
+
+int tmio_sd_bind(struct udevice *dev)
+{
+ struct tmio_sd_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+int tmio_sd_probe(struct udevice *dev, u32 quirks)
+{
+ struct tmio_sd_plat *plat = dev_get_platdata(dev);
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ fdt_addr_t base;
+ struct clk clk;
+ int ret;
+
+ base = devfdt_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regbase = devm_ioremap(dev, base, SZ_2K);
+ if (!priv->regbase)
+ return -ENOMEM;
+
+#ifdef CONFIG_DM_REGULATOR
+ device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
+#endif
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get host clock\n");
+ return ret;
+ }
+
+ /* set to max rate */
+ priv->mclk = clk_set_rate(&clk, ULONG_MAX);
+ if (IS_ERR_VALUE(priv->mclk)) {
+ dev_err(dev, "failed to set rate for host clock\n");
+ clk_free(&clk);
+ return priv->mclk;
+ }
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable host clock\n");
+ return ret;
+ }
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret < 0) {
+ dev_err(dev, "failed to parse host caps\n");
+ return ret;
+ }
+
+ plat->cfg.name = dev->name;
+ plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ if (quirks)
+ priv->caps = quirks;
+
+ priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
+ TMIO_SD_VERSION_IP;
+ dev_dbg(dev, "version %x\n", priv->version);
+ if (priv->version >= 0x10) {
+ priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
+ priv->caps |= TMIO_SD_CAP_DIV1024;
+ }
+
+ if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
+ NULL))
+ priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
+
+ tmio_sd_host_init(priv);
+
+ plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+ plat->cfg.f_min = priv->mclk /
+ (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
+ plat->cfg.f_max = priv->mclk;
+ plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
+
+ upriv->mmc = &plat->mmc;
+
+ return 0;
+}
diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
new file mode 100644
index 0000000..ef94044
--- /dev/null
+++ b/drivers/mmc/tmio-common.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TMIO_COMMON_H__
+#define __TMIO_COMMON_H__
+
+#define TMIO_SD_CMD 0x000 /* command */
+#define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
+#define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
+#define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
+#define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
+#define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
+#define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
+#define TMIO_SD_CMD_RSP_NONE (3 << 8)/* response: none */
+#define TMIO_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
+#define TMIO_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
+#define TMIO_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
+#define TMIO_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
+#define TMIO_SD_ARG 0x008 /* command argument */
+#define TMIO_SD_STOP 0x010 /* stop action control */
+#define TMIO_SD_STOP_SEC BIT(8) /* use sector count */
+#define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
+#define TMIO_SD_SECCNT 0x014 /* sector counter */
+#define TMIO_SD_RSP10 0x018 /* response[39:8] */
+#define TMIO_SD_RSP32 0x020 /* response[71:40] */
+#define TMIO_SD_RSP54 0x028 /* response[103:72] */
+#define TMIO_SD_RSP76 0x030 /* response[127:104] */
+#define TMIO_SD_INFO1 0x038 /* IRQ status 1 */
+#define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */
+#define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */
+#define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */
+#define TMIO_SD_INFO1_CMP BIT(2) /* data complete */
+#define TMIO_SD_INFO1_RSP BIT(0) /* response complete */
+#define TMIO_SD_INFO2 0x03c /* IRQ status 2 */
+#define TMIO_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
+#define TMIO_SD_INFO2_CBSY BIT(14) /* command busy */
+#define TMIO_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
+#define TMIO_SD_INFO2_BWE BIT(9) /* write buffer ready */
+#define TMIO_SD_INFO2_BRE BIT(8) /* read buffer ready */
+#define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
+#define TMIO_SD_INFO2_ERR_RTO BIT(6) /* response time out */
+#define TMIO_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
+#define TMIO_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
+#define TMIO_SD_INFO2_ERR_TO BIT(3) /* time out error */
+#define TMIO_SD_INFO2_ERR_END BIT(2) /* END bit error */
+#define TMIO_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
+#define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
+#define TMIO_SD_INFO1_MASK 0x040
+#define TMIO_SD_INFO2_MASK 0x044
+#define TMIO_SD_CLKCTL 0x048 /* clock divisor */
+#define TMIO_SD_CLKCTL_DIV_MASK 0x104ff
+#define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
+#define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
+#define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
+#define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
+#define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
+#define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
+#define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
+#define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
+#define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
+#define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
+#define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
+#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
+#define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
+#define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
+#define TMIO_SD_SIZE 0x04c /* block size */
+#define TMIO_SD_OPTION 0x050
+#define TMIO_SD_OPTION_WIDTH_MASK (5 << 13)
+#define TMIO_SD_OPTION_WIDTH_1 (4 << 13)
+#define TMIO_SD_OPTION_WIDTH_4 (0 << 13)
+#define TMIO_SD_OPTION_WIDTH_8 (1 << 13)
+#define TMIO_SD_BUF 0x060 /* read/write buffer */
+#define TMIO_SD_EXTMODE 0x1b0
+#define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
+#define TMIO_SD_SOFT_RST 0x1c0
+#define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
+#define TMIO_SD_VERSION 0x1c4 /* version register */
+#define TMIO_SD_VERSION_IP 0xff /* IP version */
+#define TMIO_SD_HOST_MODE 0x1c8
+#define TMIO_SD_IF_MODE 0x1cc
+#define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */
+#define TMIO_SD_VOLT 0x1e4 /* voltage switch */
+#define TMIO_SD_VOLT_MASK (3 << 0)
+#define TMIO_SD_VOLT_OFF (0 << 0)
+#define TMIO_SD_VOLT_330 (1 << 0)/* 3.3V signal */
+#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
+#define TMIO_SD_DMA_MODE 0x410
+#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
+#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
+#define TMIO_SD_DMA_CTL 0x414
+#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
+#define TMIO_SD_DMA_RST 0x418
+#define TMIO_SD_DMA_RST_RD BIT(9)
+#define TMIO_SD_DMA_RST_WR BIT(8)
+#define TMIO_SD_DMA_INFO1 0x420
+#define TMIO_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
+#define TMIO_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
+#define TMIO_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
+#define TMIO_SD_DMA_INFO1_MASK 0x424
+#define TMIO_SD_DMA_INFO2 0x428
+#define TMIO_SD_DMA_INFO2_ERR_RD BIT(17)
+#define TMIO_SD_DMA_INFO2_ERR_WR BIT(16)
+#define TMIO_SD_DMA_INFO2_MASK 0x42c
+#define TMIO_SD_DMA_ADDR_L 0x440
+#define TMIO_SD_DMA_ADDR_H 0x444
+
+/* alignment required by the DMA engine of this controller */
+#define TMIO_SD_DMA_MINALIGN 0x10
+
+struct tmio_sd_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct tmio_sd_priv {
+ void __iomem *regbase;
+ unsigned long mclk;
+ unsigned int version;
+ u32 caps;
+#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
+#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
+#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
+#define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
+#define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */
+#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */
+#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */
+#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */
+#define TMIO_SD_CAP_RCAR \
+ (TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
+#ifdef CONFIG_DM_REGULATOR
+ struct udevice *vqmmc_dev;
+#endif
+};
+
+int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data);
+int tmio_sd_set_ios(struct udevice *dev);
+int tmio_sd_get_cd(struct udevice *dev);
+
+int tmio_sd_bind(struct udevice *dev);
+int tmio_sd_probe(struct udevice *dev, u32 quirks);
+
+u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg);
+void tmio_sd_writel(struct tmio_sd_priv *priv,
+ u32 val, unsigned int reg);
+
+#endif /* __TMIO_COMMON_H__ */
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 525b170..47379b0 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -17,857 +17,31 @@
#include <power/regulator.h>
#include <asm/unaligned.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UNIPHIER_SD_CMD 0x000 /* command */
-#define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
-#define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
-#define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
-#define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
-#define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
-#define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
-#define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
-#define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
-#define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
-#define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
-#define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
-#define UNIPHIER_SD_ARG 0x008 /* command argument */
-#define UNIPHIER_SD_STOP 0x010 /* stop action control */
-#define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
-#define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
-#define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
-#define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
-#define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
-#define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
-#define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
-#define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
-#define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
-#define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
-#define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
-#define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
-#define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
-#define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
-#define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
-#define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
-#define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
-#define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
-#define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
-#define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
-#define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
-#define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
-#define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
-#define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
-#define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
-#define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
-#define UNIPHIER_SD_INFO1_MASK 0x040
-#define UNIPHIER_SD_INFO2_MASK 0x044
-#define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
-#define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
-#define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
-#define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
-#define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
-#define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
-#define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
-#define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
-#define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
-#define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
-#define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
-#define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
-#define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
-#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
-#define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
-#define UNIPHIER_SD_SIZE 0x04c /* block size */
-#define UNIPHIER_SD_OPTION 0x050
-#define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
-#define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
-#define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
-#define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
-#define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
-#define UNIPHIER_SD_EXTMODE 0x1b0
-#define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
-#define UNIPHIER_SD_SOFT_RST 0x1c0
-#define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
-#define UNIPHIER_SD_VERSION 0x1c4 /* version register */
-#define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
-#define UNIPHIER_SD_HOST_MODE 0x1c8
-#define UNIPHIER_SD_IF_MODE 0x1cc
-#define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
-#define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
-#define UNIPHIER_SD_VOLT_MASK (3 << 0)
-#define UNIPHIER_SD_VOLT_OFF (0 << 0)
-#define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
-#define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
-#define UNIPHIER_SD_DMA_MODE 0x410
-#define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
-#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
-#define UNIPHIER_SD_DMA_CTL 0x414
-#define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
-#define UNIPHIER_SD_DMA_RST 0x418
-#define UNIPHIER_SD_DMA_RST_RD BIT(9)
-#define UNIPHIER_SD_DMA_RST_WR BIT(8)
-#define UNIPHIER_SD_DMA_INFO1 0x420
-#define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
-#define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
-#define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
-#define UNIPHIER_SD_DMA_INFO1_MASK 0x424
-#define UNIPHIER_SD_DMA_INFO2 0x428
-#define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
-#define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
-#define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
-#define UNIPHIER_SD_DMA_ADDR_L 0x440
-#define UNIPHIER_SD_DMA_ADDR_H 0x444
-
-/* alignment required by the DMA engine of this controller */
-#define UNIPHIER_SD_DMA_MINALIGN 0x10
-
-struct uniphier_sd_plat {
- struct mmc_config cfg;
- struct mmc mmc;
-};
-
-struct uniphier_sd_priv {
- void __iomem *regbase;
- unsigned long mclk;
- unsigned int version;
- u32 caps;
-#define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
-#define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
-#define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
-#define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
-};
-
-static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg)
-{
- if (priv->caps & UNIPHIER_SD_CAP_64BIT)
- return readq(priv->regbase + (reg << 1));
- else
- return readq(priv->regbase + reg);
-}
-
-static void uniphier_sd_writeq(struct uniphier_sd_priv *priv,
- u64 val, unsigned int reg)
-{
- if (priv->caps & UNIPHIER_SD_CAP_64BIT)
- writeq(val, priv->regbase + (reg << 1));
- else
- writeq(val, priv->regbase + reg);
-}
-
-static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
-{
- if (priv->caps & UNIPHIER_SD_CAP_64BIT)
- return readl(priv->regbase + (reg << 1));
- else
- return readl(priv->regbase + reg);
-}
-
-static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
- u32 val, unsigned int reg)
-{
- if (priv->caps & UNIPHIER_SD_CAP_64BIT)
- writel(val, priv->regbase + (reg << 1));
- else
- writel(val, priv->regbase + reg);
-}
-
-static dma_addr_t __dma_map_single(void *ptr, size_t size,
- enum dma_data_direction dir)
-{
- unsigned long addr = (unsigned long)ptr;
-
- if (dir == DMA_FROM_DEVICE)
- invalidate_dcache_range(addr, addr + size);
- else
- flush_dcache_range(addr, addr + size);
-
- return addr;
-}
-
-static void __dma_unmap_single(dma_addr_t addr, size_t size,
- enum dma_data_direction dir)
-{
- if (dir != DMA_TO_DEVICE)
- invalidate_dcache_range(addr, addr + size);
-}
-
-static int uniphier_sd_check_error(struct udevice *dev)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
-
- if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
- /*
- * TIMEOUT must be returned for unsupported command. Do not
- * display error log since this might be a part of sequence to
- * distinguish between SD and MMC.
- */
- return -ETIMEDOUT;
- }
-
- if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
- dev_err(dev, "timeout error\n");
- return -ETIMEDOUT;
- }
-
- if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
- UNIPHIER_SD_INFO2_ERR_IDX)) {
- dev_err(dev, "communication out of sync\n");
- return -EILSEQ;
- }
-
- if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
- UNIPHIER_SD_INFO2_ERR_ILW)) {
- dev_err(dev, "illegal access\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
- u32 flag)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- long wait = 1000000;
- int ret;
-
- while (!(uniphier_sd_readl(priv, reg) & flag)) {
- if (wait-- < 0) {
- dev_err(dev, "timeout\n");
- return -ETIMEDOUT;
- }
-
- ret = uniphier_sd_check_error(dev);
- if (ret)
- return ret;
-
- udelay(1);
- }
-
- return 0;
-}
-
-static int uniphier_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
- uint blocksize)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- int i, ret;
-
- /* wait until the buffer is filled with data */
- ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
- UNIPHIER_SD_INFO2_BRE);
- if (ret)
- return ret;
-
- /*
- * Clear the status flag _before_ read the buffer out because
- * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
- */
- uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
-
- if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
- u64 *buf = (u64 *)pbuf;
- if (likely(IS_ALIGNED((uintptr_t)buf, 8))) {
- for (i = 0; i < blocksize / 8; i++) {
- *buf++ = uniphier_sd_readq(priv,
- UNIPHIER_SD_BUF);
- }
- } else {
- for (i = 0; i < blocksize / 8; i++) {
- u64 data;
- data = uniphier_sd_readq(priv,
- UNIPHIER_SD_BUF);
- put_unaligned(data, buf++);
- }
- }
- } else {
- u32 *buf = (u32 *)pbuf;
- if (likely(IS_ALIGNED((uintptr_t)buf, 4))) {
- for (i = 0; i < blocksize / 4; i++) {
- *buf++ = uniphier_sd_readl(priv,
- UNIPHIER_SD_BUF);
- }
- } else {
- for (i = 0; i < blocksize / 4; i++) {
- u32 data;
- data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
- put_unaligned(data, buf++);
- }
- }
- }
-
- return 0;
-}
-
-static int uniphier_sd_pio_write_one_block(struct udevice *dev,
- const char *pbuf, uint blocksize)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- int i, ret;
-
- /* wait until the buffer becomes empty */
- ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
- UNIPHIER_SD_INFO2_BWE);
- if (ret)
- return ret;
-
- uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
-
- if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
- const u64 *buf = (const u64 *)pbuf;
- if (likely(IS_ALIGNED((uintptr_t)buf, 8))) {
- for (i = 0; i < blocksize / 8; i++) {
- uniphier_sd_writeq(priv, *buf++,
- UNIPHIER_SD_BUF);
- }
- } else {
- for (i = 0; i < blocksize / 8; i++) {
- u64 data = get_unaligned(buf++);
- uniphier_sd_writeq(priv, data,
- UNIPHIER_SD_BUF);
- }
- }
- } else {
- const u32 *buf = (const u32 *)pbuf;
- if (likely(IS_ALIGNED((uintptr_t)buf, 4))) {
- for (i = 0; i < blocksize / 4; i++) {
- uniphier_sd_writel(priv, *buf++,
- UNIPHIER_SD_BUF);
- }
- } else {
- for (i = 0; i < blocksize / 4; i++) {
- u32 data = get_unaligned(buf++);
- uniphier_sd_writel(priv, data,
- UNIPHIER_SD_BUF);
- }
- }
- }
-
- return 0;
-}
-
-static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
-{
- const char *src = data->src;
- char *dest = data->dest;
- int i, ret;
-
- for (i = 0; i < data->blocks; i++) {
- if (data->flags & MMC_DATA_READ)
- ret = uniphier_sd_pio_read_one_block(dev, dest,
- data->blocksize);
- else
- ret = uniphier_sd_pio_write_one_block(dev, src,
- data->blocksize);
- if (ret)
- return ret;
-
- if (data->flags & MMC_DATA_READ)
- dest += data->blocksize;
- else
- src += data->blocksize;
- }
-
- return 0;
-}
-
-static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
- dma_addr_t dma_addr)
-{
- u32 tmp;
-
- uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
- uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
-
- /* enable DMA */
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
- tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
-
- uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
-
- /* suppress the warning "right shift count >= width of type" */
- dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
-
- uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
-
- uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
-}
-
-static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
- unsigned int blocks)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- long wait = 1000000 + 10 * blocks;
-
- while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
- if (wait-- < 0) {
- dev_err(dev, "timeout during DMA\n");
- return -ETIMEDOUT;
- }
-
- udelay(10);
- }
-
- if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
- dev_err(dev, "error during DMA\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- size_t len = data->blocks * data->blocksize;
- void *buf;
- enum dma_data_direction dir;
- dma_addr_t dma_addr;
- u32 poll_flag, tmp;
- int ret;
-
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
-
- if (data->flags & MMC_DATA_READ) {
- buf = data->dest;
- dir = DMA_FROM_DEVICE;
- poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
- tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
- } else {
- buf = (void *)data->src;
- dir = DMA_TO_DEVICE;
- poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
- tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
- }
-
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
-
- dma_addr = __dma_map_single(buf, len, dir);
-
- uniphier_sd_dma_start(priv, dma_addr);
-
- ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
-
- __dma_unmap_single(dma_addr, len, dir);
-
- return ret;
-}
-
-/* check if the address is DMA'able */
-static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
-{
- if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
- return false;
-
-#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
- defined(CONFIG_SPL_BUILD)
- /*
- * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
- * of L2, which is unreachable from the DMA engine.
- */
- if (addr < CONFIG_SPL_STACK)
- return false;
-#endif
-
- return true;
-}
-
-static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- int ret;
- u32 tmp;
-
- if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
- dev_err(dev, "command busy\n");
- return -EBUSY;
- }
-
- /* clear all status flags */
- uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
- uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
-
- /* disable DMA once */
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
- tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
-
- uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
-
- tmp = cmd->cmdidx;
-
- if (data) {
- uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
- uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
-
- /* Do not send CMD12 automatically */
- tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
-
- if (data->blocks > 1)
- tmp |= UNIPHIER_SD_CMD_MULTI;
-
- if (data->flags & MMC_DATA_READ)
- tmp |= UNIPHIER_SD_CMD_RD;
- }
-
- /*
- * Do not use the response type auto-detection on this hardware.
- * CMD8, for example, has different response types on SD and eMMC,
- * while this controller always assumes the response type for SD.
- * Set the response type manually.
- */
- switch (cmd->resp_type) {
- case MMC_RSP_NONE:
- tmp |= UNIPHIER_SD_CMD_RSP_NONE;
- break;
- case MMC_RSP_R1:
- tmp |= UNIPHIER_SD_CMD_RSP_R1;
- break;
- case MMC_RSP_R1b:
- tmp |= UNIPHIER_SD_CMD_RSP_R1B;
- break;
- case MMC_RSP_R2:
- tmp |= UNIPHIER_SD_CMD_RSP_R2;
- break;
- case MMC_RSP_R3:
- tmp |= UNIPHIER_SD_CMD_RSP_R3;
- break;
- default:
- dev_err(dev, "unknown response type\n");
- return -EINVAL;
- }
-
- dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
- cmd->cmdidx, tmp, cmd->cmdarg);
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
-
- ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
- UNIPHIER_SD_INFO1_RSP);
- if (ret)
- return ret;
-
- if (cmd->resp_type & MMC_RSP_136) {
- u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
- u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
- u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
- u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
-
- cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
- ((rsp_103_72 & 0xff000000) >> 24);
- cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
- ((rsp_71_40 & 0xff000000) >> 24);
- cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
- ((rsp_39_8 & 0xff000000) >> 24);
- cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
- } else {
- /* bit 39-8 */
- cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
- }
-
- if (data) {
- /* use DMA if the HW supports it and the buffer is aligned */
- if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
- uniphier_sd_addr_is_dmaable((long)data->src))
- ret = uniphier_sd_dma_xfer(dev, data);
- else
- ret = uniphier_sd_pio_xfer(dev, data);
-
- ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
- UNIPHIER_SD_INFO1_CMP);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
-static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
- struct mmc *mmc)
-{
- u32 val, tmp;
-
- switch (mmc->bus_width) {
- case 1:
- val = UNIPHIER_SD_OPTION_WIDTH_1;
- break;
- case 4:
- val = UNIPHIER_SD_OPTION_WIDTH_4;
- break;
- case 8:
- val = UNIPHIER_SD_OPTION_WIDTH_8;
- break;
- default:
- return -EINVAL;
- }
-
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
- tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
- tmp |= val;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
-
- return 0;
-}
-
-static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
- struct mmc *mmc)
-{
- u32 tmp;
-
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
- if (mmc->ddr_mode)
- tmp |= UNIPHIER_SD_IF_MODE_DDR;
- else
- tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
-}
-
-static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
- struct mmc *mmc)
-{
- unsigned int divisor;
- u32 val, tmp;
-
- if (!mmc->clock)
- return;
-
- divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
-
- if (divisor <= 1)
- val = UNIPHIER_SD_CLKCTL_DIV1;
- else if (divisor <= 2)
- val = UNIPHIER_SD_CLKCTL_DIV2;
- else if (divisor <= 4)
- val = UNIPHIER_SD_CLKCTL_DIV4;
- else if (divisor <= 8)
- val = UNIPHIER_SD_CLKCTL_DIV8;
- else if (divisor <= 16)
- val = UNIPHIER_SD_CLKCTL_DIV16;
- else if (divisor <= 32)
- val = UNIPHIER_SD_CLKCTL_DIV32;
- else if (divisor <= 64)
- val = UNIPHIER_SD_CLKCTL_DIV64;
- else if (divisor <= 128)
- val = UNIPHIER_SD_CLKCTL_DIV128;
- else if (divisor <= 256)
- val = UNIPHIER_SD_CLKCTL_DIV256;
- else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
- val = UNIPHIER_SD_CLKCTL_DIV512;
- else
- val = UNIPHIER_SD_CLKCTL_DIV1024;
-
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
- if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
- (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
- return;
-
- /* stop the clock before changing its rate to avoid a glitch signal */
- tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
-
- tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
- tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
-
- tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
-
- udelay(1000);
-}
-
-static int uniphier_sd_set_ios(struct udevice *dev)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- struct mmc *mmc = mmc_get_mmc_dev(dev);
- int ret;
-
- dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
- mmc->clock, mmc->ddr_mode, mmc->bus_width);
-
- ret = uniphier_sd_set_bus_width(priv, mmc);
- if (ret)
- return ret;
- uniphier_sd_set_ddr_mode(priv, mmc);
- uniphier_sd_set_clk_rate(priv, mmc);
-
- return 0;
-}
-
-static int uniphier_sd_get_cd(struct udevice *dev)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
-
- if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
- return 1;
-
- return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
- UNIPHIER_SD_INFO1_CD);
-}
+#include "tmio-common.h"
static const struct dm_mmc_ops uniphier_sd_ops = {
- .send_cmd = uniphier_sd_send_cmd,
- .set_ios = uniphier_sd_set_ios,
- .get_cd = uniphier_sd_get_cd,
+ .send_cmd = tmio_sd_send_cmd,
+ .set_ios = tmio_sd_set_ios,
+ .get_cd = tmio_sd_get_cd,
};
-static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
-{
- u32 tmp;
-
- /* soft reset of the host */
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
- tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
- tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
-
- /* FIXME: implement eMMC hw_reset */
-
- uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
-
- /*
- * Connected to 32bit AXI.
- * This register dropped backward compatibility at version 0x10.
- * Write an appropriate value depending on the IP version.
- */
- uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
- UNIPHIER_SD_HOST_MODE);
-
- if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
- tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
- tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
- uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
- }
-}
-
-static int uniphier_sd_bind(struct udevice *dev)
-{
- struct uniphier_sd_plat *plat = dev_get_platdata(dev);
-
- return mmc_bind(dev, &plat->mmc, &plat->cfg);
-}
-
-static int uniphier_sd_probe(struct udevice *dev)
-{
- struct uniphier_sd_plat *plat = dev_get_platdata(dev);
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- const u32 quirks = dev_get_driver_data(dev);
- fdt_addr_t base;
- struct clk clk;
- int ret;
-#ifdef CONFIG_DM_REGULATOR
- struct udevice *vqmmc_dev;
-#endif
-
- base = devfdt_get_addr(dev);
- if (base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- priv->regbase = devm_ioremap(dev, base, SZ_2K);
- if (!priv->regbase)
- return -ENOMEM;
-
-#ifdef CONFIG_DM_REGULATOR
- ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
- if (!ret) {
- /* Set the regulator to 3.3V until we support 1.8V modes */
- regulator_set_value(vqmmc_dev, 3300000);
- regulator_set_enable(vqmmc_dev, true);
- }
-#endif
-
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0) {
- dev_err(dev, "failed to get host clock\n");
- return ret;
- }
-
- /* set to max rate */
- priv->mclk = clk_set_rate(&clk, ULONG_MAX);
- if (IS_ERR_VALUE(priv->mclk)) {
- dev_err(dev, "failed to set rate for host clock\n");
- clk_free(&clk);
- return priv->mclk;
- }
-
- ret = clk_enable(&clk);
- clk_free(&clk);
- if (ret) {
- dev_err(dev, "failed to enable host clock\n");
- return ret;
- }
-
- plat->cfg.name = dev->name;
- plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
-
- switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
- 1)) {
- case 8:
- plat->cfg.host_caps |= MMC_MODE_8BIT;
- break;
- case 4:
- plat->cfg.host_caps |= MMC_MODE_4BIT;
- break;
- case 1:
- break;
- default:
- dev_err(dev, "Invalid \"bus-width\" value\n");
- return -EINVAL;
- }
-
- if (quirks) {
- priv->caps = quirks;
- } else {
- priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
- UNIPHIER_SD_VERSION_IP;
- dev_dbg(dev, "version %x\n", priv->version);
- if (priv->version >= 0x10) {
- priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
- priv->caps |= UNIPHIER_SD_CAP_DIV1024;
- }
- }
-
- if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
- NULL))
- priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
-
- uniphier_sd_host_init(priv);
-
- plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
- plat->cfg.f_min = priv->mclk /
- (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
- plat->cfg.f_max = priv->mclk;
- plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
-
- upriv->mmc = &plat->mmc;
-
- return 0;
-}
-
static const struct udevice_id uniphier_sd_match[] = {
- { .compatible = "renesas,sdhi-r8a7790", .data = 0 },
- { .compatible = "renesas,sdhi-r8a7791", .data = 0 },
- { .compatible = "renesas,sdhi-r8a7792", .data = 0 },
- { .compatible = "renesas,sdhi-r8a7793", .data = 0 },
- { .compatible = "renesas,sdhi-r8a7794", .data = 0 },
- { .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT },
- { .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT },
- { .compatible = "renesas,sdhi-r8a77965", .data = UNIPHIER_SD_CAP_64BIT },
- { .compatible = "renesas,sdhi-r8a77970", .data = UNIPHIER_SD_CAP_64BIT },
- { .compatible = "renesas,sdhi-r8a77995", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "socionext,uniphier-sdhc", .data = 0 },
{ /* sentinel */ }
};
+static int uniphier_sd_probe(struct udevice *dev)
+{
+ return tmio_sd_probe(dev, 0);
+}
+
U_BOOT_DRIVER(uniphier_mmc) = {
.name = "uniphier-mmc",
.id = UCLASS_MMC,
.of_match = uniphier_sd_match,
- .bind = uniphier_sd_bind,
+ .bind = tmio_sd_bind,
.probe = uniphier_sd_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
- .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
+ .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
+ .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
.ops = &uniphier_sd_ops,
};
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 1957980..707359d 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -40,6 +40,13 @@
This enables access to Microchip PIC32 internal non-CFI flash
chips through PIC32 Non-Volatile-Memory Controller.
+config RENESAS_RPC_HF
+ bool "Renesas RCar Gen3 RPC Hyperflash driver"
+ depends on RCAR_GEN3 && MTD
+ help
+ This enables access to Hyperflash memory through the Renesas
+ RCar Gen3 RPC controller.
+
endmenu
source "drivers/mtd/nand/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 20c0d0a..e46cbd8 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -20,3 +20,4 @@
obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
obj-$(CONFIG_ST_SMI) += st_smi.o
obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
+obj-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a820af6..94fbf89 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -95,9 +95,11 @@
config NAND_SUNXI
bool "Support for NAND on Allwinner SoCs"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ default ARCH_SUNXI
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
select SYS_NAND_SELF_INIT
select SYS_NAND_U_BOOT_LOCATIONS
+ select SPL_NAND_SUPPORT
imply CMD_NAND
---help---
Enable support for NAND. This option enables the standard and
@@ -166,6 +168,28 @@
comment "Generic NAND options"
+config SYS_NAND_BLOCK_SIZE
+ hex "NAND chip eraseblock size"
+ depends on ARCH_SUNXI
+ help
+ Number of data bytes in one eraseblock for the NAND chip on the
+ board. This is the multiple of NAND_PAGE_SIZE and the number of
+ pages.
+
+config SYS_NAND_PAGE_SIZE
+ hex "NAND chip page size"
+ depends on ARCH_SUNXI
+ help
+ Number of data bytes in one page for the NAND chip on the
+ board, not including the OOB area.
+
+config SYS_NAND_OOBSIZE
+ hex "NAND chip OOB size"
+ depends on ARCH_SUNXI
+ help
+ Number of bytes in the Out-Of-Band area for the NAND chip on
+ the board.
+
# Enhance depends when converting drivers to Kconfig which use this config
# option (mxc_nand, ndfc, omap_gpmc).
config SYS_NAND_BUSWIDTH_16BIT
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 9f7d9d6..332d905 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -57,7 +57,6 @@
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
-obj-$(CONFIG_NAND_NDFC) += ndfc.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 3c9a021..3be66ef 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -795,10 +795,11 @@
writel(reg_val, &arasan_nand_base->cmd_reg);
- page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
- ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
+ page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
+ ARASAN_NAND_MEM_ADDR1_COL_MASK;
column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
- writel(page | column, &arasan_nand_base->memadr_reg1);
+ writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
+ &arasan_nand_base->memadr_reg1);
reg_val = readl(&arasan_nand_base->memadr_reg2);
reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 8b548b2..13a6535 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -29,11 +29,6 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand_ecc.h>
-/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
-#ifdef CONFIG_NAND_NDFC
-#define CONFIG_MTD_NAND_ECC_SMC
-#endif
-
/*
* NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
* only nand_correct_data() is needed
@@ -110,13 +105,8 @@
tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
/* Calculate final ECC code */
-#ifdef CONFIG_MTD_NAND_ECC_SMC
- ecc_code[0] = ~tmp2;
- ecc_code[1] = ~tmp1;
-#else
ecc_code[0] = ~tmp1;
ecc_code[1] = ~tmp2;
-#endif
ecc_code[2] = ((~reg1) << 2) | 0x03;
return 0;
@@ -146,15 +136,9 @@
{
uint8_t s0, s1, s2;
-#ifdef CONFIG_MTD_NAND_ECC_SMC
- s0 = calc_ecc[0] ^ read_ecc[0];
- s1 = calc_ecc[1] ^ read_ecc[1];
- s2 = calc_ecc[2] ^ read_ecc[2];
-#else
s1 = calc_ecc[0] ^ read_ecc[0];
s0 = calc_ecc[1] ^ read_ecc[1];
s2 = calc_ecc[2] ^ read_ecc[2];
-#endif
if ((s0 | s1 | s2) == 0)
return 0;
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
deleted file mode 100644
index 0a9849e..0000000
--- a/drivers/mtd/nand/ndfc.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Overview:
- * Platform independent driver for NDFC (NanD Flash Controller)
- * integrated into IBM/AMCC PPC4xx cores
- *
- * (C) Copyright 2006-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- * Thomas Gleixner
- * Copyright 2006 IBM
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <linux/mtd/ndfc.h>
-#include <linux/mtd/nand_ecc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx.h>
-
-#ifndef CONFIG_SYS_NAND_BCR
-#define CONFIG_SYS_NAND_BCR 0x80002222
-#endif
-#ifndef CONFIG_SYS_NDFC_EBC0_CFG
-#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
-#endif
-
-/*
- * We need to store the info, which chip-select (CS) is used for the
- * chip number. For example on Sequoia NAND chip #0 uses
- * CS #3.
- */
-static int ndfc_cs[NDFC_MAX_BANKS];
-
-static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
- else
- out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
-}
-
-static int ndfc_dev_ready(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
- return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
-}
-
-static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- u32 ccr;
-
- ccr = in_be32((u32 *)(base + NDFC_CCR));
- ccr |= NDFC_CCR_RESET_ECC;
- out_be32((u32 *)(base + NDFC_CCR), ccr);
-}
-
-static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
- const u_char *dat, u_char *ecc_code)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- u32 ecc;
- u8 *p = (u8 *)&ecc;
-
- ecc = in_be32((u32 *)(base + NDFC_ECC));
-
- /* The NDFC uses Smart Media (SMC) bytes order
- */
- ecc_code[0] = p[1];
- ecc_code[1] = p[2];
- ecc_code[2] = p[3];
-
- return 0;
-}
-
-/*
- * Speedups for buffer read/write/verify
- *
- * NDFC allows 32bit read/write of data. So we can speed up the buffer
- * functions. No further checking, as nand_base will always read/write
- * page aligned.
- */
-static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (;len > 0; len -= 4)
- *p++ = in_be32((u32 *)(base + NDFC_DATA));
-}
-
-/*
- * Don't use these speedup functions in NAND boot image, since the image
- * has to fit into 4kByte.
- */
-static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (; len > 0; len -= 4)
- out_be32((u32 *)(base + NDFC_DATA), *p++);
-}
-
-/*
- * Read a byte from the NDFC.
- */
-static uint8_t ndfc_read_byte(struct mtd_info *mtd)
-{
-
- struct nand_chip *chip = mtd_to_nand(mtd);
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- return (uint8_t) readw(chip->IO_ADDR_R);
-#else
- return readb(chip->IO_ADDR_R);
-#endif
-
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
- /*
- * Don't use "chip" to address the NAND device,
- * generate the cs from the address where it is encoded.
- */
- ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
- int cs = ndfc_cs[chip];
-
- /* Set NandFlash Core Configuration Register */
- /* 1 col x 2 rows */
- out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
- out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
-}
-
-static void ndfc_select_chip(struct mtd_info *mtd, int chip)
-{
- /*
- * Nothing to do here!
- */
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
- ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
- static int chip = 0;
-
- /*
- * Save chip-select for this chip #
- */
- ndfc_cs[chip] = cs;
-
- /*
- * Select required NAND chip in NDFC
- */
- board_nand_select_device(nand, chip);
-
- nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
- nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
- nand->cmd_ctrl = ndfc_hwcontrol;
- nand->chip_delay = 50;
- nand->read_buf = ndfc_read_buf;
- nand->dev_ready = ndfc_dev_ready;
- nand->ecc.correct = nand_correct_data;
- nand->ecc.hwctl = ndfc_enable_hwecc;
- nand->ecc.calculate = ndfc_calculate_ecc;
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.size = 256;
- nand->ecc.bytes = 3;
- nand->ecc.strength = 1;
- nand->select_chip = ndfc_select_chip;
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- nand->options |= NAND_BUSWIDTH_16;
-#endif
-
- nand->write_buf = ndfc_write_buf;
- nand->read_byte = ndfc_read_byte;
-
- chip++;
-
- return 0;
-}
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 532e03c..37160aa 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1407,8 +1407,14 @@
/* Add ECC info retrieval from DT */
for (i = 0; i < ARRAY_SIZE(strengths); i++) {
- if (ecc->strength <= strengths[i])
+ if (ecc->strength <= strengths[i]) {
+ /*
+ * Update ecc->strength value with the actual strength
+ * that will be used by the ECC engine.
+ */
+ ecc->strength = strengths[i];
break;
+ }
}
if (i >= ARRAY_SIZE(strengths)) {
diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
index eed4472..7241e9a 100644
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <config.h>
#include <nand.h>
+#include <linux/ctype.h>
/* registers */
#define NFC_CTL 0x00000000
@@ -55,7 +56,7 @@
#define NFC_ADDR_NUM_OFFSET 16
-#define NFC_SEND_ADR (1 << 19)
+#define NFC_SEND_ADDR (1 << 19)
#define NFC_ACCESS_DIR (1 << 20)
#define NFC_DATA_TRANS (1 << 21)
#define NFC_SEND_CMD1 (1 << 22)
@@ -67,10 +68,12 @@
#define NFC_SEND_CMD3 (1 << 28)
#define NFC_SEND_CMD4 (1 << 29)
#define NFC_RAW_CMD (0 << 30)
+#define NFC_ECC_CMD (1 << 30)
#define NFC_PAGE_CMD (2 << 30)
#define NFC_ST_CMD_INT_FLAG (1 << 1)
#define NFC_ST_DMA_INT_FLAG (1 << 2)
+#define NFC_ST_CMD_FIFO_STAT (1 << 3)
#define NFC_READ_CMD_OFFSET 0
#define NFC_RANDOM_READ_CMD0_OFFSET 8
@@ -80,22 +83,6 @@
#define NFC_CMD_RNDOUT 0x05
#define NFC_CMD_READSTART 0x30
-#define SUNXI_DMA_CFG_REG0 0x300
-#define SUNXI_DMA_SRC_START_ADDR_REG0 0x304
-#define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
-#define SUNXI_DMA_DDMA_BC_REG0 0x30C
-#define SUNXI_DMA_DDMA_PARA_REG0 0x318
-
-#define SUNXI_DMA_DDMA_CFG_REG_LOADING (1 << 31)
-#define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
-#define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
-#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
-#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
-#define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
-
-#define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
-#define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
-
struct nfc_config {
int page_size;
int ecc_strength;
@@ -155,6 +142,42 @@
return check_value_inner(offset, unexpected_bits, timeout_us, 1);
}
+static int nand_wait_cmd_fifo_empty(void)
+{
+ if (!check_value_negated(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_FIFO_STAT,
+ DEFAULT_TIMEOUT_US)) {
+ printf("nand: timeout waiting for empty cmd FIFO\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int nand_wait_int(void)
+{
+ if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
+ DEFAULT_TIMEOUT_US)) {
+ printf("nand: timeout waiting for interruption\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int nand_exec_cmd(u32 cmd)
+{
+ int ret;
+
+ ret = nand_wait_cmd_fifo_empty();
+ if (ret)
+ return ret;
+
+ writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
+ writel(cmd, SUNXI_NFC_BASE + NFC_CMD);
+
+ return nand_wait_int();
+}
+
void nand_init(void)
{
uint32_t val;
@@ -172,22 +195,15 @@
}
/* reset NAND */
- writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
- writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
- SUNXI_NFC_BASE + NFC_CMD);
-
- if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
- DEFAULT_TIMEOUT_US)) {
- printf("Error timeout waiting for nand reset\n");
- return;
- }
- writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
+ nand_exec_cmd(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET);
}
static void nand_apply_config(const struct nfc_config *conf)
{
u32 val;
+ nand_wait_cmd_fifo_empty();
+
val = readl(SUNXI_NFC_BASE + NFC_CTL);
val &= ~NFC_CTL_PAGE_SIZE_MASK;
writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
@@ -206,128 +222,111 @@
SUNXI_NFC_BASE + NFC_RCMD_SET);
writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
- writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
- writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | NFC_WAIT_FLAG |
- ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR,
- SUNXI_NFC_BASE + NFC_CMD);
- if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
- DEFAULT_TIMEOUT_US)) {
- printf("Error while initializing dma interrupt\n");
- return -EIO;
- }
-
- return 0;
+ return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
+ NFC_SEND_ADDR | NFC_WAIT_FLAG |
+ ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET));
}
-static int nand_reset_column(void)
+static int nand_change_column(u16 column)
{
+ int ret;
+
writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
(NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
(NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET),
SUNXI_NFC_BASE + NFC_RCMD_SET);
- writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW);
- writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
- (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR | NFC_CMD_RNDOUT,
- SUNXI_NFC_BASE + NFC_CMD);
+ writel(column, SUNXI_NFC_BASE + NFC_ADDR_LOW);
- if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
- DEFAULT_TIMEOUT_US)) {
- printf("Error while initializing dma interrupt\n");
- return -1;
- }
+ ret = nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
+ (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR |
+ NFC_CMD_RNDOUT);
+ if (ret)
+ return ret;
+
+ /* Ensure tCCS has passed before reading data */
+ udelay(1);
return 0;
}
+static const int ecc_bytes[] = {32, 46, 54, 60, 74, 88, 102, 110, 116};
+
static int nand_read_page(const struct nfc_config *conf, u32 offs,
void *dest, int len)
{
- dma_addr_t dst = (dma_addr_t)dest;
int nsectors = len / conf->ecc_size;
u16 rand_seed = 0;
- u32 val;
- int page;
-
- page = offs / conf->page_size;
+ int oob_chunk_sz = ecc_bytes[conf->ecc_strength];
+ int page = offs / conf->page_size;
+ u32 ecc_st;
+ int i;
if (offs % conf->page_size || len % conf->ecc_size ||
len > conf->page_size || len < 0)
return -EINVAL;
- /* clear ecc status */
- writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
-
/* Choose correct seed if randomized */
if (conf->randomize)
rand_seed = random_seed[page % conf->nseeds];
- writel((rand_seed << 16) | (conf->ecc_strength << 12) |
- (conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
- (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
- NFC_ECC_EN | NFC_ECC_PIPELINE | NFC_ECC_EXCEPTION,
- SUNXI_NFC_BASE + NFC_ECC_CTL);
+ /* Retrieve data from SRAM (PIO) */
+ for (i = 0; i < nsectors; i++) {
+ int data_off = i * conf->ecc_size;
+ int oob_off = conf->page_size + (i * oob_chunk_sz);
+ u8 *data = dest + data_off;
- flush_dcache_range(dst, ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
+ /* Clear ECC status and restart ECC engine */
+ writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
+ writel((rand_seed << 16) | (conf->ecc_strength << 12) |
+ (conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
+ (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
+ NFC_ECC_EN | NFC_ECC_EXCEPTION,
+ SUNXI_NFC_BASE + NFC_ECC_CTL);
- /* SUNXI_DMA */
- writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
- /* read from REG_IO_DATA */
- writel(SUNXI_NFC_BASE + NFC_IO_DATA,
- SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
- /* read to RAM */
- writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
- writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC |
- SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
- SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
- writel(len, SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0);
- writel(SUNXI_DMA_DDMA_CFG_REG_LOADING |
- SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 |
- SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM |
- SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 |
- SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO |
- SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
- SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
+ /* Move the data in SRAM */
+ nand_change_column(data_off);
+ writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
+ nand_exec_cmd(NFC_DATA_TRANS);
- writel(nsectors, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
- writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
- writel(NFC_DATA_TRANS | NFC_PAGE_CMD | NFC_DATA_SWAP_METHOD,
- SUNXI_NFC_BASE + NFC_CMD);
+ /*
+ * Let the ECC engine consume the ECC bytes and possibly correct
+ * the data.
+ */
+ nand_change_column(oob_off);
+ nand_exec_cmd(NFC_DATA_TRANS | NFC_ECC_CMD);
- if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
- DEFAULT_TIMEOUT_US)) {
- printf("Error while initializing dma interrupt\n");
- return -EIO;
- }
- writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
+ /* Get the ECC status */
+ ecc_st = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
- if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
- SUNXI_DMA_DDMA_CFG_REG_LOADING,
- DEFAULT_TIMEOUT_US)) {
- printf("Error while waiting for dma transfer to finish\n");
- return -EIO;
+ /* ECC error detected. */
+ if (ecc_st & 0xffff)
+ return -EIO;
+
+ /*
+ * Return 1 if the first chunk is empty (needed for
+ * configuration detection).
+ */
+ if (!i && (ecc_st & 0x10000))
+ return 1;
+
+ /* Retrieve the data from SRAM */
+ memcpy_fromio(data, SUNXI_NFC_BASE + NFC_RAM0_BASE,
+ conf->ecc_size);
+
+ /* Stop the ECC engine */
+ writel(readl(SUNXI_NFC_BASE + NFC_ECC_CTL) & ~NFC_ECC_EN,
+ SUNXI_NFC_BASE + NFC_ECC_CTL);
+
+ if (data_off + conf->ecc_size >= len)
+ break;
}
- invalidate_dcache_range(dst,
- ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
-
- val = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
-
- /* ECC error detected. */
- if (val & 0xffff)
- return -EIO;
-
- /*
- * Return 1 if the page is empty.
- * We consider the page as empty if the first ECC block is marked
- * empty.
- */
- return (val & 0x10000) ? 1 : 0;
+ return 0;
}
static int nand_max_ecc_strength(struct nfc_config *conf)
{
- static const int ecc_bytes[] = { 32, 46, 54, 60, 74, 88, 102, 110, 116 };
int max_oobsize, max_ecc_bytes;
int nsectors = conf->page_size / conf->ecc_size;
int i;
@@ -393,7 +392,7 @@
conf->ecc_strength >= 0;
conf->ecc_strength--) {
conf->randomize = false;
- if (nand_reset_column())
+ if (nand_change_column(0))
return -EIO;
/*
@@ -413,7 +412,7 @@
conf->randomize = true;
conf->nseeds = ARRAY_SIZE(random_seed);
do {
- if (nand_reset_column())
+ if (nand_change_column(0))
return -EIO;
if (!nand_read_page(conf, offs, dest,
@@ -475,11 +474,12 @@
static int nand_read_buffer(struct nfc_config *conf, uint32_t offs,
unsigned int size, void *dest)
{
- int first_seed, page, ret;
+ int first_seed = 0, page, ret;
size = ALIGN(size, conf->page_size);
page = offs / conf->page_size;
- first_seed = page % conf->nseeds;
+ if (conf->randomize)
+ first_seed = page % conf->nseeds;
for (; size; size -= conf->page_size) {
if (nand_load_page(conf, offs))
@@ -504,7 +504,7 @@
/* Try to adjust ->nseeds and read the page again... */
conf->nseeds = cur_seed;
- if (nand_reset_column())
+ if (nand_change_column(0))
return -EIO;
/* ... it still fails => it's a real corruption. */
diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c
new file mode 100644
index 0000000..1ba6e35
--- /dev/null
+++ b/drivers/mtd/renesas_rpc_hf.c
@@ -0,0 +1,398 @@
+/*
+ * Renesas RCar Gen3 RPC Hyperflash driver
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <flash.h>
+#include <mtd.h>
+#include <wait_bit.h>
+#include <mtd/cfi_flash.h>
+
+#define RPC_CMNCR 0x0000 /* R/W */
+#define RPC_CMNCR_MD BIT(31)
+#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
+#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
+#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
+#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
+#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
+ RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
+#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
+#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
+#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
+#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
+ RPC_CMNCR_IO3FV(3))
+#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
+
+#define RPC_SSLDR 0x0004 /* R/W */
+#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
+#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
+#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
+
+#define RPC_DRCR 0x000C /* R/W */
+#define RPC_DRCR_SSLN BIT(24)
+#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
+#define RPC_DRCR_RCF BIT(9)
+#define RPC_DRCR_RBE BIT(8)
+#define RPC_DRCR_SSLE BIT(0)
+
+#define RPC_DRCMR 0x0010 /* R/W */
+#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
+#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
+
+#define RPC_DREAR 0x0014 /* R/W */
+#define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
+#define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
+
+#define RPC_DROPR 0x0018 /* R/W */
+#define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
+#define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
+#define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
+#define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
+
+#define RPC_DRENR 0x001C /* R/W */
+#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
+#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
+#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
+#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
+#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
+#define RPC_DRENR_DME BIT(15)
+#define RPC_DRENR_CDE BIT(14)
+#define RPC_DRENR_OCDE BIT(12)
+#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
+#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
+
+#define RPC_SMCR 0x0020 /* R/W */
+#define RPC_SMCR_SSLKP BIT(8)
+#define RPC_SMCR_SPIRE BIT(2)
+#define RPC_SMCR_SPIWE BIT(1)
+#define RPC_SMCR_SPIE BIT(0)
+
+#define RPC_SMCMR 0x0024 /* R/W */
+#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
+#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
+
+#define RPC_SMADR 0x0028 /* R/W */
+#define RPC_SMOPR 0x002C /* R/W */
+#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
+#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
+#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
+#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
+
+#define RPC_SMENR 0x0030 /* R/W */
+#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
+#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
+#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
+#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
+#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
+#define RPC_SMENR_DME BIT(15)
+#define RPC_SMENR_CDE BIT(14)
+#define RPC_SMENR_OCDE BIT(12)
+#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
+#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
+#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
+
+#define RPC_SMRDR0 0x0038 /* R */
+#define RPC_SMRDR1 0x003C /* R */
+#define RPC_SMWDR0 0x0040 /* R/W */
+#define RPC_SMWDR1 0x0044 /* R/W */
+#define RPC_CMNSR 0x0048 /* R */
+#define RPC_CMNSR_SSLF BIT(1)
+#define RPC_CMNSR_TEND BIT(0)
+
+#define RPC_DRDMCR 0x0058 /* R/W */
+#define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
+
+#define RPC_DRDRENR 0x005C /* R/W */
+#define RPC_DRDRENR_HYPE (0x5 << 12)
+#define RPC_DRDRENR_ADDRE BIT(8)
+#define RPC_DRDRENR_OPDRE BIT(4)
+#define RPC_DRDRENR_DRDRE BIT(0)
+
+#define RPC_SMDMCR 0x0060 /* R/W */
+#define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
+
+#define RPC_SMDRENR 0x0064 /* R/W */
+#define RPC_SMDRENR_HYPE (0x5 << 12)
+#define RPC_SMDRENR_ADDRE BIT(8)
+#define RPC_SMDRENR_OPDRE BIT(4)
+#define RPC_SMDRENR_SPIDRE BIT(0)
+
+#define RPC_PHYCNT 0x007C /* R/W */
+#define RPC_PHYCNT_CAL BIT(31)
+#define PRC_PHYCNT_OCTA_AA BIT(22)
+#define PRC_PHYCNT_OCTA_SA BIT(23)
+#define PRC_PHYCNT_EXDS BIT(21)
+#define RPC_PHYCNT_OCT BIT(20)
+#define RPC_PHYCNT_WBUF2 BIT(4)
+#define RPC_PHYCNT_WBUF BIT(2)
+#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
+
+#define RPC_PHYINT 0x0088 /* R/W */
+#define RPC_PHYINT_RSTEN BIT(18)
+#define RPC_PHYINT_WPEN BIT(17)
+#define RPC_PHYINT_INTEN BIT(16)
+#define RPC_PHYINT_RST BIT(2)
+#define RPC_PHYINT_WP BIT(1)
+#define RPC_PHYINT_INT BIT(0)
+
+#define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
+#define RPC_WBUF_SIZE 0x100
+
+static phys_addr_t rpc_base;
+
+enum rpc_hf_size {
+ RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8),
+ RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC),
+ RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF),
+};
+
+static int rpc_hf_wait_tend(void)
+{
+ void __iomem *reg = (void __iomem *)rpc_base + RPC_CMNSR;
+ return wait_for_bit_le32(reg, RPC_CMNSR_TEND, true, 1000, 0);
+}
+
+static int rpc_hf_mode(bool man)
+{
+ int ret;
+
+ ret = rpc_hf_wait_tend();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(rpc_base + RPC_PHYCNT,
+ RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 |
+ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3),
+ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3));
+
+ clrsetbits_le32(rpc_base + RPC_CMNCR,
+ RPC_CMNCR_MD | RPC_CMNCR_BSZ(3),
+ RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
+ (man ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1));
+
+ if (man)
+ return 0;
+
+ writel(RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE,
+ rpc_base + RPC_DRCR);
+
+ writel(RPC_DRCMR_CMD(0xA0), rpc_base + RPC_DRCMR);
+ writel(RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | RPC_DRENR_ADB(2) |
+ RPC_DRENR_SPIDB(2) | RPC_DRENR_CDE | RPC_DRENR_OCDE |
+ RPC_DRENR_ADE(4), rpc_base + RPC_DRENR);
+ writel(RPC_DRDMCR_DMCYC(0xE), rpc_base + RPC_DRDMCR);
+ writel(RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE,
+ rpc_base + RPC_DRDRENR);
+
+ /* Dummy read */
+ readl(rpc_base + RPC_DRCR);
+
+ return 0;
+}
+
+static int rpc_hf_xfer(void *addr, u64 wdata, u64 *rdata,
+ enum rpc_hf_size size, bool write)
+{
+ int ret;
+ u32 val;
+
+ ret = rpc_hf_mode(1);
+ if (ret)
+ return ret;
+
+ /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */
+ writel(write ? 0 : RPC_SMCMR_CMD(0x80), rpc_base + RPC_SMCMR);
+ writel((uintptr_t)addr >> 1, rpc_base + RPC_SMADR);
+ writel(0x0, rpc_base + RPC_SMOPR);
+
+ writel(RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE,
+ rpc_base + RPC_SMDRENR);
+
+ val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) |
+ RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) |
+ RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size;
+
+ if (write) {
+ writel(val, rpc_base + RPC_SMENR);
+
+ if (size == RPC_HF_SIZE_64BIT)
+ writeq(cpu_to_be64(wdata), rpc_base + RPC_SMWDR0);
+ else
+ writel(cpu_to_be32(wdata), rpc_base + RPC_SMWDR0);
+
+ writel(RPC_SMCR_SPIWE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
+ } else {
+ val |= RPC_SMENR_DME;
+
+ writel(RPC_SMDMCR_DMCYC(0xE), rpc_base + RPC_SMDMCR);
+
+ writel(val, rpc_base + RPC_SMENR);
+
+ writel(RPC_SMCR_SPIRE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
+
+ ret = rpc_hf_wait_tend();
+ if (ret)
+ return ret;
+
+ if (size == RPC_HF_SIZE_64BIT)
+ *rdata = be64_to_cpu(readq(rpc_base + RPC_SMRDR0));
+ else
+ *rdata = be32_to_cpu(readl(rpc_base + RPC_SMRDR0));
+ }
+
+ return rpc_hf_mode(0);
+}
+
+static void rpc_hf_write_cmd(void *addr, u64 wdata, enum rpc_hf_size size)
+{
+ int ret;
+
+ ret = rpc_hf_xfer(addr, wdata, NULL, size, 1);
+ if (ret)
+ printf("RPC: Write failed, ret=%i\n", ret);
+}
+
+static u64 rpc_hf_read_reg(void *addr, enum rpc_hf_size size)
+{
+ u64 rdata = 0;
+ int ret;
+
+ ret = rpc_hf_xfer(addr, 0, &rdata, size, 0);
+ if (ret)
+ printf("RPC: Read failed, ret=%i\n", ret);
+
+ return rdata;
+}
+
+void flash_write8(u8 value, void *addr)
+{
+ rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
+}
+
+void flash_write16(u16 value, void *addr)
+{
+ rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
+}
+
+void flash_write32(u32 value, void *addr)
+{
+ rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_32BIT);
+}
+
+void flash_write64(u64 value, void *addr)
+{
+ rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_64BIT);
+}
+
+u8 flash_read8(void *addr)
+{
+ return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
+}
+
+u16 flash_read16(void *addr)
+{
+ return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
+}
+
+u32 flash_read32(void *addr)
+{
+ return rpc_hf_read_reg(addr, RPC_HF_SIZE_32BIT);
+}
+
+u64 flash_read64(void *addr)
+{
+ return rpc_hf_read_reg(addr, RPC_HF_SIZE_64BIT);
+}
+
+static int rpc_hf_bind(struct udevice *parent)
+{
+ const void *fdt = gd->fdt_blob;
+ ofnode node;
+ int ret, off;
+
+ /*
+ * Check if there are any SPI NOR child nodes, if so, do NOT bind
+ * as this controller will be operated by the QSPI driver instead.
+ */
+ dev_for_each_subnode(node, parent) {
+ off = ofnode_to_offset(node);
+
+ ret = fdt_node_check_compatible(fdt, off, "spi-flash");
+ if (!ret)
+ return -ENODEV;
+
+ ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
+ if (!ret)
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int rpc_hf_probe(struct udevice *dev)
+{
+ void *blob = (void *)gd->fdt_blob;
+ const fdt32_t *cell;
+ int node = dev_of_offset(dev);
+ int parent, addrc, sizec, len, ret;
+ struct clk clk;
+ phys_addr_t flash_base;
+
+ parent = fdt_parent_offset(blob, node);
+ fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell)
+ return -ENOENT;
+
+ if (addrc != 2 || sizec != 2)
+ return -EINVAL;
+
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get RPC clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable RPC clock\n");
+ return ret;
+ }
+
+ rpc_base = fdt_translate_address(blob, node, cell);
+ flash_base = fdt_translate_address(blob, node, cell + addrc + sizec);
+
+ flash_info[0].dev = dev;
+ flash_info[0].base = flash_base;
+ cfi_flash_num_flash_banks = 1;
+ gd->bd->bi_flashstart = flash_base;
+
+ return 0;
+}
+
+static const struct udevice_id rpc_hf_ids[] = {
+ { .compatible = "renesas,rpc" },
+ {}
+};
+
+U_BOOT_DRIVER(rpc_hf) = {
+ .name = "rpc_hf",
+ .id = UCLASS_MTD,
+ .of_match = rpc_hf_ids,
+ .bind = rpc_hf_bind,
+ .probe = rpc_hf_probe,
+};
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 6ba255d..4484cf8 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -135,17 +135,4 @@
If unsure, say N
-if SPL
-
-config SPL_SPI_SUNXI
- bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
- select SPL_SPI_FLASH_SUPPORT
- ---help---
- Enable support for SPI Flash. This option allows SPL to read from
- sunxi SPI Flash. It uses the same method as the boot ROM, so does
- not need any extra configuration.
-
-endif
-
endmenu # menu "SPI Flash Support"
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index fcda023..4be6e9b 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -9,7 +9,6 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
-obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o
endif
obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 294d9f9..2e61685 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -320,7 +320,7 @@
erase_size = flash->erase_size;
if (offset % erase_size || len % erase_size) {
- debug("SF: Erase offset/length not multiple of erase size\n");
+ printf("SF: Erase offset/length not multiple of erase size\n");
return -1;
}
diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c
index 472499d..a828142 100644
--- a/drivers/mtd/stm32_flash.c
+++ b/drivers/mtd/stm32_flash.c
@@ -12,7 +12,7 @@
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-#define STM32_FLASH ((struct stm32_flash_regs *)FLASH_CNTL_BASE)
+#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_CNTL_BASE)
void stm32_flash_latency_cfg(int latency)
{
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index caa5197..cf84783 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -1,5 +1,12 @@
menu "UBI support"
+config CONFIG_UBI_SILENCE_MSG
+ bool "UBI silence verbose messages"
+ default ENV_IS_IN_UBI
+ help
+ Make the verbose messages from UBI stop printing. This leaves
+ warnings and errors enabled.
+
config MTD_UBI
bool "Enable UBI - Unsorted block images"
select CRC32
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de1947c..3a374d8 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,4 +1,5 @@
source "drivers/net/phy/Kconfig"
+source "drivers/net/pfe_eth/Kconfig"
config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
@@ -10,6 +11,13 @@
This is currently implemented in net/eth.c
Look in include/net.h for details.
+config DRIVER_TI_CPSW
+ bool "TI Common Platform Ethernet Switch"
+ select PHYLIB
+ help
+ This driver supports the TI three port switch gigabit ethernet
+ subsystem found in the TI SoCs.
+
menuconfig NETDEVICES
bool "Network device support"
depends on NET
@@ -147,9 +155,20 @@
help
This MAC is present in OpenRISC and Xtensa XTFPGA boards.
+config FEC_MXC_SHARE_MDIO
+ bool "Share the MDIO bus for FEC controller"
+ depends on FEC_MXC
+
+config FEC_MXC_MDIO_BASE
+ hex "MDIO base address for the FEC controller"
+ depends on FEC_MXC_SHARE_MDIO
+ help
+ This specifies the MDIO registers base address. It is used when
+ two FEC controllers share MDIO bus.
+
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX5 || MX6
+ depends on MX5 || MX6 || MX7
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
@@ -330,7 +349,7 @@
config MPC8XX_FEC
bool "Fast Ethernet Controller on MPC8XX"
- depends on 8xx
+ depends on MPC8xx
select MII
help
This driver implements support for the Fast Ethernet Controller
@@ -410,4 +429,11 @@
help
QBman fixups to allow deep sleep in DPAA 1 SOCs
+config TSEC_ENET
+ select PHYLIB
+ bool "Enable Three-Speed Ethernet Controller"
+ help
+ This driver implements support for the (Enhanced) Three-Speed
+ Ethernet Controller found on Freescale SoCs.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4a16c62..2687fbb 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -23,7 +23,6 @@
obj-$(CONFIG_EEPRO100) += eepro100.o
obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
-obj-$(CONFIG_ENC28J60) += enc28j60.o
obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
@@ -73,3 +72,4 @@
obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/
diff --git a/drivers/net/cpsw-common.c b/drivers/net/cpsw-common.c
index 0dc83ab..7bd312a 100644
--- a/drivers/net/cpsw-common.c
+++ b/drivers/net/cpsw-common.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <cpsw.h>
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index b72258f..e2395db 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -949,7 +949,7 @@
{
void *buffer;
int len;
- int ret = -EAGAIN;
+ int ret;
ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
if (ret < 0)
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
deleted file mode 100644
index 588a84d..0000000
--- a/drivers/net/enc28j60.c
+++ /dev/null
@@ -1,959 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- * Martin Krause, Martin.Krause@tqs.de
- * reworked original enc28j60.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <spi.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include "enc28j60.h"
-
-/*
- * IMPORTANT: spi_claim_bus() and spi_release_bus()
- * are called at begin and end of each of the following functions:
- * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
- * enc_init(), enc_recv(), enc_send(), enc_halt()
- * ALL other functions assume that the bus has already been claimed!
- * Since net_process_received_packet() might call enc_send() in return, the bus
- * must be released, net_process_received_packet() called and claimed again.
- */
-
-/*
- * Controller memory layout.
- * We only allow 1 frame for transmission and reserve the rest
- * for reception to handle as many broadcast packets as possible.
- * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
- * 0x0000 - 0x19ff 6656 bytes receive buffer
- * 0x1a00 - 0x1fff 1536 bytes transmit buffer =
- * control(1)+frame(1518)+status(7)+reserve(10).
- */
-#define ENC_RX_BUF_START 0x0000
-#define ENC_RX_BUF_END 0x19ff
-#define ENC_TX_BUF_START 0x1a00
-#define ENC_TX_BUF_END 0x1fff
-#define ENC_MAX_FRM_LEN 1518
-#define RX_RESET_COUNTER 1000
-
-/*
- * For non data transfer functions, like phy read/write, set hwaddr, init
- * we do not need a full, time consuming init including link ready wait.
- * This enum helps to bring the chip through the minimum necessary inits.
- */
-enum enc_initstate {none=0, setupdone, linkready};
-typedef struct enc_device {
- struct eth_device *dev; /* back pointer */
- struct spi_slave *slave;
- int rx_reset_counter;
- u16 next_pointer;
- u8 bank; /* current bank in enc28j60 */
- enum enc_initstate initstate;
-} enc_dev_t;
-
-/*
- * enc_bset: set bits in a common register
- * enc_bclr: clear bits in a common register
- *
- * making the reg parameter u8 will give a compile time warning if the
- * functions are called with a register not accessible in all Banks
- */
-static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
-{
- u8 dout[2];
-
- dout[0] = CMD_BFS(reg);
- dout[1] = data;
- spi_xfer(enc->slave, 2 * 8, dout, NULL,
- SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
-{
- u8 dout[2];
-
- dout[0] = CMD_BFC(reg);
- dout[1] = data;
- spi_xfer(enc->slave, 2 * 8, dout, NULL,
- SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-/*
- * high byte of the register contains bank number:
- * 0: no bank switch necessary
- * 1: switch to bank 0
- * 2: switch to bank 1
- * 3: switch to bank 2
- * 4: switch to bank 3
- */
-static void enc_set_bank(enc_dev_t *enc, const u16 reg)
-{
- u8 newbank = reg >> 8;
-
- if (newbank == 0 || newbank == enc->bank)
- return;
- switch (newbank) {
- case 1:
- enc_bclr(enc, CTL_REG_ECON1,
- ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
- break;
- case 2:
- enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
- enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
- break;
- case 3:
- enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
- enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
- break;
- case 4:
- enc_bset(enc, CTL_REG_ECON1,
- ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
- break;
- }
- enc->bank = newbank;
-}
-
-/*
- * local functions to access SPI
- *
- * reg: register inside ENC28J60
- * data: 8/16 bits to write
- * c: number of retries
- *
- * enc_r8: read 8 bits
- * enc_r16: read 16 bits
- * enc_w8: write 8 bits
- * enc_w16: write 16 bits
- * enc_w8_retry: write 8 bits, verify and retry
- * enc_rbuf: read from ENC28J60 into buffer
- * enc_wbuf: write from buffer into ENC28J60
- */
-
-/*
- * MAC and MII registers need a 3 byte SPI transfer to read,
- * all other registers need a 2 byte SPI transfer.
- */
-static int enc_reg2nbytes(const u16 reg)
-{
- /* check if MAC or MII register */
- return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
- (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
- (reg == CTL_REG_MISTAT)) ? 3 : 2;
-}
-
-/*
- * Read a byte register
- */
-static u8 enc_r8(enc_dev_t *enc, const u16 reg)
-{
- u8 dout[3];
- u8 din[3];
- int nbytes = enc_reg2nbytes(reg);
-
- enc_set_bank(enc, reg);
- dout[0] = CMD_RCR(reg);
- spi_xfer(enc->slave, nbytes * 8, dout, din,
- SPI_XFER_BEGIN | SPI_XFER_END);
- return din[nbytes-1];
-}
-
-/*
- * Read a L/H register pair and return a word.
- * Must be called with the L register's address.
- */
-static u16 enc_r16(enc_dev_t *enc, const u16 reg)
-{
- u8 dout[3];
- u8 din[3];
- u16 result;
- int nbytes = enc_reg2nbytes(reg);
-
- enc_set_bank(enc, reg);
- dout[0] = CMD_RCR(reg);
- spi_xfer(enc->slave, nbytes * 8, dout, din,
- SPI_XFER_BEGIN | SPI_XFER_END);
- result = din[nbytes-1];
- dout[0]++; /* next register */
- spi_xfer(enc->slave, nbytes * 8, dout, din,
- SPI_XFER_BEGIN | SPI_XFER_END);
- result |= din[nbytes-1] << 8;
- return result;
-}
-
-/*
- * Write a byte register
- */
-static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
-{
- u8 dout[2];
-
- enc_set_bank(enc, reg);
- dout[0] = CMD_WCR(reg);
- dout[1] = data;
- spi_xfer(enc->slave, 2 * 8, dout, NULL,
- SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-/*
- * Write a L/H register pair.
- * Must be called with the L register's address.
- */
-static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
-{
- u8 dout[2];
-
- enc_set_bank(enc, reg);
- dout[0] = CMD_WCR(reg);
- dout[1] = data;
- spi_xfer(enc->slave, 2 * 8, dout, NULL,
- SPI_XFER_BEGIN | SPI_XFER_END);
- dout[0]++; /* next register */
- dout[1] = data >> 8;
- spi_xfer(enc->slave, 2 * 8, dout, NULL,
- SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-/*
- * Write a byte register, verify and retry
- */
-static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
-{
- u8 dout[2];
- u8 readback;
- int i;
-
- enc_set_bank(enc, reg);
- for (i = 0; i < c; i++) {
- dout[0] = CMD_WCR(reg);
- dout[1] = data;
- spi_xfer(enc->slave, 2 * 8, dout, NULL,
- SPI_XFER_BEGIN | SPI_XFER_END);
- readback = enc_r8(enc, reg);
- if (readback == data)
- break;
- /* wait 1ms */
- udelay(1000);
- }
- if (i == c) {
- printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
- }
-}
-
-/*
- * Read ENC RAM into buffer
- */
-static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
-{
- u8 dout[1];
-
- dout[0] = CMD_RBM;
- spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
- spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
-#ifdef DEBUG
- puts("Rx:\n");
- print_buffer(0, buf, 1, length, 0);
-#endif
-}
-
-/*
- * Write buffer into ENC RAM
- */
-static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
-{
- u8 dout[2];
- dout[0] = CMD_WBM;
- dout[1] = control;
- spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
- spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
-#ifdef DEBUG
- puts("Tx:\n");
- print_buffer(0, buf, 1, length, 0);
-#endif
-}
-
-/*
- * Try to claim the SPI bus.
- * Print error message on failure.
- */
-static int enc_claim_bus(enc_dev_t *enc)
-{
- int rc = spi_claim_bus(enc->slave);
- if (rc)
- printf("%s: failed to claim SPI bus\n", enc->dev->name);
- return rc;
-}
-
-/*
- * Release previously claimed SPI bus.
- * This function is mainly for symmetry to enc_claim_bus().
- * Let the toolchain decide to inline it...
- */
-static void enc_release_bus(enc_dev_t *enc)
-{
- spi_release_bus(enc->slave);
-}
-
-/*
- * Read PHY register
- */
-static u16 enc_phy_read(enc_dev_t *enc, const u8 addr)
-{
- uint64_t etime;
- u8 status;
-
- enc_w8(enc, CTL_REG_MIREGADR, addr);
- enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
- /* 1 second timeout - only happens on hardware problem */
- etime = get_ticks() + get_tbclk();
- /* poll MISTAT.BUSY bit until operation is complete */
- do
- {
- status = enc_r8(enc, CTL_REG_MISTAT);
- } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
- if (status & ENC_MISTAT_BUSY) {
- printf("%s: timeout reading phy\n", enc->dev->name);
- return 0;
- }
- enc_w8(enc, CTL_REG_MICMD, 0);
- return enc_r16(enc, CTL_REG_MIRDL);
-}
-
-/*
- * Write PHY register
- */
-static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
-{
- uint64_t etime;
- u8 status;
-
- enc_w8(enc, CTL_REG_MIREGADR, addr);
- enc_w16(enc, CTL_REG_MIWRL, data);
- /* 1 second timeout - only happens on hardware problem */
- etime = get_ticks() + get_tbclk();
- /* poll MISTAT.BUSY bit until operation is complete */
- do
- {
- status = enc_r8(enc, CTL_REG_MISTAT);
- } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
- if (status & ENC_MISTAT_BUSY) {
- printf("%s: timeout writing phy\n", enc->dev->name);
- return;
- }
-}
-
-/*
- * Verify link status, wait if necessary
- *
- * Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
- * half/full duplex is a pure setup matter. For the time being, this driver
- * will setup in half duplex mode only.
- */
-static int enc_phy_link_wait(enc_dev_t *enc)
-{
- u16 status;
- int duplex;
- uint64_t etime;
-
-#ifdef CONFIG_ENC_SILENTLINK
- /* check if we have a link, then just return */
- status = enc_phy_read(enc, PHY_REG_PHSTAT1);
- if (status & ENC_PHSTAT1_LLSTAT)
- return 0;
-#endif
-
- /* wait for link with 1 second timeout */
- etime = get_ticks() + get_tbclk();
- while (get_ticks() <= etime) {
- status = enc_phy_read(enc, PHY_REG_PHSTAT1);
- if (status & ENC_PHSTAT1_LLSTAT) {
- /* now we have a link */
- status = enc_phy_read(enc, PHY_REG_PHSTAT2);
- duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
- printf("%s: link up, 10Mbps %s-duplex\n",
- enc->dev->name, duplex ? "full" : "half");
- return 0;
- }
- udelay(1000);
- }
-
- /* timeout occurred */
- printf("%s: link down\n", enc->dev->name);
- return 1;
-}
-
-/*
- * This function resets the receiver only.
- */
-static void enc_reset_rx(enc_dev_t *enc)
-{
- u8 econ1;
-
- econ1 = enc_r8(enc, CTL_REG_ECON1);
- if ((econ1 & ENC_ECON1_RXRST) == 0) {
- enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
- enc->rx_reset_counter = RX_RESET_COUNTER;
- }
-}
-
-/*
- * Reset receiver and reenable it.
- */
-static void enc_reset_rx_call(enc_dev_t *enc)
-{
- enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
- enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
-}
-
-/*
- * Copy a packet from the receive ring and forward it to
- * the protocol stack.
- */
-static void enc_receive(enc_dev_t *enc)
-{
- u8 *packet = (u8 *)net_rx_packets[0];
- u16 pkt_len;
- u16 copy_len;
- u16 status;
- u8 pkt_cnt = 0;
- u16 rxbuf_rdpt;
- u8 hbuf[6];
-
- enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
- do {
- enc_rbuf(enc, 6, hbuf);
- enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
- pkt_len = hbuf[2] | (hbuf[3] << 8);
- status = hbuf[4] | (hbuf[5] << 8);
- debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
- enc->next_pointer, pkt_len, status);
- if (pkt_len <= ENC_MAX_FRM_LEN)
- copy_len = pkt_len;
- else
- copy_len = 0;
- if ((status & (1L << 7)) == 0) /* check Received Ok bit */
- copy_len = 0;
- /* check if next pointer is resonable */
- if (enc->next_pointer >= ENC_TX_BUF_START)
- copy_len = 0;
- if (copy_len > 0) {
- enc_rbuf(enc, copy_len, packet);
- }
- /* advance read pointer to next pointer */
- enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
- /* decrease packet counter */
- enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
- /*
- * Only odd values should be written to ERXRDPTL,
- * see errata B4 pt.13
- */
- rxbuf_rdpt = enc->next_pointer - 1;
- if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
- (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
- enc_w16(enc, CTL_REG_ERXRDPTL,
- enc_r16(enc, CTL_REG_ERXNDL));
- } else {
- enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
- }
- /* read pktcnt */
- pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
- if (copy_len == 0) {
- (void)enc_r8(enc, CTL_REG_EIR);
- enc_reset_rx(enc);
- printf("%s: receive copy_len=0\n", enc->dev->name);
- continue;
- }
- /*
- * Because net_process_received_packet() might call enc_send(),
- * we need to release the SPI bus, call
- * net_process_received_packet(), reclaim the bus.
- */
- enc_release_bus(enc);
- net_process_received_packet(packet, pkt_len);
- if (enc_claim_bus(enc))
- return;
- (void)enc_r8(enc, CTL_REG_EIR);
- } while (pkt_cnt);
- /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
-}
-
-/*
- * Poll for completely received packets.
- */
-static void enc_poll(enc_dev_t *enc)
-{
- u8 eir_reg;
- u8 pkt_cnt;
-
- (void)enc_r8(enc, CTL_REG_ESTAT);
- eir_reg = enc_r8(enc, CTL_REG_EIR);
- if (eir_reg & ENC_EIR_TXIF) {
- /* clear TXIF bit in EIR */
- enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
- }
- /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
- pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
- if (pkt_cnt > 0) {
- if ((eir_reg & ENC_EIR_PKTIF) == 0) {
- debug("enc_poll: pkt cnt > 0, but pktif not set\n");
- }
- enc_receive(enc);
- /*
- * clear PKTIF bit in EIR, this should not need to be done
- * but it seems like we get problems if we do not
- */
- enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
- }
- if (eir_reg & ENC_EIR_RXERIF) {
- printf("%s: rx error\n", enc->dev->name);
- enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
- }
- if (eir_reg & ENC_EIR_TXERIF) {
- printf("%s: tx error\n", enc->dev->name);
- enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
- }
-}
-
-/*
- * Completely Reset the ENC
- */
-static void enc_reset(enc_dev_t *enc)
-{
- u8 dout[1];
-
- dout[0] = CMD_SRC;
- spi_xfer(enc->slave, 8, dout, NULL,
- SPI_XFER_BEGIN | SPI_XFER_END);
- /* sleep 1 ms. See errata pt. 2 */
- udelay(1000);
-}
-
-/*
- * Initialisation data for most of the ENC registers
- */
-static const u16 enc_initdata[] = {
- /*
- * Setup the buffer space. The reset values are valid for the
- * other pointers.
- *
- * We shall not write to ERXST, see errata pt. 5. Instead we
- * have to make sure that ENC_RX_BUS_START is 0.
- */
- CTL_REG_ERXSTL, ENC_RX_BUF_START,
- CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
- CTL_REG_ERXNDL, ENC_RX_BUF_END,
- CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
- CTL_REG_ERDPTL, ENC_RX_BUF_START,
- CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
- /*
- * Set the filter to receive only good-CRC, unicast and broadcast
- * frames.
- * Note: some DHCP servers return their answers as broadcasts!
- * So its unwise to remove broadcast from this. This driver
- * might incur receiver overruns with packet loss on a broadcast
- * flooded network.
- */
- CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
-
- /* enable MAC to receive frames */
- CTL_REG_MACON1,
- ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
-
- /* configure pad, tx-crc and duplex */
- CTL_REG_MACON3,
- ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
- ENC_MACON3_FRMLNEN,
-
- /* Allow infinite deferals if the medium is continously busy */
- CTL_REG_MACON4, ENC_MACON4_DEFER,
-
- /* Late collisions occur beyond 63 bytes */
- CTL_REG_MACLCON2, 63,
-
- /*
- * Set (low byte) Non-Back-to_Back Inter-Packet Gap.
- * Recommended 0x12
- */
- CTL_REG_MAIPGL, 0x12,
-
- /*
- * Set (high byte) Non-Back-to_Back Inter-Packet Gap.
- * Recommended 0x0c for half-duplex. Nothing for full-duplex
- */
- CTL_REG_MAIPGH, 0x0C,
-
- /* set maximum frame length */
- CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
- CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
-
- /*
- * Set MAC back-to-back inter-packet gap.
- * Recommended 0x12 for half duplex
- * and 0x15 for full duplex.
- */
- CTL_REG_MABBIPG, 0x12,
-
- /* end of table */
- 0xffff
-};
-
-/*
- * Wait for the XTAL oscillator to become ready
- */
-static int enc_clock_wait(enc_dev_t *enc)
-{
- uint64_t etime;
-
- /* one second timeout */
- etime = get_ticks() + get_tbclk();
-
- /*
- * Wait for CLKRDY to become set (i.e., check that we can
- * communicate with the ENC)
- */
- do
- {
- if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
- return 0;
- } while (get_ticks() <= etime);
-
- printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
- return -1;
-}
-
-/*
- * Write the MAC address into the ENC
- */
-static int enc_write_macaddr(enc_dev_t *enc)
-{
- unsigned char *p = enc->dev->enetaddr;
-
- enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
- enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
- enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
- enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
- enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
- enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
- return 0;
-}
-
-/*
- * Setup most of the ENC registers
- */
-static int enc_setup(enc_dev_t *enc)
-{
- u16 phid1 = 0;
- u16 phid2 = 0;
- const u16 *tp;
-
- /* reset enc struct values */
- enc->next_pointer = ENC_RX_BUF_START;
- enc->rx_reset_counter = RX_RESET_COUNTER;
- enc->bank = 0xff; /* invalidate current bank in enc28j60 */
-
- /* verify PHY identification */
- phid1 = enc_phy_read(enc, PHY_REG_PHID1);
- phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
- if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
- printf("%s: failed to identify PHY. Found %04x:%04x\n",
- enc->dev->name, phid1, phid2);
- return -1;
- }
-
- /* now program registers */
- for (tp = enc_initdata; *tp != 0xffff; tp += 2)
- enc_w8_retry(enc, tp[0], tp[1], 10);
-
- /*
- * Prevent automatic loopback of data beeing transmitted by setting
- * ENC_PHCON2_HDLDIS
- */
- enc_phy_write(enc, PHY_REG_PHCON2, (1<<8));
-
- /*
- * LEDs configuration
- * LEDA: LACFG = 0100 -> display link status
- * LEDB: LBCFG = 0111 -> display TX & RX activity
- * STRCH = 1 -> LED pulses
- */
- enc_phy_write(enc, PHY_REG_PHLCON, 0x0472);
-
- /* Reset PDPXMD-bit => half duplex */
- enc_phy_write(enc, PHY_REG_PHCON1, 0);
-
- return 0;
-}
-
-/*
- * Check if ENC has been initialized.
- * If not, try to initialize it.
- * Remember initialized state in struct.
- */
-static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
-{
- if (enc->initstate >= requiredstate)
- return 0;
-
- if (enc->initstate < setupdone) {
- /* Initialize the ENC only */
- enc_reset(enc);
- /* if any of functions fails, skip the rest and return an error */
- if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
- return -1;
- }
- enc->initstate = setupdone;
- }
- /* if that's all we need, return here */
- if (enc->initstate >= requiredstate)
- return 0;
-
- /* now wait for link ready condition */
- if (enc_phy_link_wait(enc)) {
- return -1;
- }
- enc->initstate = linkready;
- return 0;
-}
-
-#if defined(CONFIG_CMD_MII)
-/*
- * Read a PHY register.
- *
- * This function is registered with miiphy_register().
- */
-int enc_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
-{
- u16 value = 0;
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- enc_dev_t *enc;
-
- if (!dev || phy_adr != 0)
- return -1;
-
- enc = dev->priv;
- if (enc_claim_bus(enc))
- return -1;
- if (enc_initcheck(enc, setupdone)) {
- enc_release_bus(enc);
- return -1;
- }
- value = enc_phy_read(enc, reg);
- enc_release_bus(enc);
- return value;
-}
-
-/*
- * Write a PHY register.
- *
- * This function is registered with miiphy_register().
- */
-int enc_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
- u16 value)
-{
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- enc_dev_t *enc;
-
- if (!dev || phy_adr != 0)
- return -1;
-
- enc = dev->priv;
- if (enc_claim_bus(enc))
- return -1;
- if (enc_initcheck(enc, setupdone)) {
- enc_release_bus(enc);
- return -1;
- }
- enc_phy_write(enc, reg, value);
- enc_release_bus(enc);
- return 0;
-}
-#endif
-
-/*
- * Write hardware (MAC) address.
- *
- * This function entered into eth_device structure.
- */
-static int enc_write_hwaddr(struct eth_device *dev)
-{
- enc_dev_t *enc = dev->priv;
-
- if (enc_claim_bus(enc))
- return -1;
- if (enc_initcheck(enc, setupdone)) {
- enc_release_bus(enc);
- return -1;
- }
- enc_release_bus(enc);
- return 0;
-}
-
-/*
- * Initialize ENC28J60 for use.
- *
- * This function entered into eth_device structure.
- */
-static int enc_init(struct eth_device *dev, bd_t *bis)
-{
- enc_dev_t *enc = dev->priv;
-
- if (enc_claim_bus(enc))
- return -1;
- if (enc_initcheck(enc, linkready)) {
- enc_release_bus(enc);
- return -1;
- }
- /* enable receive */
- enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
- enc_release_bus(enc);
- return 0;
-}
-
-/*
- * Check for received packets.
- *
- * This function entered into eth_device structure.
- */
-static int enc_recv(struct eth_device *dev)
-{
- enc_dev_t *enc = dev->priv;
-
- if (enc_claim_bus(enc))
- return -1;
- if (enc_initcheck(enc, linkready)) {
- enc_release_bus(enc);
- return -1;
- }
- /* Check for dead receiver */
- if (enc->rx_reset_counter > 0)
- enc->rx_reset_counter--;
- else
- enc_reset_rx_call(enc);
- enc_poll(enc);
- enc_release_bus(enc);
- return 0;
-}
-
-/*
- * Send a packet.
- *
- * This function entered into eth_device structure.
- *
- * Should we wait here until we have a Link? Or shall we leave that to
- * protocol retries?
- */
-static int enc_send(
- struct eth_device *dev,
- void *packet,
- int length)
-{
- enc_dev_t *enc = dev->priv;
-
- if (enc_claim_bus(enc))
- return -1;
- if (enc_initcheck(enc, linkready)) {
- enc_release_bus(enc);
- return -1;
- }
- /* setup transmit pointers */
- enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
- enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
- enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
- /* write packet to ENC */
- enc_wbuf(enc, length, (u8 *) packet, 0x00);
- /*
- * Check that the internal transmit logic has not been altered
- * by excessive collisions. Reset transmitter if so.
- * See Errata B4 12 and 14.
- */
- if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
- enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
- enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
- }
- enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
- /* start transmitting */
- enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
- enc_release_bus(enc);
- return 0;
-}
-
-/*
- * Finish use of ENC.
- *
- * This function entered into eth_device structure.
- */
-static void enc_halt(struct eth_device *dev)
-{
- enc_dev_t *enc = dev->priv;
-
- if (enc_claim_bus(enc))
- return;
- /* Just disable receiver */
- enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
- enc_release_bus(enc);
-}
-
-/*
- * This is the only exported function.
- *
- * It may be called several times with different bus:cs combinations.
- */
-int enc28j60_initialize(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct eth_device *dev;
- enc_dev_t *enc;
-
- /* try to allocate, check and clear eth_device object */
- dev = malloc(sizeof(*dev));
- if (!dev) {
- return -1;
- }
- memset(dev, 0, sizeof(*dev));
-
- /* try to allocate, check and clear enc_dev_t object */
- enc = malloc(sizeof(*enc));
- if (!enc) {
- free(dev);
- return -1;
- }
- memset(enc, 0, sizeof(*enc));
-
- /* try to setup the SPI slave */
- enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
- if (!enc->slave) {
- printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
- free(enc);
- free(dev);
- return -1;
- }
-
- enc->dev = dev;
- /* now fill the eth_device object */
- dev->priv = enc;
- dev->init = enc_init;
- dev->halt = enc_halt;
- dev->send = enc_send;
- dev->recv = enc_recv;
- dev->write_hwaddr = enc_write_hwaddr;
- sprintf(dev->name, "enc%i.%i", bus, cs);
- eth_register(dev);
-#if defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = enc_miiphy_read;
- mdiodev->write = enc_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
- return 0;
-}
diff --git a/drivers/net/enc28j60.h b/drivers/net/enc28j60.h
deleted file mode 100644
index 289e412..0000000
--- a/drivers/net/enc28j60.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * (X) extracted from enc28j60.c
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _enc28j60_h
-#define _enc28j60_h
-
-/*
- * SPI Commands
- *
- * Bits 7-5: Command
- * Bits 4-0: Register
- */
-#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */
-#define CMD_RBM 0x3a /* Read Buffer Memory */
-#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */
-#define CMD_WBM 0x7a /* Write Buffer Memory */
-#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */
-#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */
-#define CMD_SRC 0xff /* System Reset Command */
-
-/* NEW: encode (bank number+1) in upper byte */
-
-/* Common Control Registers accessible in all Banks */
-#define CTL_REG_EIE 0x01B
-#define CTL_REG_EIR 0x01C
-#define CTL_REG_ESTAT 0x01D
-#define CTL_REG_ECON2 0x01E
-#define CTL_REG_ECON1 0x01F
-
-/* Control Registers accessible in Bank 0 */
-#define CTL_REG_ERDPTL 0x100
-#define CTL_REG_ERDPTH 0x101
-#define CTL_REG_EWRPTL 0x102
-#define CTL_REG_EWRPTH 0x103
-#define CTL_REG_ETXSTL 0x104
-#define CTL_REG_ETXSTH 0x105
-#define CTL_REG_ETXNDL 0x106
-#define CTL_REG_ETXNDH 0x107
-#define CTL_REG_ERXSTL 0x108
-#define CTL_REG_ERXSTH 0x109
-#define CTL_REG_ERXNDL 0x10A
-#define CTL_REG_ERXNDH 0x10B
-#define CTL_REG_ERXRDPTL 0x10C
-#define CTL_REG_ERXRDPTH 0x10D
-#define CTL_REG_ERXWRPTL 0x10E
-#define CTL_REG_ERXWRPTH 0x10F
-#define CTL_REG_EDMASTL 0x110
-#define CTL_REG_EDMASTH 0x111
-#define CTL_REG_EDMANDL 0x112
-#define CTL_REG_EDMANDH 0x113
-#define CTL_REG_EDMADSTL 0x114
-#define CTL_REG_EDMADSTH 0x115
-#define CTL_REG_EDMACSL 0x116
-#define CTL_REG_EDMACSH 0x117
-
-/* Control Registers accessible in Bank 1 */
-#define CTL_REG_EHT0 0x200
-#define CTL_REG_EHT1 0x201
-#define CTL_REG_EHT2 0x202
-#define CTL_REG_EHT3 0x203
-#define CTL_REG_EHT4 0x204
-#define CTL_REG_EHT5 0x205
-#define CTL_REG_EHT6 0x206
-#define CTL_REG_EHT7 0x207
-#define CTL_REG_EPMM0 0x208
-#define CTL_REG_EPMM1 0x209
-#define CTL_REG_EPMM2 0x20A
-#define CTL_REG_EPMM3 0x20B
-#define CTL_REG_EPMM4 0x20C
-#define CTL_REG_EPMM5 0x20D
-#define CTL_REG_EPMM6 0x20E
-#define CTL_REG_EPMM7 0x20F
-#define CTL_REG_EPMCSL 0x210
-#define CTL_REG_EPMCSH 0x211
-#define CTL_REG_EPMOL 0x214
-#define CTL_REG_EPMOH 0x215
-#define CTL_REG_EWOLIE 0x216
-#define CTL_REG_EWOLIR 0x217
-#define CTL_REG_ERXFCON 0x218
-#define CTL_REG_EPKTCNT 0x219
-
-/* Control Registers accessible in Bank 2 */
-#define CTL_REG_MACON1 0x300
-#define CTL_REG_MACON2 0x301
-#define CTL_REG_MACON3 0x302
-#define CTL_REG_MACON4 0x303
-#define CTL_REG_MABBIPG 0x304
-#define CTL_REG_MAIPGL 0x306
-#define CTL_REG_MAIPGH 0x307
-#define CTL_REG_MACLCON1 0x308
-#define CTL_REG_MACLCON2 0x309
-#define CTL_REG_MAMXFLL 0x30A
-#define CTL_REG_MAMXFLH 0x30B
-#define CTL_REG_MAPHSUP 0x30D
-#define CTL_REG_MICON 0x311
-#define CTL_REG_MICMD 0x312
-#define CTL_REG_MIREGADR 0x314
-#define CTL_REG_MIWRL 0x316
-#define CTL_REG_MIWRH 0x317
-#define CTL_REG_MIRDL 0x318
-#define CTL_REG_MIRDH 0x319
-
-/* Control Registers accessible in Bank 3 */
-#define CTL_REG_MAADR1 0x400
-#define CTL_REG_MAADR0 0x401
-#define CTL_REG_MAADR3 0x402
-#define CTL_REG_MAADR2 0x403
-#define CTL_REG_MAADR5 0x404
-#define CTL_REG_MAADR4 0x405
-#define CTL_REG_EBSTSD 0x406
-#define CTL_REG_EBSTCON 0x407
-#define CTL_REG_EBSTCSL 0x408
-#define CTL_REG_EBSTCSH 0x409
-#define CTL_REG_MISTAT 0x40A
-#define CTL_REG_EREVID 0x412
-#define CTL_REG_ECOCON 0x415
-#define CTL_REG_EFLOCON 0x417
-#define CTL_REG_EPAUSL 0x418
-#define CTL_REG_EPAUSH 0x419
-
-/* PHY Register */
-#define PHY_REG_PHCON1 0x00
-#define PHY_REG_PHSTAT1 0x01
-#define PHY_REG_PHID1 0x02
-#define PHY_REG_PHID2 0x03
-#define PHY_REG_PHCON2 0x10
-#define PHY_REG_PHSTAT2 0x11
-#define PHY_REG_PHLCON 0x14
-
-/* Receive Filter Register (ERXFCON) bits */
-#define ENC_RFR_UCEN 0x80
-#define ENC_RFR_ANDOR 0x40
-#define ENC_RFR_CRCEN 0x20
-#define ENC_RFR_PMEN 0x10
-#define ENC_RFR_MPEN 0x08
-#define ENC_RFR_HTEN 0x04
-#define ENC_RFR_MCEN 0x02
-#define ENC_RFR_BCEN 0x01
-
-/* ECON1 Register Bits */
-#define ENC_ECON1_TXRST 0x80
-#define ENC_ECON1_RXRST 0x40
-#define ENC_ECON1_DMAST 0x20
-#define ENC_ECON1_CSUMEN 0x10
-#define ENC_ECON1_TXRTS 0x08
-#define ENC_ECON1_RXEN 0x04
-#define ENC_ECON1_BSEL1 0x02
-#define ENC_ECON1_BSEL0 0x01
-
-/* ECON2 Register Bits */
-#define ENC_ECON2_AUTOINC 0x80
-#define ENC_ECON2_PKTDEC 0x40
-#define ENC_ECON2_PWRSV 0x20
-#define ENC_ECON2_VRPS 0x08
-
-/* EIR Register Bits */
-#define ENC_EIR_PKTIF 0x40
-#define ENC_EIR_DMAIF 0x20
-#define ENC_EIR_LINKIF 0x10
-#define ENC_EIR_TXIF 0x08
-#define ENC_EIR_WOLIF 0x04
-#define ENC_EIR_TXERIF 0x02
-#define ENC_EIR_RXERIF 0x01
-
-/* ESTAT Register Bits */
-#define ENC_ESTAT_INT 0x80
-#define ENC_ESTAT_LATECOL 0x10
-#define ENC_ESTAT_RXBUSY 0x04
-#define ENC_ESTAT_TXABRT 0x02
-#define ENC_ESTAT_CLKRDY 0x01
-
-/* EIE Register Bits */
-#define ENC_EIE_INTIE 0x80
-#define ENC_EIE_PKTIE 0x40
-#define ENC_EIE_DMAIE 0x20
-#define ENC_EIE_LINKIE 0x10
-#define ENC_EIE_TXIE 0x08
-#define ENC_EIE_WOLIE 0x04
-#define ENC_EIE_TXERIE 0x02
-#define ENC_EIE_RXERIE 0x01
-
-/* MACON1 Register Bits */
-#define ENC_MACON1_LOOPBK 0x10
-#define ENC_MACON1_TXPAUS 0x08
-#define ENC_MACON1_RXPAUS 0x04
-#define ENC_MACON1_PASSALL 0x02
-#define ENC_MACON1_MARXEN 0x01
-
-/* MACON2 Register Bits */
-#define ENC_MACON2_MARST 0x80
-#define ENC_MACON2_RNDRST 0x40
-#define ENC_MACON2_MARXRST 0x08
-#define ENC_MACON2_RFUNRST 0x04
-#define ENC_MACON2_MATXRST 0x02
-#define ENC_MACON2_TFUNRST 0x01
-
-/* MACON3 Register Bits */
-#define ENC_MACON3_PADCFG2 0x80
-#define ENC_MACON3_PADCFG1 0x40
-#define ENC_MACON3_PADCFG0 0x20
-#define ENC_MACON3_TXCRCEN 0x10
-#define ENC_MACON3_PHDRLEN 0x08
-#define ENC_MACON3_HFRMEN 0x04
-#define ENC_MACON3_FRMLNEN 0x02
-#define ENC_MACON3_FULDPX 0x01
-
-/* MACON4 Register Bits */
-#define ENC_MACON4_DEFER 0x40
-
-/* MICMD Register Bits */
-#define ENC_MICMD_MIISCAN 0x02
-#define ENC_MICMD_MIIRD 0x01
-
-/* MISTAT Register Bits */
-#define ENC_MISTAT_NVALID 0x04
-#define ENC_MISTAT_SCAN 0x02
-#define ENC_MISTAT_BUSY 0x01
-
-/* PHID1 and PHID2 values */
-#define ENC_PHID1_VALUE 0x0083
-#define ENC_PHID2_VALUE 0x1400
-#define ENC_PHID2_MASK 0xFC00
-
-/* PHCON1 values */
-#define ENC_PHCON1_PDPXMD 0x0100
-
-/* PHSTAT1 values */
-#define ENC_PHSTAT1_LLSTAT 0x0004
-
-/* PHSTAT2 values */
-#define ENC_PHSTAT2_LSTAT 0x0400
-#define ENC_PHSTAT2_DPXSTAT 0x0200
-
-#endif
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ff7ad91..0076d63 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <malloc.h>
#include <memalign.h>
#include <miiphy.h>
@@ -806,7 +807,16 @@
uint16_t bd_status;
ulong addr, size, end;
int i;
+
+#ifdef CONFIG_DM_ETH
+ *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
+ if (*packetp == 0) {
+ printf("%s: error allocating packetp\n", __func__);
+ return -ENOMEM;
+ }
+#else
ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
+#endif
/* Check if any critical events have happened */
ievent = readl(&fec->eth->ievent);
@@ -882,8 +892,13 @@
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)addr, frame_length);
#endif
+
+#ifdef CONFIG_DM_ETH
+ memcpy(*packetp, (char *)addr, frame_length);
+#else
memcpy(buff, (char *)addr, frame_length);
net_process_received_packet(buff, frame_length);
+#endif
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR)
@@ -997,18 +1012,9 @@
free(fec->tbd_base);
}
-#ifdef CONFIG_DM_ETH
-struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id)
-#else
-struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
-#endif
+struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
{
-#ifdef CONFIG_DM_ETH
- struct fec_priv *priv = dev_get_priv(dev);
- struct ethernet_regs *eth = priv->eth;
-#else
- struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr;
-#endif
+ struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
struct mii_dev *bus;
int ret;
@@ -1140,12 +1146,12 @@
#endif
int ret;
-#ifdef CONFIG_MX28
+#ifdef CONFIG_FEC_MXC_MDIO_BASE
/*
* The i.MX28 has two ethernet interfaces, but they are not equal.
* Only the first one can access the MDIO bus.
*/
- base_mii = MXS_ENET0_BASE;
+ base_mii = CONFIG_FEC_MXC_MDIO_BASE;
#else
base_mii = addr;
#endif
@@ -1201,10 +1207,19 @@
return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
}
+static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ if (packet)
+ free(packet);
+
+ return 0;
+}
+
static const struct eth_ops fecmxc_ops = {
.start = fecmxc_init,
.send = fecmxc_send,
.recv = fecmxc_recv,
+ .free_pkt = fecmxc_free_pkt,
.stop = fecmxc_halt,
.write_hwaddr = fecmxc_set_hwaddr,
.read_rom_hwaddr = fecmxc_read_rom_hwaddr,
@@ -1236,7 +1251,6 @@
struct eth_pdata *pdata = dev_get_platdata(dev);
struct fec_priv *priv = dev_get_priv(dev);
struct mii_dev *bus = NULL;
- int dev_id = -1;
uint32_t start;
int ret;
@@ -1257,9 +1271,13 @@
}
fec_reg_setup(priv);
- priv->dev_id = (dev_id == -1) ? 0 : dev_id;
- bus = fec_get_miibus(dev, dev_id);
+ priv->dev_id = dev->seq;
+#ifdef CONFIG_FEC_MXC_MDIO_BASE
+ bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
+#else
+ bus = fec_get_miibus((ulong)priv->eth, dev->seq);
+#endif
if (!bus) {
ret = -ENOMEM;
goto err_mii;
@@ -1274,12 +1292,11 @@
return 0;
-err_timeout:
- free(priv->phydev);
err_phy:
mdio_unregister(bus);
free(bus);
err_mii:
+err_timeout:
fec_free_descs(priv);
return ret;
}
@@ -1325,6 +1342,9 @@
static const struct udevice_id fecmxc_ids[] = {
{ .compatible = "fsl,imx6q-fec" },
+ { .compatible = "fsl,imx6sl-fec" },
+ { .compatible = "fsl,imx6sx-fec" },
+ { .compatible = "fsl,imx6ul-fec" },
{ }
};
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index 2d89cea..00d905c 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <malloc.h>
#include <command.h>
#include <config.h>
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e62aefc..fe370bf 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -915,7 +915,7 @@
if (length >= 0) {
net_process_received_packet(packet, length);
reclaim_rx_buffers(macb, macb->next_rx_tail);
- } else if (length < 0) {
+ } else {
return length;
}
}
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index ebcbed9..505a2d1 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <environment.h>
#include <malloc.h>
#include <command.h>
diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c
index 71fe984..1dd41df 100644
--- a/drivers/net/mpc8xx_fec.c
+++ b/drivers/net/mpc8xx_fec.c
@@ -7,10 +7,10 @@
#include <common.h>
#include <command.h>
-#include <commproc.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
+#include <asm/cpm_8xx.h>
#include <asm/io.h>
#include <phy.h>
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 83e3153..f2e9acf 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -890,6 +890,15 @@
mvneta_set_ucast_addr(pp, addr[5], queue);
}
+static int mvneta_write_hwaddr(struct udevice *dev)
+{
+ mvneta_mac_addr_set(dev_get_priv(dev),
+ ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
+ rxq_def);
+
+ return 0;
+}
+
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
u32 phys_addr, u32 cookie)
@@ -1753,6 +1762,7 @@
.send = mvneta_send,
.recv = mvneta_recv,
.stop = mvneta_stop,
+ .write_hwaddr = mvneta_write_hwaddr,
};
static int mvneta_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e3d31a5..62c0c2b 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5598,6 +5598,10 @@
id += base_id_add;
name = calloc(1, 16);
+ if (!name) {
+ free(plat);
+ return -ENOMEM;
+ }
sprintf(name, "mvpp2-%d", id);
/* Create child device UCLASS_ETH and bind it */
diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c
index fb088e0..421aa20 100644
--- a/drivers/net/ne2000_base.c
+++ b/drivers/net/ne2000_base.c
@@ -74,6 +74,7 @@
#include <common.h>
#include <command.h>
+#include <environment.h>
#include <net.h>
#include <malloc.h>
#include <linux/compiler.h>
diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
new file mode 100644
index 0000000..a13b331
--- /dev/null
+++ b/drivers/net/pfe_eth/Kconfig
@@ -0,0 +1,12 @@
+menuconfig FSL_PFE
+ bool "NXP PFE Ethernet driver"
+ help
+ This driver provides support for NXP's Packet Forwarding Engine.
+
+if FSL_PFE
+
+config SYS_FSL_PFE_ADDR
+ hex "PFE base address"
+ default 0x04000000
+
+endif
diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
new file mode 100644
index 0000000..6b5248f
--- /dev/null
+++ b/drivers/net/pfe_eth/Makefile
@@ -0,0 +1,12 @@
+# Copyright 2015-2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:GPL-2.0+
+
+# Layerscape PFE driver
+obj-y += pfe_cmd.o \
+ pfe_driver.o \
+ pfe_eth.o \
+ pfe_firmware.o \
+ pfe_hw.o \
+ pfe_mdio.o
diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
new file mode 100644
index 0000000..822dc0f
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * @file
+ * @brief PFE utility commands
+ */
+
+#include <net/pfe_eth/pfe_eth.h>
+
+static inline void pfe_command_help(void)
+{
+ printf("Usage: pfe [pe | status | expt ] <options>\n");
+}
+
+static void pfe_command_pe(int argc, char * const argv[])
+{
+ if (argc >= 3 && strcmp(argv[2], "pmem") == 0) {
+ if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+ int i;
+ int num;
+ int id;
+ u32 addr;
+ u32 size;
+ u32 val;
+
+ if (argc == 7) {
+ num = simple_strtoul(argv[6], NULL, 0);
+ } else if (argc == 6) {
+ num = 1;
+ } else {
+ printf("Usage: pfe pe pmem read <id> <addr> [<num>]\n");
+ return;
+ }
+
+ id = simple_strtoul(argv[4], NULL, 0);
+ addr = simple_strtoul(argv[5], NULL, 16);
+ size = 4;
+
+ for (i = 0; i < num; i++, addr += 4) {
+ val = pe_pmem_read(id, addr, size);
+ val = be32_to_cpu(val);
+ if (!(i & 3))
+ printf("%08x: ", addr);
+ printf("%08x%s", val, i == num - 1 || (i & 3)
+ == 3 ? "\n" : " ");
+ }
+
+ } else {
+ printf("Usage: pfe pe pmem read <parameters>\n");
+ }
+ } else if (argc >= 3 && strcmp(argv[2], "dmem") == 0) {
+ if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+ int i;
+ int num;
+ int id;
+ u32 addr;
+ u32 size;
+ u32 val;
+
+ if (argc == 7) {
+ num = simple_strtoul(argv[6], NULL, 0);
+ } else if (argc == 6) {
+ num = 1;
+ } else {
+ printf("Usage: pfe pe dmem read <id> <addr> [<num>]\n");
+ return;
+ }
+
+ id = simple_strtoul(argv[4], NULL, 0);
+ addr = simple_strtoul(argv[5], NULL, 16);
+ size = 4;
+
+ for (i = 0; i < num; i++, addr += 4) {
+ val = pe_dmem_read(id, addr, size);
+ val = be32_to_cpu(val);
+ if (!(i & 3))
+ printf("%08x: ", addr);
+ printf("%08x%s", val, i == num - 1 || (i & 3)
+ == 3 ? "\n" : " ");
+ }
+
+ } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+ int id;
+ u32 val;
+ u32 addr;
+ u32 size;
+
+ if (argc != 7) {
+ printf("Usage: pfe pe dmem write <id> <val> <addr>\n");
+ return;
+ }
+
+ id = simple_strtoul(argv[4], NULL, 0);
+ val = simple_strtoul(argv[5], NULL, 16);
+ val = cpu_to_be32(val);
+ addr = simple_strtoul(argv[6], NULL, 16);
+ size = 4;
+ pe_dmem_write(id, val, addr, size);
+ } else {
+ printf("Usage: pfe pe dmem [read | write] <parameters>\n");
+ }
+ } else if (argc >= 3 && strcmp(argv[2], "lmem") == 0) {
+ if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+ int i;
+ int num;
+ u32 val;
+ u32 offset;
+
+ if (argc == 6) {
+ num = simple_strtoul(argv[5], NULL, 0);
+ } else if (argc == 5) {
+ num = 1;
+ } else {
+ printf("Usage: pfe pe lmem read <offset> [<num>]\n");
+ return;
+ }
+
+ offset = simple_strtoul(argv[4], NULL, 16);
+
+ for (i = 0; i < num; i++, offset += 4) {
+ pe_lmem_read(&val, 4, offset);
+ val = be32_to_cpu(val);
+ printf("%08x%s", val, i == num - 1 || (i & 7)
+ == 7 ? "\n" : " ");
+ }
+
+ } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+ u32 val;
+ u32 offset;
+
+ if (argc != 6) {
+ printf("Usage: pfe pe lmem write <val> <offset>\n");
+ return;
+ }
+
+ val = simple_strtoul(argv[4], NULL, 16);
+ val = cpu_to_be32(val);
+ offset = simple_strtoul(argv[5], NULL, 16);
+ pe_lmem_write(&val, 4, offset);
+ } else {
+ printf("Usage: pfe pe lmem [read | write] <parameters>\n");
+ }
+ } else {
+ if (strcmp(argv[2], "help") != 0)
+ printf("Unknown option: %s\n", argv[2]);
+
+ printf("Usage: pfe pe <parameters>\n");
+ }
+}
+
+#define NUM_QUEUES 16
+
+/*
+ * qm_read_drop_stat
+ * This function is used to read the drop statistics from the TMU
+ * hw drop counter. Since the hw counter is always cleared afer
+ * reading, this function maintains the previous drop count, and
+ * adds the new value to it. That value can be retrieved by
+ * passing a pointer to it with the total_drops arg.
+ *
+ * @param tmu TMU number (0 - 3)
+ * @param queue queue number (0 - 15)
+ * @param total_drops pointer to location to store total drops (or NULL)
+ * @param do_reset if TRUE, clear total drops after updating
+ *
+ */
+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
+{
+ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
+ u32 val;
+
+ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
+ writel((tmu << 8) | queue, TMU_LLM_CTRL);
+ val = readl(TMU_TEQ_DROP_STAT);
+ qtotal[tmu][queue] += val;
+ if (total_drops)
+ *total_drops = qtotal[tmu][queue];
+ if (do_reset)
+ qtotal[tmu][queue] = 0;
+ return val;
+}
+
+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
+{
+ ssize_t len = 0;
+ u32 drops;
+
+ printf("%d-%02d, ", tmu, queue);
+
+ drops = qm_read_drop_stat(tmu, queue, NULL, 0);
+
+ /* Select queue */
+ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
+ writel((tmu << 8) | queue, TMU_LLM_CTRL);
+
+ printf("(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
+ drops, readl(TMU_TEQ_TRANS_STAT),
+ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
+ readl(TMU_LLM_QUE_DROPCNT));
+
+ return len;
+}
+
+static ssize_t tmu_queues(char *buf, int tmu)
+{
+ ssize_t len = 0;
+ int queue;
+
+ for (queue = 0; queue < 16; queue++)
+ len += tmu_queue_stats(buf + len, tmu, queue);
+
+ return len;
+}
+
+static inline void hif_status(void)
+{
+ printf("hif:\n");
+
+ printf(" tx curr bd: %x\n", readl(HIF_TX_CURR_BD_ADDR));
+ printf(" tx status: %x\n", readl(HIF_TX_STATUS));
+ printf(" tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
+
+ printf(" rx curr bd: %x\n", readl(HIF_RX_CURR_BD_ADDR));
+ printf(" rx status: %x\n", readl(HIF_RX_STATUS));
+ printf(" rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
+
+ printf("hif nocopy:\n");
+
+ printf(" tx curr bd: %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
+ printf(" tx status: %x\n", readl(HIF_NOCPY_TX_STATUS));
+ printf(" tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
+
+ printf(" rx curr bd: %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
+ printf(" rx status: %x\n", readl(HIF_NOCPY_RX_STATUS));
+ printf(" rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
+}
+
+static void gpi(int id, void *base)
+{
+ u32 val;
+
+ printf("%s%d:\n", __func__, id);
+
+ printf(" tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
+ val = readl(base + GPI_FIFO_DEBUG);
+ printf(" tx pkts: %x\n", (val >> 23) & 0x3f);
+ printf(" rx pkts: %x\n", (val >> 18) & 0x3f);
+ printf(" tx bytes: %x\n", (val >> 9) & 0x1ff);
+ printf(" rx bytes: %x\n", (val >> 0) & 0x1ff);
+ printf(" overrun: %x\n", readl(base + GPI_OVERRUN_DROPCNT));
+}
+
+static void bmu(int id, void *base)
+{
+ printf("%s%d:\n", __func__, id);
+
+ printf(" buf size: %x\n", (1 << readl(base + BMU_BUF_SIZE)));
+ printf(" buf count: %x\n", readl(base + BMU_BUF_CNT));
+ printf(" buf rem: %x\n", readl(base + BMU_REM_BUF_CNT));
+ printf(" buf curr: %x\n", readl(base + BMU_CURR_BUF_CNT));
+ printf(" free err: %x\n", readl(base + BMU_FREE_ERR_ADDR));
+}
+
+#define PESTATUS_ADDR_CLASS 0x800
+#define PEMBOX_ADDR_CLASS 0x890
+#define PESTATUS_ADDR_TMU 0x80
+#define PEMBOX_ADDR_TMU 0x290
+#define PESTATUS_ADDR_UTIL 0x0
+
+static void pfe_pe_status(int argc, char * const argv[])
+{
+ int do_clear = 0;
+ u32 id;
+ u32 dmem_addr;
+ u32 cpu_state;
+ u32 activity_counter;
+ u32 rx;
+ u32 tx;
+ u32 drop;
+ char statebuf[5];
+ u32 class_debug_reg = 0;
+
+ if (argc == 4 && strcmp(argv[3], "clear") == 0)
+ do_clear = 1;
+
+ for (id = CLASS0_ID; id < MAX_PE; id++) {
+ if (id >= TMU0_ID) {
+ if (id == TMU2_ID)
+ continue;
+ if (id == TMU0_ID)
+ printf("tmu:\n");
+ dmem_addr = PESTATUS_ADDR_TMU;
+ } else {
+ if (id == CLASS0_ID)
+ printf("class:\n");
+ dmem_addr = PESTATUS_ADDR_CLASS;
+ class_debug_reg = readl(CLASS_PE0_DEBUG + id * 4);
+ }
+
+ cpu_state = pe_dmem_read(id, dmem_addr, 4);
+ dmem_addr += 4;
+ memcpy(statebuf, (char *)&cpu_state, 4);
+ statebuf[4] = '\0';
+ activity_counter = pe_dmem_read(id, dmem_addr, 4);
+ dmem_addr += 4;
+ rx = pe_dmem_read(id, dmem_addr, 4);
+ if (do_clear)
+ pe_dmem_write(id, 0, dmem_addr, 4);
+ dmem_addr += 4;
+ tx = pe_dmem_read(id, dmem_addr, 4);
+ if (do_clear)
+ pe_dmem_write(id, 0, dmem_addr, 4);
+ dmem_addr += 4;
+ drop = pe_dmem_read(id, dmem_addr, 4);
+ if (do_clear)
+ pe_dmem_write(id, 0, dmem_addr, 4);
+ dmem_addr += 4;
+
+ if (id >= TMU0_ID) {
+ printf("%d: state=%4s ctr=%08x rx=%x qstatus=%x\n",
+ id - TMU0_ID, statebuf,
+ cpu_to_be32(activity_counter),
+ cpu_to_be32(rx), cpu_to_be32(tx));
+ } else {
+ printf("%d: pc=1%04x ldst=%04x state=%4s ctr=%08x rx=%x tx=%x drop=%x\n",
+ id - CLASS0_ID, class_debug_reg & 0xFFFF,
+ class_debug_reg >> 16,
+ statebuf, cpu_to_be32(activity_counter),
+ cpu_to_be32(rx), cpu_to_be32(tx),
+ cpu_to_be32(drop));
+ }
+ }
+}
+
+static void pfe_command_status(int argc, char * const argv[])
+{
+ if (argc >= 3 && strcmp(argv[2], "pe") == 0) {
+ pfe_pe_status(argc, argv);
+ } else if (argc == 3 && strcmp(argv[2], "bmu") == 0) {
+ bmu(1, BMU1_BASE_ADDR);
+ bmu(2, BMU2_BASE_ADDR);
+ } else if (argc == 3 && strcmp(argv[2], "hif") == 0) {
+ hif_status();
+ } else if (argc == 3 && strcmp(argv[2], "gpi") == 0) {
+ gpi(0, EGPI1_BASE_ADDR);
+ gpi(1, EGPI2_BASE_ADDR);
+ gpi(3, HGPI_BASE_ADDR);
+ } else if (argc == 3 && strcmp(argv[2], "tmu0_queues") == 0) {
+ tmu_queues(NULL, 0);
+ } else if (argc == 3 && strcmp(argv[2], "tmu1_queues") == 0) {
+ tmu_queues(NULL, 1);
+ } else if (argc == 3 && strcmp(argv[2], "tmu3_queues") == 0) {
+ tmu_queues(NULL, 3);
+ } else {
+ printf("Usage: pfe status [pe <clear> | bmu | gpi | hif | tmuX_queues ]\n");
+ }
+}
+
+#define EXPT_DUMP_ADDR 0x1fa8
+#define EXPT_REG_COUNT 20
+static const char *register_names[EXPT_REG_COUNT] = {
+ " pc", "ECAS", " EID", " ED",
+ " sp", " r1", " r2", " r3",
+ " r4", " r5", " r6", " r7",
+ " r8", " r9", " r10", " r11",
+ " r12", " r13", " r14", " r15"
+};
+
+static void pfe_command_expt(int argc, char * const argv[])
+{
+ unsigned int id, i, val, addr;
+
+ if (argc == 3) {
+ id = simple_strtoul(argv[2], NULL, 0);
+ addr = EXPT_DUMP_ADDR;
+ printf("Exception information for PE %d:\n", id);
+ for (i = 0; i < EXPT_REG_COUNT; i++) {
+ val = pe_dmem_read(id, addr, 4);
+ val = be32_to_cpu(val);
+ printf("%s:%08x%s", register_names[i], val,
+ (i & 3) == 3 ? "\n" : " ");
+ addr += 4;
+ }
+ } else {
+ printf("Usage: pfe expt <id>\n");
+ }
+}
+
+#ifdef PFE_RESET_WA
+/*This function sends a dummy packet to HIF through TMU3 */
+static void send_dummy_pkt_to_hif(void)
+{
+ u32 buf;
+ static u32 dummy_pkt[] = {
+ 0x4200800a, 0x01000003, 0x00018100, 0x00000000,
+ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
+ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
+ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
+
+ /*Allocate BMU2 buffer */
+ buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
+
+ debug("Sending a dummy pkt to HIF %x\n", buf);
+ buf += 0x80;
+ memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
+
+ /*Write length and pkt to TMU*/
+ writel(0x03000042, TMU_PHY_INQ_PKTPTR);
+ writel(buf, TMU_PHY_INQ_PKTINFO);
+}
+
+static void pfe_command_stop(int argc, char * const argv[])
+{
+ int pfe_pe_id, hif_stop_loop = 10;
+ u32 rx_status;
+
+ printf("Stopping PFE...\n");
+
+ /*Mark all descriptors as LAST_BD */
+ hif_rx_desc_disable();
+
+ /*If HIF Rx BDP is busy send a dummy packet */
+ do {
+ rx_status = readl(HIF_RX_STATUS);
+ if (rx_status & BDP_CSR_RX_DMA_ACTV)
+ send_dummy_pkt_to_hif();
+ udelay(10);
+ } while (hif_stop_loop--);
+
+ if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
+ printf("Unable to stop HIF\n");
+
+ /*Disable Class PEs */
+ for (pfe_pe_id = CLASS0_ID; pfe_pe_id <= CLASS_MAX_ID; pfe_pe_id++) {
+ /*Inform PE to stop */
+ pe_dmem_write(pfe_pe_id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
+ udelay(10);
+
+ /*Read status */
+ if (!pe_dmem_read(pfe_pe_id, PEMBOX_ADDR_CLASS + 4, 4))
+ printf("Failed to stop PE%d\n", pfe_pe_id);
+ }
+
+ /*Disable TMU PEs */
+ for (pfe_pe_id = TMU0_ID; pfe_pe_id <= TMU_MAX_ID; pfe_pe_id++) {
+ if (pfe_pe_id == TMU2_ID)
+ continue;
+
+ /*Inform PE to stop */
+ pe_dmem_write(pfe_pe_id, 1, PEMBOX_ADDR_TMU, 4);
+ udelay(10);
+
+ /*Read status */
+ if (!pe_dmem_read(pfe_pe_id, PEMBOX_ADDR_TMU + 4, 4))
+ printf("Failed to stop PE%d\n", pfe_pe_id);
+ }
+}
+#endif
+
+static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc == 1 || strcmp(argv[1], "help") == 0) {
+ pfe_command_help();
+ return CMD_RET_SUCCESS;
+ }
+
+ if (strcmp(argv[1], "pe") == 0) {
+ pfe_command_pe(argc, argv);
+ } else if (strcmp(argv[1], "status") == 0) {
+ pfe_command_status(argc, argv);
+ } else if (strcmp(argv[1], "expt") == 0) {
+ pfe_command_expt(argc, argv);
+#ifdef PFE_RESET_WA
+ } else if (strcmp(argv[1], "stop") == 0) {
+ pfe_command_stop(argc, argv);
+#endif
+ } else {
+ printf("Unknown option: %s\n", argv[1]);
+ pfe_command_help();
+ return CMD_RET_FAILURE;
+ }
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ pfe, 7, 1, pfe_command,
+ "Performs PFE lib utility functions",
+ "Usage:\n"
+ "pfe <options>"
+);
diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
new file mode 100644
index 0000000..a9991f5
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe_firmware.h>
+
+static struct tx_desc_s *g_tx_desc;
+static struct rx_desc_s *g_rx_desc;
+
+/*
+ * HIF Rx interface function
+ * Reads the rx descriptor from the current location (rx_to_read).
+ * - If the descriptor has a valid data/pkt, then get the data pointer
+ * - check for the input rx phy number
+ * - increment the rx data pointer by pkt_head_room_size
+ * - decrement the data length by pkt_head_room_size
+ * - handover the packet to caller.
+ *
+ * @param[out] pkt_ptr - Pointer to store rx packet
+ * @param[out] phy_port - Pointer to store recv phy port
+ *
+ * @return -1 if no packet, else return length of packet.
+ */
+int pfe_recv(uchar **pkt_ptr, int *phy_port)
+{
+ struct rx_desc_s *rx_desc = g_rx_desc;
+ struct buf_desc *bd;
+ int len = 0;
+
+ struct hif_header_s *hif_header;
+
+ bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+ if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+ return len; /* No pending Rx packet */
+
+ /* this len include hif_header(8 bytes) */
+ len = readl(&bd->ctrl) & 0xFFFF;
+
+ hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
+
+ /* Get the receive port info from the packet */
+ debug("Pkt received:");
+ debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+ hif_header, len, hif_header->port_no, readl(&bd->status));
+#ifdef DEBUG
+ {
+ int i;
+ unsigned char *p = (unsigned char *)hif_header;
+
+ for (i = 0; i < len; i++) {
+ if (!(i % 16))
+ printf("\n");
+ printf(" %02x", p[i]);
+ }
+ printf("\n");
+ }
+#endif
+
+ *pkt_ptr = (uchar *)(hif_header + 1);
+ *phy_port = hif_header->port_no;
+ len -= sizeof(struct hif_header_s);
+
+ return len;
+}
+
+/*
+ * HIF function to check the Rx done
+ * This function will check the rx done indication of the current rx_to_read
+ * locations
+ * if success, moves the rx_to_read to next location.
+ */
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct rx_desc_s *rx_desc = g_rx_desc;
+ struct buf_desc *bd;
+
+ debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
+ rx_desc->rx_to_read);
+
+ bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+ /* reset the control field */
+ writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
+ | BD_CTRL_DIR), &bd->ctrl);
+ writel(0, &bd->status);
+
+ debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
+ readl(&bd->ctrl));
+
+ /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
+ * BDP need not wait for rx_poll_cycle time to fetch the descriptor,
+ * In idle state (ie., no rx pkt), BDP will not fetch
+ * the descriptor even if strobe is given.
+ */
+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+ /* increment the rx_to_read index to next location */
+ rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
+ & (rx_desc->rx_ring_size - 1);
+
+ debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
+
+ return 0;
+}
+
+/*
+ * HIF Tx interface function
+ * This function sends a single packet to PFE from HIF interface.
+ * - No interrupt indication on tx completion.
+ * - Data is copied to tx buffers before tx descriptor is updated
+ * and TX DMA is enabled.
+ *
+ * @param[in] phy_port Phy port number to send out this packet
+ * @param[in] data Pointer to the data
+ * @param[in] length Length of the ethernet packet to be transferred.
+ *
+ * @return -1 if tx Q is full, else returns the tx location where the pkt is
+ * placed.
+ */
+int pfe_send(int phy_port, void *data, int length)
+{
+ struct tx_desc_s *tx_desc = g_tx_desc;
+ struct buf_desc *bd;
+ struct hif_header_s hif_header;
+ u8 *tx_buf_va;
+
+ debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
+ data, length, tx_desc->tx_base, tx_desc->tx_to_send);
+
+ bd = tx_desc->tx_base + tx_desc->tx_to_send;
+
+ /* check queue-full condition */
+ if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+ return -1;
+
+ /* PFE checks for min pkt size */
+ if (length < MIN_PKT_SIZE)
+ length = MIN_PKT_SIZE;
+
+ tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
+ debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
+ readl(&bd->data));
+
+ /* Fill the gemac/phy port number to send this packet out */
+ memset(&hif_header, 0, sizeof(struct hif_header_s));
+ hif_header.port_no = phy_port;
+
+ memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
+ memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
+ length += sizeof(struct hif_header_s);
+
+#ifdef DEBUG
+ {
+ int i;
+ unsigned char *p = (unsigned char *)tx_buf_va;
+
+ for (i = 0; i < length; i++) {
+ if (!(i % 16))
+ printf("\n");
+ printf("%02x ", p[i]);
+ }
+ }
+#endif
+
+ debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
+ readl(&bd->ctrl));
+
+ /* fill the tx desc */
+ writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
+ &bd->ctrl);
+ writel(0, &bd->status);
+
+ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
+
+ udelay(100);
+
+ return tx_desc->tx_to_send;
+}
+
+/*
+ * HIF function to check the Tx done
+ * This function will check the tx done indication of the current tx_to_send
+ * locations
+ * if success, moves the tx_to_send to next location.
+ *
+ * @return -1 if TX ownership bit is not cleared by hw.
+ * else on success (tx done completion) return zero.
+ */
+int pfe_tx_done(void)
+{
+ struct tx_desc_s *tx_desc = g_tx_desc;
+ struct buf_desc *bd;
+
+ debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
+ tx_desc->tx_to_send);
+
+ bd = tx_desc->tx_base + tx_desc->tx_to_send;
+
+ /* check queue-full condition */
+ if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+ return -1;
+
+ /* reset the control field */
+ writel(0, &bd->ctrl);
+ writel(0, &bd->status);
+
+ debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
+ readl(&bd->ctrl));
+
+ /* increment the txtosend index to next location */
+ tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
+ & (tx_desc->tx_ring_size - 1);
+
+ debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
+
+ return 0;
+}
+
+/*
+ * Helper function to dump Rx descriptors.
+ */
+static inline void hif_rx_desc_dump(void)
+{
+ struct buf_desc *bd_va;
+ int i;
+ struct rx_desc_s *rx_desc;
+
+ if (!g_rx_desc) {
+ printf("%s: HIF Rx desc no init\n", __func__);
+ return;
+ }
+
+ rx_desc = g_rx_desc;
+ bd_va = rx_desc->rx_base;
+
+ debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
+ rx_desc->rx_base_pa);
+ for (i = 0; i < rx_desc->rx_ring_size; i++) {
+ debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
+ readl(&bd_va->status),
+ readl(&bd_va->ctrl),
+ readl(&bd_va->data),
+ readl(&bd_va->next));
+ bd_va++;
+ }
+}
+
+/*
+ * This function mark all Rx descriptors as LAST_BD.
+ */
+void hif_rx_desc_disable(void)
+{
+ int i;
+ struct rx_desc_s *rx_desc;
+ struct buf_desc *bd_va;
+
+ if (!g_rx_desc) {
+ printf("%s: HIF Rx desc not initialized\n", __func__);
+ return;
+ }
+
+ rx_desc = g_rx_desc;
+ bd_va = rx_desc->rx_base;
+
+ for (i = 0; i < rx_desc->rx_ring_size; i++) {
+ writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
+ bd_va++;
+ }
+}
+
+/*
+ * HIF Rx Desc initialization function.
+ */
+static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
+{
+ u32 ctrl;
+ struct buf_desc *bd_va;
+ struct buf_desc *bd_pa;
+ struct rx_desc_s *rx_desc;
+ u32 rx_buf_pa;
+ int i;
+
+ /* sanity check */
+ if (g_rx_desc) {
+ printf("%s: HIF Rx desc re-init request\n", __func__);
+ return 0;
+ }
+
+ rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
+ if (!rx_desc) {
+ printf("%s: Memory allocation failure\n", __func__);
+ return -ENOMEM;
+ }
+ memset(rx_desc, 0, sizeof(struct rx_desc_s));
+
+ /* init: Rx ring buffer */
+ rx_desc->rx_ring_size = HIF_RX_DESC_NT;
+
+ /* NOTE: must be 64bit aligned */
+ bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
+ + RX_BD_BASEADDR);
+ bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
+ + RX_BD_BASEADDR);
+
+ rx_desc->rx_base = bd_va;
+ rx_desc->rx_base_pa = (unsigned long)bd_pa;
+
+ rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
+
+ debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
+ __func__, rx_desc->rx_base, rx_desc->rx_base_pa,
+ rx_desc->rx_ring_size);
+
+ memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
+
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+
+ for (i = 0; i < rx_desc->rx_ring_size; i++) {
+ writel((unsigned long)(bd_pa + 1), &bd_va->next);
+ writel(ctrl, &bd_va->ctrl);
+ writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
+ bd_va++;
+ bd_pa++;
+ }
+ --bd_va;
+ writel((u32)rx_desc->rx_base_pa, &bd_va->next);
+
+ writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+ g_rx_desc = rx_desc;
+
+ return 0;
+}
+
+/*
+ * Helper function to dump Tx Descriptors.
+ */
+static inline void hif_tx_desc_dump(void)
+{
+ struct tx_desc_s *tx_desc;
+ int i;
+ struct buf_desc *bd_va;
+
+ if (!g_tx_desc) {
+ printf("%s: HIF Tx desc no init\n", __func__);
+ return;
+ }
+
+ tx_desc = g_tx_desc;
+ bd_va = tx_desc->tx_base;
+
+ debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
+ tx_desc->tx_base_pa);
+
+ for (i = 0; i < tx_desc->tx_ring_size; i++)
+ bd_va++;
+}
+
+/*
+ * HIF Tx descriptor initialization function.
+ */
+static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct buf_desc *bd_va;
+ struct buf_desc *bd_pa;
+ int i;
+ struct tx_desc_s *tx_desc;
+ u32 tx_buf_pa;
+
+ /* sanity check */
+ if (g_tx_desc) {
+ printf("%s: HIF Tx desc re-init request\n", __func__);
+ return 0;
+ }
+
+ tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
+ if (!tx_desc) {
+ printf("%s:%d:Memory allocation failure\n", __func__,
+ __LINE__);
+ return -ENOMEM;
+ }
+ memset(tx_desc, 0, sizeof(struct tx_desc_s));
+
+ /* init: Tx ring buffer */
+ tx_desc->tx_ring_size = HIF_TX_DESC_NT;
+
+ /* NOTE: must be 64bit aligned */
+ bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
+ + TX_BD_BASEADDR);
+ bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
+ + TX_BD_BASEADDR);
+
+ tx_desc->tx_base_pa = (unsigned long)bd_pa;
+ tx_desc->tx_base = bd_va;
+
+ debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
+ __func__, tx_desc->tx_base, tx_desc->tx_base_pa,
+ tx_desc->tx_ring_size);
+
+ memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
+
+ tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
+
+ for (i = 0; i < tx_desc->tx_ring_size; i++) {
+ writel((unsigned long)(bd_pa + 1), &bd_va->next);
+ writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
+ bd_va++;
+ bd_pa++;
+ }
+ --bd_va;
+ writel((u32)tx_desc->tx_base_pa, &bd_va->next);
+
+ writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
+
+ g_tx_desc = tx_desc;
+
+ return 0;
+}
+
+/*
+ * PFE/Class initialization.
+ */
+static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct class_cfg class_cfg = {
+ .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
+ ROUTE_TABLE_BASEADDR,
+ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
+ };
+
+ class_init(&class_cfg);
+
+ debug("class init complete\n");
+}
+
+/*
+ * PFE/TMU initialization.
+ */
+static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct tmu_cfg tmu_cfg = {
+ .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
+ + TMU_LLM_BASEADDR,
+ .llm_queue_len = TMU_LLM_QUEUE_LEN,
+ };
+
+ tmu_init(&tmu_cfg);
+
+ debug("tmu init complete\n");
+}
+
+/*
+ * PFE/BMU (both BMU1 & BMU2) initialization.
+ */
+static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct bmu_cfg bmu1_cfg = {
+ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
+ BMU1_LMEM_BASEADDR),
+ .count = BMU1_BUF_COUNT,
+ .size = BMU1_BUF_SIZE,
+ };
+
+ struct bmu_cfg bmu2_cfg = {
+ .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
+ .count = BMU2_BUF_COUNT,
+ .size = BMU2_BUF_SIZE,
+ };
+
+ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
+ debug("bmu1 init: done\n");
+
+ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
+ debug("bmu2 init: done\n");
+}
+
+/*
+ * PFE/GPI initialization function.
+ * - egpi1, egpi2, egpi3, hgpi
+ */
+static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct gpi_cfg egpi1_cfg = {
+ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
+ .tmlf_txthres = EGPI1_TMLF_TXTHRES,
+ .aseq_len = EGPI1_ASEQ_LEN,
+ };
+
+ struct gpi_cfg egpi2_cfg = {
+ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
+ .tmlf_txthres = EGPI2_TMLF_TXTHRES,
+ .aseq_len = EGPI2_ASEQ_LEN,
+ };
+
+ struct gpi_cfg hgpi_cfg = {
+ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
+ .tmlf_txthres = HGPI_TMLF_TXTHRES,
+ .aseq_len = HGPI_ASEQ_LEN,
+ };
+
+ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
+ debug("GPI1 init complete\n");
+
+ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
+ debug("GPI2 init complete\n");
+
+ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
+ debug("HGPI init complete\n");
+}
+
+/*
+ * PFE/HIF initialization function.
+ */
+static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
+{
+ int ret = 0;
+
+ hif_tx_disable();
+ hif_rx_disable();
+
+ ret = hif_tx_desc_init(pfe_addr);
+ if (ret)
+ return ret;
+ ret = hif_rx_desc_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ hif_init();
+
+ hif_tx_enable();
+ hif_rx_enable();
+
+ hif_rx_desc_dump();
+ hif_tx_desc_dump();
+
+ debug("HIF init complete\n");
+ return ret;
+}
+
+/*
+ * PFE initialization
+ * - Firmware loading (CLASS-PE and TMU-PE)
+ * - BMU1 and BMU2 init
+ * - GEMAC init
+ * - GPI init
+ * - CLASS-PE init
+ * - TMU-PE init
+ * - HIF tx and rx descriptors init
+ *
+ * @param[in] edev Pointer to eth device structure.
+ *
+ * @return 0, on success.
+ */
+static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
+{
+ int ret = 0;
+
+ debug("%s: start\n", __func__);
+
+ writel(0x3, CLASS_PE_SYS_CLK_RATIO);
+ writel(0x3, TMU_PE_SYS_CLK_RATIO);
+ writel(0x3, UTIL_PE_SYS_CLK_RATIO);
+ udelay(10);
+
+ pfe_class_init(pfe_addr);
+
+ pfe_tmu_init(pfe_addr);
+
+ pfe_bmu_init(pfe_addr);
+
+ pfe_gpi_init(pfe_addr);
+
+ ret = pfe_hif_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ bmu_enable(BMU1_BASE_ADDR);
+ debug("bmu1 enabled\n");
+
+ bmu_enable(BMU2_BASE_ADDR);
+ debug("bmu2 enabled\n");
+
+ debug("%s: done\n", __func__);
+
+ return ret;
+}
+
+/*
+ * PFE driver init function.
+ * - Initializes pfe_lib
+ * - pfe hw init
+ * - fw loading and enables PEs
+ * - should be executed once.
+ *
+ * @param[in] pfe Pointer the pfe control block
+ */
+int pfe_drv_init(struct pfe_ddr_address *pfe_addr)
+{
+ int ret = 0;
+
+ pfe_lib_init();
+
+ ret = pfe_hw_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ /* Load the class,TM, Util fw.
+ * By now pfe is:
+ * - out of reset + disabled + configured.
+ * Fw loading should be done after pfe_hw_init()
+ */
+ /* It loads default inbuilt sbl firmware */
+ pfe_firmware_init();
+
+ return ret;
+}
+
+/*
+ * PFE remove function
+ * - stops PEs
+ * - frees tx/rx descriptor resources
+ * - should be called once.
+ *
+ * @param[in] pfe Pointer to pfe control block.
+ */
+int pfe_eth_remove(struct udevice *dev)
+{
+ if (g_tx_desc)
+ free(g_tx_desc);
+
+ if (g_rx_desc)
+ free(g_rx_desc);
+
+ pfe_firmware_exit();
+
+ return 0;
+}
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
new file mode 100644
index 0000000..e6c6c8c
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <net.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe_mdio.h>
+
+struct gemac_s gem_info[] = {
+ /* PORT_0 configuration */
+ {
+ /* GEMAC config */
+ .gemac_speed = PFE_MAC_SPEED_1000M,
+ .gemac_duplex = DUPLEX_FULL,
+
+ /* phy iface */
+ .phy_address = CONFIG_PFE_EMAC1_PHY_ADDR,
+ .phy_mode = PHY_INTERFACE_MODE_SGMII,
+ },
+ /* PORT_1 configuration */
+ {
+ /* GEMAC config */
+ .gemac_speed = PFE_MAC_SPEED_1000M,
+ .gemac_duplex = DUPLEX_FULL,
+
+ /* phy iface */
+ .phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
+ .phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
+ },
+};
+
+static inline void pfe_gemac_enable(void *gemac_base)
+{
+ writel(readl(gemac_base + EMAC_ECNTRL_REG) |
+ EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+}
+
+static inline void pfe_gemac_disable(void *gemac_base)
+{
+ writel(readl(gemac_base + EMAC_ECNTRL_REG) &
+ ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+}
+
+static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
+ u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
+ u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
+ ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
+
+ if (speed == _1000BASET) {
+ ecr |= EMAC_ECNTRL_SPEED;
+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
+ } else if (speed != _100BASET) {
+ rcr |= EMAC_RCNTRL_RMII_10T;
+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
+ }
+
+ writel(ecr, gemac_base + EMAC_ECNTRL_REG);
+ out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
+
+ /* remove loop back */
+ rcr &= ~EMAC_RCNTRL_LOOP;
+ /* enable flow control */
+ rcr |= EMAC_RCNTRL_FCE;
+
+ /* Enable MII mode */
+ rcr |= EMAC_RCNTRL_MII_MODE;
+
+ writel(rcr, gemac_base + EMAC_RCNTRL_REG);
+
+ /* Enable Tx full duplex */
+ writel(readl(gemac_base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN,
+ gemac_base + EMAC_TCNTRL_REG);
+}
+
+static int pfe_eth_write_hwaddr(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct gemac_s *gem = priv->gem;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ uchar *mac = pdata->enetaddr;
+
+ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
+ gem->gemac_base + EMAC_PHY_ADDR_LOW);
+ writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
+ EMAC_PHY_ADDR_HIGH);
+ return 0;
+}
+
+/** Stops or Disables GEMAC pointing to this eth iface.
+ *
+ * @param[in] edev Pointer to eth device structure.
+ *
+ * @return none
+ */
+static inline void pfe_eth_stop(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ pfe_gemac_disable(priv->gem->gemac_base);
+
+ gpi_disable(priv->gem->egpi_base);
+}
+
+static int pfe_eth_start(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct gemac_s *gem = priv->gem;
+ int speed;
+
+ /* set ethernet mac address */
+ pfe_eth_write_hwaddr(dev);
+
+ writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
+ writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
+ writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
+ writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
+ + EMAC_TX_SECTION_EMPTY);
+ writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
+ + EMAC_MIB_CTRL_STS_REG);
+
+#ifdef CONFIG_PHYLIB
+ /* Start up the PHY */
+ if (phy_startup(priv->phydev)) {
+ printf("Could not initialize PHY %s\n",
+ priv->phydev->dev->name);
+ return -1;
+ }
+ speed = priv->phydev->speed;
+ printf("Speed detected %x\n", speed);
+ if (priv->phydev->duplex == DUPLEX_HALF) {
+ printf("Half duplex not supported\n");
+ return -1;
+ }
+#endif
+
+ pfe_gemac_set_speed(gem->gemac_base, speed);
+
+ /* Enable GPI */
+ gpi_enable(gem->egpi_base);
+
+ /* Enable GEMAC */
+ pfe_gemac_enable(gem->gemac_base);
+
+ return 0;
+}
+
+static int pfe_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev->priv;
+
+ int rc;
+ int i = 0;
+
+ rc = pfe_send(priv->gemac_port, packet, length);
+
+ if (rc < 0) {
+ printf("Tx Queue full\n");
+ return rc;
+ }
+
+ while (1) {
+ rc = pfe_tx_done();
+ if (rc == 0)
+ break;
+
+ udelay(100);
+ i++;
+ if (i == 30000)
+ printf("Tx timeout, send failed\n");
+ break;
+ }
+
+ return 0;
+}
+
+static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ uchar *pkt_buf;
+ int len;
+ int phy_port;
+
+ len = pfe_recv(&pkt_buf, &phy_port);
+
+ if (len == 0)
+ return -EAGAIN; /* no packet in rx */
+ else if (len < 0)
+ return -EAGAIN;
+
+ debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
+ phy_port, len);
+ if (phy_port != priv->gemac_port) {
+ printf("Rx pkt not on expected port\n");
+ return -EAGAIN;
+ }
+
+ *packetp = pkt_buf;
+
+ return len;
+}
+
+static int pfe_eth_probe(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct pfe_ddr_address *pfe_addr;
+ struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+ int ret = 0;
+ static int init_done;
+
+ if (!init_done) {
+ pfe_addr = (struct pfe_ddr_address *)malloc(sizeof
+ (struct pfe_ddr_address));
+ if (!pfe_addr)
+ return -ENOMEM;
+
+ pfe_addr->ddr_pfe_baseaddr =
+ (void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
+ pfe_addr->ddr_pfe_phys_baseaddr =
+ (unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
+
+ debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
+ pfe_addr->ddr_pfe_baseaddr,
+ (u32)pfe_addr->ddr_pfe_phys_baseaddr);
+
+ ret = pfe_drv_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ init_pfe_scfg_dcfg_regs();
+ init_done = 1;
+ }
+
+ priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
+ priv->gem = &gem_info[priv->gemac_port];
+ priv->dev = dev;
+
+ switch (priv->gemac_port) {
+ case EMAC_PORT_0:
+ default:
+ priv->gem->gemac_base = EMAC1_BASE_ADDR;
+ priv->gem->egpi_base = EGPI1_BASE_ADDR;
+ break;
+ case EMAC_PORT_1:
+ priv->gem->gemac_base = EMAC2_BASE_ADDR;
+ priv->gem->egpi_base = EGPI2_BASE_ADDR;
+ break;
+ }
+
+ ret = pfe_eth_board_init(dev);
+ if (ret)
+ return ret;
+
+#if defined(CONFIG_PHYLIB)
+ ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
+ gem_info[priv->gemac_port].phy_address);
+#endif
+ return ret;
+}
+
+static int pfe_eth_bind(struct udevice *dev)
+{
+ struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+ char name[20];
+
+ sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
+
+ return device_set_name(dev, name);
+}
+
+static const struct eth_ops pfe_eth_ops = {
+ .start = pfe_eth_start,
+ .send = pfe_eth_send,
+ .recv = pfe_eth_recv,
+ .free_pkt = pfe_eth_free_pkt,
+ .stop = pfe_eth_stop,
+ .write_hwaddr = pfe_eth_write_hwaddr,
+};
+
+U_BOOT_DRIVER(pfe_eth) = {
+ .name = "pfe_eth",
+ .id = UCLASS_ETH,
+ .bind = pfe_eth_bind,
+ .probe = pfe_eth_probe,
+ .remove = pfe_eth_remove,
+ .ops = &pfe_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct pfe_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct pfe_eth_pdata)
+};
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
new file mode 100644
index 0000000..9dc063d
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * @file
+ * Contains all the functions to handle parsing and loading of PE firmware
+ * files.
+ */
+
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe_firmware.h>
+
+#define PFE_FIRMEWARE_FIT_CNF_NAME "config@1"
+
+static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR;
+
+/*
+ * PFE elf firmware loader.
+ * Loads an elf firmware image into a list of PE's (specified using a bitmask)
+ *
+ * @param pe_mask Mask of PE id's to load firmware to
+ * @param pfe_firmware Pointer to the firmware image
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_load_elf(int pe_mask, uint8_t *pfe_firmware)
+{
+ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)pfe_firmware;
+ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
+ Elf32_Shdr *shdr = (Elf32_Shdr *)(pfe_firmware +
+ be32_to_cpu(elf_hdr->e_shoff));
+ int id, section;
+ int ret;
+
+ debug("%s: no of sections: %d\n", __func__, sections);
+
+ /* Some sanity checks */
+ if (strncmp((char *)&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
+ printf("%s: incorrect elf magic number\n", __func__);
+ return -1;
+ }
+
+ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) {
+ printf("%s: incorrect elf class(%x)\n", __func__,
+ elf_hdr->e_ident[EI_CLASS]);
+ return -1;
+ }
+
+ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) {
+ printf("%s: incorrect elf data(%x)\n", __func__,
+ elf_hdr->e_ident[EI_DATA]);
+ return -1;
+ }
+
+ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) {
+ printf("%s: incorrect elf file type(%x)\n", __func__,
+ be16_to_cpu(elf_hdr->e_type));
+ return -1;
+ }
+
+ for (section = 0; section < sections; section++, shdr++) {
+ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC |
+ SHF_EXECINSTR)))
+ continue;
+ for (id = 0; id < MAX_PE; id++)
+ if (pe_mask & BIT(id)) {
+ ret = pe_load_elf_section(id,
+ pfe_firmware, shdr);
+ if (ret < 0)
+ goto err;
+ }
+ }
+ return 0;
+
+err:
+ return ret;
+}
+
+/*
+ * Get PFE firmware from FIT image
+ *
+ * @param data pointer to PFE firmware
+ * @param size pointer to size of the firmware
+ * @param fw_name pfe firmware name, either class or tmu
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_get_fw(const void **data,
+ size_t *size, char *fw_name)
+{
+ int conf_node_off, fw_node_off;
+ char *conf_node_name = NULL;
+ char *desc;
+ int ret = 0;
+
+ conf_node_name = PFE_FIRMEWARE_FIT_CNF_NAME;
+
+ conf_node_off = fit_conf_get_node(pfe_fit_addr, conf_node_name);
+ if (conf_node_off < 0) {
+ printf("PFE Firmware: %s: no such config\n", conf_node_name);
+ return -ENOENT;
+ }
+
+ fw_node_off = fit_conf_get_prop_node(pfe_fit_addr, conf_node_off,
+ fw_name);
+ if (fw_node_off < 0) {
+ printf("PFE Firmware: No '%s' in config\n",
+ fw_name);
+ return -ENOLINK;
+ }
+
+ if (!(fit_image_verify(pfe_fit_addr, fw_node_off))) {
+ printf("PFE Firmware: Bad firmware image (bad CRC)\n");
+ return -EINVAL;
+ }
+
+ if (fit_image_get_data(pfe_fit_addr, fw_node_off, data, size)) {
+ printf("PFE Firmware: Can't get %s subimage data/size",
+ fw_name);
+ return -ENOENT;
+ }
+
+ ret = fit_get_desc(pfe_fit_addr, fw_node_off, &desc);
+ if (ret)
+ printf("PFE Firmware: Can't get description\n");
+ else
+ printf("%s\n", desc);
+
+ return ret;
+}
+
+/*
+ * Check PFE FIT image
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_fit_check(void)
+{
+ int ret = 0;
+
+ ret = fdt_check_header(pfe_fit_addr);
+ if (ret) {
+ printf("PFE Firmware: Bad firmware image (not a FIT image)\n");
+ return ret;
+ }
+
+ if (!fit_check_format(pfe_fit_addr)) {
+ printf("PFE Firmware: Bad firmware image (bad FIT header)\n");
+ ret = -1;
+ return ret;
+ }
+
+ return ret;
+}
+
+/*
+ * PFE firmware initialization.
+ * Loads different firmware files from FIT image.
+ * Initializes PE IMEM/DMEM and UTIL-PE DDR
+ * Initializes control path symbol addresses (by looking them up in the elf
+ * firmware files
+ * Takes PE's out of reset
+ *
+ * @return 0 on success, a negative value on error
+ */
+int pfe_firmware_init(void)
+{
+ char *pfe_firmware_name;
+ const void *raw_image_addr;
+ size_t raw_image_size = 0;
+ u8 *pfe_firmware;
+ int ret = 0;
+ int fw_count;
+
+ ret = pfe_fit_check();
+ if (ret)
+ goto err;
+
+ for (fw_count = 0; fw_count < 2; fw_count++) {
+ if (fw_count == 0)
+ pfe_firmware_name = "class";
+ else if (fw_count == 1)
+ pfe_firmware_name = "tmu";
+
+ pfe_get_fw(&raw_image_addr, &raw_image_size, pfe_firmware_name);
+ pfe_firmware = malloc(raw_image_size);
+ if (!pfe_firmware)
+ return -ENOMEM;
+ memcpy((void *)pfe_firmware, (void *)raw_image_addr,
+ raw_image_size);
+
+ if (fw_count == 0)
+ ret = pfe_load_elf(CLASS_MASK, pfe_firmware);
+ else if (fw_count == 1)
+ ret = pfe_load_elf(TMU_MASK, pfe_firmware);
+
+ if (ret < 0) {
+ printf("%s: %s firmware load failed\n", __func__,
+ pfe_firmware_name);
+ goto err;
+ }
+ debug("%s: %s firmware loaded\n", __func__, pfe_firmware_name);
+ free(pfe_firmware);
+ }
+
+ tmu_enable(0xb);
+ class_enable();
+ gpi_enable(HGPI_BASE_ADDR);
+
+err:
+ return ret;
+}
+
+/*
+ * PFE firmware cleanup
+ * Puts PE's in reset
+ */
+void pfe_firmware_exit(void)
+{
+ debug("%s\n", __func__);
+
+ class_disable();
+ tmu_disable(0xf);
+ hif_tx_disable();
+ hif_rx_disable();
+}
diff --git a/drivers/net/pfe_eth/pfe_hw.c b/drivers/net/pfe_eth/pfe_hw.c
new file mode 100644
index 0000000..12bb0da
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_hw.c
@@ -0,0 +1,999 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe/pfe_hw.h>
+
+static struct pe_info pe[MAX_PE];
+
+/*
+ * Initializes the PFE library.
+ * Must be called before using any of the library functions.
+ */
+void pfe_lib_init(void)
+{
+ int pfe_pe_id;
+
+ for (pfe_pe_id = CLASS0_ID; pfe_pe_id <= CLASS_MAX_ID; pfe_pe_id++) {
+ pe[pfe_pe_id].dmem_base_addr =
+ (u32)CLASS_DMEM_BASE_ADDR(pfe_pe_id);
+ pe[pfe_pe_id].pmem_base_addr =
+ (u32)CLASS_IMEM_BASE_ADDR(pfe_pe_id);
+ pe[pfe_pe_id].pmem_size = (u32)CLASS_IMEM_SIZE;
+ pe[pfe_pe_id].mem_access_wdata =
+ (void *)CLASS_MEM_ACCESS_WDATA;
+ pe[pfe_pe_id].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
+ pe[pfe_pe_id].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
+ }
+
+ for (pfe_pe_id = TMU0_ID; pfe_pe_id <= TMU_MAX_ID; pfe_pe_id++) {
+ if (pfe_pe_id == TMU2_ID)
+ continue;
+ pe[pfe_pe_id].dmem_base_addr =
+ (u32)TMU_DMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
+ pe[pfe_pe_id].pmem_base_addr =
+ (u32)TMU_IMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
+ pe[pfe_pe_id].pmem_size = (u32)TMU_IMEM_SIZE;
+ pe[pfe_pe_id].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
+ pe[pfe_pe_id].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
+ pe[pfe_pe_id].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
+ }
+}
+
+/*
+ * Writes a buffer to PE internal memory from the host
+ * through indirect access registers.
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] mem_access_addr DMEM destination address (must be 32bit
+ * aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src,
+ unsigned int len)
+{
+ u32 offset = 0, val, addr;
+ unsigned int len32 = len >> 2;
+ int i;
+
+ addr = mem_access_addr | PE_MEM_ACCESS_WRITE |
+ PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
+
+ for (i = 0; i < len32; i++, offset += 4, src += 4) {
+ val = *(u32 *)src;
+ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+ writel(addr + offset, pe[id].mem_access_addr);
+ }
+
+ len = (len & 0x3);
+ if (len) {
+ val = 0;
+
+ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE |
+ PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
+
+ for (i = 0; i < len; i++, src++)
+ val |= (*(u8 *)src) << (8 * i);
+
+ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+ writel(addr, pe[id].mem_access_addr);
+ }
+}
+
+/*
+ * Writes a buffer to PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] dst DMEM destination address (must be 32bit
+ * aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void pe_dmem_memcpy_to32(int id, u32 dst, const void *src,
+ unsigned int len)
+{
+ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM,
+ src, len);
+}
+
+/*
+ * Writes a buffer to PE internal program memory (PMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., TMU3_ID)
+ * @param[in] dst PMEM destination address (must be 32bit
+ * aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void pe_pmem_memcpy_to32(int id, u32 dst, const void *src,
+ unsigned int len)
+{
+ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size
+ - 1)) | PE_MEM_ACCESS_IMEM, src, len);
+}
+
+/*
+ * Reads PE internal program memory (IMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., TMU3_ID)
+ * @param[in] addr PMEM read address (must be aligned on size)
+ * @param[in] size Number of bytes to read (maximum 4, must not
+ * cross 32bit boundaries)
+ * @return the data read (in PE endianness, i.e BE).
+ */
+u32 pe_pmem_read(int id, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+ u32 mask = 0xffffffff >> ((4 - size) << 3);
+ u32 val;
+
+ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))
+ | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM |
+ PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+ writel(addr, pe[id].mem_access_addr);
+ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+ return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * Writes PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] val Value to write (in PE endianness, i.e BE)
+ * @param[in] addr DMEM write address (must be aligned on size)
+ * @param[in] size Number of bytes to write (maximum 4, must not
+ * cross 32bit boundaries)
+ */
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+
+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |
+ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+ /* Indirect access interface is byte swapping data being written */
+ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
+ writel(addr, pe[id].mem_access_addr);
+}
+
+/*
+ * Reads PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] addr DMEM read address (must be aligned on size)
+ * @param[in] size Number of bytes to read (maximum 4, must not
+ * cross 32bit boundaries)
+ * @return the data read (in PE endianness, i.e BE).
+ */
+u32 pe_dmem_read(int id, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+ u32 mask = 0xffffffff >> ((4 - size) << 3);
+ u32 val;
+
+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ |
+ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+ writel(addr, pe[id].mem_access_addr);
+
+ /* Indirect access interface is byte swapping data being read */
+ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+ return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * This function is used to write to CLASS internal bus peripherals (ccu,
+ * pe-lem) from the host
+ * through indirect access registers.
+ * @param[in] val value to write
+ * @param[in] addr Address to write to (must be aligned on size)
+ * @param[in] size Number of bytes to write (1, 2 or 4)
+ *
+ */
+static void class_bus_write(u32 val, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+
+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |
+ (size << 24);
+
+ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
+ writel(addr, CLASS_BUS_ACCESS_ADDR);
+}
+
+/*
+ * Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
+ * through indirect access registers.
+ * @param[in] addr Address to read from (must be aligned on size)
+ * @param[in] size Number of bytes to read (1, 2 or 4)
+ * @return the read data
+ */
+static u32 class_bus_read(u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+ u32 mask = 0xffffffff >> ((4 - size) << 3);
+ u32 val;
+
+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
+
+ writel(addr, CLASS_BUS_ACCESS_ADDR);
+ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
+
+ return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * Writes data to the cluster memory (PE_LMEM)
+ * @param[in] dst PE LMEM destination address (must be 32bit aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void class_pe_lmem_memcpy_to32(u32 dst, const void *src,
+ unsigned int len)
+{
+ u32 len32 = len >> 2;
+ int i;
+
+ for (i = 0; i < len32; i++, src += 4, dst += 4)
+ class_bus_write(*(u32 *)src, dst, 4);
+
+ if (len & 0x2) {
+ class_bus_write(*(u16 *)src, dst, 2);
+ src += 2;
+ dst += 2;
+ }
+
+ if (len & 0x1) {
+ class_bus_write(*(u8 *)src, dst, 1);
+ src++;
+ dst++;
+ }
+}
+
+/*
+ * Writes value to the cluster memory (PE_LMEM)
+ * @param[in] dst PE LMEM destination address (must be 32bit aligned)
+ * @param[in] val Value to write
+ * @param[in] len Number of bytes to write
+ */
+static void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
+{
+ u32 len32 = len >> 2;
+ int i;
+
+ val = val | (val << 8) | (val << 16) | (val << 24);
+
+ for (i = 0; i < len32; i++, dst += 4)
+ class_bus_write(val, dst, 4);
+
+ if (len & 0x2) {
+ class_bus_write(val, dst, 2);
+ dst += 2;
+ }
+
+ if (len & 0x1) {
+ class_bus_write(val, dst, 1);
+ dst++;
+ }
+}
+
+/*
+ * Reads data from the cluster memory (PE_LMEM)
+ * @param[out] dst pointer to the source buffer data are copied to
+ * @param[in] len length in bytes of the amount of data to read
+ * from cluster memory
+ * @param[in] offset offset in bytes in the cluster memory where data are
+ * read from
+ */
+void pe_lmem_read(u32 *dst, u32 len, u32 offset)
+{
+ u32 len32 = len >> 2;
+ int i = 0;
+
+ for (i = 0; i < len32; dst++, i++, offset += 4)
+ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
+
+ if (len & 0x03)
+ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
+}
+
+/*
+ * Writes data to the cluster memory (PE_LMEM)
+ * @param[in] src pointer to the source buffer data are copied from
+ * @param[in] len length in bytes of the amount of data to write to the
+ * cluster memory
+ * @param[in] offset offset in bytes in the cluster memory where data are
+ * written to
+ */
+void pe_lmem_write(u32 *src, u32 len, u32 offset)
+{
+ u32 len32 = len >> 2;
+ int i = 0;
+
+ for (i = 0; i < len32; src++, i++, offset += 4)
+ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
+
+ if (len & 0x03)
+ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len &
+ 0x03));
+}
+
+/*
+ * Loads an elf section into pmem
+ * Code needs to be at least 16bit aligned and only PROGBITS sections are
+ * supported
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ...,
+ * TMU3_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+
+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr, (unsigned long)data + offset);
+
+ return -1;
+ }
+
+ if (addr & 0x1) {
+ printf("%s: load address(%x) is not 16bit aligned\n",
+ __func__, addr);
+ return -1;
+ }
+
+ if (size & 0x1) {
+ printf("%s: load size(%x) is not 16bit aligned\n", __func__,
+ size);
+ return -1;
+ }
+
+ debug("pmem pe%d @%x len %d\n", id, addr, size);
+ switch (type) {
+ case SHT_PROGBITS:
+ pe_pmem_memcpy_to32(id, addr, data + offset, size);
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into dmem
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+ u32 size32 = size >> 2;
+ int i;
+
+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr, (unsigned long)data + offset);
+
+ return -1;
+ }
+
+ if (addr & 0x3) {
+ printf("%s: load address(%x) is not 32bit aligned\n",
+ __func__, addr);
+ return -1;
+ }
+
+ switch (type) {
+ case SHT_PROGBITS:
+ debug("dmem pe%d @%x len %d\n", id, addr, size);
+ pe_dmem_memcpy_to32(id, addr, data + offset, size);
+ break;
+
+ case SHT_NOBITS:
+ debug("dmem zero pe%d @%x len %d\n", id, addr, size);
+ for (i = 0; i < size32; i++, addr += 4)
+ pe_dmem_write(id, 0, addr, 4);
+
+ if (size & 0x3)
+ pe_dmem_write(id, 0, addr, size & 0x3);
+
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into DDR
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+ u32 flags = be32_to_cpu(shdr->sh_flags);
+
+ switch (type) {
+ case SHT_PROGBITS:
+ debug("ddr pe%d @%x len %d\n", id, addr, size);
+ if (flags & SHF_EXECINSTR) {
+ if (id <= CLASS_MAX_ID) {
+ /* DO the loading only once in DDR */
+ if (id == CLASS0_ID) {
+ debug(
+ "%s: load address(%x) and elf file address(%lx) rcvd\n"
+ , __func__, addr,
+ (unsigned long)data + offset);
+ if (((unsigned long)(data + offset)
+ & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr,
+ (unsigned long)data +
+ offset);
+
+ return -1;
+ }
+
+ if (addr & 0x1) {
+ printf(
+ "%s: load address(%x) is not 16bit aligned\n"
+ , __func__, addr);
+ return -1;
+ }
+
+ if (size & 0x1) {
+ printf(
+ "%s: load length(%x) is not 16bit aligned\n"
+ , __func__, size);
+ return -1;
+ }
+
+ memcpy((void *)DDR_PFE_TO_VIRT(addr),
+ data + offset, size);
+ }
+ } else {
+ printf(
+ "%s: unsupported ddr section type(%x) for PE(%d)\n"
+ , __func__, type, id);
+ return -1;
+ }
+
+ } else {
+ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset,
+ size);
+ }
+
+ break;
+
+ case SHT_NOBITS:
+ debug("ddr zero pe%d @%x len %d\n", id, addr, size);
+ memset((void *)DDR_PFE_TO_VIRT(addr), 0, size);
+
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into pe lmem
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+
+ if (id > CLASS_MAX_ID) {
+ printf("%s: unsupported pe-lmem section type(%x) for PE(%d)\n",
+ __func__, type, id);
+ return -1;
+ }
+
+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr, (unsigned long)data + offset);
+
+ return -1;
+ }
+
+ if (addr & 0x3) {
+ printf("%s: load address(%x) is not 32bit aligned\n",
+ __func__, addr);
+ return -1;
+ }
+
+ debug("lmem pe%d @%x len %d\n", id, addr, size);
+
+ switch (type) {
+ case SHT_PROGBITS:
+ class_pe_lmem_memcpy_to32(addr, data + offset, size);
+ break;
+
+ case SHT_NOBITS:
+ class_pe_lmem_memset(addr, 0, size);
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into a PE
+ * For now only supports loading a section to dmem (all PE's), pmem (class and
+ * tmu PE's), DDDR (util PE code)
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+
+ if (IS_DMEM(addr, size))
+ return pe_load_dmem_section(id, data, shdr);
+ else if (IS_PMEM(addr, size))
+ return pe_load_pmem_section(id, data, shdr);
+ else if (IS_PFE_LMEM(addr, size))
+ return 0;
+ else if (IS_PHYS_DDR(addr, size))
+ return pe_load_ddr_section(id, data, shdr);
+ else if (IS_PE_LMEM(addr, size))
+ return pe_load_pe_lmem_section(id, data, shdr);
+
+ printf("%s: unsupported memory range(%x)\n", __func__, addr);
+
+ return 0;
+}
+
+/**************************** BMU ***************************/
+/*
+ * Resets a BMU block.
+ * @param[in] base BMU block base address
+ */
+static inline void bmu_reset(void *base)
+{
+ writel(CORE_SW_RESET, base + BMU_CTRL);
+
+ /* Wait for self clear */
+ while (readl(base + BMU_CTRL) & CORE_SW_RESET)
+ ;
+}
+
+/*
+ * Enabled a BMU block.
+ * @param[in] base BMU block base address
+ */
+void bmu_enable(void *base)
+{
+ writel(CORE_ENABLE, base + BMU_CTRL);
+}
+
+/*
+ * Disables a BMU block.
+ * @param[in] base BMU block base address
+ */
+static inline void bmu_disable(void *base)
+{
+ writel(CORE_DISABLE, base + BMU_CTRL);
+}
+
+/*
+ * Sets the configuration of a BMU block.
+ * @param[in] base BMU block base address
+ * @param[in] cfg BMU configuration
+ */
+static inline void bmu_set_config(void *base, struct bmu_cfg *cfg)
+{
+ writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
+ writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
+ writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);
+
+ /* Interrupts are never used */
+ writel(0x0, base + BMU_INT_ENABLE);
+}
+
+/*
+ * Initializes a BMU block.
+ * @param[in] base BMU block base address
+ * @param[in] cfg BMU configuration
+ */
+void bmu_init(void *base, struct bmu_cfg *cfg)
+{
+ bmu_disable(base);
+
+ bmu_set_config(base, cfg);
+
+ bmu_reset(base);
+}
+
+/**************************** GPI ***************************/
+/*
+ * Resets a GPI block.
+ * @param[in] base GPI base address
+ */
+static inline void gpi_reset(void *base)
+{
+ writel(CORE_SW_RESET, base + GPI_CTRL);
+}
+
+/*
+ * Enables a GPI block.
+ * @param[in] base GPI base address
+ */
+void gpi_enable(void *base)
+{
+ writel(CORE_ENABLE, base + GPI_CTRL);
+}
+
+/*
+ * Disables a GPI block.
+ * @param[in] base GPI base address
+ */
+void gpi_disable(void *base)
+{
+ writel(CORE_DISABLE, base + GPI_CTRL);
+}
+
+/*
+ * Sets the configuration of a GPI block.
+ * @param[in] base GPI base address
+ * @param[in] cfg GPI configuration
+ */
+static inline void gpi_set_config(void *base, struct gpi_cfg *cfg)
+{
+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base
+ + GPI_LMEM_ALLOC_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base
+ + GPI_LMEM_FREE_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base
+ + GPI_DDR_ALLOC_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base
+ + GPI_DDR_FREE_ADDR);
+ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
+ writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
+ writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
+ writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
+ writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
+ writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
+
+ writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
+ GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
+ writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
+ writel(cfg->aseq_len, base + GPI_DTX_ASEQ);
+
+ /*Make GPI AXI transactions non-bufferable */
+ writel(0x1, base + GPI_AXI_CTRL);
+}
+
+/*
+ * Initializes a GPI block.
+ * @param[in] base GPI base address
+ * @param[in] cfg GPI configuration
+ */
+void gpi_init(void *base, struct gpi_cfg *cfg)
+{
+ gpi_reset(base);
+
+ gpi_disable(base);
+
+ gpi_set_config(base, cfg);
+}
+
+/**************************** CLASSIFIER ***************************/
+/*
+ * Resets CLASSIFIER block.
+ */
+static inline void class_reset(void)
+{
+ writel(CORE_SW_RESET, CLASS_TX_CTRL);
+}
+
+/*
+ * Enables all CLASS-PE's cores.
+ */
+void class_enable(void)
+{
+ writel(CORE_ENABLE, CLASS_TX_CTRL);
+}
+
+/*
+ * Disables all CLASS-PE's cores.
+ */
+void class_disable(void)
+{
+ writel(CORE_DISABLE, CLASS_TX_CTRL);
+}
+
+/*
+ * Sets the configuration of the CLASSIFIER block.
+ * @param[in] cfg CLASSIFIER configuration
+ */
+static inline void class_set_config(struct class_cfg *cfg)
+{
+ if (PLL_CLK_EN == 0) {
+ /* Clock ratio: for 1:1 the value is 0 */
+ writel(0x0, CLASS_PE_SYS_CLK_RATIO);
+ } else {
+ /* Clock ratio: for 1:2 the value is 1 */
+ writel(0x1, CLASS_PE_SYS_CLK_RATIO);
+ }
+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
+ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
+ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |
+ CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),
+ CLASS_ROUTE_HASH_ENTRY_SIZE);
+ writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
+
+ writel(cfg->route_table_baseaddr, CLASS_ROUTE_TABLE_BASE);
+ memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0,
+ ROUTE_TABLE_SIZE);
+
+ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
+ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
+ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
+ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
+ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
+
+ writel(23, CLASS_AFULL_THRES);
+ writel(23, CLASS_TSQ_FIFO_THRES);
+
+ writel(24, CLASS_MAX_BUF_CNT);
+ writel(24, CLASS_TSQ_MAX_CNT);
+
+ /*Make Class AXI transactions non-bufferable */
+ writel(0x1, CLASS_AXI_CTRL);
+
+ /*Make Util AXI transactions non-bufferable */
+ /*Util is disabled in U-boot, do it from here */
+ writel(0x1, UTIL_AXI_CTRL);
+}
+
+/*
+ * Initializes CLASSIFIER block.
+ * @param[in] cfg CLASSIFIER configuration
+ */
+void class_init(struct class_cfg *cfg)
+{
+ class_reset();
+
+ class_disable();
+
+ class_set_config(cfg);
+}
+
+/**************************** TMU ***************************/
+/*
+ * Enables TMU-PE cores.
+ * @param[in] pe_mask TMU PE mask
+ */
+void tmu_enable(u32 pe_mask)
+{
+ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
+}
+
+/*
+ * Disables TMU cores.
+ * @param[in] pe_mask TMU PE mask
+ */
+void tmu_disable(u32 pe_mask)
+{
+ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
+}
+
+/*
+ * Initializes TMU block.
+ * @param[in] cfg TMU configuration
+ */
+void tmu_init(struct tmu_cfg *cfg)
+{
+ int q, phyno;
+
+ /* keep in soft reset */
+ writel(SW_RESET, TMU_CTRL);
+
+ /*Make Class AXI transactions non-bufferable */
+ writel(0x1, TMU_AXI_CTRL);
+
+ /* enable EMAC PHY ports */
+ writel(0x3, TMU_SYS_GENERIC_CONTROL);
+
+ writel(750, TMU_INQ_WATERMARK);
+
+ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR),
+ TMU_PHY0_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR),
+ TMU_PHY1_INQ_ADDR);
+
+ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR),
+ TMU_PHY3_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),
+ TMU_BMU_INQ_ADDR);
+
+ /* enabling all 10 schedulers [9:0] of each TDQ */
+ writel(0x3FF, TMU_TDQ0_SCH_CTRL);
+ writel(0x3FF, TMU_TDQ1_SCH_CTRL);
+ writel(0x3FF, TMU_TDQ3_SCH_CTRL);
+
+ if (PLL_CLK_EN == 0) {
+ /* Clock ratio: for 1:1 the value is 0 */
+ writel(0x0, TMU_PE_SYS_CLK_RATIO);
+ } else {
+ /* Clock ratio: for 1:2 the value is 1 */
+ writel(0x1, TMU_PE_SYS_CLK_RATIO);
+ }
+
+ /* Extra packet pointers will be stored from this address onwards */
+ debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
+ writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR);
+
+ debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
+ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
+
+ writel(5, TMU_TDQ_IIFG_CFG);
+ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
+
+ writel(0x0, TMU_CTRL);
+
+ /* MEM init */
+ writel(MEM_INIT, TMU_CTRL);
+
+ while (!(readl(TMU_CTRL) & MEM_INIT_DONE))
+ ;
+
+ /* LLM init */
+ writel(LLM_INIT, TMU_CTRL);
+
+ while (!(readl(TMU_CTRL) & LLM_INIT_DONE))
+ ;
+
+ /* set up each queue for tail drop */
+ for (phyno = 0; phyno < 4; phyno++) {
+ if (phyno == 2)
+ continue;
+ for (q = 0; q < 16; q++) {
+ u32 qmax;
+
+ writel((phyno << 8) | q, TMU_TEQ_CTRL);
+ writel(BIT(22), TMU_TEQ_QCFG);
+
+ if (phyno == 3)
+ qmax = DEFAULT_TMU3_QDEPTH;
+ else
+ qmax = (q == 0) ? DEFAULT_Q0_QDEPTH :
+ DEFAULT_MAX_QDEPTH;
+
+ writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
+ writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
+ }
+ }
+ writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
+ writel(0, TMU_CTRL);
+}
+
+/**************************** HIF ***************************/
+/*
+ * Enable hif tx DMA and interrupt
+ */
+void hif_tx_enable(void)
+{
+ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
+}
+
+/*
+ * Disable hif tx DMA and interrupt
+ */
+void hif_tx_disable(void)
+{
+ u32 hif_int;
+
+ writel(0, HIF_TX_CTRL);
+
+ hif_int = readl(HIF_INT_ENABLE);
+ hif_int &= HIF_TXPKT_INT_EN;
+ writel(hif_int, HIF_INT_ENABLE);
+}
+
+/*
+ * Enable hif rx DMA and interrupt
+ */
+void hif_rx_enable(void)
+{
+ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+}
+
+/*
+ * Disable hif rx DMA and interrupt
+ */
+void hif_rx_disable(void)
+{
+ u32 hif_int;
+
+ writel(0, HIF_RX_CTRL);
+
+ hif_int = readl(HIF_INT_ENABLE);
+ hif_int &= HIF_RXPKT_INT_EN;
+ writel(hif_int, HIF_INT_ENABLE);
+}
+
+/*
+ * Initializes HIF copy block.
+ */
+void hif_init(void)
+{
+ /* Initialize HIF registers */
+ writel(HIF_RX_POLL_CTRL_CYCLE << 16 | HIF_TX_POLL_CTRL_CYCLE,
+ HIF_POLL_CTRL);
+ /* Make HIF AXI transactions non-bufferable */
+ writel(0x1, HIF_AXI_CTRL);
+}
diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
new file mode 100644
index 0000000..a78a4d6
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <net.h>
+#include <net/pfe_eth/pfe_eth.h>
+
+extern struct gemac_s gem_info[];
+#if defined(CONFIG_PHYLIB)
+
+#define MDIO_TIMEOUT 5000
+static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr)
+{
+ void *reg_base = bus->priv;
+ u32 devadr;
+ u32 phy;
+ u32 reg_data;
+ int timeout = MDIO_TIMEOUT;
+
+ devadr = ((dev_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+ reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr);
+
+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+ /*
+ * wait for the MII interrupt
+ */
+ while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+ if (timeout-- <= 0) {
+ printf("Phy MDIO read/write timeout\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt
+ */
+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+ return 0;
+}
+
+static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr)
+{
+ void *reg_base = bus->priv;
+ u32 reg;
+ u32 phy;
+ u32 reg_data;
+ u16 val;
+ int timeout = MDIO_TIMEOUT;
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ } else {
+ pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
+ reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ }
+
+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+ if (dev_addr == MDIO_DEVAD_NONE)
+ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
+ EMAC_MII_DATA_TA | phy | reg);
+ else
+ reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA |
+ phy | reg);
+
+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+ /*
+ * wait for the MII interrupt
+ */
+ while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+ if (timeout-- <= 0) {
+ printf("Phy MDIO read/write timeout\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt
+ */
+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+ /*
+ * it's now safe to read the PHY's register
+ */
+ val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
+ debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base,
+ phy_addr, reg_addr, val);
+
+ return val;
+}
+
+static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr, u16 data)
+{
+ void *reg_base = bus->priv;
+ u32 reg;
+ u32 phy;
+ u32 reg_data;
+ int timeout = MDIO_TIMEOUT;
+ int val;
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ } else {
+ pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
+ reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ }
+
+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+ if (dev_addr == MDIO_DEVAD_NONE)
+ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
+ EMAC_MII_DATA_TA | phy | reg | data);
+ else
+ reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA |
+ phy | reg | data);
+
+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+ /*
+ * wait for the MII interrupt
+ */
+ while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+ if (timeout-- <= 0) {
+ printf("Phy MDIO read/write timeout\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt
+ */
+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+ debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
+ reg_addr, data);
+
+ return val;
+}
+
+static void pfe_configure_serdes(struct pfe_eth_dev *priv)
+{
+ struct mii_dev bus;
+ int value, sgmii_2500 = 0;
+ struct gemac_s *gem = priv->gem;
+
+ if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
+ sgmii_2500 = 1;
+
+ printf("%s %d\n", __func__, priv->gemac_port);
+
+ /* PCS configuration done with corresponding GEMAC */
+ bus.priv = gem_info[priv->gemac_port].gemac_base;
+
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
+
+ /* Reset serdes */
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
+
+ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
+ value = PHY_SGMII_IF_MODE_SGMII;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_IF_MODE_AN;
+ else
+ value |= PHY_SGMII_IF_MODE_SGMII_GBT;
+
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+
+ /* Dev ability according to SGMII specification */
+ value = PHY_SGMII_DEV_ABILITY_SGMII;
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+
+ /* These values taken from validation team */
+ if (!sgmii_2500) {
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
+ } else {
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x7);
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xa120);
+ }
+
+ /* Restart AN */
+ value = PHY_SGMII_CR_DEF_VAL;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_CR_RESET_AN;
+ /* Disable Auto neg for 2.5G SGMII as it doesn't support auto neg*/
+ if (sgmii_2500)
+ value &= ~PHY_SGMII_ENABLE_AN;
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+}
+
+int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
+{
+ struct phy_device *phydev = NULL;
+ struct udevice *dev = priv->dev;
+ struct gemac_s *gem = priv->gem;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ if (!gem->bus)
+ return -1;
+
+ /* Configure SGMII PCS */
+ if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
+ gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
+ out_be32(&scfg->mdioselcr, 0x00000000);
+ pfe_configure_serdes(priv);
+ }
+
+ mdelay(100);
+
+ /* By this time on-chip SGMII initialization is done
+ * we can switch mdio interface to external PHYs
+ */
+ out_be32(&scfg->mdioselcr, 0x80000000);
+
+ phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
+ if (!phydev) {
+ printf("phy_connect failed\n");
+ return -ENODEV;
+ }
+
+ phy_config(phydev);
+
+ priv->phydev = phydev;
+
+ return 0;
+}
+#endif
+
+struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info)
+{
+ struct mii_dev *bus;
+ int ret;
+ u32 mdio_speed;
+ u32 pclk = 250000000;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("mdio_alloc failed\n");
+ return NULL;
+ }
+ bus->read = pfe_phy_read;
+ bus->write = pfe_phy_write;
+
+ /* MAC1 MDIO used to communicate with external PHYS */
+ bus->priv = mdio_info->reg_base;
+ sprintf(bus->name, mdio_info->name);
+
+ /* configure mdio speed */
+ mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
+ mdio_speed |= EMAC_HOLDTIME(0x5);
+ writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
+
+ ret = mdio_register(bus);
+ if (ret) {
+ printf("mdio_register failed\n");
+ free(bus);
+ return NULL;
+ }
+ return bus;
+}
+
+void pfe_set_mdio(int dev_id, struct mii_dev *bus)
+{
+ gem_info[dev_id].bus = bus;
+}
+
+void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
+{
+ gem_info[dev_id].phy_address = phy_id;
+ gem_info[dev_id].phy_mode = phy_mode;
+}
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 7fd4a8d..f5821df 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -13,6 +13,21 @@
if PHYLIB
+config PHY_ADDR_ENABLE
+ bool "Limit phy address"
+ default y if ARCH_SUNXI
+ help
+ Select this if you want to control which phy address is used
+
+if PHY_ADDR_ENABLE
+config PHY_ADDR
+ int "PHY address"
+ default 1 if ARCH_SUNXI
+ default 0
+ help
+ The address of PHY on MII bus. Usually in range of 0 to 31.
+endif
+
config B53_SWITCH
bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
help
@@ -132,6 +147,16 @@
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
+config RTL8211E_PINE64_GIGABIT_FIX
+ bool "Fix gigabit throughput on some Pine64+ models"
+ depends on PHY_REALTEK
+ help
+ Configure the Realtek RTL8211E found on some Pine64+ models differently to
+ fix throughput on Gigabit links, turning off all internal delays in the
+ process. The settings that this touches are not documented in the CONFREG
+ section of the RTL8211E datasheet, but come from Realtek by way of the
+ Pine64 engineering team.
+
config RTL8211X_PHY_FORCE_MASTER
bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
depends on PHY_REALTEK
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ad12f6d..6678147 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -7,6 +7,7 @@
*/
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <phy.h>
#ifndef CONFIG_PHYLIB_10G
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 637d89a..9cb3a52c 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*
*/
@@ -27,6 +28,7 @@
#error The Cortina PHY needs 10G support
#endif
+#ifndef CORTINA_NO_FW_UPLOAD
struct cortina_reg_config cortina_reg_cfg[] = {
/* CS4315_enable_sr_mode */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
@@ -215,12 +217,22 @@
phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
}
}
+#endif
int cs4340_phy_init(struct phy_device *phydev)
{
+#ifndef CORTINA_NO_FW_UPLOAD
int timeout = 100; /* 100ms */
+#endif
int reg_value;
+ /*
+ * Cortina phy has provision to store
+ * phy firmware in attached dedicated EEPROM.
+ * Boards designed with EEPROM attached to Cortina
+ * does not require FW upload.
+ */
+#ifndef CORTINA_NO_FW_UPLOAD
/* step1: BIST test */
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
@@ -241,6 +253,7 @@
/* setp2: upload ucode */
cs4340_upload_firmware(phydev);
+#endif
reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
if (reg_value) {
debug("%s checksum status failed.\n", __func__);
@@ -295,45 +308,33 @@
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
- bool is_cortina_phy = false;
-
- switch (addr) {
-#ifdef CORTINA_PHY_ADDR1
- case CORTINA_PHY_ADDR1:
-#endif
-#ifdef CORTINA_PHY_ADDR2
- case CORTINA_PHY_ADDR2:
-#endif
-#ifdef CORTINA_PHY_ADDR3
- case CORTINA_PHY_ADDR3:
-#endif
-#ifdef CORTINA_PHY_ADDR4
- case CORTINA_PHY_ADDR4:
-#endif
- is_cortina_phy = true;
- break;
- default:
- break;
- }
/* Cortina PHY has non-standard offset of PHY ID registers */
- if (is_cortina_phy)
- phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
- else
- phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
-
+ phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
if (phy_reg < 0)
return -EIO;
-
*phy_id = (phy_reg & 0xffff) << 16;
- if (is_cortina_phy)
- phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
- else
- phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+ phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
if (phy_reg < 0)
return -EIO;
+ *phy_id |= (phy_reg & 0xffff);
+ if (*phy_id == PHY_UID_CS4340)
+ return 0;
+
+ /*
+ * If Cortina PHY not detected,
+ * try generic way to find PHY ID registers
+ */
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
+ if (phy_reg < 0)
+ return -EIO;
+ *phy_id = (phy_reg & 0xffff) << 16;
+
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+ if (phy_reg < 0)
+ return -EIO;
*phy_id |= (phy_reg & 0xffff);
return 0;
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 6d917f8..d5c2a46 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -13,6 +13,7 @@
#include <phy.h>
#define PHY_RTL8211x_FORCE_MASTER BIT(1)
+#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
@@ -47,6 +48,13 @@
#define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
#define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
+#define MIIM_RTL8211E_CONFREG 0x1c
+#define MIIM_RTL8211E_CONFREG_TXD 0x0002
+#define MIIM_RTL8211E_CONFREG_RXD 0x0004
+#define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
+
+#define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
+
#define MIIM_RTL8211F_PAGE_SELECT 0x1f
#define MIIM_RTL8211F_TX_DELAY 0x100
#define MIIM_RTL8211F_LCR 0x10
@@ -60,6 +68,15 @@
return 0;
}
+static int rtl8211e_probe(struct phy_device *phydev)
+{
+#ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
+ phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
+#endif
+
+ return 0;
+}
+
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
{
@@ -81,6 +98,22 @@
reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
}
+ if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
+ unsigned int reg;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
+ 7);
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
+ /* Ensure both internal delays are turned off */
+ reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
+ /* Flip the magic undocumented bits */
+ reg |= MIIM_RTL8211E_CONFREG_MAGIC;
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
+ 0);
+ }
/* read interrupt status just to clear it */
phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
@@ -279,6 +312,7 @@
.uid = 0x1cc915,
.mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
+ .probe = &rtl8211e_probe,
.config = &rtl8211x_config,
.startup = &rtl8211e_startup,
.shutdown = &genphy_shutdown,
diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
index 3f80f04..7142a99 100644
--- a/drivers/net/phy/xilinx_phy.c
+++ b/drivers/net/phy/xilinx_phy.c
@@ -105,7 +105,7 @@
debug("%s\n", __func__);
phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
- "phy-type", -1);
+ "xlnx,phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 6f48e93..cb3970e 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -11,6 +11,7 @@
#include <config.h>
#include <common.h>
+#include <environment.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
@@ -905,7 +906,10 @@
}
static const struct udevice_id sh_ether_ids[] = {
+ { .compatible = "renesas,ether-r8a7790" },
{ .compatible = "renesas,ether-r8a7791" },
+ { .compatible = "renesas,ether-r8a7793" },
+ { .compatible = "renesas,ether-r8a7794" },
{ }
};
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 3ccc6b0..b6e5daf 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -21,6 +21,7 @@
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
#ifdef CONFIG_DM_GPIO
#include <asm-generic/gpio.h>
#endif
@@ -278,7 +279,7 @@
int ret;
u32 reg;
- reg = readl(priv->sysctl_reg);
+ reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == H3_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, ®);
@@ -309,7 +310,7 @@
return -EINVAL;
}
- writel(reg, priv->sysctl_reg);
+ writel(reg, priv->sysctl_reg + 0x30);
return 0;
}
@@ -431,7 +432,7 @@
tx_descs_init(priv);
/* PHY Start Up */
- genphy_parse_link(priv->phydev);
+ phy_startup(priv->phydev);
sun8i_adjust_link(priv, priv->phydev);
@@ -455,7 +456,7 @@
{
int offset;
const char *pin_name;
- int drive, pull, i;
+ int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"pinctrl-0");
@@ -465,30 +466,44 @@
}
drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,drive", 4);
- pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,pull", 0);
+ "drive-strength", ~0);
+ if (drive != ~0) {
+ if (drive <= 10)
+ drive = SUN4I_PINCTRL_10_MA;
+ else if (drive <= 20)
+ drive = SUN4I_PINCTRL_20_MA;
+ else if (drive <= 30)
+ drive = SUN4I_PINCTRL_30_MA;
+ else
+ drive = SUN4I_PINCTRL_40_MA;
+ }
+
+ if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
+ pull = SUN4I_PINCTRL_PULL_UP;
+ else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
+ pull = SUN4I_PINCTRL_PULL_DOWN;
+
for (i = 0; ; i++) {
int pin;
pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
- "allwinner,pins", i, NULL);
+ "pins", i, NULL);
if (!pin_name)
break;
- if (pin_name[0] != 'P')
+
+ pin = sunxi_name_to_gpio(pin_name);
+ if (pin < 0)
continue;
- pin = (pin_name[1] - 'A') << 5;
- if (pin >= 26 << 5)
- continue;
- pin += simple_strtol(&pin_name[2], NULL, 10);
sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
- sunxi_gpio_set_drv(pin, drive);
- sunxi_gpio_set_pull(pin, pull);
+ if (drive != ~0)
+ sunxi_gpio_set_drv(pin, drive);
+ if (pull != ~0)
+ sunxi_gpio_set_pull(pin, pull);
}
if (!i) {
- printf("WARNING: emac: cannot find allwinner,pins property\n");
+ printf("WARNING: emac: cannot find pins property\n");
return -2;
}
@@ -772,6 +787,7 @@
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
+ const fdt32_t *reg;
int node = dev_of_offset(dev);
int offset = 0;
#ifdef CONFIG_DM_GPIO
@@ -779,18 +795,40 @@
int ret = 0;
#endif
- pdata->iobase = devfdt_get_addr_name(dev, "emac");
- priv->sysctl_reg = devfdt_get_addr_name(dev, "syscon");
+ pdata->iobase = devfdt_get_addr(dev);
+ if (pdata->iobase == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find MAC base address\n", __func__);
+ return -EINVAL;
+ }
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+ if (offset < 0) {
+ debug("%s: cannot find syscon node\n", __func__);
+ return -EINVAL;
+ }
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+ if (!reg) {
+ debug("%s: cannot find reg property in syscon node\n",
+ __func__);
+ return -EINVAL;
+ }
+ priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+ offset, reg);
+ if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find syscon base address\n", __func__);
+ return -EINVAL;
+ }
pdata->phy_interface = -1;
priv->phyaddr = -1;
priv->use_internal_phy = false;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy");
- if (offset > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
- -1);
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
+ if (offset < 0) {
+ debug("%s: Cannot find PHY address\n", __func__);
+ return -EINVAL;
+ }
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
@@ -812,8 +850,11 @@
}
if (priv->variant == H3_EMAC) {
- if (fdt_getprop(gd->fdt_blob, node,
- "allwinner,use-internal-phy", NULL))
+ int parent = fdt_parent_offset(gd->fdt_blob, offset);
+
+ if (parent >= 0 &&
+ !fdt_node_check_compatible(gd->fdt_blob, parent,
+ "allwinner,sun8i-h3-mdio-internal"))
priv->use_internal_phy = true;
}
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 70a2e95..80ed06a 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -78,9 +78,10 @@
struct axidma_reg {
u32 control; /* DMACR */
u32 status; /* DMASR */
- u32 current; /* CURDESC */
- u32 reserved;
- u32 tail; /* TAILDESC */
+ u32 current; /* CURDESC low 32 bit */
+ u32 current_hi; /* CURDESC high 32 bit */
+ u32 tail; /* TAILDESC low 32 bit */
+ u32 tail_hi; /* TAILDESC high 32 bit */
};
/* Private driver structures */
@@ -168,6 +169,22 @@
return 0;
}
+/**
+ * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
+ * @bd: pointer to BD descriptor structure
+ * @desc: Address offset of DMA descriptors
+ *
+ * This function writes the value into the corresponding Axi DMA register.
+ */
+static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
+{
+#if defined(CONFIG_PHYS_64BIT)
+ writeq(bd, desc);
+#else
+ writel((u32)bd, desc);
+#endif
+}
+
static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
u16 *val)
{
@@ -465,7 +482,7 @@
writel(temp, &priv->dmarx->control);
/* Start DMA RX channel. Now it's ready to receive data.*/
- writel((u32)&rx_bd, &priv->dmarx->current);
+ axienet_dma_write(&rx_bd, &priv->dmarx->current);
/* Setup the BD. */
memset(&rx_bd, 0, sizeof(rx_bd));
@@ -485,7 +502,7 @@
writel(temp, &priv->dmarx->control);
/* Rx BD is ready - start */
- writel((u32)&rx_bd, &priv->dmarx->tail);
+ axienet_dma_write(&rx_bd, &priv->dmarx->tail);
/* Enable TX */
writel(XAE_TC_TX_MASK, ®s->tc);
@@ -527,7 +544,7 @@
if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
u32 temp;
- writel((u32)&tx_bd, &priv->dmatx->current);
+ axienet_dma_write(&tx_bd, &priv->dmatx->current);
/* Start the hardware */
temp = readl(&priv->dmatx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
@@ -535,7 +552,7 @@
}
/* Start transfer */
- writel((u32)&tx_bd, &priv->dmatx->tail);
+ axienet_dma_write(&tx_bd, &priv->dmatx->tail);
/* Wait for transmission to complete */
debug("axiemac: Waiting for tx to be done\n");
@@ -626,7 +643,7 @@
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Rx BD is ready - start again */
- writel((u32)&rx_bd, &priv->dmarx->tail);
+ axienet_dma_write(&rx_bd, &priv->dmarx->tail);
debug("axiemac: RX completed, framelength = %d\n", length);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 2cc49bc..dd36a8c 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -182,6 +182,7 @@
int phy_of_handle;
struct mii_dev *bus;
struct clk clk;
+ u32 max_speed;
bool int_pcs;
};
@@ -325,7 +326,8 @@
/* Enable only MDIO bus */
writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
- if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
+ if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
+ (priv->interface != PHY_INTERFACE_MODE_GMII)) {
ret = phy_detection(dev);
if (ret) {
printf("GEM PHY init failed\n");
@@ -340,6 +342,12 @@
priv->phydev->supported &= supported | ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
+ if (priv->max_speed) {
+ ret = phy_set_supported(priv->phydev, priv->max_speed);
+ if (ret)
+ return ret;
+ }
+
priv->phydev->advertising = priv->phydev->supported;
if (priv->phy_of_handle > 0)
@@ -703,6 +711,8 @@
}
priv->interface = pdata->phy_interface;
+ priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
+ "max-speed", SPEED_1000);
priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
"is-internal-pcspma");
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index da6421f..c20a0cc 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -26,6 +26,16 @@
measure when porting a board to use driver model for PCI. Once the
board is fully supported, this option should be disabled.
+config PCI_AARDVARK
+ bool "Enable Aardvark PCIe driver"
+ default n
+ depends on DM_PCI
+ depends on ARMADA_3700
+ help
+ Say Y here if you want to enable PCIe controller support on
+ Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
+ Aardvark hardware.
+
config PCI_PNP
bool "Enable Plug & Play support for PCI"
depends on PCI || DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 8fbab46..40ebc06 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -30,6 +30,7 @@
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
+obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
new file mode 100644
index 0000000..69a4d81
--- /dev/null
+++ b/drivers/pci/pci-aardvark.c
@@ -0,0 +1,690 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2015 Marvell International Ltd.
+ * ***************************************************************************
+ * This program is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation, either version 2 of the License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * ***************************************************************************
+ */
+/* pcie_advk.c
+ *
+ * Ported from Linux driver - driver/pci/host/pci-aardvark.c
+ *
+ * Author: Victor Gu <xigu@marvell.com>
+ * Hezi Shahmoon <hezi.shahmoon@marvell.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <linux/ioport.h>
+
+/* PCIe core registers */
+#define PCIE_CORE_CMD_STATUS_REG 0x4
+#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
+#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
+#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
+#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
+#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
+#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
+#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
+#define PCIE_CORE_LINK_TRAINING BIT(5)
+#define PCIE_CORE_ERR_CAPCTL_REG 0x118
+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
+
+/* PIO registers base address and register offsets */
+#define PIO_BASE_ADDR 0x4000
+#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
+#define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
+#define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
+#define PIO_STAT (PIO_BASE_ADDR + 0x4)
+#define PIO_COMPLETION_STATUS_SHIFT 7
+#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
+#define PIO_COMPLETION_STATUS_OK 0
+#define PIO_COMPLETION_STATUS_UR 1
+#define PIO_COMPLETION_STATUS_CRS 2
+#define PIO_COMPLETION_STATUS_CA 4
+#define PIO_NON_POSTED_REQ BIT(10)
+#define PIO_ERR_STATUS BIT(11)
+#define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
+#define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
+#define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
+#define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
+#define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
+#define PIO_START (PIO_BASE_ADDR + 0x1c)
+#define PIO_ISR (PIO_BASE_ADDR + 0x20)
+
+/* Aardvark Control registers */
+#define CONTROL_BASE_ADDR 0x4800
+#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
+#define PCIE_GEN_SEL_MSK 0x3
+#define PCIE_GEN_SEL_SHIFT 0x0
+#define SPEED_GEN_1 0
+#define SPEED_GEN_2 1
+#define SPEED_GEN_3 2
+#define IS_RC_MSK 1
+#define IS_RC_SHIFT 2
+#define LANE_CNT_MSK 0x18
+#define LANE_CNT_SHIFT 0x3
+#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
+#define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
+#define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
+#define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
+#define LINK_TRAINING_EN BIT(6)
+#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
+#define PCIE_CORE_CTRL2_RESERVED 0x7
+#define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
+#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
+#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
+
+/* LMI registers base address and register offsets */
+#define LMI_BASE_ADDR 0x6000
+#define CFG_REG (LMI_BASE_ADDR + 0x0)
+#define LTSSM_SHIFT 24
+#define LTSSM_MASK 0x3f
+#define LTSSM_L0 0x10
+
+/* PCIe core controller registers */
+#define CTRL_CORE_BASE_ADDR 0x18000
+#define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
+#define CTRL_MODE_SHIFT 0x0
+#define CTRL_MODE_MASK 0x1
+#define PCIE_CORE_MODE_DIRECT 0x0
+#define PCIE_CORE_MODE_COMMAND 0x1
+
+/* Transaction types */
+#define PCIE_CONFIG_RD_TYPE0 0x8
+#define PCIE_CONFIG_RD_TYPE1 0x9
+#define PCIE_CONFIG_WR_TYPE0 0xa
+#define PCIE_CONFIG_WR_TYPE1 0xb
+
+/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
+#define PCIE_BDF(dev) (dev << 4)
+#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
+#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
+#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
+#define PCIE_CONF_REG(reg) ((reg) & 0xffc)
+#define PCIE_CONF_ADDR(bus, devfn, where) \
+ (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
+
+/* PCIe Retries & Timeout definitions */
+#define MAX_RETRIES 10
+#define PIO_WAIT_TIMEOUT 100
+#define LINK_WAIT_TIMEOUT 100000
+
+#define CFG_RD_UR_VAL 0xFFFFFFFF
+#define CFG_RD_CRS_VAL 0xFFFF0001
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct pcie_advk - Advk PCIe controller state
+ *
+ * @reg_base: The base address of the register space.
+ * @first_busno: This driver supports multiple PCIe controllers.
+ * first_busno stores the bus number of the PCIe root-port
+ * number which may vary depending on the PCIe setup
+ * (PEX switches etc).
+ * @device: The pointer to PCI uclass device.
+ */
+struct pcie_advk {
+ void *base;
+ int first_busno;
+ struct udevice *dev;
+};
+
+static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
+{
+ writel(val, pcie->base + reg);
+}
+
+static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
+{
+ return readl(pcie->base + reg);
+}
+
+/**
+ * pcie_advk_addr_valid() - Check for valid bus address
+ *
+ * @bdf: The PCI device to access
+ * @first_busno: Bus number of the PCIe controller root complex
+ *
+ * Return: 1 on valid, 0 on invalid
+ */
+static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
+{
+ /*
+ * In PCIE-E only a single device (0) can exist
+ * on the local bus. Beyound the local bus, there might be
+ * a Switch and everything is possible.
+ */
+ if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+ return 0;
+
+ return 1;
+}
+
+/**
+ * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
+ *
+ * @pcie: The PCI device to access
+ *
+ * Wait up to 1 micro second for PIO access to be accomplished.
+ *
+ * Return 1 (true) if PIO access is accomplished.
+ * Return 0 (false) if PIO access is timed out.
+ */
+static int pcie_advk_wait_pio(struct pcie_advk *pcie)
+{
+ uint start, isr;
+ uint count;
+
+ for (count = 0; count < MAX_RETRIES; count++) {
+ start = advk_readl(pcie, PIO_START);
+ isr = advk_readl(pcie, PIO_ISR);
+ if (!start && isr)
+ return 1;
+ /*
+ * Do not check the PIO state too frequently,
+ * 100us delay is appropriate.
+ */
+ udelay(PIO_WAIT_TIMEOUT);
+ }
+
+ dev_err(pcie->dev, "config read/write timed out\n");
+ return 0;
+}
+
+/**
+ * pcie_advk_check_pio_status() - Validate PIO status and get the read result
+ *
+ * @pcie: Pointer to the PCI bus
+ * @read: Read from or write to configuration space - true(read) false(write)
+ * @read_val: Pointer to the read result, only valid when read is true
+ *
+ */
+static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
+ bool read,
+ uint *read_val)
+{
+ uint reg;
+ unsigned int status;
+ char *strcomp_status, *str_posted;
+
+ reg = advk_readl(pcie, PIO_STAT);
+ status = (reg & PIO_COMPLETION_STATUS_MASK) >>
+ PIO_COMPLETION_STATUS_SHIFT;
+
+ switch (status) {
+ case PIO_COMPLETION_STATUS_OK:
+ if (reg & PIO_ERR_STATUS) {
+ strcomp_status = "COMP_ERR";
+ break;
+ }
+ /* Get the read result */
+ if (read)
+ *read_val = advk_readl(pcie, PIO_RD_DATA);
+ /* No error */
+ strcomp_status = NULL;
+ break;
+ case PIO_COMPLETION_STATUS_UR:
+ if (read) {
+ /* For reading, UR is not an error status. */
+ *read_val = CFG_RD_UR_VAL;
+ strcomp_status = NULL;
+ } else {
+ strcomp_status = "UR";
+ }
+ break;
+ case PIO_COMPLETION_STATUS_CRS:
+ if (read) {
+ /* For reading, CRS is not an error status. */
+ *read_val = CFG_RD_CRS_VAL;
+ strcomp_status = NULL;
+ } else {
+ strcomp_status = "CRS";
+ }
+ break;
+ case PIO_COMPLETION_STATUS_CA:
+ strcomp_status = "CA";
+ break;
+ default:
+ strcomp_status = "Unknown";
+ break;
+ }
+
+ if (!strcomp_status)
+ return 0;
+
+ if (reg & PIO_NON_POSTED_REQ)
+ str_posted = "Non-posted";
+ else
+ str_posted = "Posted";
+
+ dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
+ str_posted, strcomp_status, reg,
+ advk_readl(pcie, PIO_ADDR_LS));
+
+ return -EFAULT;
+}
+
+/**
+ * pcie_advk_read_config() - Read from configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_advk_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct pcie_advk *pcie = dev_get_priv(bus);
+ uint reg;
+ int ret;
+
+ dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+
+ if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ dev_dbg(pcie->dev, "- out of range\n");
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ /* Start PIO */
+ advk_writel(pcie, 0, PIO_START);
+ advk_writel(pcie, 1, PIO_ISR);
+
+ /* Program the control register */
+ reg = advk_readl(pcie, PIO_CTRL);
+ reg &= ~PIO_CTRL_TYPE_MASK;
+ if (PCI_BUS(bdf) == pcie->first_busno)
+ reg |= PCIE_CONFIG_RD_TYPE0;
+ else
+ reg |= PCIE_CONFIG_RD_TYPE1;
+ advk_writel(pcie, reg, PIO_CTRL);
+
+ /* Program the address registers */
+ reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ advk_writel(pcie, reg, PIO_ADDR_LS);
+ advk_writel(pcie, 0, PIO_ADDR_MS);
+
+ /* Start the transfer */
+ advk_writel(pcie, 1, PIO_START);
+
+ if (!pcie_advk_wait_pio(pcie))
+ return -EINVAL;
+
+ /* Check PIO status and get the read result */
+ ret = pcie_advk_check_pio_status(pcie, true, ®);
+ if (ret)
+ return ret;
+
+ dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
+ offset, size, reg);
+ *valuep = pci_conv_32_to_size(reg, offset, size);
+
+ return 0;
+}
+
+/**
+ * pcie_calc_datastrobe() - Calculate data strobe
+ *
+ * @offset: The offset into the device's configuration space
+ * @size: Indicates the size of access to perform
+ *
+ * Calculate data strobe according to offset and size
+ *
+ */
+static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
+{
+ uint bytes, data_strobe;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ bytes = 1;
+ break;
+ case PCI_SIZE_16:
+ bytes = 2;
+ break;
+ default:
+ bytes = 4;
+ }
+
+ data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
+
+ return data_strobe;
+}
+
+/**
+ * pcie_advk_write_config() - Write to configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct pcie_advk *pcie = dev_get_priv(bus);
+ uint reg;
+
+ dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
+ offset, size, value);
+
+ if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ dev_dbg(pcie->dev, "- out of range\n");
+ return 0;
+ }
+
+ /* Start PIO */
+ advk_writel(pcie, 0, PIO_START);
+ advk_writel(pcie, 1, PIO_ISR);
+
+ /* Program the control register */
+ reg = advk_readl(pcie, PIO_CTRL);
+ reg &= ~PIO_CTRL_TYPE_MASK;
+ if (PCI_BUS(bdf) == pcie->first_busno)
+ reg |= PCIE_CONFIG_WR_TYPE0;
+ else
+ reg |= PCIE_CONFIG_WR_TYPE1;
+ advk_writel(pcie, reg, PIO_CTRL);
+
+ /* Program the address registers */
+ reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ advk_writel(pcie, reg, PIO_ADDR_LS);
+ advk_writel(pcie, 0, PIO_ADDR_MS);
+ dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
+
+ /* Program the data register */
+ reg = pci_conv_size_to_32(0, value, offset, size);
+ advk_writel(pcie, reg, PIO_WR_DATA);
+ dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
+
+ /* Program the data strobe */
+ reg = pcie_calc_datastrobe(offset, size);
+ advk_writel(pcie, reg, PIO_WR_DATA_STRB);
+ dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
+
+ /* Start the transfer */
+ advk_writel(pcie, 1, PIO_START);
+
+ if (!pcie_advk_wait_pio(pcie)) {
+ dev_dbg(pcie->dev, "- wait pio timeout\n");
+ return -EINVAL;
+ }
+
+ /* Check PIO status */
+ pcie_advk_check_pio_status(pcie, false, ®);
+
+ return 0;
+}
+
+/**
+ * pcie_advk_link_up() - Check if PCIe link is up or not
+ *
+ * @pcie: The PCI device to access
+ *
+ * Return 1 (true) on link up.
+ * Return 0 (false) on link down.
+ */
+static int pcie_advk_link_up(struct pcie_advk *pcie)
+{
+ u32 val, ltssm_state;
+
+ val = advk_readl(pcie, CFG_REG);
+ ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
+ return ltssm_state >= LTSSM_L0;
+}
+
+/**
+ * pcie_advk_wait_for_link() - Wait for link training to be accomplished
+ *
+ * @pcie: The PCI device to access
+ *
+ * Wait up to 1 second for link training to be accomplished.
+ *
+ * Return 1 (true) if link training ends up with link up success.
+ * Return 0 (false) if link training ends up with link up failure.
+ */
+static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
+{
+ int retries;
+
+ /* check if the link is up or not */
+ for (retries = 0; retries < MAX_RETRIES; retries++) {
+ if (pcie_advk_link_up(pcie)) {
+ printf("PCIE-%d: Link up\n", pcie->first_busno);
+ return 0;
+ }
+
+ udelay(LINK_WAIT_TIMEOUT);
+ }
+
+ printf("PCIE-%d: Link down\n", pcie->first_busno);
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * pcie_advk_setup_hw() - PCIe initailzation
+ *
+ * @pcie: The PCI device to access
+ *
+ * Return: 0 on success
+ */
+static int pcie_advk_setup_hw(struct pcie_advk *pcie)
+{
+ u32 reg;
+
+ /* Set to Direct mode */
+ reg = advk_readl(pcie, CTRL_CONFIG_REG);
+ reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
+ reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
+ advk_writel(pcie, reg, CTRL_CONFIG_REG);
+
+ /* Set PCI global control register to RC mode */
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+ reg |= (IS_RC_MSK << IS_RC_SHIFT);
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+ /* Set Advanced Error Capabilities and Control PF0 register */
+ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
+ PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
+ PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
+ PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
+ advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
+
+ /* Set PCIe Device Control and Status 1 PF0 register */
+ reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
+ PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+
+ /* Program PCIe Control 2 to disable strict ordering */
+ reg = PCIE_CORE_CTRL2_RESERVED |
+ PCIE_CORE_CTRL2_TD_ENABLE;
+ advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+
+ /* Set GEN2 */
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+ reg &= ~PCIE_GEN_SEL_MSK;
+ reg |= SPEED_GEN_2;
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+ /* Set lane X1 */
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+ reg &= ~LANE_CNT_MSK;
+ reg |= LANE_COUNT_1;
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+ /* Enable link training */
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+ reg |= LINK_TRAINING_EN;
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+ /*
+ * Enable AXI address window location generation:
+ * When it is enabled, the default outbound window
+ * configurations (Default User Field: 0xD0074CFC)
+ * are used to transparent address translation for
+ * the outbound transactions. Thus, PCIe address
+ * windows are not required.
+ */
+ reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
+ reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
+ advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+
+ /*
+ * Bypass the address window mapping for PIO:
+ * Since PIO access already contains all required
+ * info over AXI interface by PIO registers, the
+ * address window is not required.
+ */
+ reg = advk_readl(pcie, PIO_CTRL);
+ reg |= PIO_CTRL_ADDR_WIN_DISABLE;
+ advk_writel(pcie, reg, PIO_CTRL);
+
+ /* Start link training */
+ reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
+ reg |= PCIE_CORE_LINK_TRAINING;
+ advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
+
+ /* Wait for PCIe link up */
+ if (pcie_advk_wait_for_link(pcie))
+ return -ENXIO;
+
+ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
+ reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
+ PCIE_CORE_CMD_IO_ACCESS_EN |
+ PCIE_CORE_CMD_MEM_IO_REQ_EN;
+ advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
+
+ return 0;
+}
+
+/**
+ * pcie_advk_probe() - Probe the PCIe bus for active link
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Probe for an active link on the PCIe bus and configure the controller
+ * to enable this port.
+ *
+ * Return: 0 on success, else -ENODEV
+ */
+static int pcie_advk_probe(struct udevice *dev)
+{
+ struct pcie_advk *pcie = dev_get_priv(dev);
+
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc reset_gpio;
+
+ gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
+ GPIOD_IS_OUT);
+ /*
+ * Issue reset to add-in card through the dedicated GPIO.
+ * Some boards are connecting the card reset pin to common system
+ * reset wire and others are using separate GPIO port.
+ * In the last case we have to release a reset of the addon card
+ * using this GPIO.
+ *
+ * FIX-ME:
+ * The PCIe RESET signal is not supposed to be released along
+ * with the SOC RESET signal. It should be lowered as early as
+ * possible before PCIe PHY initialization. Moreover, the PCIe
+ * clock should be gated as well.
+ */
+ if (dm_gpio_is_valid(&reset_gpio)) {
+ dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
+ dm_gpio_set_value(&reset_gpio, 0);
+ mdelay(200);
+ dm_gpio_set_value(&reset_gpio, 1);
+ }
+#else
+ dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
+#endif /* CONFIG_DM_GPIO */
+
+ pcie->first_busno = dev->seq;
+ pcie->dev = pci_get_controller(dev);
+
+ return pcie_advk_setup_hw(pcie);
+}
+
+/**
+ * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pcie_advk *pcie = dev_get_priv(dev);
+
+ /* Get the register base address */
+ pcie->base = (void *)dev_read_addr_index(dev, 0);
+ if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops pcie_advk_ops = {
+ .read_config = pcie_advk_read_config,
+ .write_config = pcie_advk_write_config,
+};
+
+static const struct udevice_id pcie_advk_ids[] = {
+ { .compatible = "marvell,armada-37xx-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_advk) = {
+ .name = "pcie_advk",
+ .id = UCLASS_PCI,
+ .of_match = pcie_advk_ids,
+ .ops = &pcie_advk_ops,
+ .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
+ .probe = pcie_advk_probe,
+ .priv_auto_alloc_size = sizeof(struct pcie_advk),
+};
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index ad43e8a..a2e8296 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -876,6 +876,9 @@
#ifdef CONFIG_NR_DRAM_BANKS
bd_t *bd = gd->bd;
+ if (!bd)
+ return 0;
+
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
pci_set_region(hose->regions + hose->region_count++,
@@ -894,8 +897,9 @@
#endif
if (gd->pci_ram_top && gd->pci_ram_top < base + size)
size = gd->pci_ram_top - base;
- pci_set_region(hose->regions + hose->region_count++, base, base,
- size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ if (size)
+ pci_set_region(hose->regions + hose->region_count++, base,
+ base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#endif
return 0;
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index a198855..a0032b7 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -111,6 +111,10 @@
void *cfg_base;
fdt_size_t cfg_size;
int first_busno;
+
+ /* IO and MEM PCI regions */
+ struct pci_region io;
+ struct pci_region mem;
};
static int pcie_dw_get_link_speed(const void *regs_base)
@@ -126,6 +130,34 @@
}
/**
+ * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
+ *
+ * @pcie: Pointer to the PCI controller state
+ * @index: ATU region index
+ * @type: ATU accsess type
+ * @cpu_addr: the physical address for the translation entry
+ * @pci_addr: the pcie bus address for the translation entry
+ * @size: the size of the translation entry
+ */
+static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
+ int type, u64 cpu_addr, u64 pci_addr,
+ u32 size)
+{
+ writel(PCIE_ATU_REGION_OUTBOUND | index,
+ pcie->ctrl_base + PCIE_ATU_VIEWPORT);
+ writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
+ writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
+ writel(lower_32_bits(cpu_addr + size - 1),
+ pcie->ctrl_base + PCIE_ATU_LIMIT);
+ writel(lower_32_bits(pci_addr),
+ pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
+ writel(upper_32_bits(pci_addr),
+ pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
+ writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
+ writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
+}
+
+/**
* set_cfg_address() - Configure the PCIe controller config space access
*
* @pcie: Pointer to the PCI controller state
@@ -143,27 +175,29 @@
pci_dev_t d, uint where)
{
uintptr_t va_address;
+ u32 atu_type;
/*
* Region #0 is used for Outbound CFG space access.
* Direction = Outbound
* Region Index = 0
*/
- writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
if (PCI_BUS(d) == (pcie->first_busno + 1))
/* For local bus, change TLP Type field to 4. */
- writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
+ atu_type = PCIE_ATU_TYPE_CFG0;
else
/* Otherwise, change TLP Type field to 5. */
- writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1);
+ atu_type = PCIE_ATU_TYPE_CFG1;
if (PCI_BUS(d) == pcie->first_busno) {
/* Accessing root port configuration space. */
va_address = (uintptr_t)pcie->ctrl_base;
} else {
d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
- writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
+ pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+ atu_type, (u64)pcie->cfg_base,
+ d << 8, pcie->cfg_size);
va_address = (uintptr_t)pcie->cfg_base;
}
@@ -231,6 +265,10 @@
debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
*valuep = pci_conv_32_to_size(value, offset, size);
+ pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+ pcie->io.bus_start, pcie->io.size);
+
return 0;
}
@@ -272,6 +310,10 @@
value = pci_conv_size_to_32(old, value, offset, size);
writel(value, va_address);
+ pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+ pcie->io.bus_start, pcie->io.size);
+
return 0;
}
@@ -388,34 +430,6 @@
}
/**
- * pcie_dw_regions_setup() - iATU region setup
- *
- * @pcie: Pointer to the PCI controller state
- *
- * Configure the iATU regions in the PCIe controller for outbound access.
- */
-static void pcie_dw_regions_setup(struct pcie_dw_mvebu *pcie)
-{
- /*
- * Region #0 is used for Outbound CFG space access.
- * Direction = Outbound
- * Region Index = 0
- */
- writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
-
- writel((u32)(uintptr_t)pcie->cfg_base, pcie->ctrl_base
- + PCIE_ATU_LOWER_BASE);
- writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
- writel((u32)(uintptr_t)pcie->cfg_base + pcie->cfg_size,
- pcie->ctrl_base + PCIE_ATU_LIMIT);
-
- writel(0, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
- writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
- writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
- writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
-}
-
-/**
* pcie_dw_set_host_bars() - Configure the host BARs
*
* @regs_base: A pointer to the PCIe controller registers
@@ -495,7 +509,18 @@
hose->first_busno);
}
- pcie_dw_regions_setup(pcie);
+ /* Store the IO and MEM windows settings for future use by the ATU */
+ pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
+ pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
+ pcie->io.size = hose->regions[0].size; /* IO size */
+
+ pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
+ pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
+ pcie->mem.size = hose->regions[1].size; /* MEM size */
+
+ pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
+ pcie->mem.bus_start, pcie->mem.size);
/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3b9a09c..119edec 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -59,6 +59,31 @@
This is useful when a driver uses the PHY framework but no real PHY
hardware exists.
+config BCM6318_USBH_PHY
+ bool "BCM6318 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ select POWER_DOMAIN
+ help
+ Support for the Broadcom MIPS BCM6318 USBH PHY.
+
+config BCM6348_USBH_PHY
+ bool "BCM6348 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ help
+ Support for the Broadcom MIPS BCM6348 USBH PHY.
+
+config BCM6358_USBH_PHY
+ bool "BCM6358 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ help
+ Support for the Broadcom MIPS BCM6358 USBH PHY.
+
+config BCM6368_USBH_PHY
+ bool "BCM6368 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ help
+ Support for the Broadcom MIPS BCM6368 USBH PHY.
+
config PIPE3_PHY
bool "Support omap's PIPE3 PHY"
depends on PHY && ARCH_OMAP2PLUS
@@ -85,4 +110,12 @@
used by USB2 and USB3 Host controllers available on
STiH407 SoC families.
+config MESON_GXL_USB_PHY
+ bool "Amlogic Meson GXL USB PHYs"
+ depends on PHY && ARCH_MESON && MESON_GXL
+ imply REGMAP
+ help
+ This is the generic phy driver for the Amlogic Meson GXL
+ USB2 and USB3 PHYS.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 668040b..72c1492 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,11 @@
obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
+obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
+obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
+obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
+obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c
new file mode 100644
index 0000000..6d542145
--- /dev/null
+++ b/drivers/phy/bcm6318-usbh-phy.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH Setup register */
+#define USBH_SETUP_REG 0x00
+#define USBH_SETUP_IOC BIT(4)
+
+/* USBH PLL Control register */
+#define USBH_PLL_REG 0x04
+#define USBH_PLL_SUSP_EN BIT(27)
+#define USBH_PLL_IDDQ_PWRDN BIT(31)
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG 0x0c
+#define USBH_SWAP_OHCI_DATA BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN BIT(1)
+#define USBH_SWAP_EHCI_DATA BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN BIT(4)
+
+/* USBH Sim Control register */
+#define USBH_SIM_REG 0x20
+#define USBH_SIM_LADDR BIT(5)
+
+struct bcm6318_usbh_priv {
+ void __iomem *regs;
+};
+
+static int bcm6318_usbh_init(struct phy *phy)
+{
+ struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev);
+
+ /* enable pll control susp */
+ setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN);
+
+ /* configure to work in native cpu endian */
+ clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+ USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+ USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+ /* setup config */
+ setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
+
+ /* disable pll control pwrdn */
+ clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN);
+
+ /* sim control config */
+ setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);
+
+ return 0;
+}
+
+static struct phy_ops bcm6318_usbh_ops = {
+ .init = bcm6318_usbh_init,
+};
+
+static const struct udevice_id bcm6318_usbh_ids[] = {
+ { .compatible = "brcm,bcm6318-usbh" },
+ { /* sentinel */ }
+};
+
+static int bcm6318_usbh_probe(struct udevice *dev)
+{
+ struct bcm6318_usbh_priv *priv = dev_get_priv(dev);
+ struct power_domain pwr_dom;
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+
+ /* enable usbh clock */
+ ret = clk_get_by_name(dev, "usbh", &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+ /* enable power domain */
+ ret = power_domain_get(dev, &pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_on(&pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_free(&pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ mdelay(100);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6318_usbh) = {
+ .name = "bcm6318-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6318_usbh_ids,
+ .ops = &bcm6318_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv),
+ .probe = bcm6318_usbh_probe,
+};
diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c
new file mode 100644
index 0000000..169ee0e
--- /dev/null
+++ b/drivers/phy/bcm6348-usbh-phy.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+#define USBH_SETUP_PORT1_EN BIT(0)
+
+struct bcm6348_usbh_priv {
+ void __iomem *regs;
+};
+
+static int bcm6348_usbh_init(struct phy *phy)
+{
+ struct bcm6348_usbh_priv *priv = dev_get_priv(phy->dev);
+
+ writel_be(USBH_SETUP_PORT1_EN, priv->regs);
+
+ return 0;
+}
+
+static struct phy_ops bcm6348_usbh_ops = {
+ .init = bcm6348_usbh_init,
+};
+
+static const struct udevice_id bcm6348_usbh_ids[] = {
+ { .compatible = "brcm,bcm6348-usbh" },
+ { /* sentinel */ }
+};
+
+static int bcm6348_usbh_probe(struct udevice *dev)
+{
+ struct bcm6348_usbh_priv *priv = dev_get_priv(dev);
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+
+ /* enable usbh clock */
+ ret = clk_get_by_name(dev, "usbh", &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6348_usbh) = {
+ .name = "bcm6348-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6348_usbh_ids,
+ .ops = &bcm6348_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6348_usbh_priv),
+ .probe = bcm6348_usbh_probe,
+};
diff --git a/drivers/phy/bcm6358-usbh-phy.c b/drivers/phy/bcm6358-usbh-phy.c
new file mode 100644
index 0000000..e000316
--- /dev/null
+++ b/drivers/phy/bcm6358-usbh-phy.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG 0x00
+#define USBH_SWAP_OHCI_DATA BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN BIT(1)
+#define USBH_SWAP_EHCI_DATA BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN BIT(4)
+
+/* USBH Test register */
+#define USBH_TEST_REG 0x24
+#define USBH_TEST_PORT_CTL 0x1c0020
+
+struct bcm6358_usbh_priv {
+ void __iomem *regs;
+};
+
+static int bcm6358_usbh_init(struct phy *phy)
+{
+ struct bcm6358_usbh_priv *priv = dev_get_priv(phy->dev);
+
+ /* configure to work in native cpu endian */
+ clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+ USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+ USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+ /* test port control */
+ writel_be(USBH_TEST_PORT_CTL, priv->regs + USBH_TEST_REG);
+
+ return 0;
+}
+
+static struct phy_ops bcm6358_usbh_ops = {
+ .init = bcm6358_usbh_init,
+};
+
+static const struct udevice_id bcm6358_usbh_ids[] = {
+ { .compatible = "brcm,bcm6358-usbh" },
+ { /* sentinel */ }
+};
+
+static int bcm6358_usbh_probe(struct udevice *dev)
+{
+ struct bcm6358_usbh_priv *priv = dev_get_priv(dev);
+ struct reset_ctl rst_ctl;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6358_usbh) = {
+ .name = "bcm6358-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6358_usbh_ids,
+ .ops = &bcm6358_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6358_usbh_priv),
+ .probe = bcm6358_usbh_probe,
+};
diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c
new file mode 100644
index 0000000..71abc0f
--- /dev/null
+++ b/drivers/phy/bcm6368-usbh-phy.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH PLL Control register */
+#define USBH_PLL_REG 0x18
+#define USBH_PLL_IDDQ_PWRDN BIT(9)
+#define USBH_PLL_PWRDN_DELAY BIT(10)
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG 0x1c
+#define USBH_SWAP_OHCI_DATA BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN BIT(1)
+#define USBH_SWAP_EHCI_DATA BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN BIT(4)
+
+/* USBH Setup register */
+#define USBH_SETUP_REG 0x28
+#define USBH_SETUP_IOC BIT(4)
+#define USBH_SETUP_IPP BIT(5)
+
+struct bcm6368_usbh_hw {
+ uint32_t setup_clr;
+ uint32_t pll_clr;
+};
+
+struct bcm6368_usbh_priv {
+ const struct bcm6368_usbh_hw *hw;
+ void __iomem *regs;
+};
+
+static int bcm6368_usbh_init(struct phy *phy)
+{
+ struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev);
+ const struct bcm6368_usbh_hw *hw = priv->hw;
+
+ /* configure to work in native cpu endian */
+ clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+ USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+ USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+ /* setup config */
+ if (hw->setup_clr)
+ clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr);
+
+ setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
+
+ /* enable pll control */
+ if (hw->pll_clr)
+ clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr);
+
+ return 0;
+}
+
+static struct phy_ops bcm6368_usbh_ops = {
+ .init = bcm6368_usbh_init,
+};
+
+static const struct bcm6368_usbh_hw bcm6328_hw = {
+ .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
+ .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm6362_hw = {
+ .pll_clr = 0,
+ .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm6368_hw = {
+ .pll_clr = 0,
+ .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm63268_hw = {
+ .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
+ .setup_clr = USBH_SETUP_IPP,
+};
+
+static const struct udevice_id bcm6368_usbh_ids[] = {
+ {
+ .compatible = "brcm,bcm6328-usbh",
+ .data = (ulong)&bcm6328_hw,
+ }, {
+ .compatible = "brcm,bcm6362-usbh",
+ .data = (ulong)&bcm6362_hw,
+ }, {
+ .compatible = "brcm,bcm6368-usbh",
+ .data = (ulong)&bcm6368_hw,
+ }, {
+ .compatible = "brcm,bcm63268-usbh",
+ .data = (ulong)&bcm63268_hw,
+ }, { /* sentinel */ }
+};
+
+static int bcm6368_usbh_probe(struct udevice *dev)
+{
+ struct bcm6368_usbh_priv *priv = dev_get_priv(dev);
+ const struct bcm6368_usbh_hw *hw =
+ (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev);
+#if defined(CONFIG_POWER_DOMAIN)
+ struct power_domain pwr_dom;
+#endif
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ priv->hw = hw;
+
+ /* enable usbh clock */
+ ret = clk_get_by_name(dev, "usbh", &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+#if defined(CONFIG_POWER_DOMAIN)
+ /* enable power domain */
+ ret = power_domain_get(dev, &pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_on(&pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_free(&pwr_dom);
+ if (ret < 0)
+ return ret;
+#endif
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ /* enable usb_ref clock */
+ ret = clk_get_by_name(dev, "usb_ref", &clk);
+ if (!ret) {
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+ }
+
+ mdelay(100);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6368_usbh) = {
+ .name = "bcm6368-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6368_usbh_ids,
+ .ops = &bcm6368_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv),
+ .probe = bcm6368_usbh_probe,
+};
diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c
new file mode 100644
index 0000000..15c9c89
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb2.c
@@ -0,0 +1,238 @@
+/*
+ * Meson GXL and GXM USB2 PHY driver
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* bits [31:27] are read-only */
+#define U2P_R0 0x0
+ #define U2P_R0_BYPASS_SEL BIT(0)
+ #define U2P_R0_BYPASS_DM_EN BIT(1)
+ #define U2P_R0_BYPASS_DP_EN BIT(2)
+ #define U2P_R0_TXBITSTUFF_ENH BIT(3)
+ #define U2P_R0_TXBITSTUFF_EN BIT(4)
+ #define U2P_R0_DM_PULLDOWN BIT(5)
+ #define U2P_R0_DP_PULLDOWN BIT(6)
+ #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
+ #define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
+ #define U2P_R0_ADP_PRB_EN BIT(9)
+ #define U2P_R0_ADP_DISCHARGE BIT(10)
+ #define U2P_R0_ADP_CHARGE BIT(11)
+ #define U2P_R0_DRV_VBUS BIT(12)
+ #define U2P_R0_ID_PULLUP BIT(13)
+ #define U2P_R0_LOOPBACK_EN_B BIT(14)
+ #define U2P_R0_OTG_DISABLE BIT(15)
+ #define U2P_R0_COMMON_ONN BIT(16)
+ #define U2P_R0_FSEL_MASK GENMASK(19, 17)
+ #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
+ #define U2P_R0_POWER_ON_RESET BIT(22)
+ #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
+ #define U2P_R0_ID_SET_ID_DQ BIT(25)
+ #define U2P_R0_ATE_RESET BIT(26)
+ #define U2P_R0_FSV_MINUS BIT(27)
+ #define U2P_R0_FSV_PLUS BIT(28)
+ #define U2P_R0_BYPASS_DM_DATA BIT(29)
+ #define U2P_R0_BYPASS_DP_DATA BIT(30)
+
+#define U2P_R1 0x4
+ #define U2P_R1_BURN_IN_TEST BIT(0)
+ #define U2P_R1_ACA_ENABLE BIT(1)
+ #define U2P_R1_DCD_ENABLE BIT(2)
+ #define U2P_R1_VDAT_SRC_EN_B BIT(3)
+ #define U2P_R1_VDAT_DET_EN_B BIT(4)
+ #define U2P_R1_CHARGES_SEL BIT(5)
+ #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
+ #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
+ #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
+ #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
+ #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
+ #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
+ #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
+ #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
+ #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
+ #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
+
+/* bits [31:14] are read-only */
+#define U2P_R2 0x8
+ #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)
+ #define U2P_R2_TESTADDR_MASK GENMASK(11, 8)
+ #define U2P_R2_TESTDATA_OUT_SEL BIT(12)
+ #define U2P_R2_TESTCLK BIT(13)
+ #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)
+ #define U2P_R2_ACA_PIN_RANGE_C BIT(18)
+ #define U2P_R2_ACA_PIN_RANGE_B BIT(19)
+ #define U2P_R2_ACA_PIN_RANGE_A BIT(20)
+ #define U2P_R2_ACA_PIN_GND BIT(21)
+ #define U2P_R2_ACA_PIN_FLOAT BIT(22)
+ #define U2P_R2_CHARGE_DETECT BIT(23)
+ #define U2P_R2_DEVICE_SESSION_VALID BIT(24)
+ #define U2P_R2_ADP_PROBE BIT(25)
+ #define U2P_R2_ADP_SENSE BIT(26)
+ #define U2P_R2_SESSION_END BIT(27)
+ #define U2P_R2_VBUS_VALID BIT(28)
+ #define U2P_R2_B_VALID BIT(29)
+ #define U2P_R2_A_VALID BIT(30)
+ #define U2P_R2_ID_DIG BIT(31)
+
+#define U2P_R3 0xc
+
+#define RESET_COMPLETE_TIME 500
+
+struct phy_meson_gxl_usb2_priv {
+ struct regmap *regmap;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *phy_supply;
+#endif
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+};
+
+static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
+{
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+
+ /* reset the PHY and wait until settings are stabilized */
+ val |= U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+ udelay(RESET_COMPLETE_TIME);
+
+ val &= ~U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+ udelay(RESET_COMPLETE_TIME);
+}
+
+static void
+phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv)
+{
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+ val |= U2P_R0_DM_PULLDOWN;
+ val |= U2P_R0_DP_PULLDOWN;
+ val &= ~U2P_R0_ID_PULLUP;
+ regmap_write(priv->regmap, U2P_R0, val);
+
+ phy_meson_gxl_usb2_reset(priv);
+}
+
+static int phy_meson_gxl_usb2_power_on(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+ /* power on the PHY by taking it out of reset mode */
+ val &= ~U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+
+ phy_meson_gxl_usb2_set_host_mode(priv);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->phy_supply) {
+ int ret = regulator_set_enable(priv->phy_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb2_power_off(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+ /* power off the PHY by putting it into reset mode */
+ val |= U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->phy_supply) {
+ int ret = regulator_set_enable(priv->phy_supply, false);
+ if (ret) {
+ pr_err("Error disabling PHY supply\n");
+ return ret;
+ }
+ }
+#endif
+
+ return 0;
+}
+
+struct phy_ops meson_gxl_usb2_phy_ops = {
+ .power_on = phy_meson_gxl_usb2_power_on,
+ .power_off = phy_meson_gxl_usb2_power_off,
+};
+
+int meson_gxl_usb2_phy_probe(struct udevice *dev)
+{
+ struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev, &priv->regmap);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get PHY regulator\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
+ { .compatible = "amlogic,meson-gxl-usb2-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
+ .name = "meson_gxl_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = meson_gxl_usb2_phy_ids,
+ .probe = meson_gxl_usb2_phy_probe,
+ .ops = &meson_gxl_usb2_phy_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
+};
diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c
new file mode 100644
index 0000000..a385fbd
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb3.c
@@ -0,0 +1,201 @@
+/*
+ * Meson GXL USB3 PHY driver
+ *
+ * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USB_R0 0x00
+ #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
+ #define USB_R0_P30_PHY_RESET BIT(6)
+ #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
+ #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
+ #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
+ #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
+ #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
+ #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
+ #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
+ #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
+ #define USB_R0_U2D_ACT BIT(31)
+
+#define USB_R1 0x04
+ #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
+ #define USB_R1_U3H_PME_ENABLE BIT(1)
+ #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
+ #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
+ #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
+ #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
+ #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
+ #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
+ #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
+ #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
+
+#define USB_R2 0x08
+ #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
+ #define USB_R2_P30_CR_READ BIT(16)
+ #define USB_R2_P30_CR_WRITE BIT(17)
+ #define USB_R2_P30_CR_CAP_ADDR BIT(18)
+ #define USB_R2_P30_CR_CAP_DATA BIT(19)
+ #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
+ #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
+
+#define USB_R3 0x0c
+ #define USB_R3_P30_SSC_ENABLE BIT(0)
+ #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
+ #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
+ #define USB_R3_P30_REF_SSP_EN BIT(13)
+ #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
+ #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
+ #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
+
+#define USB_R4 0x10
+ #define USB_R4_P21_PORT_RESET_0 BIT(0)
+ #define USB_R4_P21_SLEEP_M0 BIT(1)
+ #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
+ #define USB_R4_P21_ONLY BIT(4)
+
+#define USB_R5 0x14
+ #define USB_R5_ID_DIG_SYNC BIT(0)
+ #define USB_R5_ID_DIG_REG BIT(1)
+ #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
+ #define USB_R5_ID_DIG_EN_0 BIT(4)
+ #define USB_R5_ID_DIG_EN_1 BIT(5)
+ #define USB_R5_ID_DIG_CURR BIT(6)
+ #define USB_R5_ID_DIG_IRQ BIT(7)
+ #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
+ #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
+
+/* read-only register */
+#define USB_R6 0x18
+ #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
+ #define USB_R6_P30_CR_ACK BIT(16)
+
+struct phy_meson_gxl_usb3_priv {
+ struct regmap *regmap;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+};
+
+static int
+phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv)
+{
+ uint val;
+
+ regmap_read(priv->regmap, USB_R0, &val);
+ val &= ~USB_R0_U2D_ACT;
+ regmap_write(priv->regmap, USB_R0, val);
+
+ regmap_read(priv->regmap, USB_R4, &val);
+ val &= ~USB_R4_P21_SLEEP_M0;
+ regmap_write(priv->regmap, USB_R4, val);
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb3_power_on(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, USB_R5, &val);
+ val |= USB_R5_ID_DIG_EN_0;
+ val |= USB_R5_ID_DIG_EN_1;
+ val &= ~USB_R5_ID_DIG_TH_MASK;
+ val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff);
+ regmap_write(priv->regmap, USB_R5, val);
+
+ return phy_meson_gxl_usb3_set_host_mode(priv);
+}
+
+static int phy_meson_gxl_usb3_power_off(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, USB_R5, &val);
+ val &= ~USB_R5_ID_DIG_EN_0;
+ val &= ~USB_R5_ID_DIG_EN_1;
+ regmap_write(priv->regmap, USB_R5, val);
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb3_init(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, USB_R1, &val);
+ val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
+ val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20);
+ regmap_write(priv->regmap, USB_R1, val);
+
+ return 0;
+}
+
+struct phy_ops meson_gxl_usb3_phy_ops = {
+ .init = phy_meson_gxl_usb3_init,
+ .power_on = phy_meson_gxl_usb3_power_on,
+ .power_off = phy_meson_gxl_usb3_power_off,
+};
+
+int meson_gxl_usb3_phy_probe(struct udevice *dev)
+{
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev, &priv->regmap);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id meson_gxl_usb3_phy_ids[] = {
+ { .compatible = "amlogic,meson-gxl-usb3-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
+ .name = "meson_gxl_usb3_phy",
+ .id = UCLASS_PHY,
+ .of_match = meson_gxl_usb3_phy_ids,
+ .probe = meson_gxl_usb3_phy_probe,
+ .ops = &meson_gxl_usb3_phy_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv),
+};
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 2bf853e..010eb20 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -44,7 +44,7 @@
#define IRQ_STATUS 0x10
#define IRQ_WKUP 0x18
-#define NB_FUNCS 2
+#define NB_FUNCS 3
#define GPIO_PER_REG 32
/**
@@ -128,6 +128,16 @@
.funcs = {_func1, "gpio"} \
}
+#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
+ { \
+ .name = _name, \
+ .start_pin = _start, \
+ .npins = _nr, \
+ .reg_mask = _mask, \
+ .val = {_v1, _v2, _v3}, \
+ .funcs = {_f1, _f2, "gpio"} \
+ }
+
#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
_f1, _f2) \
{ \
@@ -149,8 +159,8 @@
PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
- PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
- PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
+ PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
+ PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
@@ -172,13 +182,15 @@
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
- PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
- PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
- PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
- PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
+ PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
+ PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
+ PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
+ PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
+ PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
- PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),
+ PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
+ "mii", "mii_err"),
};
const struct armada_37xx_pin_data armada_37xx_pin_nb = {
@@ -189,18 +201,18 @@
};
const struct armada_37xx_pin_data armada_37xx_pin_sb = {
- .nr_pins = 29,
+ .nr_pins = 30,
.name = "GPIO2",
.groups = armada_37xx_sb_groups,
.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
};
static inline void armada_37xx_update_reg(unsigned int *reg,
- unsigned int offset)
+ unsigned int *offset)
{
/* We never have more than 2 registers */
- if (offset >= GPIO_PER_REG) {
- offset -= GPIO_PER_REG;
+ if (*offset >= GPIO_PER_REG) {
+ *offset -= GPIO_PER_REG;
*reg += sizeof(u32);
}
}
@@ -210,7 +222,7 @@
{
int f;
- for (f = 0; f < NB_FUNCS; f++)
+ for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
if (!strcmp(grp->funcs[f], func))
return f;
@@ -352,7 +364,7 @@
for (j = 0; j < grp->extra_npins; j++)
grp->pins[i+j] = grp->extra_pin + j;
- for (f = 0; f < NB_FUNCS; f++) {
+ for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
int ret;
/* check for unique functions and count groups */
ret = armada_37xx_add_function(info->funcs, &funcsize,
@@ -404,7 +416,7 @@
struct armada_37xx_pin_group *gp = &info->groups[g];
int f;
- for (f = 0; f < NB_FUNCS; f++) {
+ for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
if (strcmp(gp->funcs[f], name) == 0) {
*groups = gp->name;
groups++;
@@ -421,7 +433,7 @@
unsigned int reg = INPUT_VAL;
unsigned int val, mask;
- armada_37xx_update_reg(®, offset);
+ armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
val = readl(info->base + reg);
@@ -436,7 +448,7 @@
unsigned int reg = OUTPUT_VAL;
unsigned int mask, val;
- armada_37xx_update_reg(®, offset);
+ armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
val = value ? mask : 0;
@@ -452,7 +464,7 @@
unsigned int reg = OUTPUT_EN;
unsigned int val, mask;
- armada_37xx_update_reg(®, offset);
+ armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
val = readl(info->base + reg);
@@ -469,7 +481,7 @@
unsigned int reg = OUTPUT_EN;
unsigned int mask;
- armada_37xx_update_reg(®, offset);
+ armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
clrbits_le32(info->base + reg, mask);
@@ -484,7 +496,7 @@
unsigned int reg = OUTPUT_EN;
unsigned int mask;
- armada_37xx_update_reg(®, offset);
+ armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
setbits_le32(info->base + reg, mask);
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index 6a73a06..a0a326a 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -12,6 +12,7 @@
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <dm/util.h>
+#include <dm/of_access.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -63,16 +64,13 @@
*/
static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
{
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
char propname[32]; /* long enough */
const fdt32_t *list;
uint32_t phandle;
- int config_node;
struct udevice *config;
int state, size, i, ret;
- state = fdt_stringlist_search(fdt, node, "pinctrl-names", statename);
+ state = dev_read_stringlist_search(dev, "pinctrl-names", statename);
if (state < 0) {
char *end;
/*
@@ -85,22 +83,15 @@
}
snprintf(propname, sizeof(propname), "pinctrl-%d", state);
- list = fdt_getprop(fdt, node, propname, &size);
+ list = dev_read_prop(dev, propname, &size);
if (!list)
return -EINVAL;
size /= sizeof(*list);
for (i = 0; i < size; i++) {
phandle = fdt32_to_cpu(*list++);
-
- config_node = fdt_node_offset_by_phandle(fdt, phandle);
- if (config_node < 0) {
- dev_err(dev, "prop %s index %d invalid phandle\n",
- propname, i);
- return -EINVAL;
- }
- ret = uclass_get_device_by_of_offset(UCLASS_PINCONFIG,
- config_node, &config);
+ ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG, phandle,
+ &config);
if (ret)
return ret;
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 2066e11..31285cd 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -41,9 +41,10 @@
return 0;
}
+
static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
{
- gpio_dsc->port = (port_pin & 0xF000) >> 12;
+ gpio_dsc->port = (port_pin & 0x1F000) >> 12;
gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
gpio_dsc->pin);
@@ -115,11 +116,13 @@
return -EINVAL;
for (i = 0; i < len; i++) {
struct gpio_desc desc;
+
debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
rv = uclass_get_device_by_seq(UCLASS_GPIO,
- gpio_dsc.port, &desc.dev);
+ gpio_dsc.port,
+ &desc.dev);
if (rv)
return rv;
desc.offset = gpio_dsc.pin;
@@ -186,6 +189,8 @@
{ .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
+ { .compatible = "st,stm32mp157-pinctrl" },
+ { .compatible = "st,stm32mp157-z-pinctrl" },
{ }
};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 94f6d7a..7e93d85 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -18,6 +18,416 @@
DECLARE_GLOBAL_DATA_PTR;
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 1 << GPIO0A3_SHIFT,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_I2C1_SDA,
+
+ GPIO0A2_SHIFT = 4,
+ GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
+ GPIO0A2_GPIO = 0,
+ GPIO0A2_I2C1_SCL,
+
+ GPIO0A1_SHIFT = 2,
+ GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
+ GPIO0A1_GPIO = 0,
+ GPIO0A1_I2C0_SDA,
+ GPIO0A1_PWM2,
+
+ GPIO0A0_SHIFT = 0,
+ GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
+ GPIO0A0_GPIO = 0,
+ GPIO0A0_I2C0_SCL,
+ GPIO0A0_PWM1,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B6_SHIFT = 12,
+ GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
+ GPIO0B6_GPIO = 0,
+ GPIO0B6_MMC1_D3,
+ GPIO0B6_I2S1_SCLK,
+
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_MMC1_D2,
+ GPIO0B5_I2S1_SDI,
+
+ GPIO0B4_SHIFT = 8,
+ GPIO0B4_MASK = 3 << GPIO0B4_SHIFT,
+ GPIO0B4_GPIO = 0,
+ GPIO0B4_MMC1_D1,
+ GPIO0B4_I2S1_LRCKTX,
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_MMC1_D0,
+ GPIO0B3_I2S1_LRCKRX,
+
+ GPIO0B1_SHIFT = 2,
+ GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
+ GPIO0B1_GPIO = 0,
+ GPIO0B1_MMC1_CLKOUT,
+ GPIO0B1_I2S1_MCLK,
+
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = 3,
+ GPIO0B0_GPIO = 0,
+ GPIO0B0_MMC1_CMD,
+ GPIO0B0_I2S1_SDO,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK = 1 << GPIO0C4_SHIFT,
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_DRIVE_VBUS,
+
+ GPIO0C3_SHIFT = 6,
+ GPIO0C3_MASK = 1 << GPIO0C3_SHIFT,
+ GPIO0C3_GPIO = 0,
+ GPIO0C3_UART0_CTSN,
+
+ GPIO0C2_SHIFT = 4,
+ GPIO0C2_MASK = 1 << GPIO0C2_SHIFT,
+ GPIO0C2_GPIO = 0,
+ GPIO0C2_UART0_RTSN,
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK = 1 << GPIO0C1_SHIFT,
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_UART0_SIN,
+
+
+ GPIO0C0_SHIFT = 0,
+ GPIO0C0_MASK = 1 << GPIO0C0_SHIFT,
+ GPIO0C0_GPIO = 0,
+ GPIO0C0_UART0_SOUT,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_SPDIF,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_PWM3,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A5_SHIFT = 10,
+ GPIO1A5_MASK = 1 << GPIO1A5_SHIFT,
+ GPIO1A5_GPIO = 0,
+ GPIO1A5_I2S_SDI,
+
+ GPIO1A4_SHIFT = 8,
+ GPIO1A4_MASK = 1 << GPIO1A4_SHIFT,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_I2S_SD0,
+
+ GPIO1A3_SHIFT = 6,
+ GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_I2S_LRCKTX,
+
+ GPIO1A2_SHIFT = 4,
+ GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_I2S_LRCKRX,
+ GPIO1A2_PWM1_0,
+
+ GPIO1A1_SHIFT = 2,
+ GPIO1A1_MASK = 1 << GPIO1A1_SHIFT,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_I2S_SCLK,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 1 << GPIO1A0_SHIFT,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_I2S_MCLK,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_MMC0_CMD,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 1 << GPIO1B3_SHIFT,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_HDMI_HPD,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 1 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_HDMI_SCL,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 1 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_HDMI_SDA,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 1 << GPIO1B0_SHIFT,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_HDMI_CEC,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_MMC0_D3,
+ GPIO1C5_JTAG_TMS,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_MMC0_D2,
+ GPIO1C4_JTAG_TCK,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_MMC0_D1,
+ GPIO1C3_UART2_SOUT,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_MMC0_D0,
+ GPIO1C2_UART2_SIN,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_MMC0_DETN,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_NAND_D7,
+ GPIO1D7_EMMC_D7,
+ GPIO1D7_SPI_CSN1,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_NAND_D6,
+ GPIO1D6_EMMC_D6,
+ GPIO1D6_SPI_CSN0,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_NAND_D5,
+ GPIO1D5_EMMC_D5,
+ GPIO1D5_SPI_TXD,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_NAND_D4,
+ GPIO1D4_EMMC_D4,
+ GPIO1D4_SPI_RXD,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_NAND_D3,
+ GPIO1D3_EMMC_D3,
+ GPIO1D3_SFC_SIO3,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_NAND_D2,
+ GPIO1D2_EMMC_D2,
+ GPIO1D2_SFC_SIO2,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_NAND_D1,
+ GPIO1D1_EMMC_D1,
+ GPIO1D1_SFC_SIO1,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_NAND_D0,
+ GPIO1D0_EMMC_D0,
+ GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 1 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_TESTCLK_OUT,
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_NAND_CS0,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_NAND_RDY,
+ GPIO2A4_EMMC_CMD,
+ GPIO2A3_SFC_CLK,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_NAND_RDN,
+ GPIO2A4_SFC_CSN1,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_NAND_WRN,
+ GPIO2A4_SFC_CSN0,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_NAND_CLE,
+ GPIO2A1_EMMC_CLKOUT,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_NAND_ALE,
+ GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 1 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_MAC_RXER,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_MAC_CLKOUT,
+ GPIO2B6_MAC_CLKIN,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_MAC_TXEN,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 1 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_MAC_MDIO,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_MAC_CRS,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C7_SHIFT = 14,
+ GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_UART1_SOUT,
+ GPIO2C7_TESTCLK_OUT1,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 1 << GPIO2C6_SHIFT,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_UART1_SIN,
+
+ GPIO2C5_SHIFT = 10,
+ GPIO2C5_MASK = 1 << GPIO2C5_SHIFT,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_I2C2_SCL,
+
+ GPIO2C4_SHIFT = 8,
+ GPIO2C4_MASK = 1 << GPIO2C4_SHIFT,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_I2C2_SDA,
+
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 1 << GPIO2C3_SHIFT,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_MAC_TXD0,
+
+ GPIO2C2_SHIFT = 4,
+ GPIO2C2_MASK = 1 << GPIO2C2_SHIFT,
+ GPIO2C2_GPIO = 0,
+ GPIO2C2_MAC_TXD1,
+
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 1 << GPIO2C1_SHIFT,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_MAC_RXD0,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 1 << GPIO2C0_SHIFT,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_MAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_I2S_SDO1,
+
+ GPIO2D5_SHIFT = 10,
+ GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_I2S_SDO2,
+
+ GPIO2D4_SHIFT = 8,
+ GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_I2S_SDO3,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 1 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_MAC_MDC,
+};
+
struct rk3036_pinctrl_priv {
struct rk3036_grf *grf;
};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
index 692d8e2..fdab836 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
@@ -20,6 +20,386 @@
DECLARE_GLOBAL_DATA_PTR;
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D7_SHIFT = 14,
+ GPIO0D7_MASK = 1,
+ GPIO0D7_GPIO = 0,
+ GPIO0D7_SPI1_CSN0,
+
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = 1,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_SPI1_CLK,
+
+ GPIO0D5_SHIFT = 10,
+ GPIO0D5_MASK = 1,
+ GPIO0D5_GPIO = 0,
+ GPIO0D5_SPI1_TXD,
+
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 1,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_SPI0_RXD,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 3,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_FLASH_CSN3,
+ GPIO0D3_EMMC_RSTN_OUT,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 3,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_FLASH_CSN2,
+ GPIO0D2_EMMC_CMD,
+
+ GPIO0D1_SHIFT = 2,
+ GPIO0D1_MASK = 1,
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_FLASH_CSN1,
+
+ GPIO0D0_SHIFT = 0,
+ GPIO0D0_MASK = 3,
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_FLASH_DQS,
+ GPIO0D0_EMMC_CLKOUT
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A7_SHIFT = 14,
+ GPIO1A7_MASK = 3,
+ GPIO1A7_GPIO = 0,
+ GPIO1A7_UART1_RTS_N,
+ GPIO1A7_SPI0_CSN0,
+
+ GPIO1A6_SHIFT = 12,
+ GPIO1A6_MASK = 3,
+ GPIO1A6_GPIO = 0,
+ GPIO1A6_UART1_CTS_N,
+ GPIO1A6_SPI0_CLK,
+
+ GPIO1A5_SHIFT = 10,
+ GPIO1A5_MASK = 3,
+ GPIO1A5_GPIO = 0,
+ GPIO1A5_UART1_SOUT,
+ GPIO1A5_SPI0_TXD,
+
+ GPIO1A4_SHIFT = 8,
+ GPIO1A4_MASK = 3,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_UART1_SIN,
+ GPIO1A4_SPI0_RXD,
+
+ GPIO1A3_SHIFT = 6,
+ GPIO1A3_MASK = 1,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_UART0_RTS_N,
+
+ GPIO1A2_SHIFT = 4,
+ GPIO1A2_MASK = 1,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_UART0_CTS_N,
+
+ GPIO1A1_SHIFT = 2,
+ GPIO1A1_MASK = 1,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_UART0_SOUT,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 1,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_UART0_SIN,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 1,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_SPI0_CSN1,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 3,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_SPDIF_TX,
+ GPIO1B6_SPI1_CSN1,
+
+ GPIO1B5_SHIFT = 10,
+ GPIO1B5_MASK = 3,
+ GPIO1B5_GPIO = 0,
+ GPIO1B5_UART3_RTS_N,
+ GPIO1B5_RESERVED,
+
+ GPIO1B4_SHIFT = 8,
+ GPIO1B4_MASK = 3,
+ GPIO1B4_GPIO = 0,
+ GPIO1B4_UART3_CTS_N,
+ GPIO1B4_GPS_RFCLK,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 3,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_UART3_SOUT,
+ GPIO1B3_GPS_SIG,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART3_SIN,
+ GPIO1B2_GPS_MAG,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART2_SOUT,
+ GPIO1B1_JTAG_TDO,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 3,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_UART2_SIN,
+ GPIO1B0_JTAG_TDI,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 1,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_I2C4_SCL,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 1,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_I2C4_SDA,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 1,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_I2C2_SCL,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 1,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_I2C2_SDA,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 1,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_I2C1_SCL,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 1,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_I2C1_SDA,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 1,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_I2C0_SCL,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 1,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_I2C0_SDA,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+ GPIO3A7_SHIFT = 14,
+ GPIO3A7_MASK = 1,
+ GPIO3A7_GPIO = 0,
+ GPIO3A7_SDMMC0_DATA3,
+
+ GPIO3A6_SHIFT = 12,
+ GPIO3A6_MASK = 1,
+ GPIO3A6_GPIO = 0,
+ GPIO3A6_SDMMC0_DATA2,
+
+ GPIO3A5_SHIFT = 10,
+ GPIO3A5_MASK = 1,
+ GPIO3A5_GPIO = 0,
+ GPIO3A5_SDMMC0_DATA1,
+
+ GPIO3A4_SHIFT = 8,
+ GPIO3A4_MASK = 1,
+ GPIO3A4_GPIO = 0,
+ GPIO3A4_SDMMC0_DATA0,
+
+ GPIO3A3_SHIFT = 6,
+ GPIO3A3_MASK = 1,
+ GPIO3A3_GPIO = 0,
+ GPIO3A3_SDMMC0_CMD,
+
+ GPIO3A2_SHIFT = 4,
+ GPIO3A2_MASK = 1,
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_SDMMC0_CLKOUT,
+
+ GPIO3A1_SHIFT = 2,
+ GPIO3A1_MASK = 1,
+ GPIO3A1_GPIO = 0,
+ GPIO3A1_SDMMC0_PWREN,
+
+ GPIO3A0_SHIFT = 0,
+ GPIO3A0_MASK = 1,
+ GPIO3A0_GPIO = 0,
+ GPIO3A0_SDMMC0_RSTN,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+ GPIO3B7_SHIFT = 14,
+ GPIO3B7_MASK = 3,
+ GPIO3B7_GPIO = 0,
+ GPIO3B7_CIF_DATA11,
+ GPIO3B7_I2C3_SCL,
+
+ GPIO3B6_SHIFT = 12,
+ GPIO3B6_MASK = 3,
+ GPIO3B6_GPIO = 0,
+ GPIO3B6_CIF_DATA10,
+ GPIO3B6_I2C3_SDA,
+
+ GPIO3B5_SHIFT = 10,
+ GPIO3B5_MASK = 3,
+ GPIO3B5_GPIO = 0,
+ GPIO3B5_CIF_DATA1,
+ GPIO3B5_HSADC_DATA9,
+
+ GPIO3B4_SHIFT = 8,
+ GPIO3B4_MASK = 3,
+ GPIO3B4_GPIO = 0,
+ GPIO3B4_CIF_DATA0,
+ GPIO3B4_HSADC_DATA8,
+
+ GPIO3B3_SHIFT = 6,
+ GPIO3B3_MASK = 1,
+ GPIO3B3_GPIO = 0,
+ GPIO3B3_CIF_CLKOUT,
+
+ GPIO3B2_SHIFT = 4,
+ GPIO3B2_MASK = 1,
+ GPIO3B2_GPIO = 0,
+ /* no muxes */
+
+ GPIO3B1_SHIFT = 2,
+ GPIO3B1_MASK = 1,
+ GPIO3B1_GPIO = 0,
+ GPIO3B1_SDMMC0_WRITE_PRT,
+
+ GPIO3B0_SHIFT = 0,
+ GPIO3B0_MASK = 1,
+ GPIO3B0_GPIO = 0,
+ GPIO3B0_SDMMC_DETECT_N,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C7_SHIFT = 14,
+ GPIO3C7_MASK = 3,
+ GPIO3C7_GPIO = 0,
+ GPIO3C7_SDMMC1_WRITE_PRT,
+ GPIO3C7_RMII_CRS_DVALID,
+ GPIO3C7_RESERVED,
+
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 3,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_SDMMC1_DECTN,
+ GPIO3C6_RMII_RX_ERR,
+ GPIO3C6_RESERVED,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 3,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_SDMMC1_CLKOUT,
+ GPIO3C5_RMII_CLKOUT,
+ GPIO3C5_RMII_CLKIN,
+
+ GPIO3C4_SHIFT = 8,
+ GPIO3C4_MASK = 3,
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_SDMMC1_DATA3,
+ GPIO3C4_RMII_RXD1,
+ GPIO3C4_RESERVED,
+
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = 3,
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_SDMMC1_DATA2,
+ GPIO3C3_RMII_RXD0,
+ GPIO3C3_RESERVED,
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 3,
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_SDMMC1_DATA1,
+ GPIO3C2_RMII_TXD0,
+ GPIO3C2_RESERVED,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 3,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_SDMMC1_DATA0,
+ GPIO3C1_RMII_TXD1,
+ GPIO3C1_RESERVED,
+
+ GPIO3C0_SHIFT = 0,
+ GPIO3C0_MASK = 3,
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_SDMMC1_CMD,
+ GPIO3C0_RMII_TX_EN,
+ GPIO3C0_RESERVED,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+ GPIO3D6_SHIFT = 12,
+ GPIO3D6_MASK = 3,
+ GPIO3D6_GPIO = 0,
+ GPIO3D6_PWM_3,
+ GPIO3D6_JTAG_TMS,
+ GPIO3D6_HOST_DRV_VBUS,
+
+ GPIO3D5_SHIFT = 10,
+ GPIO3D5_MASK = 3,
+ GPIO3D5_GPIO = 0,
+ GPIO3D5_PWM_2,
+ GPIO3D5_JTAG_TCK,
+ GPIO3D5_OTG_DRV_VBUS,
+
+ GPIO3D4_SHIFT = 8,
+ GPIO3D4_MASK = 3,
+ GPIO3D4_GPIO = 0,
+ GPIO3D4_PWM_1,
+ GPIO3D4_JTAG_TRSTN,
+
+ GPIO3D3_SHIFT = 6,
+ GPIO3D3_MASK = 3,
+ GPIO3D3_GPIO = 0,
+ GPIO3D3_PWM_0,
+
+ GPIO3D2_SHIFT = 4,
+ GPIO3D2_MASK = 3,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_SDMMC1_INT_N,
+
+ GPIO3D1_SHIFT = 2,
+ GPIO3D1_MASK = 3,
+ GPIO3D1_GPIO = 0,
+ GPIO3D1_SDMMC1_BACKEND_PWR,
+ GPIO3D1_MII_MDCLK,
+
+ GPIO3D0_SHIFT = 0,
+ GPIO3D0_MASK = 3,
+ GPIO3D0_GPIO = 0,
+ GPIO3D0_SDMMC1_PWR_EN,
+ GPIO3D0_MII_MD,
+};
+
struct rk3188_pinctrl_priv {
struct rk3188_grf *grf;
struct rk3188_pmu *pmu;
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index 19a7415..c705225 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -70,6 +70,60 @@
PMUGRF_GPIO1C0_SEL_MASK,
PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
break;
+
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio4a_iomux,
+ GRF_GPIO4A1_SEL_MASK,
+ GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio4a_iomux,
+ GRF_GPIO4A2_SEL_MASK,
+ GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
+ break;
+
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A0_SEL_MASK,
+ GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A1_SEL_MASK,
+ GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C0_SEL_MASK,
+ GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C1_SEL_MASK,
+ GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
+ break;
+
+ case PERIPH_ID_I2C4:
+ rk_clrsetreg(&pmugrf->gpio1b_iomux,
+ PMUGRF_GPIO1B3_SEL_MASK,
+ PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
+ rk_clrsetreg(&pmugrf->gpio1b_iomux,
+ PMUGRF_GPIO1B4_SEL_MASK,
+ PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
+ break;
+
+ case PERIPH_ID_I2C7:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A7_SEL_MASK,
+ GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2b_iomux,
+ GRF_GPIO2B0_SEL_MASK,
+ GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
+ break;
+
+ case PERIPH_ID_I2C6:
+ rk_clrsetreg(&grf->gpio2b_iomux,
+ GRF_GPIO2B1_SEL_MASK,
+ GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2b_iomux,
+ GRF_GPIO2B2_SEL_MASK,
+ GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
+ break;
+
case PERIPH_ID_I2C8:
rk_clrsetreg(&pmugrf->gpio1c_iomux,
PMUGRF_GPIO1C4_SEL_MASK,
@@ -78,13 +132,8 @@
PMUGRF_GPIO1C5_SEL_MASK,
PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
break;
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
+
case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
default:
debug("i2c id = %d iomux error!\n", i2c_id);
break;
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index d8c107e..1a38524 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -22,6 +22,7 @@
config AXP152_POWER
bool "axp152 pmic support"
depends on MACH_SUN5I
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Select this to enable support for the axp152 pmic found on most
@@ -30,6 +31,7 @@
config AXP209_POWER
bool "axp209 pmic support"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Select this to enable support for the axp209 pmic found on most
@@ -38,6 +40,7 @@
config AXP221_POWER
bool "axp221 / axp223 pmic support"
depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Select this to enable support for the axp221/axp223 pmic found on most
@@ -46,6 +49,7 @@
config AXP809_POWER
bool "axp809 pmic support"
depends on MACH_SUN9I
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Say y here to enable support for the axp809 pmic found on A80 boards.
@@ -53,6 +57,7 @@
config AXP818_POWER
bool "axp818 pmic support"
depends on MACH_SUN8I_A83T
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Say y here to enable support for the axp818 pmic found on
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 5d49c93..40ab9f7 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -209,3 +209,11 @@
The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
pmic children.
+
+config PMIC_STPMU1
+ bool "Enable support for STMicroelectronics STPMU1 PMIC"
+ depends on DM_PMIC && DM_I2C
+ ---help---
+ The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
+ It is accessed via an I2C interface. The device is used with STM32MP1
+ SoCs. This driver implements register read/write operations.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index fc19fdc..ad32068 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -23,6 +23,7 @@
obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
+obj-$(CONFIG_PMIC_STPMU1) += stpmu1.o
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/stpmu1.c b/drivers/power/pmic/stpmu1.c
new file mode 100644
index 0000000..4615365
--- /dev/null
+++ b/drivers/power/pmic/stpmu1.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+
+#define STMPU1_NUM_OF_REGS 0x100
+
+static int stpmu1_reg_count(struct udevice *dev)
+{
+ return STMPU1_NUM_OF_REGS;
+}
+
+static int stpmu1_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret)
+ dev_err(dev, "%s: failed to write register %#x :%d",
+ __func__, reg, ret);
+
+ return ret;
+}
+
+static int stpmu1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret)
+ dev_err(dev, "%s: failed to read register %#x : %d",
+ __func__, reg, ret);
+
+ return ret;
+}
+
+static struct dm_pmic_ops stpmu1_ops = {
+ .reg_count = stpmu1_reg_count,
+ .read = stpmu1_read,
+ .write = stpmu1_write,
+};
+
+static const struct udevice_id stpmu1_ids[] = {
+ { .compatible = "st,stpmu1" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_stpmu1) = {
+ .name = "stpmu1_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = stpmu1_ids,
+ .ops = &stpmu1_ops,
+};
diff --git a/drivers/power/regulator/pbias_regulator.c b/drivers/power/regulator/pbias_regulator.c
index 116b7f4..adf589b 100644
--- a/drivers/power/regulator/pbias_regulator.c
+++ b/drivers/power/regulator/pbias_regulator.c
@@ -225,9 +225,6 @@
int rc;
u32 reg;
- debug("Setting %s voltage to %s\n", p->name,
- (reg & p->vmode) ? "3.0v" : "1.8v");
-
rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
if (rc)
return rc;
@@ -239,6 +236,9 @@
else
return -EINVAL;
+ debug("Setting %s voltage to %s\n", p->name,
+ (reg & p->vmode) ? "3.0v" : "1.8v");
+
return pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg));
}
diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index 2364c2d..7d3e11d 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -76,7 +76,7 @@
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
- priv->regs = (struct rk3288_pwm *)devfdt_get_addr(dev);
+ priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
return 0;
}
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 47969f3..496e2b7 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -33,3 +33,5 @@
STM32F7 family devices support flexible memory controller(FMC) to
support external memories like sdram, psram & nand.
This driver is for the sdram memory interface with the FMC.
+
+source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 51ae6be..3820d03 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -6,6 +6,7 @@
#
obj-$(CONFIG_RAM) += ram-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
+obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/
obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 76c1fe8..5cb470c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1015,6 +1015,7 @@
writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
mdelay(10);
+ i++;
if (i > 10) {
debug("index1 frequency done overtime\n");
return -ETIME;
diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig
new file mode 100644
index 0000000..b9c8166
--- /dev/null
+++ b/drivers/ram/stm32mp1/Kconfig
@@ -0,0 +1,12 @@
+
+config STM32MP1_DDR
+ bool "STM32MP1 DDR driver"
+ depends on DM && OF_CONTROL && ARCH_STM32MP
+ select RAM
+ select SPL_RAM if SPL
+ default y
+ help
+ activate STM32MP1 DDR controller driver for STM32MP1 soc
+ family: support for LPDDR2, LPDDR3 and DDR3
+ the SDRAM parameters for controleur and phy need to be provided
+ in device tree (computed by DDR tuning tools)
diff --git a/drivers/ram/stm32mp1/Makefile b/drivers/ram/stm32mp1/Makefile
new file mode 100644
index 0000000..9f05cd4
--- /dev/null
+++ b/drivers/ram/stm32mp1/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+obj-y += stm32mp1_ram.o
+obj-y += stm32mp1_ddr.o
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
new file mode 100644
index 0000000..ffe50d9
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -0,0 +1,496 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <ram.h>
+#include <reset.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <linux/iopoll.h>
+#include "stm32mp1_ddr.h"
+#include "stm32mp1_ddr_regs.h"
+
+#define RCC_DDRITFCR 0xD8
+
+#define RCC_DDRITFCR_DDRCAPBRST (BIT(14))
+#define RCC_DDRITFCR_DDRCAXIRST (BIT(15))
+#define RCC_DDRITFCR_DDRCORERST (BIT(16))
+#define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
+#define RCC_DDRITFCR_DPHYRST (BIT(18))
+#define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
+
+struct reg_desc {
+ const char *name;
+ u16 offset; /* offset for base address */
+ u8 par_offset; /* offset for parameter array */
+};
+
+#define INVALID_OFFSET 0xFF
+
+#define DDRCTL_REG(x, y) \
+ {#x,\
+ offsetof(struct stm32mp1_ddrctl, x),\
+ offsetof(struct y, x)}
+
+#define DDRPHY_REG(x, y) \
+ {#x,\
+ offsetof(struct stm32mp1_ddrphy, x),\
+ offsetof(struct y, x)}
+
+#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
+static const struct reg_desc ddr_reg[] = {
+ DDRCTL_REG_REG(mstr),
+ DDRCTL_REG_REG(mrctrl0),
+ DDRCTL_REG_REG(mrctrl1),
+ DDRCTL_REG_REG(derateen),
+ DDRCTL_REG_REG(derateint),
+ DDRCTL_REG_REG(pwrctl),
+ DDRCTL_REG_REG(pwrtmg),
+ DDRCTL_REG_REG(hwlpctl),
+ DDRCTL_REG_REG(rfshctl0),
+ DDRCTL_REG_REG(rfshctl3),
+ DDRCTL_REG_REG(crcparctl0),
+ DDRCTL_REG_REG(zqctl0),
+ DDRCTL_REG_REG(dfitmg0),
+ DDRCTL_REG_REG(dfitmg1),
+ DDRCTL_REG_REG(dfilpcfg0),
+ DDRCTL_REG_REG(dfiupd0),
+ DDRCTL_REG_REG(dfiupd1),
+ DDRCTL_REG_REG(dfiupd2),
+ DDRCTL_REG_REG(dfiphymstr),
+ DDRCTL_REG_REG(odtmap),
+ DDRCTL_REG_REG(dbg0),
+ DDRCTL_REG_REG(dbg1),
+ DDRCTL_REG_REG(dbgcmd),
+ DDRCTL_REG_REG(poisoncfg),
+ DDRCTL_REG_REG(pccfg),
+};
+
+#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
+static const struct reg_desc ddr_timing[] = {
+ DDRCTL_REG_TIMING(rfshtmg),
+ DDRCTL_REG_TIMING(dramtmg0),
+ DDRCTL_REG_TIMING(dramtmg1),
+ DDRCTL_REG_TIMING(dramtmg2),
+ DDRCTL_REG_TIMING(dramtmg3),
+ DDRCTL_REG_TIMING(dramtmg4),
+ DDRCTL_REG_TIMING(dramtmg5),
+ DDRCTL_REG_TIMING(dramtmg6),
+ DDRCTL_REG_TIMING(dramtmg7),
+ DDRCTL_REG_TIMING(dramtmg8),
+ DDRCTL_REG_TIMING(dramtmg14),
+ DDRCTL_REG_TIMING(odtcfg),
+};
+
+#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
+static const struct reg_desc ddr_map[] = {
+ DDRCTL_REG_MAP(addrmap1),
+ DDRCTL_REG_MAP(addrmap2),
+ DDRCTL_REG_MAP(addrmap3),
+ DDRCTL_REG_MAP(addrmap4),
+ DDRCTL_REG_MAP(addrmap5),
+ DDRCTL_REG_MAP(addrmap6),
+ DDRCTL_REG_MAP(addrmap9),
+ DDRCTL_REG_MAP(addrmap10),
+ DDRCTL_REG_MAP(addrmap11),
+};
+
+#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
+static const struct reg_desc ddr_perf[] = {
+ DDRCTL_REG_PERF(sched),
+ DDRCTL_REG_PERF(sched1),
+ DDRCTL_REG_PERF(perfhpr1),
+ DDRCTL_REG_PERF(perflpr1),
+ DDRCTL_REG_PERF(perfwr1),
+ DDRCTL_REG_PERF(pcfgr_0),
+ DDRCTL_REG_PERF(pcfgw_0),
+ DDRCTL_REG_PERF(pcfgqos0_0),
+ DDRCTL_REG_PERF(pcfgqos1_0),
+ DDRCTL_REG_PERF(pcfgwqos0_0),
+ DDRCTL_REG_PERF(pcfgwqos1_0),
+ DDRCTL_REG_PERF(pcfgr_1),
+ DDRCTL_REG_PERF(pcfgw_1),
+ DDRCTL_REG_PERF(pcfgqos0_1),
+ DDRCTL_REG_PERF(pcfgqos1_1),
+ DDRCTL_REG_PERF(pcfgwqos0_1),
+ DDRCTL_REG_PERF(pcfgwqos1_1),
+};
+
+#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
+static const struct reg_desc ddrphy_reg[] = {
+ DDRPHY_REG_REG(pgcr),
+ DDRPHY_REG_REG(aciocr),
+ DDRPHY_REG_REG(dxccr),
+ DDRPHY_REG_REG(dsgcr),
+ DDRPHY_REG_REG(dcr),
+ DDRPHY_REG_REG(odtcr),
+ DDRPHY_REG_REG(zq0cr1),
+ DDRPHY_REG_REG(dx0gcr),
+ DDRPHY_REG_REG(dx1gcr),
+ DDRPHY_REG_REG(dx2gcr),
+ DDRPHY_REG_REG(dx3gcr),
+};
+
+#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
+static const struct reg_desc ddrphy_timing[] = {
+ DDRPHY_REG_TIMING(ptr0),
+ DDRPHY_REG_TIMING(ptr1),
+ DDRPHY_REG_TIMING(ptr2),
+ DDRPHY_REG_TIMING(dtpr0),
+ DDRPHY_REG_TIMING(dtpr1),
+ DDRPHY_REG_TIMING(dtpr2),
+ DDRPHY_REG_TIMING(mr0),
+ DDRPHY_REG_TIMING(mr1),
+ DDRPHY_REG_TIMING(mr2),
+ DDRPHY_REG_TIMING(mr3),
+};
+
+#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
+static const struct reg_desc ddrphy_cal[] = {
+ DDRPHY_REG_CAL(dx0dllcr),
+ DDRPHY_REG_CAL(dx0dqtr),
+ DDRPHY_REG_CAL(dx0dqstr),
+ DDRPHY_REG_CAL(dx1dllcr),
+ DDRPHY_REG_CAL(dx1dqtr),
+ DDRPHY_REG_CAL(dx1dqstr),
+ DDRPHY_REG_CAL(dx2dllcr),
+ DDRPHY_REG_CAL(dx2dqtr),
+ DDRPHY_REG_CAL(dx2dqstr),
+ DDRPHY_REG_CAL(dx3dllcr),
+ DDRPHY_REG_CAL(dx3dqtr),
+ DDRPHY_REG_CAL(dx3dqstr),
+};
+
+enum reg_type {
+ REG_REG,
+ REG_TIMING,
+ REG_PERF,
+ REG_MAP,
+ REGPHY_REG,
+ REGPHY_TIMING,
+ REGPHY_CAL,
+ REG_TYPE_NB
+};
+
+enum base_type {
+ DDR_BASE,
+ DDRPHY_BASE,
+ NONE_BASE
+};
+
+struct ddr_reg_info {
+ const char *name;
+ const struct reg_desc *desc;
+ u8 size;
+ enum base_type base;
+};
+
+#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
+
+const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
+[REG_REG] = {
+ "static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE},
+[REG_TIMING] = {
+ "timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE},
+[REG_PERF] = {
+ "perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE},
+[REG_MAP] = {
+ "map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE},
+[REGPHY_REG] = {
+ "static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE},
+[REGPHY_TIMING] = {
+ "timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE},
+[REGPHY_CAL] = {
+ "cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE},
+};
+
+const char *base_name[] = {
+ [DDR_BASE] = "ctl",
+ [DDRPHY_BASE] = "phy",
+};
+
+static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
+{
+ if (base == DDRPHY_BASE)
+ return (u32)priv->phy;
+ else
+ return (u32)priv->ctl;
+}
+
+static void set_reg(const struct ddr_info *priv,
+ enum reg_type type,
+ const void *param)
+{
+ unsigned int i;
+ unsigned int *ptr, value;
+ enum base_type base = ddr_registers[type].base;
+ u32 base_addr = get_base_addr(priv, base);
+ const struct reg_desc *desc = ddr_registers[type].desc;
+
+ debug("init %s\n", ddr_registers[type].name);
+ for (i = 0; i < ddr_registers[type].size; i++) {
+ ptr = (unsigned int *)(base_addr + desc[i].offset);
+ if (desc[i].par_offset == INVALID_OFFSET) {
+ pr_err("invalid parameter offset for %s", desc[i].name);
+ } else {
+ value = *((u32 *)((u32)param +
+ desc[i].par_offset));
+ writel(value, ptr);
+ debug("[0x%x] %s= 0x%08x\n",
+ (u32)ptr, desc[i].name, value);
+ }
+ }
+}
+
+static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
+{
+ u32 pgsr;
+ int ret;
+
+ ret = readl_poll_timeout(&phy->pgsr, pgsr,
+ pgsr & (DDRPHYC_PGSR_IDONE |
+ DDRPHYC_PGSR_DTERR |
+ DDRPHYC_PGSR_DTIERR |
+ DDRPHYC_PGSR_DFTERR |
+ DDRPHYC_PGSR_RVERR |
+ DDRPHYC_PGSR_RVEIRR),
+ 1000000);
+ debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
+ (u32)&phy->pgsr, pgsr, ret);
+}
+
+void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
+{
+ pir |= DDRPHYC_PIR_INIT;
+ writel(pir, &phy->pir);
+ debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
+ (u32)&phy->pir, pir, readl(&phy->pir));
+
+ /* need to wait 10 configuration clock before start polling */
+ udelay(10);
+
+ /* Wait DRAM initialization and Gate Training Evaluation complete */
+ ddrphy_idone_wait(phy);
+}
+
+/* start quasi dynamic register update */
+static void start_sw_done(struct stm32mp1_ddrctl *ctl)
+{
+ clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+}
+
+/* wait quasi dynamic register update */
+static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
+{
+ int ret;
+ u32 swstat;
+
+ setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+
+ ret = readl_poll_timeout(&ctl->swstat, swstat,
+ swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
+ 1000000);
+ if (ret)
+ panic("Timeout initialising DRAM : DDR->swstat = %x\n",
+ swstat);
+
+ debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
+}
+
+/* wait quasi dynamic register update */
+static void wait_operating_mode(struct ddr_info *priv, int mode)
+{
+ u32 stat, val, mask, val2 = 0, mask2 = 0;
+ int ret;
+
+ mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
+ val = mode;
+ /* self-refresh due to software => check also STAT.selfref_type */
+ if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
+ mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
+ stat |= DDRCTRL_STAT_SELFREF_TYPE_SR;
+ } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
+ /* normal mode: handle also automatic self refresh */
+ mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
+ DDRCTRL_STAT_SELFREF_TYPE_MASK;
+ val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
+ DDRCTRL_STAT_SELFREF_TYPE_ASR;
+ }
+
+ ret = readl_poll_timeout(&priv->ctl->stat, stat,
+ ((stat & mask) == val) ||
+ (mask2 && ((stat & mask2) == val2)),
+ 1000000);
+
+ if (ret)
+ panic("Timeout DRAM : DDR->stat = %x\n", stat);
+
+ debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
+}
+
+void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
+{
+ start_sw_done(ctl);
+ /* quasi-dynamic register update*/
+ setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+ clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+ clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ wait_sw_done_ack(ctl);
+}
+
+void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
+ u32 rfshctl3, u32 pwrctl)
+{
+ start_sw_done(ctl);
+ if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
+ clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+ if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
+ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+ setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ wait_sw_done_ack(ctl);
+}
+
+/* board-specific DDR power initializations. */
+__weak int board_ddr_power_init(void)
+{
+ return 0;
+}
+
+__maybe_unused
+void stm32mp1_ddr_init(struct ddr_info *priv,
+ const struct stm32mp1_ddr_config *config)
+{
+ u32 pir;
+ int ret;
+
+ ret = board_ddr_power_init();
+
+ if (ret)
+ panic("ddr power init failed\n");
+
+ debug("name = %s\n", config->info.name);
+ debug("speed = %d MHz\n", config->info.speed);
+ debug("size = 0x%x\n", config->info.size);
+/*
+ * 1. Program the DWC_ddr_umctl2 registers
+ * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
+ */
+ /* Assert All DDR part */
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
+
+/* 1.2. start CLOCK */
+ if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
+ panic("invalid DRAM clock : %d MHz\n",
+ config->info.speed);
+
+/* 1.3. deassert reset */
+ /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
+ /* De-assert presetn once the clocks are active
+ * and stable via DDRCAPBRST bit
+ */
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
+
+/* 1.4. wait 4 cycles for synchronization */
+ asm(" nop");
+ asm(" nop");
+ asm(" nop");
+ asm(" nop");
+
+/* 1.5. initialize registers ddr_umctl2 */
+ /* Stop uMCTL2 before PHY is ready */
+ clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ debug("[0x%08x] dfimisc = 0x%08x\n",
+ (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
+
+ set_reg(priv, REG_REG, &config->c_reg);
+ set_reg(priv, REG_TIMING, &config->c_timing);
+ set_reg(priv, REG_MAP, &config->c_map);
+
+ /* skip CTRL init, SDRAM init is done by PHY PUBL */
+ clrsetbits_le32(&priv->ctl->init0,
+ DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
+ DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
+
+ set_reg(priv, REG_PERF, &config->c_perf);
+
+/* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
+
+/* 3. start PHY init by accessing relevant PUBL registers
+ * (DXGCR, DCR, PTR*, MR*, DTPR*)
+ */
+ set_reg(priv, REGPHY_REG, &config->p_reg);
+ set_reg(priv, REGPHY_TIMING, &config->p_timing);
+ set_reg(priv, REGPHY_CAL, &config->p_cal);
+
+/* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
+ * Perform DDR PHY DRAM initialization and Gate Training Evaluation
+ */
+ ddrphy_idone_wait(priv->phy);
+
+/* 5. Indicate to PUBL that controller performs SDRAM initialization
+ * by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
+ * DRAM init is done by PHY, init0.skip_dram.init = 1
+ */
+ pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
+ DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
+
+ if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
+ pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
+
+ stm32mp1_ddrphy_init(priv->phy, pir);
+
+/* 6. SET DFIMISC.dfi_init_complete_en to 1 */
+ /* Enable quasi-dynamic register programming*/
+ start_sw_done(priv->ctl);
+ setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ wait_sw_done_ack(priv->ctl);
+
+/* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode
+ * by monitoring STAT.operating_mode signal
+ */
+ /* wait uMCTL2 ready */
+
+ wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
+
+ debug("DDR DQS training : ");
+/* 8. Disable Auto refresh and power down by setting
+ * - RFSHCTL3.dis_au_refresh = 1
+ * - PWRCTL.powerdown_en = 0
+ * - DFIMISC.dfiinit_complete_en = 0
+ */
+ stm32mp1_refresh_disable(priv->ctl);
+
+/* 9. Program PUBL PGCR to enable refresh during training and rank to train
+ * not done => keep the programed value in PGCR
+ */
+
+/* 10. configure PUBL PIR register to specify which training step to run */
+ /* warning : RVTRN is not supported by this PUBL */
+ stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
+
+/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
+ ddrphy_idone_wait(priv->phy);
+
+/* 12. set back registers in step 8 to the orginal values if desidered */
+ stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
+ config->c_reg.pwrctl);
+
+ /* enable uMCTL2 AXI port 0 and 1 */
+ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
+ setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
+}
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h
new file mode 100644
index 0000000..b77d823
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _RAM_STM32MP1_DDR_H
+#define _RAM_STM32MP1_DDR_H
+
+enum stm32mp1_ddr_interact_step {
+ STEP_DDR_RESET,
+ STEP_CTL_INIT,
+ STEP_PHY_INIT,
+ STEP_DDR_READY,
+ STEP_RUN,
+};
+
+/* DDR CTL and DDR PHY REGISTERS */
+struct stm32mp1_ddrctl;
+struct stm32mp1_ddrphy;
+
+/**
+ * struct ddr_info
+ *
+ * @dev: pointer for the device
+ * @info: UCLASS RAM information
+ * @ctl: DDR controleur base address
+ * @clk: DDR clock
+ * @phy: DDR PHY base address
+ * @rcc: rcc base address
+ */
+struct ddr_info {
+ struct udevice *dev;
+ struct ram_info info;
+ struct clk clk;
+ struct stm32mp1_ddrctl *ctl;
+ struct stm32mp1_ddrphy *phy;
+ u32 rcc;
+};
+
+struct stm32mp1_ddrctrl_reg {
+ u32 mstr;
+ u32 mrctrl0;
+ u32 mrctrl1;
+ u32 derateen;
+ u32 derateint;
+ u32 pwrctl;
+ u32 pwrtmg;
+ u32 hwlpctl;
+ u32 rfshctl0;
+ u32 rfshctl3;
+ u32 crcparctl0;
+ u32 zqctl0;
+ u32 dfitmg0;
+ u32 dfitmg1;
+ u32 dfilpcfg0;
+ u32 dfiupd0;
+ u32 dfiupd1;
+ u32 dfiupd2;
+ u32 dfiphymstr;
+ u32 odtmap;
+ u32 dbg0;
+ u32 dbg1;
+ u32 dbgcmd;
+ u32 poisoncfg;
+ u32 pccfg;
+
+};
+
+struct stm32mp1_ddrctrl_timing {
+ u32 rfshtmg;
+ u32 dramtmg0;
+ u32 dramtmg1;
+ u32 dramtmg2;
+ u32 dramtmg3;
+ u32 dramtmg4;
+ u32 dramtmg5;
+ u32 dramtmg6;
+ u32 dramtmg7;
+ u32 dramtmg8;
+ u32 dramtmg14;
+ u32 odtcfg;
+};
+
+struct stm32mp1_ddrctrl_map {
+ u32 addrmap1;
+ u32 addrmap2;
+ u32 addrmap3;
+ u32 addrmap4;
+ u32 addrmap5;
+ u32 addrmap6;
+ u32 addrmap9;
+ u32 addrmap10;
+ u32 addrmap11;
+};
+
+struct stm32mp1_ddrctrl_perf {
+ u32 sched;
+ u32 sched1;
+ u32 perfhpr1;
+ u32 perflpr1;
+ u32 perfwr1;
+ u32 pcfgr_0;
+ u32 pcfgw_0;
+ u32 pcfgqos0_0;
+ u32 pcfgqos1_0;
+ u32 pcfgwqos0_0;
+ u32 pcfgwqos1_0;
+ u32 pcfgr_1;
+ u32 pcfgw_1;
+ u32 pcfgqos0_1;
+ u32 pcfgqos1_1;
+ u32 pcfgwqos0_1;
+ u32 pcfgwqos1_1;
+};
+
+struct stm32mp1_ddrphy_reg {
+ u32 pgcr;
+ u32 aciocr;
+ u32 dxccr;
+ u32 dsgcr;
+ u32 dcr;
+ u32 odtcr;
+ u32 zq0cr1;
+ u32 dx0gcr;
+ u32 dx1gcr;
+ u32 dx2gcr;
+ u32 dx3gcr;
+};
+
+struct stm32mp1_ddrphy_timing {
+ u32 ptr0;
+ u32 ptr1;
+ u32 ptr2;
+ u32 dtpr0;
+ u32 dtpr1;
+ u32 dtpr2;
+ u32 mr0;
+ u32 mr1;
+ u32 mr2;
+ u32 mr3;
+};
+
+struct stm32mp1_ddrphy_cal {
+ u32 dx0dllcr;
+ u32 dx0dqtr;
+ u32 dx0dqstr;
+ u32 dx1dllcr;
+ u32 dx1dqtr;
+ u32 dx1dqstr;
+ u32 dx2dllcr;
+ u32 dx2dqtr;
+ u32 dx2dqstr;
+ u32 dx3dllcr;
+ u32 dx3dqtr;
+ u32 dx3dqstr;
+};
+
+struct stm32mp1_ddr_info {
+ const char *name;
+ u16 speed; /* in MHZ */
+ u32 size; /* memory size in byte = col * row * width */
+};
+
+struct stm32mp1_ddr_config {
+ struct stm32mp1_ddr_info info;
+ struct stm32mp1_ddrctrl_reg c_reg;
+ struct stm32mp1_ddrctrl_timing c_timing;
+ struct stm32mp1_ddrctrl_map c_map;
+ struct stm32mp1_ddrctrl_perf c_perf;
+ struct stm32mp1_ddrphy_reg p_reg;
+ struct stm32mp1_ddrphy_timing p_timing;
+ struct stm32mp1_ddrphy_cal p_cal;
+};
+
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed);
+void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
+void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
+void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
+ u32 rfshctl3,
+ u32 pwrctl);
+
+void stm32mp1_ddr_init(
+ struct ddr_info *priv,
+ const struct stm32mp1_ddr_config *config);
+
+int stm32mp1_dump_reg(const struct ddr_info *priv,
+ const char *name);
+
+void stm32mp1_edit_reg(const struct ddr_info *priv,
+ char *name,
+ char *string);
+
+int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
+ const char *name);
+
+void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
+ char *name,
+ char *string);
+
+void stm32mp1_dump_info(
+ const struct ddr_info *priv,
+ const struct stm32mp1_ddr_config *config);
+
+bool stm32mp1_ddr_interactive(
+ void *priv,
+ enum stm32mp1_ddr_interact_step step,
+ const struct stm32mp1_ddr_config *config);
+
+#endif
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
new file mode 100644
index 0000000..82c254b
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _RAM_STM32MP1_DDR_REGS_H
+#define _RAM_STM32MP1_DDR_REGS_H
+
+/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
+struct stm32mp1_ddrctl {
+ u32 mstr ; /* 0x0 Master*/
+ u32 stat; /* 0x4 Operating Mode Status*/
+ u8 reserved008[0x10 - 0x8];
+ u32 mrctrl0; /* 0x10 Control 0.*/
+ u32 mrctrl1; /* 0x14 Control 1*/
+ u32 mrstat; /* 0x18 Status*/
+ u32 reserved01c; /* 0x1c */
+ u32 derateen; /* 0x20 Temperature Derate Enable*/
+ u32 derateint; /* 0x24 Temperature Derate Interval*/
+ u8 reserved028[0x30 - 0x28];
+ u32 pwrctl; /* 0x30 Low Power Control*/
+ u32 pwrtmg; /* 0x34 Low Power Timing*/
+ u32 hwlpctl; /* 0x38 Hardware Low Power Control*/
+ u8 reserved03c[0x50 - 0x3C];
+ u32 rfshctl0; /* 0x50 Refresh Control 0*/
+ u32 reserved054; /* 0x54 Refresh Control 1*/
+ u32 reserved058; /* 0x58 Refresh Control 2*/
+ u32 reserved05C;
+ u32 rfshctl3; /* 0x60 Refresh Control 0*/
+ u32 rfshtmg; /* 0x64 Refresh Timing*/
+ u8 reserved068[0xc0 - 0x68];
+ u32 crcparctl0; /* 0xc0 CRC Parity Control0*/
+ u32 reserved0c4; /* 0xc4 CRC Parity Control1*/
+ u32 reserved0c8; /* 0xc8 CRC Parity Control2*/
+ u32 crcparstat; /* 0xcc CRC Parity Status*/
+ u32 init0; /* 0xd0 SDRAM Initialization 0*/
+ u32 init1; /* 0xd4 SDRAM Initialization 1*/
+ u32 init2; /* 0xd8 SDRAM Initialization 2*/
+ u32 init3; /* 0xdc SDRAM Initialization 3*/
+ u32 init4; /* 0xe0 SDRAM Initialization 4*/
+ u32 init5; /* 0xe4 SDRAM Initialization 5*/
+ u32 reserved0e8;
+ u32 reserved0ec;
+ u32 dimmctl; /* 0xf0 DIMM Control*/
+ u8 reserved0f4[0x100 - 0xf4];
+ u32 dramtmg0; /* 0x100 SDRAM Timing 0*/
+ u32 dramtmg1; /* 0x104 SDRAM Timing 1*/
+ u32 dramtmg2; /* 0x108 SDRAM Timing 2*/
+ u32 dramtmg3; /* 0x10c SDRAM Timing 3*/
+ u32 dramtmg4; /* 0x110 SDRAM Timing 4*/
+ u32 dramtmg5; /* 0x114 SDRAM Timing 5*/
+ u32 dramtmg6; /* 0x118 SDRAM Timing 6*/
+ u32 dramtmg7; /* 0x11c SDRAM Timing 7*/
+ u32 dramtmg8; /* 0x120 SDRAM Timing 8*/
+ u8 reserved124[0x138 - 0x124];
+ u32 dramtmg14; /* 0x138 SDRAM Timing 14*/
+ u32 dramtmg15; /* 0x13C SDRAM Timing 15*/
+ u8 reserved140[0x180 - 0x140];
+ u32 zqctl0; /* 0x180 ZQ Control 0*/
+ u32 zqctl1; /* 0x184 ZQ Control 1*/
+ u32 zqctl2; /* 0x188 ZQ Control 2*/
+ u32 zqstat; /* 0x18c ZQ Status*/
+ u32 dfitmg0; /* 0x190 DFI Timing 0*/
+ u32 dfitmg1; /* 0x194 DFI Timing 1*/
+ u32 dfilpcfg0; /* 0x198 DFI Low Power Configuration 0*/
+ u32 reserved19c;
+ u32 dfiupd0; /* 0x1a0 DFI Update 0*/
+ u32 dfiupd1; /* 0x1a4 DFI Update 1*/
+ u32 dfiupd2; /* 0x1a8 DFI Update 2*/
+ u32 reserved1ac;
+ u32 dfimisc; /* 0x1b0 DFI Miscellaneous Control*/
+ u8 reserved1b4[0x1bc - 0x1b4];
+ u32 dfistat; /* 0x1bc DFI Miscellaneous Control*/
+ u8 reserved1c0[0x1c4 - 0x1c0];
+ u32 dfiphymstr; /* 0x1c4 DFI PHY Master interface*/
+ u8 reserved1c8[0x204 - 0x1c8];
+ u32 addrmap1; /* 0x204 Address Map 1*/
+ u32 addrmap2; /* 0x208 Address Map 2*/
+ u32 addrmap3; /* 0x20c Address Map 3*/
+ u32 addrmap4; /* 0x210 Address Map 4*/
+ u32 addrmap5; /* 0x214 Address Map 5*/
+ u32 addrmap6; /* 0x218 Address Map 6*/
+ u8 reserved21c[0x224 - 0x21c];
+ u32 addrmap9; /* 0x224 Address Map 9*/
+ u32 addrmap10; /* 0x228 Address Map 10*/
+ u32 addrmap11; /* 0x22C Address Map 11*/
+ u8 reserved230[0x240 - 0x230];
+ u32 odtcfg; /* 0x240 ODT Configuration*/
+ u32 odtmap; /* 0x244 ODT/Rank Map*/
+ u8 reserved248[0x250 - 0x248];
+ u32 sched; /* 0x250 Scheduler Control*/
+ u32 sched1; /* 0x254 Scheduler Control 1*/
+ u32 reserved258;
+ u32 perfhpr1; /* 0x25c High Priority Read CAM 1*/
+ u32 reserved260;
+ u32 perflpr1; /* 0x264 Low Priority Read CAM 1*/
+ u32 reserved268;
+ u32 perfwr1; /* 0x26c Write CAM 1*/
+ u8 reserved27c[0x300 - 0x270];
+ u32 dbg0; /* 0x300 Debug 0*/
+ u32 dbg1; /* 0x304 Debug 1*/
+ u32 dbgcam; /* 0x308 CAM Debug*/
+ u32 dbgcmd; /* 0x30c Command Debug*/
+ u32 dbgstat; /* 0x310 Status Debug*/
+ u8 reserved314[0x320 - 0x314];
+ u32 swctl; /* 0x320 Software Programming Control Enable*/
+ u32 swstat; /* 0x324 Software Programming Control Status*/
+ u8 reserved328[0x36c - 0x328];
+ u32 poisoncfg; /* 0x36c AXI Poison Configuration Register*/
+ u32 poisonstat; /* 0x370 AXI Poison Status Register*/
+ u8 reserved374[0x3fc - 0x374];
+
+ /* Multi Port registers */
+ u32 pstat; /* 0x3fc Port Status*/
+ u32 pccfg; /* 0x400 Port Common Configuration*/
+
+ /* PORT 0 */
+ u32 pcfgr_0; /* 0x404 Configuration Read*/
+ u32 pcfgw_0; /* 0x408 Configuration Write*/
+ u8 reserved40c[0x490 - 0x40c];
+ u32 pctrl_0; /* 0x490 Port Control Register */
+ u32 pcfgqos0_0; /* 0x494 Read QoS Configuration 0*/
+ u32 pcfgqos1_0; /* 0x498 Read QoS Configuration 1*/
+ u32 pcfgwqos0_0; /* 0x49c Write QoS Configuration 0*/
+ u32 pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1*/
+ u8 reserved4a4[0x4b4 - 0x4a4];
+
+ /* PORT 1 */
+ u32 pcfgr_1; /* 0x4b4 Configuration Read*/
+ u32 pcfgw_1; /* 0x4b8 Configuration Write*/
+ u8 reserved4bc[0x540 - 0x4bc];
+ u32 pctrl_1; /* 0x540 Port 2 Control Register */
+ u32 pcfgqos0_1; /* 0x544 Read QoS Configuration 0*/
+ u32 pcfgqos1_1; /* 0x548 Read QoS Configuration 1*/
+ u32 pcfgwqos0_1; /* 0x54c Write QoS Configuration 0*/
+ u32 pcfgwqos1_1; /* 0x550 Write QoS Configuration 1*/
+};
+
+/* DDR Physical Interface Control (DDRPHYC) registers*/
+struct stm32mp1_ddrphy {
+ u32 ridr; /* 0x00 R Revision Identification*/
+ u32 pir; /* 0x04 R/W PHY Initialization*/
+ u32 pgcr; /* 0x08 R/W PHY General Configuration*/
+ u32 pgsr; /* 0x0C PHY General Status*/
+ u32 dllgcr; /* 0x10 R/W DLL General Control*/
+ u32 acdllcr; /* 0x14 R/W AC DLL Control*/
+ u32 ptr0; /* 0x18 R/W PHY Timing 0*/
+ u32 ptr1; /* 0x1C R/W PHY Timing 1*/
+ u32 ptr2; /* 0x20 R/W PHY Timing 2*/
+ u32 aciocr; /* 0x24 AC I/O Configuration*/
+ u32 dxccr; /* 0x28 DATX8 Common Configuration*/
+ u32 dsgcr; /* 0x2C DDR System General Configuration*/
+ u32 dcr; /* 0x30 DRAM Configuration*/
+ u32 dtpr0; /* 0x34 DRAM Timing Parameters0*/
+ u32 dtpr1; /* 0x38 DRAM Timing Parameters1*/
+ u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/
+ u32 mr0; /* 0x40 Mode 0*/
+ u32 mr1; /* 0x44 Mode 1*/
+ u32 mr2; /* 0x48 Mode 2*/
+ u32 mr3; /* 0x4C Mode 3*/
+ u32 odtcr; /* 0x50 ODT Configuration*/
+ u32 dtar; /* 0x54 data training address*/
+ u32 dtdr0; /* 0x58 */
+ u32 dtdr1; /* 0x5c */
+ u8 res1[0x0c0 - 0x060]; /* 0x60 */
+ u32 dcuar; /* 0xc0 Address*/
+ u32 dcudr; /* 0xc4 DCU Data*/
+ u32 dcurr; /* 0xc8 DCU Run*/
+ u32 dculr; /* 0xcc DCU Loop*/
+ u32 dcugcr; /* 0xd0 DCU General Configuration*/
+ u32 dcutpr; /* 0xd4 DCU Timing Parameters */
+ u32 dcusr0; /* 0xd8 DCU Status 0*/
+ u32 dcusr1; /* 0xdc DCU Status 1*/
+ u8 res2[0x100 - 0xe0]; /* 0xe0 */
+ u32 bistrr; /* 0x100 BIST Run*/
+ u32 bistmskr0; /* 0x104 BIST Mask 0*/
+ u32 bistmskr1; /* 0x108 BIST Mask 0*/
+ u32 bistwcr; /* 0x10c BIST Word Count*/
+ u32 bistlsr; /* 0x110 BIST LFSR Seed*/
+ u32 bistar0; /* 0x114 BIST Address 0*/
+ u32 bistar1; /* 0x118 BIST Address 1*/
+ u32 bistar2; /* 0x11c BIST Address 2*/
+ u32 bistupdr; /* 0x120 BIST User Data Pattern*/
+ u32 bistgsr; /* 0x124 BIST General Status*/
+ u32 bistwer; /* 0x128 BIST Word Error*/
+ u32 bistber0; /* 0x12c BIST Bit Error 0*/
+ u32 bistber1; /* 0x130 BIST Bit Error 1*/
+ u32 bistber2; /* 0x134 BIST Bit Error 2*/
+ u32 bistwcsr; /* 0x138 BIST Word Count Status*/
+ u32 bistfwr0; /* 0x13c BIST Fail Word 0*/
+ u32 bistfwr1; /* 0x140 BIST Fail Word 1*/
+ u8 res3[0x178 - 0x144]; /* 0x144 */
+ u32 gpr0; /* 0x178 General Purpose 0 (GPR0)*/
+ u32 gpr1; /* 0x17C General Purpose 1 (GPR1)*/
+ u32 zq0cr0; /* 0x180 zq 0 control 0 */
+ u32 zq0cr1; /* 0x184 zq 0 control 1 */
+ u32 zq0sr0; /* 0x188 zq 0 status 0 */
+ u32 zq0sr1; /* 0x18C zq 0 status 1 */
+ u8 res4[0x1C0 - 0x190]; /* 0x190 */
+ u32 dx0gcr; /* 0x1c0 Byte lane 0 General Configuration*/
+ u32 dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0*/
+ u32 dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1*/
+ u32 dx0dllcr; /* 0x1cc Byte lane 0 DLL Control*/
+ u32 dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing*/
+ u32 dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing*/
+ u8 res5[0x200 - 0x1d8]; /* 0x1d8 */
+ u32 dx1gcr; /* 0x200 Byte lane 1 General Configuration*/
+ u32 dx1gsr0; /* 0x204 Byte lane 1 General Status 0*/
+ u32 dx1gsr1; /* 0x208 Byte lane 1 General Status 1*/
+ u32 dx1dllcr; /* 0x20c Byte lane 1 DLL Control*/
+ u32 dx1dqtr; /* 0x210 Byte lane 1 DQ Timing*/
+ u32 dx1dqstr; /* 0x214 Byte lane 1 QS Timing*/
+ u8 res6[0x240 - 0x218]; /* 0x218 */
+ u32 dx2gcr; /* 0x240 Byte lane 2 General Configuration*/
+ u32 dx2gsr0; /* 0x244 Byte lane 2 General Status 0*/
+ u32 dx2gsr1; /* 0x248 Byte lane 2 General Status 1*/
+ u32 dx2dllcr; /* 0x24c Byte lane 2 DLL Control*/
+ u32 dx2dqtr; /* 0x250 Byte lane 2 DQ Timing*/
+ u32 dx2dqstr; /* 0x254 Byte lane 2 QS Timing*/
+ u8 res7[0x280 - 0x258]; /* 0x258 */
+ u32 dx3gcr; /* 0x280 Byte lane 3 General Configuration*/
+ u32 dx3gsr0; /* 0x284 Byte lane 3 General Status 0*/
+ u32 dx3gsr1; /* 0x288 Byte lane 3 General Status 1*/
+ u32 dx3dllcr; /* 0x28c Byte lane 3 DLL Control*/
+ u32 dx3dqtr; /* 0x290 Byte lane 3 DQ Timing*/
+ u32 dx3dqstr; /* 0x294 Byte lane 3 QS Timing*/
+};
+
+#define DXN(phy, offset, byte) ((u32)(phy) + (offset) + ((u32)(byte) * 0x40))
+#define DXNGCR(phy, byte) DXN(phy, 0x1c0, byte)
+#define DXNDLLCR(phy, byte) DXN(phy, 0x1cc, byte)
+#define DXNDQTR(phy, byte) DXN(phy, 0x1d0, byte)
+#define DXNDQSTR(phy, byte) DXN(phy, 0x1d4, byte)
+
+/* DDRCTRL REGISTERS */
+#define DDRCTRL_MSTR_DDR3 BIT(0)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12)
+#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15)
+
+#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
+#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 1
+#define DDRCTRL_STAT_OPERATING_MODE_SR 3
+#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_ASR (3 << 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_SR (2 << 4)
+
+#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE 0
+/* only one rank supported */
+#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4
+#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
+ (0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
+#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12
+#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
+#define DDRCTRL_MRCTRL0_MR_WR BIT(31)
+
+#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0)
+
+#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
+#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
+
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
+
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
+
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000)
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL (BIT(30))
+
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
+
+#define DDRCTRL_DBG1_DIS_HIF BIT(1)
+
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
+#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
+ (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
+ DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
+#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
+ (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
+ DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
+ DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
+
+#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0)
+
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0)
+
+#define DDRCTRL_SWCTL_SW_DONE BIT(0)
+
+#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
+
+#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
+
+/* DDRPHYC registers */
+#define DDRPHYC_PIR_INIT BIT(0)
+#define DDRPHYC_PIR_DLLSRST BIT(1)
+#define DDRPHYC_PIR_DLLLOCK BIT(2)
+#define DDRPHYC_PIR_ZCAL BIT(3)
+#define DDRPHYC_PIR_ITMSRST BIT(4)
+#define DDRPHYC_PIR_DRAMRST BIT(5)
+#define DDRPHYC_PIR_DRAMINIT BIT(6)
+#define DDRPHYC_PIR_QSTRN BIT(7)
+#define DDRPHYC_PIR_ICPC BIT(16)
+#define DDRPHYC_PIR_ZCALBYP BIT(30)
+#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
+
+#define DDRPHYC_PGCR_DFTCMP BIT(2)
+#define DDRPHYC_PGCR_PDDISDX BIT(24)
+#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
+
+#define DDRPHYC_PGSR_IDONE BIT(0)
+#define DDRPHYC_PGSR_DTERR BIT(5)
+#define DDRPHYC_PGSR_DTIERR BIT(6)
+#define DDRPHYC_PGSR_DFTERR BIT(7)
+#define DDRPHYC_PGSR_RVERR BIT(8)
+#define DDRPHYC_PGSR_RVEIRR BIT(9)
+
+#define DDRPHYC_DLLGCR_BPS200 BIT(23)
+
+#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
+
+#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
+#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
+#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
+
+#define DDRPHYC_DXNGCR_DXEN BIT(0)
+
+#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
+#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
+#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
+
+#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit))
+#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2)
+
+#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20)
+#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20
+#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23)
+#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23
+#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0)
+#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0
+#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12)
+#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12
+
+#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19)
+#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19
+
+#define DDRPHYC_BISTGSR_BDDONE BIT(0)
+#define DDRPHYC_BISTGSR_BDXERR BIT(2)
+
+#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16
+
+/* PWR registers */
+#define PWR_CR3 0x00C
+#define PWR_CR3_DDRSRDIS BIT(11)
+#define PWR_CR3_DDRRETEN BIT(12)
+
+#endif
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
new file mode 100644
index 0000000..9599444
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include "stm32mp1_ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *const clkname[] = {
+ "ddrc1",
+ "ddrc2",
+ "ddrcapb",
+ "ddrphycapb",
+ "ddrphyc" /* LAST clock => used for get_rate() */
+};
+
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed)
+{
+ unsigned long ddrphy_clk;
+ unsigned long ddr_clk;
+ struct clk clk;
+ int ret;
+ int idx;
+
+ for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
+ ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
+
+ if (!ret)
+ ret = clk_enable(&clk);
+
+ if (ret) {
+ printf("error for %s : %d\n", clkname[idx], ret);
+ return ret;
+ }
+ }
+
+ priv->clk = clk;
+ ddrphy_clk = clk_get_rate(&priv->clk);
+
+ debug("DDR: mem_speed (%d MHz), RCC %d MHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+ /* max 10% frequency delta */
+ ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000);
+ if (ddr_clk > (mem_speed * 1000 * 100)) {
+ pr_err("DDR expected freq %d MHz, current is %d MHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+ int ret, idx;
+ struct clk axidcg;
+ struct stm32mp1_ddr_config config;
+
+#define PARAM(x, y) \
+ { x,\
+ offsetof(struct stm32mp1_ddr_config, y),\
+ sizeof(config.y) / sizeof(u32)}
+
+#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
+#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
+
+ const struct {
+ const char *name; /* name in DT */
+ const u32 offset; /* offset in config struct */
+ const u32 size; /* size of parameters */
+ } param[] = {
+ CTL_PARAM(reg),
+ CTL_PARAM(timing),
+ CTL_PARAM(map),
+ CTL_PARAM(perf),
+ PHY_PARAM(reg),
+ PHY_PARAM(timing),
+ PHY_PARAM(cal)
+ };
+
+ config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
+ config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+ config.info.name = dev_read_string(dev, "st,mem-name");
+ if (!config.info.name) {
+ debug("%s: no st,mem-name\n", __func__);
+ return -EINVAL;
+ }
+ printf("RAM: %s\n", config.info.name);
+
+ for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
+ ret = dev_read_u32_array(dev, param[idx].name,
+ (void *)((u32)&config +
+ param[idx].offset),
+ param[idx].size);
+ debug("%s: %s[0x%x] = %d\n", __func__,
+ param[idx].name, param[idx].size, ret);
+ if (ret) {
+ pr_err("%s: Cannot read %s\n",
+ __func__, param[idx].name);
+ return -EINVAL;
+ }
+ }
+
+ ret = clk_get_by_name(dev, "axidcg", &axidcg);
+ if (ret) {
+ debug("%s: Cannot found axidcg\n", __func__);
+ return -EINVAL;
+ }
+ clk_disable(&axidcg); /* disable clock gating during init */
+
+ stm32mp1_ddr_init(priv, &config);
+
+ clk_enable(&axidcg); /* enable clock gating */
+
+ /* check size */
+ debug("%s : get_ram_size(%x, %x)\n", __func__,
+ (u32)priv->info.base, (u32)STM32_DDR_SIZE);
+
+ priv->info.size = get_ram_size((long *)priv->info.base,
+ STM32_DDR_SIZE);
+
+ debug("%s : %x\n", __func__, (u32)priv->info.size);
+
+ /* check memory access for all memory */
+ if (config.info.size != priv->info.size) {
+ printf("DDR invalid size : 0x%x, expected 0x%x\n",
+ priv->info.size, config.info.size);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int stm32mp1_ddr_probe(struct udevice *dev)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+ struct regmap *map;
+ int ret;
+
+ debug("STM32MP1 DDR probe\n");
+ priv->dev = dev;
+
+ ret = regmap_init_mem(dev, &map);
+ if (ret)
+ return ret;
+
+ priv->ctl = regmap_get_range(map, 0);
+ priv->phy = regmap_get_range(map, 1);
+
+ priv->rcc = STM32_RCC_BASE;
+
+ priv->info.base = STM32_DDR_BASE;
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ priv->info.size = 0;
+ return stm32mp1_ddr_setup(dev);
+#else
+ priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+ return 0;
+#endif
+}
+
+static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops stm32mp1_ddr_ops = {
+ .get_info = stm32mp1_ddr_get_info,
+};
+
+static const struct udevice_id stm32mp1_ddr_ids[] = {
+ { .compatible = "st,stm32mp1-ddr" },
+ { }
+};
+
+U_BOOT_DRIVER(ddr_stm32mp1) = {
+ .name = "stm32mp1_ddr",
+ .id = UCLASS_RAM,
+ .of_match = stm32mp1_ddr_ids,
+ .ops = &stm32mp1_ddr_ops,
+ .probe = stm32mp1_ddr_probe,
+ .priv_auto_alloc_size = sizeof(struct ddr_info),
+};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3964b9e..ccfdac7 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -30,7 +30,7 @@
config STM32_RESET
bool "Enable the STM32 reset"
- depends on STM32
+ depends on STM32 || ARCH_STM32MP
help
Support for reset controllers on STMicroelectronics STM32 family SoCs.
This resset driver is compatible with STM32 F4/F7 and H7 SoCs.
@@ -83,4 +83,12 @@
though is that some reset signals, like I2C or MISC reset multiple
devices.
+config RESET_MESON
+ bool "Reset controller driver for Amlogic Meson SoCs"
+ depends on DM_RESET && ARCH_MESON
+ imply REGMAP
+ default y
+ help
+ Support for reset controller on Amlogic Meson SoC.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 7d7e080..d1d5146 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -13,3 +13,4 @@
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
+obj-$(CONFIG_RESET_MESON) += reset-meson.o
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
new file mode 100644
index 0000000..5324f86
--- /dev/null
+++ b/drivers/reset/reset-meson.c
@@ -0,0 +1,90 @@
+/*
+ * Amlogic Meson Reset Controller driver
+ *
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <regmap.h>
+
+#define REG_COUNT 8
+#define BITS_PER_REG 32
+#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_priv {
+ struct regmap *regmap;
+};
+
+static int meson_reset_request(struct reset_ctl *reset_ctl)
+{
+ if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int meson_reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert)
+{
+ struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ uint bank = reset_ctl->id / BITS_PER_REG;
+ uint offset = reset_ctl->id % BITS_PER_REG;
+ uint reg_offset = LEVEL_OFFSET + (bank << 2);
+ uint val;
+
+ regmap_read(priv->regmap, reg_offset, &val);
+ if (assert)
+ val &= ~BIT(offset);
+ else
+ val |= BIT(offset);
+ regmap_write(priv->regmap, reg_offset, val);
+
+ return 0;
+}
+
+static int meson_reset_assert(struct reset_ctl *reset_ctl)
+{
+ return meson_reset_level(reset_ctl, true);
+}
+
+static int meson_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return meson_reset_level(reset_ctl, false);
+}
+
+struct reset_ops meson_reset_ops = {
+ .request = meson_reset_request,
+ .free = meson_reset_free,
+ .rst_assert = meson_reset_assert,
+ .rst_deassert = meson_reset_deassert,
+};
+
+static const struct udevice_id meson_reset_ids[] = {
+ { .compatible = "amlogic,meson-gxbb-reset" },
+ { }
+};
+
+static int meson_reset_probe(struct udevice *dev)
+{
+ struct meson_reset_priv *priv = dev_get_priv(dev);
+
+ return regmap_init_mem(dev, &priv->regmap);
+}
+
+U_BOOT_DRIVER(meson_reset) = {
+ .name = "meson_reset",
+ .id = UCLASS_RESET,
+ .of_match = meson_reset_ids,
+ .probe = meson_reset_probe,
+ .ops = &meson_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct meson_reset_priv),
+};
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 307a297..9a5c9c9 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -81,6 +81,40 @@
return 0;
}
+int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
+{
+ int i, ret, err, count;
+
+ bulk->count = 0;
+
+ count = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
+ if (!count)
+ return 0;
+
+ bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl),
+ GFP_KERNEL);
+ if (!bulk->resets)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ ret = reset_get_by_index(dev, i, &bulk->resets[i]);
+ if (ret < 0)
+ goto bulk_get_err;
+
+ ++bulk->count;
+ }
+
+ return 0;
+
+bulk_get_err:
+ err = reset_release_all(bulk->resets, bulk->count);
+ if (err)
+ debug("%s: could release all resets for %p\n",
+ __func__, dev);
+
+ return ret;
+}
+
int reset_get_by_name(struct udevice *dev, const char *name,
struct reset_ctl *reset_ctl)
{
@@ -126,6 +160,19 @@
return ops->rst_assert(reset_ctl);
}
+int reset_assert_bulk(struct reset_ctl_bulk *bulk)
+{
+ int i, ret;
+
+ for (i = 0; i < bulk->count; i++) {
+ ret = reset_assert(&bulk->resets[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
int reset_deassert(struct reset_ctl *reset_ctl)
{
struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
@@ -135,6 +182,19 @@
return ops->rst_deassert(reset_ctl);
}
+int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
+{
+ int i, ret;
+
+ for (i = 0; i < bulk->count; i++) {
+ ret = reset_deassert(&bulk->resets[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
int reset_release_all(struct reset_ctl *reset_ctl, int count)
{
int i, ret;
diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c
index e37d6c9..f0ceaa0 100644
--- a/drivers/reset/sandbox-reset-test.c
+++ b/drivers/reset/sandbox-reset-test.c
@@ -12,6 +12,7 @@
struct sandbox_reset_test {
struct reset_ctl ctl;
+ struct reset_ctl_bulk bulk;
};
int sandbox_reset_test_get(struct udevice *dev)
@@ -21,6 +22,13 @@
return reset_get_by_name(dev, "test", &sbrt->ctl);
}
+int sandbox_reset_test_get_bulk(struct udevice *dev)
+{
+ struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+ return reset_get_bulk(dev, &sbrt->bulk);
+}
+
int sandbox_reset_test_assert(struct udevice *dev)
{
struct sandbox_reset_test *sbrt = dev_get_priv(dev);
@@ -28,6 +36,13 @@
return reset_assert(&sbrt->ctl);
}
+int sandbox_reset_test_assert_bulk(struct udevice *dev)
+{
+ struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+ return reset_assert_bulk(&sbrt->bulk);
+}
+
int sandbox_reset_test_deassert(struct udevice *dev)
{
struct sandbox_reset_test *sbrt = dev_get_priv(dev);
@@ -35,6 +50,13 @@
return reset_deassert(&sbrt->ctl);
}
+int sandbox_reset_test_deassert_bulk(struct udevice *dev)
+{
+ struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+ return reset_deassert_bulk(&sbrt->bulk);
+}
+
int sandbox_reset_test_free(struct udevice *dev)
{
struct sandbox_reset_test *sbrt = dev_get_priv(dev);
@@ -42,6 +64,13 @@
return reset_free(&sbrt->ctl);
}
+int sandbox_reset_test_release_bulk(struct udevice *dev)
+{
+ struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+ return reset_release_bulk(&sbrt->bulk);
+}
+
static const struct udevice_id sandbox_reset_test_ids[] = {
{ .compatible = "sandbox,reset-ctl-test" },
{ }
diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c
index 4258af5..c310749 100644
--- a/drivers/reset/sandbox-reset.c
+++ b/drivers/reset/sandbox-reset.c
@@ -10,7 +10,7 @@
#include <asm/io.h>
#include <asm/reset.h>
-#define SANDBOX_RESET_SIGNALS 3
+#define SANDBOX_RESET_SIGNALS 101
struct sandbox_reset_signal {
bool asserted;
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index b266f46..e98f34b 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -11,7 +11,13 @@
#include <reset-uclass.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
+/* reset clear offset for STM32MP RCC */
+#define RCC_CL 0x4
+
+enum rcc_type {
+ RCC_STM32 = 0,
+ RCC_STM32MP,
+};
struct stm32_reset_priv {
fdt_addr_t base;
@@ -35,7 +41,11 @@
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
- setbits_le32(priv->base + bank, BIT(offset));
+ if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+ /* reset assert is done in rcc set register */
+ writel(BIT(offset), priv->base + bank);
+ else
+ setbits_le32(priv->base + bank, BIT(offset));
return 0;
}
@@ -48,7 +58,11 @@
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
- clrbits_le32(priv->base + bank, BIT(offset));
+ if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+ /* reset deassert is done in rcc clr register */
+ writel(BIT(offset), priv->base + bank + RCC_CL);
+ else
+ clrbits_le32(priv->base + bank, BIT(offset));
return 0;
}
@@ -64,16 +78,26 @@
{
struct stm32_reset_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
- if (priv->base == FDT_ADDR_T_NONE)
- return -EINVAL;
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE) {
+ /* for MFD, get address of parent */
+ priv->base = dev_read_addr(dev->parent);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ }
return 0;
}
+static const struct udevice_id stm32_reset_ids[] = {
+ { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
+ { }
+};
+
U_BOOT_DRIVER(stm32_rcc_reset) = {
.name = "stm32_rcc_reset",
.id = UCLASS_RESET,
+ .of_match = stm32_reset_ids,
.probe = stm32_reset_probe,
.priv_auto_alloc_size = sizeof(struct stm32_reset_priv),
.ops = &stm32_reset_ops,
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 95ac031..277dc3d 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -30,6 +30,18 @@
Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and
compatible Real Time Clock devices.
+config RTC_ISL1208
+ bool "Enable ISL1208 driver"
+ depends on DM_RTC
+ help
+ The Renesas (formerly Intersil) ISL1208 is a I2C Real Time Clock (RTC) and
+ calendar with automatic leap year correction, 2-byte battery backed SRAM,
+ automatic power switch-over, alarm function and 15 selectable frequency
+ outputs.
+
+ This driver supports reading and writing the RTC/calendar and detects
+ total power failures.
+
config RTC_RX8010SJ
bool "Enable RX8010SJ driver"
depends on DM_RTC
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 5df15c7..5e74b93 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -184,25 +184,8 @@
*/
void rtc_reset (void)
{
- struct rtc_time tmp;
-
rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
-
- tmp.tm_year = 1970;
- tmp.tm_mon = 1;
- tmp.tm_mday= 1;
- tmp.tm_hour = 0;
- tmp.tm_min = 0;
- tmp.tm_sec = 0;
-
- rtc_set(&tmp);
-
- printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
- tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
-
- return;
}
@@ -321,14 +304,6 @@
static int ds1307_rtc_reset(struct udevice *dev)
{
int ret;
- struct rtc_time tmp = {
- .tm_year = 1970,
- .tm_mon = 1,
- .tm_mday = 1,
- .tm_hour = 0,
- .tm_min = 0,
- .tm_sec = 0,
- };
/* clear Clock Halt */
ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
@@ -340,14 +315,6 @@
if (ret < 0)
return ret;
- ret = ds1307_rtc_set(dev, &tmp);
- if (ret < 0)
- return ret;
-
- debug("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
- tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
-
return 0;
}
diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c
index 7847357..9e440d8 100644
--- a/drivers/rtc/ds1374.c
+++ b/drivers/rtc/ds1374.c
@@ -172,8 +172,6 @@
*/
void rtc_reset (void){
- struct rtc_time tmp;
-
/* clear status flags */
rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
@@ -189,19 +187,6 @@
|RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
set BBSQW and SQW to 32k
- set to 1 */
- tmp.tm_year = 1970;
- tmp.tm_mon = 1;
- tmp.tm_mday= 1;
- tmp.tm_hour = 0;
- tmp.tm_min = 0;
- tmp.tm_sec = 0;
-
- rtc_set(&tmp);
-
- printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
- tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
-
rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c
index 807e2e4..fa1178a 100644
--- a/drivers/rtc/isl1208.c
+++ b/drivers/rtc/isl1208.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <rtc.h>
#include <i2c.h>
@@ -51,45 +52,38 @@
#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
-static uchar rtc_read (uchar reg);
-static void rtc_write (uchar reg, uchar val);
-
/*
* Get the current time from the RTC
*/
-int rtc_get (struct rtc_time *tmp)
+static int isl1208_rtc_get(struct udevice *dev, struct rtc_time *tmp)
{
- int rel = 0;
- uchar sec, min, hour, mday, wday, mon, year, status;
+ int ret;
+ uchar buf[8], val;
- status = rtc_read (RTC_STAT_REG_ADDR);
- sec = rtc_read (RTC_SEC_REG_ADDR);
- min = rtc_read (RTC_MIN_REG_ADDR);
- hour = rtc_read (RTC_HR_REG_ADDR);
- wday = rtc_read (RTC_DAY_REG_ADDR);
- mday = rtc_read (RTC_DATE_REG_ADDR);
- mon = rtc_read (RTC_MON_REG_ADDR);
- year = rtc_read (RTC_YR_REG_ADDR);
+ ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
- DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
- "hr: %02x min: %02x sec: %02x status: %02x\n",
- year, mon, mday, wday, hour, min, sec, status);
-
- if (status & RTC_STAT_BIT_RTCF) {
+ if (buf[RTC_STAT_REG_ADDR] & RTC_STAT_BIT_RTCF) {
printf ("### Warning: RTC oscillator has stopped\n");
- rtc_write(RTC_STAT_REG_ADDR,
- rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF));
- rel = -1;
+ ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
+ if (ret < 0)
+ return ret;
+
+ val = val & ~(RTC_STAT_BIT_BAT | RTC_STAT_BIT_RTCF);
+ ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
+ if (ret < 0)
+ return ret;
}
- tmp->tm_sec = bcd2bin (sec & 0x7F);
- tmp->tm_min = bcd2bin (min & 0x7F);
- tmp->tm_hour = bcd2bin (hour & 0x3F);
- tmp->tm_mday = bcd2bin (mday & 0x3F);
- tmp->tm_mon = bcd2bin (mon & 0x1F);
- tmp->tm_year = bcd2bin (year)+2000;
- tmp->tm_wday = bcd2bin (wday & 0x07);
+ tmp->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
+ tmp->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
+ tmp->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
+ tmp->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
+ tmp->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
+ tmp->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) + 2000;
+ tmp->tm_wday = bcd2bin(buf[RTC_DAY_REG_ADDR] & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
@@ -97,51 +91,88 @@
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
- return rel;
+ return 0;
}
/*
* Set the RTC
*/
-int rtc_set (struct rtc_time *tmp)
+static int isl1208_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
{
+ int ret;
+ uchar val, buf[7];
+
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
- /* enable write */
- rtc_write(RTC_STAT_REG_ADDR,
- rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC);
+ if (tmp->tm_year < 2000 || tmp->tm_year > 2099)
+ printf("WARNING: year should be between 2000 and 2099!\n");
- rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
- rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
- rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
- rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
- rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */
- rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
- rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+ /* enable write */
+ ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
+ if (ret < 0)
+ return ret;
+
+ val = val | RTC_STAT_BIT_WRTC;
+
+ ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
+ if (ret < 0)
+ return ret;
+
+ buf[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100);
+ buf[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon);
+ buf[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday);
+ buf[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday);
+ buf[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour) | 0x80; /* 24h clock */
+ buf[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min);
+ buf[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec);
+
+ ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
/* disable write */
- rtc_write(RTC_STAT_REG_ADDR,
- rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC);
+ ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
+ if (ret < 0)
+ return ret;
+
+ val = val & ~RTC_STAT_BIT_WRTC;
+ ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
+ if (ret < 0)
+ return ret;
return 0;
}
-void rtc_reset (void)
+static int isl1208_rtc_reset(struct udevice *dev)
{
+ return 0;
}
-/*
- * Helper functions
- */
-
-static uchar rtc_read (uchar reg)
+static int isl1208_probe(struct udevice *dev)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
+ DM_I2C_CHIP_WR_ADDRESS);
+
+ return 0;
}
-static void rtc_write (uchar reg, uchar val)
-{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
-}
+static const struct rtc_ops isl1208_rtc_ops = {
+ .get = isl1208_rtc_get,
+ .set = isl1208_rtc_set,
+ .reset = isl1208_rtc_reset,
+};
+
+static const struct udevice_id isl1208_rtc_ids[] = {
+ { .compatible = "isil,isl1208" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_isl1208) = {
+ .name = "rtc-isl1208",
+ .id = UCLASS_RTC,
+ .probe = isl1208_probe,
+ .of_match = isl1208_rtc_ids,
+ .ops = &isl1208_rtc_ops,
+};
diff --git a/drivers/rtc/mx27rtc.c b/drivers/rtc/mx27rtc.c
index 29ccdf1..b42770e 100644
--- a/drivers/rtc/mx27rtc.c
+++ b/drivers/rtc/mx27rtc.c
@@ -61,9 +61,5 @@
void rtc_reset(void)
{
- struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE;
-
- writel(0, &rtc_regs->dayr);
- writel(0, &rtc_regs->hourmin);
- writel(0, &rtc_regs->seconds);
+ /* nothing to do */
}
diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c
index 65f45ea..c815c91 100644
--- a/drivers/rtc/rs5c372.c
+++ b/drivers/rtc/rs5c372.c
@@ -247,35 +247,13 @@
}
/*
- * Reset the RTC. We set the date back to 1970-01-01.
+ * Reset the RTC.
*/
void
rtc_reset (void)
{
- struct rtc_time tmp;
-
if (!setup_done)
rs5c372_enable();
-
- if (!setup_done)
- return;
-
- tmp.tm_year = 1970;
- tmp.tm_mon = 1;
- /* Jan. 1, 1970 was a Thursday */
- tmp.tm_wday= 4;
- tmp.tm_mday= 1;
- tmp.tm_hour = 0;
- tmp.tm_min = 0;
- tmp.tm_sec = 0;
-
- rtc_set(&tmp);
-
- printf ("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
- tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
-
- return;
}
#endif
diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
index b4a149b..c43966a 100644
--- a/drivers/rtc/rx8025.c
+++ b/drivers/rtc/rx8025.c
@@ -163,11 +163,10 @@
}
/*
- * Reset the RTC. We setting the date back to 1970-01-01.
+ * Reset the RTC
*/
void rtc_reset (void)
{
- struct rtc_time tmp;
uchar buf[16];
uchar ctl2;
@@ -178,21 +177,6 @@
ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
rtc_write (RTC_CTL2_REG_ADDR, ctl2);
-
- tmp.tm_year = 1970;
- tmp.tm_mon = 1;
- tmp.tm_mday= 1;
- tmp.tm_hour = 0;
- tmp.tm_min = 0;
- tmp.tm_sec = 0;
-
- rtc_set(&tmp);
-
- printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
- tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
-
- return;
}
/*
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 93e602e..3d5b2bf 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -24,6 +24,15 @@
during serial port initialization (default y). Set this to n on
boards which have no debug serial port whatsoever.
+config SPECIFY_CONSOLE_INDEX
+ bool "Specify the port number used for console"
+ default y if !DM_SERIAL || (SPL && !SPL_DM_SERIAL) || \
+ (TPL && !TPL_DM_SERIAL)
+ help
+ In various cases, we need to specify which of the UART devices that
+ a board or SoC has available are to be used for the console device
+ in U-Boot.
+
config SERIAL_PRESENT
bool "Provide a serial driver"
depends on DM_SERIAL
@@ -44,16 +53,39 @@
This option enables the full UART in SPL, so if is it disabled,
the full UART driver will be omitted, thus saving space.
+# Logic to allow us to use the imply keyword to set what the default port
+# should be. The default is otherwise 1.
+config CONS_INDEX_0
+ bool
+
+config CONS_INDEX_2
+ bool
+
+config CONS_INDEX_3
+ bool
+
+config CONS_INDEX_4
+ bool
+
+config CONS_INDEX_5
+ bool
+
+config CONS_INDEX_6
+ bool
+
config CONS_INDEX
int "UART used for console"
- depends on ARCH_SUNXI
- default 2 if MACH_SUN5I
- default 5 if MACH_SUN8I_A23 || MACH_SUN8I_A33
+ depends on SPECIFY_CONSOLE_INDEX
+ range 0 6
+ default 0 if CONS_INDEX_0
+ default 2 if CONS_INDEX_2
+ default 3 if CONS_INDEX_3
+ default 4 if CONS_INDEX_4
+ default 5 if CONS_INDEX_5
+ default 6 if CONS_INDEX_6
default 1
help
- Configures the console index.
- For Allwinner SoC., default values are 2 for SUN5I and 5 for A23/A33.
- Otherwise, the index equals 1.
+ Set this to match the UART number of the serial console.
config DM_SERIAL
bool "Enable Driver Model for serial drivers"
@@ -93,8 +125,8 @@
config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
- depends on DM_SERIAL
- default y if SPL && DM_SERIAL
+ depends on DM_SERIAL && SPL_DM
+ default y
help
Enable driver model for serial in SPL. This replaces
drivers/serial/serial.c with the serial uclass, which
@@ -577,10 +609,10 @@
config STM32_SERIAL
bool "STMicroelectronics STM32 SoCs on-chip UART"
- depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
+ depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7 || ARCH_STM32MP)
help
- If you have a machine based on a STM32 F4, F7 or H7 SoC you can
- enable its onboard serial ports, say Y to this option.
+ If you have a machine based on a STM32 F4, F7, H7 or MP1 SOC
+ you can enable its onboard serial ports, say Y to this option.
If unsure, say N.
config ZYNQ_SERIAL
@@ -592,7 +624,7 @@
config MPC8XX_CONS
bool "Console driver for MPC8XX"
- depends on 8xx
+ depends on MPC8xx
default y
choice
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index cac9a8b..6937ef9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -5,11 +5,27 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_DM_SERIAL
-obj-$(CONFIG_$(SPL_TPL_)DM_SERIAL) += serial-uclass.o
-obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
+ifdef CONFIG_SPL_BUILD
+
+ifeq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)DM_SERIAL),yy)
+obj-y += serial-uclass.o
else
obj-y += serial.o
+endif
+
+else
+
+ifdef CONFIG_DM_SERIAL
+obj-y += serial-uclass.o
+else
+obj-y += serial.o
+endif
+
+endif
+
+ifdef CONFIG_DM_SERIAL
+obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
+else
obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index cc4bdcb..397c6f5 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -109,48 +109,16 @@
void name(void) \
__attribute__((weak, alias("serial_null")));
-serial_initfunc(amirix_serial_initialize);
-serial_initfunc(arc_serial_initialize);
-serial_initfunc(arm_dcc_initialize);
-serial_initfunc(asc_serial_initialize);
serial_initfunc(atmel_serial_initialize);
serial_initfunc(au1x00_serial_initialize);
-serial_initfunc(bfin_jtag_initialize);
-serial_initfunc(bfin_serial_initialize);
-serial_initfunc(bmw_serial_initialize);
-serial_initfunc(clps7111_serial_initialize);
-serial_initfunc(cogent_serial_initialize);
-serial_initfunc(cpci750_serial_initialize);
-serial_initfunc(evb64260_serial_initialize);
-serial_initfunc(imx_serial_initialize);
-serial_initfunc(iop480_serial_initialize);
-serial_initfunc(jz_serial_initialize);
-serial_initfunc(leon2_serial_initialize);
-serial_initfunc(leon3_serial_initialize);
-serial_initfunc(lh7a40x_serial_initialize);
-serial_initfunc(lpc32xx_serial_initialize);
-serial_initfunc(marvell_serial_initialize);
-serial_initfunc(max3100_serial_initialize);
serial_initfunc(mcf_serial_initialize);
-serial_initfunc(ml2_serial_initialize);
serial_initfunc(mpc85xx_serial_initialize);
serial_initfunc(mpc8xx_serial_initialize);
serial_initfunc(mxc_serial_initialize);
-serial_initfunc(mxs_auart_initialize);
serial_initfunc(ns16550_serial_initialize);
-serial_initfunc(oc_serial_initialize);
-serial_initfunc(p3mx_serial_initialize);
serial_initfunc(pl01x_serial_initialize);
serial_initfunc(pxa_serial_initialize);
-serial_initfunc(s3c24xx_serial_initialize);
-serial_initfunc(s5p_serial_initialize);
-serial_initfunc(sa1100_serial_initialize);
-serial_initfunc(sandbox_serial_initialize);
-serial_initfunc(sconsole_serial_initialize);
serial_initfunc(sh_serial_initialize);
-serial_initfunc(stm32_serial_initialize);
-serial_initfunc(uartlite_serial_initialize);
-serial_initfunc(zynq_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
@@ -196,48 +164,16 @@
*/
void serial_initialize(void)
{
- amirix_serial_initialize();
- arc_serial_initialize();
- arm_dcc_initialize();
- asc_serial_initialize();
atmel_serial_initialize();
au1x00_serial_initialize();
- bfin_jtag_initialize();
- bfin_serial_initialize();
- bmw_serial_initialize();
- clps7111_serial_initialize();
- cogent_serial_initialize();
- cpci750_serial_initialize();
- evb64260_serial_initialize();
- imx_serial_initialize();
- iop480_serial_initialize();
- jz_serial_initialize();
- leon2_serial_initialize();
- leon3_serial_initialize();
- lh7a40x_serial_initialize();
- lpc32xx_serial_initialize();
- marvell_serial_initialize();
- max3100_serial_initialize();
mcf_serial_initialize();
- ml2_serial_initialize();
mpc85xx_serial_initialize();
mpc8xx_serial_initialize();
mxc_serial_initialize();
- mxs_auart_initialize();
ns16550_serial_initialize();
- oc_serial_initialize();
- p3mx_serial_initialize();
pl01x_serial_initialize();
pxa_serial_initialize();
- s3c24xx_serial_initialize();
- s5p_serial_initialize();
- sa1100_serial_initialize();
- sandbox_serial_initialize();
- sconsole_serial_initialize();
sh_serial_initialize();
- stm32_serial_initialize();
- uartlite_serial_initialize();
- zynq_serial_initialize();
serial_assign(default_serial_console()->name);
}
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
index 363affb..6412ca6 100644
--- a/drivers/serial/serial_meson.c
+++ b/drivers/serial/serial_meson.c
@@ -125,6 +125,7 @@
static const struct udevice_id meson_serial_ids[] = {
{ .compatible = "amlogic,meson-uart" },
+ { .compatible = "amlogic,meson-gx-uart" },
{ }
};
diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c
index 26a8085..7a5908f 100644
--- a/drivers/serial/serial_mpc8xx.c
+++ b/drivers/serial/serial_mpc8xx.c
@@ -6,10 +6,10 @@
*/
#include <common.h>
-#include <commproc.h>
#include <command.h>
#include <serial.h>
#include <watchdog.h>
+#include <asm/cpm_8xx.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index a17698f..5f4ace7 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -270,6 +270,8 @@
# define SCIF_BASE SCIF6_BASE
#elif defined(CONFIG_CONS_SCIF7)
# define SCIF_BASE SCIF7_BASE
+#elif defined(CONFIG_CONS_SCIFA0)
+# define SCIF_BASE SCIFA0_BASE
#else
# error "Default SCIF doesn't set....."
#endif
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 235a8c7..ec92b84 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -23,6 +23,13 @@
IP core. Please find details on the "Embedded Peripherals IP
User Guide" of Altera.
+config ATCSPI200_SPI
+ bool "Andestech ATCSPI200 SPI driver"
+ help
+ Enable the Andestech ATCSPI200 SPI driver. This driver can be
+ used to access the SPI flash on AE3XX and AE250 platforms embedding
+ this Andestech IP core.
+
config ATH79_SPI
bool "Atheros SPI driver"
depends on ARCH_ATH79
@@ -34,7 +41,7 @@
config ATMEL_SPI
bool "Atmel SPI driver"
- depends on ARCH_AT91
+ default y if ARCH_AT91
help
This enables driver for the Atmel SPI Controller, present on
many AT91 (ARM) chips. This driver can be used to access
@@ -107,6 +114,14 @@
to access the SPI NOR flash, MMC-over-SPI on platforms based on
Microchip PIC32 family devices.
+config RENESAS_RPC_SPI
+ bool "Renesas RPC SPI driver"
+ depends on RCAR_GEN3
+ help
+ Enable the Renesas RPC SPI driver, used to access SPI NOR flash
+ on Renesas RCar Gen3 SoCs. This uses driver model and requires a
+ device tree binding to operate.
+
config ROCKCHIP_SPI
bool "Rockchip SPI driver"
help
@@ -232,13 +247,6 @@
used to access the SPI NOR flash on platforms embedding this
Freescale IP core.
-config ATCSPI200_SPI
- bool "Andestech ATCSPI200 SPI driver"
- help
- Enable the Andestech ATCSPI200 SPI driver. This driver can be
- used to access the SPI flash on AE3XX and AE250 platforms embedding
- this Andestech IP core.
-
config DAVINCI_SPI
bool "Davinci & Keystone SPI driver"
depends on ARCH_DAVINCI || ARCH_KEYSTONE
@@ -276,7 +284,7 @@
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
- depends on 8xx
+ depends on MPC8xx
help
Enable support for SPI on MPC8XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4b6000f..176bfa0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -39,6 +39,7 @@
obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
+obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c
index 5b2e9d6..bc08914 100644
--- a/drivers/spi/atcspi200_spi.c
+++ b/drivers/spi/atcspi200_spi.c
@@ -75,9 +75,6 @@
};
struct nds_spi_slave {
-#ifndef CONFIG_DM_SPI
- struct spi_slave slave;
-#endif
volatile struct atcspi200_spi_regs *regs;
int to;
unsigned int freq;
@@ -286,89 +283,6 @@
return ret;
}
-#ifndef CONFIG_DM_SPI
-#define to_nds_spi_slave(s) container_of(s, struct nds_spi_slave, slave)
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct nds_spi_slave *ns;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- ns = spi_alloc_slave(struct nds_spi_slave, bus, cs);
- if (!ns)
- return NULL;
-
- switch (bus) {
- case SPI0_BUS:
- ns->regs = (struct atcspi200_spi_regs *)SPI0_BASE;
- break;
-
- case SPI1_BUS:
- ns->regs = (struct atcspi200_spi_regs *)SPI1_BASE;
- break;
-
- default:
- return NULL;
- }
-
- ns->freq= max_hz;
- ns->mode = mode;
- ns->to = SPI_TIMEOUT;
- ns->max_transfer_length = MAX_TRANSFER_LEN;
- ns->slave.max_write_size = MAX_TRANSFER_LEN;
-
- return &ns->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- free(ns);
-}
-
-void spi_init(void)
-{
- /* do nothing */
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- return __atcspi200_spi_claim_bus(ns);
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __atcspi200_spi_release_bus(ns);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
- void *data_in, unsigned long flags)
-{
- struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- return __atcspi200_spi_xfer(ns, bitlen, data_out, data_in, flags);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs < NSPI_MAX_CS_NUM;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __atcspi200_spi_start(ns);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __atcspi200_spi_stop(ns);
-}
-#else
static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
@@ -496,4 +410,3 @@
.priv_auto_alloc_size = sizeof(struct nds_spi_slave),
.probe = atcspi200_spi_probe,
};
-#endif
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 8010ab4..3cdfd36 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -236,7 +236,9 @@
unsigned int freq; /* Default frequency */
unsigned int mode;
ulong bus_clk_rate;
+#ifdef CONFIG_DM_GPIO
struct gpio_desc cs_gpios[MAX_CS_COUNT];
+#endif
};
static int atmel_spi_claim_bus(struct udevice *dev)
@@ -291,6 +293,7 @@
static void atmel_spi_cs_activate(struct udevice *dev)
{
+#ifdef CONFIG_DM_GPIO
struct udevice *bus = dev_get_parent(dev);
struct atmel_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
@@ -300,10 +303,12 @@
return;
dm_gpio_set_value(&priv->cs_gpios[cs], 0);
+#endif
}
static void atmel_spi_cs_deactivate(struct udevice *dev)
{
+#ifdef CONFIG_DM_GPIO
struct udevice *bus = dev_get_parent(dev);
struct atmel_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
@@ -313,6 +318,7 @@
return;
dm_gpio_set_value(&priv->cs_gpios[cs], 1);
+#endif
}
static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
@@ -462,8 +468,7 @@
static int atmel_spi_probe(struct udevice *bus)
{
struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
- struct atmel_spi_priv *priv = dev_get_priv(bus);
- int i, ret;
+ int ret;
ret = atmel_spi_enable_clk(bus);
if (ret)
@@ -471,6 +476,10 @@
bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
+#ifdef CONFIG_DM_GPIO
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+ int i;
+
ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
ARRAY_SIZE(priv->cs_gpios), 0);
if (ret < 0) {
@@ -485,6 +494,7 @@
dm_gpio_set_dir_flags(&priv->cs_gpios[i],
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
+#endif
writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index c501aee..0e93b62 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -10,6 +10,7 @@
* SPDX-License-Identifier: GPL-2.0
*/
+#include <asm-generic/gpio.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -18,6 +19,7 @@
#include <spi.h>
#include <fdtdec.h>
#include <linux/compat.h>
+#include <linux/iopoll.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -97,6 +99,8 @@
struct clk clk;
unsigned long bus_clk_rate;
+ struct gpio_desc cs_gpio; /* External chip-select gpio */
+
int bits_per_word;
u8 cs; /* chip select pin */
u8 tmode; /* TR/TO/RO/EEPROM */
@@ -110,24 +114,40 @@
void *rx_end;
};
-static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
+static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
{
return __raw_readl(priv->regs + offset);
}
-static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val)
+static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
{
__raw_writel(val, priv->regs + offset);
}
-static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset)
+static int request_gpio_cs(struct udevice *bus)
{
- return __raw_readw(priv->regs + offset);
-}
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ int ret;
-static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val)
-{
- __raw_writew(val, priv->regs + offset);
+ /* External chip select gpio line is optional */
+ ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
+ if (ret == -ENOENT)
+ return 0;
+
+ if (ret < 0) {
+ printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
+ return ret;
+ }
+
+ if (dm_gpio_is_valid(&priv->cs_gpio)) {
+ dm_gpio_set_dir_flags(&priv->cs_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ }
+
+ debug("%s: used external gpio for CS management\n", __func__);
+#endif
+ return 0;
}
static int dw_spi_ofdata_to_platdata(struct udevice *bus)
@@ -144,19 +164,19 @@
debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
plat->frequency);
- return 0;
+ return request_gpio_cs(bus);
}
static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
{
- dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
+ dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
}
/* Restart the controller, disable all interrupts, clean rx fifo */
static void spi_hw_init(struct dw_spi_priv *priv)
{
spi_enable_chip(priv, 0);
- dw_writel(priv, DW_SPI_IMR, 0xff);
+ dw_write(priv, DW_SPI_IMR, 0xff);
spi_enable_chip(priv, 1);
/*
@@ -167,13 +187,13 @@
u32 fifo;
for (fifo = 1; fifo < 256; fifo++) {
- dw_writew(priv, DW_SPI_TXFLTR, fifo);
- if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
+ dw_write(priv, DW_SPI_TXFLTR, fifo);
+ if (fifo != dw_read(priv, DW_SPI_TXFLTR))
break;
}
priv->fifo_len = (fifo == 1) ? 0 : fifo;
- dw_writew(priv, DW_SPI_TXFLTR, 0);
+ dw_write(priv, DW_SPI_TXFLTR, 0);
}
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
}
@@ -242,7 +262,7 @@
u32 tx_left, tx_room, rxtx_gap;
tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
- tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR);
+ tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
/*
* Another concern is about the tx/rx mismatch, we
@@ -263,7 +283,7 @@
{
u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
- return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR));
+ return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
}
static void dw_writer(struct dw_spi_priv *priv)
@@ -279,34 +299,22 @@
else
txw = *(u16 *)(priv->tx);
}
- dw_writew(priv, DW_SPI_DR, txw);
+ dw_write(priv, DW_SPI_DR, txw);
debug("%s: tx=0x%02x\n", __func__, txw);
priv->tx += priv->bits_per_word >> 3;
}
}
-static int dw_reader(struct dw_spi_priv *priv)
+static void dw_reader(struct dw_spi_priv *priv)
{
- unsigned start = get_timer(0);
- u32 max;
+ u32 max = rx_max(priv);
u16 rxw;
- /* Wait for rx data to be ready */
- while (rx_max(priv) == 0) {
- if (get_timer(start) > RX_TIMEOUT)
- return -ETIMEDOUT;
- }
-
- max = rx_max(priv);
-
while (max--) {
- rxw = dw_readw(priv, DW_SPI_DR);
+ rxw = dw_read(priv, DW_SPI_DR);
debug("%s: rx=0x%02x\n", __func__, rxw);
- /*
- * Care about rx only if the transfer's original "rx" is
- * not null
- */
+ /* Care about rx if the transfer's original "rx" is not null */
if (priv->rx_end - priv->len) {
if (priv->bits_per_word == 8)
*(u8 *)(priv->rx) = rxw;
@@ -315,24 +323,30 @@
}
priv->rx += priv->bits_per_word >> 3;
}
-
- return 0;
}
static int poll_transfer(struct dw_spi_priv *priv)
{
- int ret;
-
do {
dw_writer(priv);
- ret = dw_reader(priv);
- if (ret < 0)
- return ret;
+ dw_reader(priv);
} while (priv->rx_end > priv->rx);
return 0;
}
+static void external_cs_manage(struct udevice *dev, bool on)
+{
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+ struct dw_spi_priv *priv = dev_get_priv(dev->parent);
+
+ if (!dm_gpio_is_valid(&priv->cs_gpio))
+ return;
+
+ dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
+#endif
+}
+
static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
@@ -342,6 +356,7 @@
u8 *rx = din;
int ret = 0;
u32 cr0 = 0;
+ u32 val;
u32 cs;
/* spi core configured to do 8 bit transfers */
@@ -350,6 +365,10 @@
return -1;
}
+ /* Start the transaction if necessary. */
+ if (flags & SPI_XFER_BEGIN)
+ external_cs_manage(dev, false);
+
cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
(priv->mode << SPI_MODE_OFFSET) |
(priv->tmode << SPI_TMOD_OFFSET);
@@ -359,7 +378,11 @@
else if (rx)
priv->tmode = SPI_TMOD_RO;
else
- priv->tmode = SPI_TMOD_TO;
+ /*
+ * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
+ * any data which breaks our logic in poll_transfer() above.
+ */
+ priv->tmode = SPI_TMOD_TR;
cr0 &= ~SPI_TMOD_MASK;
cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
@@ -377,8 +400,8 @@
debug("%s: cr0=%08x\n", __func__, cr0);
/* Reprogram cr0 only if changed */
- if (dw_readw(priv, DW_SPI_CTRL0) != cr0)
- dw_writew(priv, DW_SPI_CTRL0, cr0);
+ if (dw_read(priv, DW_SPI_CTRL0) != cr0)
+ dw_write(priv, DW_SPI_CTRL0, cr0);
/*
* Configure the desired SS (slave select 0...3) in the controller
@@ -386,7 +409,7 @@
* automatically. So no cs_activate() etc is needed in this driver.
*/
cs = spi_chip_select(dev);
- dw_writel(priv, DW_SPI_SER, 1 << cs);
+ dw_write(priv, DW_SPI_SER, 1 << cs);
/* Enable controller after writing control registers */
spi_enable_chip(priv, 1);
@@ -394,6 +417,23 @@
/* Start transfer in a polling loop */
ret = poll_transfer(priv);
+ /*
+ * Wait for current transmit operation to complete.
+ * Otherwise if some data still exists in Tx FIFO it can be
+ * silently flushed, i.e. dropped on disabling of the controller,
+ * which happens when writing 0 to DW_SPI_SSIENR which happens
+ * in the beginning of new transfer.
+ */
+ if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
+ !(val & SR_TF_EMPT) || (val & SR_BUSY),
+ RX_TIMEOUT * 1000)) {
+ ret = -ETIMEDOUT;
+ }
+
+ /* Stop the transaction if necessary */
+ if (flags & SPI_XFER_END)
+ external_cs_manage(dev, true);
+
return ret;
}
@@ -412,7 +452,7 @@
/* clk_div doesn't support odd number */
clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
- dw_writel(priv, DW_SPI_BAUDR, clk_div);
+ dw_write(priv, DW_SPI_BAUDR, clk_div);
/* Enable controller after writing control registers */
spi_enable_chip(priv, 1);
diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index b5bd558..eb035e9 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -19,7 +19,7 @@
#include <common.h>
#include <mpc8xx.h>
-#include <commproc.h>
+#include <asm/cpm_8xx.h>
#include <linux/ctype.h>
#include <malloc.h>
#include <post.h>
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 1da4542..1ac691a 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -456,9 +456,6 @@
conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
writel(conf, &priv->regs->modulctrl);
-
- _omap3_spi_set_mode(priv);
- _omap3_spi_set_speed(priv);
}
#ifndef CONFIG_DM_SPI
@@ -594,8 +591,6 @@
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
priv->cs = slave_plat->cs;
- priv->mode = slave_plat->mode;
- priv->freq = slave_plat->max_hz;
_omap3_spi_claim_bus(priv);
return 0;
@@ -635,8 +630,10 @@
(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
- priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in",
- MCSPI_PINDIR_D0_IN_D1_OUT);
+ if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
+ priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+ else
+ priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
priv->wordlen = SPI_DEFAULT_WORDLEN;
return 0;
}
@@ -650,13 +647,29 @@
return _spi_xfer(priv, bitlen, dout, din, flags);
}
-static int omap3_spi_set_speed(struct udevice *bus, unsigned int speed)
+static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
{
+ struct udevice *bus = dev->parent;
+ struct omap3_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ priv->cs = slave_plat->cs;
+ priv->freq = slave_plat->max_hz;
+ _omap3_spi_set_speed(priv);
+
return 0;
}
-static int omap3_spi_set_mode(struct udevice *bus, uint mode)
+static int omap3_spi_set_mode(struct udevice *dev, uint mode)
{
+ struct udevice *bus = dev->parent;
+ struct omap3_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ priv->cs = slave_plat->cs;
+ priv->mode = slave_plat->mode;
+ _omap3_spi_set_mode(priv);
+
return 0;
}
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
new file mode 100644
index 0000000..e54f24c
--- /dev/null
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -0,0 +1,465 @@
+/*
+ * Renesas RCar Gen3 RPC QSPI driver
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <linux/errno.h>
+#include <spi.h>
+#include <wait_bit.h>
+
+#define RPC_CMNCR 0x0000 /* R/W */
+#define RPC_CMNCR_MD BIT(31)
+#define RPC_CMNCR_SFDE BIT(24)
+#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
+#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
+#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
+#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
+#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
+ RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
+#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
+#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
+#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
+#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
+ RPC_CMNCR_IO3FV(3))
+#define RPC_CMNCR_CPHAT BIT(6)
+#define RPC_CMNCR_CPHAR BIT(5)
+#define RPC_CMNCR_SSLP BIT(4)
+#define RPC_CMNCR_CPOL BIT(3)
+#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
+
+#define RPC_SSLDR 0x0004 /* R/W */
+#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
+#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
+#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
+
+#define RPC_DRCR 0x000C /* R/W */
+#define RPC_DRCR_SSLN BIT(24)
+#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
+#define RPC_DRCR_RCF BIT(9)
+#define RPC_DRCR_RBE BIT(8)
+#define RPC_DRCR_SSLE BIT(0)
+
+#define RPC_DRCMR 0x0010 /* R/W */
+#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
+#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
+
+#define RPC_DREAR 0x0014 /* R/W */
+#define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
+#define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
+
+#define RPC_DROPR 0x0018 /* R/W */
+#define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
+#define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
+#define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
+#define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
+
+#define RPC_DRENR 0x001C /* R/W */
+#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
+#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
+#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
+#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
+#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
+#define RPC_DRENR_DME BIT(15)
+#define RPC_DRENR_CDE BIT(14)
+#define RPC_DRENR_OCDE BIT(12)
+#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
+#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
+
+#define RPC_SMCR 0x0020 /* R/W */
+#define RPC_SMCR_SSLKP BIT(8)
+#define RPC_SMCR_SPIRE BIT(2)
+#define RPC_SMCR_SPIWE BIT(1)
+#define RPC_SMCR_SPIE BIT(0)
+
+#define RPC_SMCMR 0x0024 /* R/W */
+#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
+#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
+
+#define RPC_SMADR 0x0028 /* R/W */
+#define RPC_SMOPR 0x002C /* R/W */
+#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
+#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
+#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
+#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
+
+#define RPC_SMENR 0x0030 /* R/W */
+#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
+#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
+#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
+#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
+#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
+#define RPC_SMENR_DME BIT(15)
+#define RPC_SMENR_CDE BIT(14)
+#define RPC_SMENR_OCDE BIT(12)
+#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
+#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
+#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
+
+#define RPC_SMRDR0 0x0038 /* R */
+#define RPC_SMRDR1 0x003C /* R */
+#define RPC_SMWDR0 0x0040 /* R/W */
+#define RPC_SMWDR1 0x0044 /* R/W */
+#define RPC_CMNSR 0x0048 /* R */
+#define RPC_CMNSR_SSLF BIT(1)
+#define RPC_CMNSR_TEND BIT(0)
+
+#define RPC_DRDMCR 0x0058 /* R/W */
+#define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
+
+#define RPC_DRDRENR 0x005C /* R/W */
+#define RPC_DRDRENR_HYPE (0x5 << 12)
+#define RPC_DRDRENR_ADDRE BIT(8)
+#define RPC_DRDRENR_OPDRE BIT(4)
+#define RPC_DRDRENR_DRDRE BIT(0)
+
+#define RPC_SMDMCR 0x0060 /* R/W */
+#define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
+
+#define RPC_SMDRENR 0x0064 /* R/W */
+#define RPC_SMDRENR_HYPE (0x5 << 12)
+#define RPC_SMDRENR_ADDRE BIT(8)
+#define RPC_SMDRENR_OPDRE BIT(4)
+#define RPC_SMDRENR_SPIDRE BIT(0)
+
+#define RPC_PHYCNT 0x007C /* R/W */
+#define RPC_PHYCNT_CAL BIT(31)
+#define PRC_PHYCNT_OCTA_AA BIT(22)
+#define PRC_PHYCNT_OCTA_SA BIT(23)
+#define PRC_PHYCNT_EXDS BIT(21)
+#define RPC_PHYCNT_OCT BIT(20)
+#define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
+#define RPC_PHYCNT_WBUF2 BIT(4)
+#define RPC_PHYCNT_WBUF BIT(2)
+#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
+
+#define RPC_PHYINT 0x0088 /* R/W */
+#define RPC_PHYINT_RSTEN BIT(18)
+#define RPC_PHYINT_WPEN BIT(17)
+#define RPC_PHYINT_INTEN BIT(16)
+#define RPC_PHYINT_RST BIT(2)
+#define RPC_PHYINT_WP BIT(1)
+#define RPC_PHYINT_INT BIT(0)
+
+#define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
+#define RPC_WBUF_SIZE 0x100
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rpc_spi_platdata {
+ fdt_addr_t regs;
+ fdt_addr_t extr;
+ s32 freq; /* Default clock freq, -1 for none */
+};
+
+struct rpc_spi_priv {
+ fdt_addr_t regs;
+ fdt_addr_t extr;
+ struct clk clk;
+
+ u8 cmdcopy[8];
+ u32 cmdlen;
+ bool cmdstarted;
+};
+
+static int rpc_spi_wait_sslf(struct udevice *dev)
+{
+ struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
+
+ return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF,
+ false, 1000, false);
+}
+
+static int rpc_spi_wait_tend(struct udevice *dev)
+{
+ struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
+
+ return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND,
+ true, 1000, false);
+}
+
+static void rpc_spi_flush_read_cache(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct rpc_spi_priv *priv = dev_get_priv(bus);
+
+ /* Flush read cache */
+ writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) |
+ RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE,
+ priv->regs + RPC_DRCR);
+ readl(priv->regs + RPC_DRCR);
+
+}
+
+static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
+{
+ struct udevice *bus = dev->parent;
+ struct rpc_spi_priv *priv = dev_get_priv(bus);
+
+ /*
+ * NOTE: The 0x260 are undocumented bits, but they must be set.
+ * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
+ * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
+ * RPC_PHYCNT_STRTIM shall be 6.
+ */
+ writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
+ priv->regs + RPC_PHYCNT);
+ writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
+ RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
+ priv->regs + RPC_CMNCR);
+
+ writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) |
+ RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR);
+
+ rpc_spi_flush_read_cache(dev);
+
+ return 0;
+}
+
+static int rpc_spi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct rpc_spi_priv *priv = dev_get_priv(bus);
+
+ /* NOTE: The 0x260 are undocumented bits, but they must be set. */
+ writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
+
+ rpc_spi_flush_read_cache(dev);
+
+ return 0;
+}
+
+static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct rpc_spi_priv *priv = dev_get_priv(bus);
+ u32 wlen = dout ? (bitlen / 8) : 0;
+ u32 rlen = din ? (bitlen / 8) : 0;
+ u32 wloop = DIV_ROUND_UP(wlen, 4);
+ u32 smenr, smcr, offset;
+ int ret = 0;
+
+ if (!priv->cmdstarted) {
+ if (!wlen || rlen)
+ BUG();
+
+ memcpy(priv->cmdcopy, dout, wlen);
+ priv->cmdlen = wlen;
+
+ /* Command transfer start */
+ priv->cmdstarted = true;
+ if (!(flags & SPI_XFER_END))
+ return 0;
+ }
+
+ offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
+ (priv->cmdcopy[3] << 0);
+
+ smenr = 0;
+
+ if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
+ if (wlen && flags == SPI_XFER_END)
+ smenr = RPC_SMENR_SPIDE(0xf);
+
+ rpc_spi_claim_bus(dev, true);
+
+ writel(0, priv->regs + RPC_SMCR);
+
+ if (priv->cmdlen >= 1) { /* Command(1) */
+ writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
+ priv->regs + RPC_SMCMR);
+ smenr |= RPC_SMENR_CDE;
+ } else {
+ writel(0, priv->regs + RPC_SMCMR);
+ }
+
+ if (priv->cmdlen >= 4) { /* Address(3) */
+ writel(offset, priv->regs + RPC_SMADR);
+ smenr |= RPC_SMENR_ADE(7);
+ } else {
+ writel(0, priv->regs + RPC_SMADR);
+ }
+
+ if (priv->cmdlen >= 5) { /* Dummy(n) */
+ writel(8 * (priv->cmdlen - 4) - 1,
+ priv->regs + RPC_SMDMCR);
+ smenr |= RPC_SMENR_DME;
+ } else {
+ writel(0, priv->regs + RPC_SMDMCR);
+ }
+
+ writel(0, priv->regs + RPC_SMOPR);
+
+ writel(0, priv->regs + RPC_SMDRENR);
+
+ if (wlen && flags == SPI_XFER_END) {
+ u32 *datout = (u32 *)dout;
+
+ while (wloop--) {
+ smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
+ if (wloop >= 1)
+ smcr |= RPC_SMCR_SSLKP;
+ writel(smenr, priv->regs + RPC_SMENR);
+ writel(*datout, priv->regs + RPC_SMWDR0);
+ writel(smcr, priv->regs + RPC_SMCR);
+ ret = rpc_spi_wait_tend(dev);
+ if (ret)
+ goto err;
+ datout++;
+ smenr = RPC_SMENR_SPIDE(0xf);
+ }
+
+ ret = rpc_spi_wait_sslf(dev);
+
+ } else {
+ writel(smenr, priv->regs + RPC_SMENR);
+ writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
+ ret = rpc_spi_wait_tend(dev);
+ }
+ } else { /* Read data only, using DRx ext access */
+ rpc_spi_claim_bus(dev, false);
+
+ if (priv->cmdlen >= 1) { /* Command(1) */
+ writel(RPC_DRCMR_CMD(priv->cmdcopy[0]),
+ priv->regs + RPC_DRCMR);
+ smenr |= RPC_DRENR_CDE;
+ } else {
+ writel(0, priv->regs + RPC_DRCMR);
+ }
+
+ if (priv->cmdlen >= 4) /* Address(3) */
+ smenr |= RPC_DRENR_ADE(7);
+
+ if (priv->cmdlen >= 5) { /* Dummy(n) */
+ writel(8 * (priv->cmdlen - 4) - 1,
+ priv->regs + RPC_DRDMCR);
+ smenr |= RPC_DRENR_DME;
+ } else {
+ writel(0, priv->regs + RPC_DRDMCR);
+ }
+
+ writel(0, priv->regs + RPC_DROPR);
+
+ writel(smenr, priv->regs + RPC_DRENR);
+
+ if (rlen)
+ memcpy_fromio(din, (void *)(priv->extr + offset), rlen);
+ else
+ readl(priv->extr); /* Dummy read */
+ }
+
+err:
+ priv->cmdstarted = false;
+
+ rpc_spi_release_bus(dev);
+
+ return ret;
+}
+
+static int rpc_spi_set_speed(struct udevice *bus, uint speed)
+{
+ /* This is a SPI NOR controller, do nothing. */
+ return 0;
+}
+
+static int rpc_spi_set_mode(struct udevice *bus, uint mode)
+{
+ /* This is a SPI NOR controller, do nothing. */
+ return 0;
+}
+
+static int rpc_spi_bind(struct udevice *parent)
+{
+ const void *fdt = gd->fdt_blob;
+ ofnode node;
+ int ret, off;
+
+ /*
+ * Check if there are any SPI NOR child nodes, if so, bind as
+ * this controller will be operated in SPI mode.
+ */
+ dev_for_each_subnode(node, parent) {
+ off = ofnode_to_offset(node);
+
+ ret = fdt_node_check_compatible(fdt, off, "spi-flash");
+ if (!ret)
+ return 0;
+
+ ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
+ if (!ret)
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+static int rpc_spi_probe(struct udevice *dev)
+{
+ struct rpc_spi_platdata *plat = dev_get_platdata(dev);
+ struct rpc_spi_priv *priv = dev_get_priv(dev);
+
+ priv->regs = plat->regs;
+ priv->extr = plat->extr;
+
+ clk_enable(&priv->clk);
+
+ return 0;
+}
+
+static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct rpc_spi_platdata *plat = dev_get_platdata(bus);
+ struct rpc_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ plat->regs = dev_read_addr_index(bus, 0);
+ plat->extr = dev_read_addr_index(bus, 1);
+
+ ret = clk_get_by_index(bus, 0, &priv->clk);
+ if (ret < 0) {
+ printf("%s: Could not get clock for %s: %d\n",
+ __func__, bus->name, ret);
+ return ret;
+ }
+
+ plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
+
+ return 0;
+}
+
+static const struct dm_spi_ops rpc_spi_ops = {
+ .xfer = rpc_spi_xfer,
+ .set_speed = rpc_spi_set_speed,
+ .set_mode = rpc_spi_set_mode,
+};
+
+static const struct udevice_id rpc_spi_ids[] = {
+ { .compatible = "renesas,rpc-r8a7795" },
+ { .compatible = "renesas,rpc-r8a7796" },
+ { .compatible = "renesas,rpc-r8a77965" },
+ { .compatible = "renesas,rpc-r8a77970" },
+ { .compatible = "renesas,rpc-r8a77995" },
+ { }
+};
+
+U_BOOT_DRIVER(rpc_spi) = {
+ .name = "rpc_spi",
+ .id = UCLASS_SPI,
+ .of_match = rpc_spi_ids,
+ .ops = &rpc_spi_ops,
+ .ofdata_to_platdata = rpc_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct rpc_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct rpc_spi_priv),
+ .bind = rpc_spi_bind,
+ .probe = rpc_spi_probe,
+};
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 75999c8..5075be3 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -11,6 +11,7 @@
#include <console.h>
#include <malloc.h>
#include <spi.h>
+#include <wait_bit.h>
#include <asm/arch/rmobile.h>
#include <asm/io.h>
@@ -35,33 +36,35 @@
SPCMD_BRDV0
#define SPBFCR_TXRST BIT(7)
#define SPBFCR_RXRST BIT(6)
+#define SPBFCR_TXTRG 0x30
+#define SPBFCR_RXTRG 0x07
/* SH QSPI register set */
struct sh_qspi_regs {
- unsigned char spcr;
- unsigned char sslp;
- unsigned char sppcr;
- unsigned char spsr;
- unsigned long spdr;
- unsigned char spscr;
- unsigned char spssr;
- unsigned char spbr;
- unsigned char spdcr;
- unsigned char spckd;
- unsigned char sslnd;
- unsigned char spnd;
- unsigned char dummy0;
- unsigned short spcmd0;
- unsigned short spcmd1;
- unsigned short spcmd2;
- unsigned short spcmd3;
- unsigned char spbfcr;
- unsigned char dummy1;
- unsigned short spbdcr;
- unsigned long spbmul0;
- unsigned long spbmul1;
- unsigned long spbmul2;
- unsigned long spbmul3;
+ u8 spcr;
+ u8 sslp;
+ u8 sppcr;
+ u8 spsr;
+ u32 spdr;
+ u8 spscr;
+ u8 spssr;
+ u8 spbr;
+ u8 spdcr;
+ u8 spckd;
+ u8 sslnd;
+ u8 spnd;
+ u8 dummy0;
+ u16 spcmd0;
+ u16 spcmd1;
+ u16 spcmd2;
+ u16 spcmd3;
+ u8 spbfcr;
+ u8 dummy1;
+ u16 spbdcr;
+ u32 spbmul0;
+ u32 spbmul1;
+ u32 spbmul2;
+ u32 spbmul3;
};
struct sh_qspi_slave {
@@ -200,11 +203,11 @@
void *din, unsigned long flags)
{
struct sh_qspi_slave *ss = to_sh_qspi(slave);
- unsigned long nbyte;
- int ret = 0;
- unsigned char dtdata = 0, drdata;
- unsigned char *tdata = &dtdata, *rdata = &drdata;
- unsigned long *spbmul0 = &ss->regs->spbmul0;
+ u32 nbyte, chunk;
+ int i, ret = 0;
+ u8 dtdata = 0, drdata;
+ u8 *tdata = &dtdata, *rdata = &drdata;
+ u32 *spbmul0 = &ss->regs->spbmul0;
if (dout == NULL && din == NULL) {
if (flags & SPI_XFER_END)
@@ -230,46 +233,44 @@
writel(nbyte, spbmul0);
if (dout != NULL)
- tdata = (unsigned char *)dout;
+ tdata = (u8 *)dout;
if (din != NULL)
rdata = din;
while (nbyte > 0) {
- while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) {
- if (ctrlc()) {
- puts("abort\n");
- return 1;
- }
- udelay(10);
+ /*
+ * Check if there is 32 Byte chunk and if there is, transfer
+ * it in one burst, otherwise transfer on byte-by-byte basis.
+ */
+ chunk = (nbyte >= 32) ? 32 : 1;
+
+ clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
+ chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
+
+ ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
+ true, 1000, true);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < chunk; i++) {
+ writeb(*tdata, &ss->regs->spdr);
+ if (dout != NULL)
+ tdata++;
}
- writeb(*tdata, (unsigned char *)(&ss->regs->spdr));
+ ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
+ true, 1000, true);
+ if (ret)
+ return ret;
- while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) {
- if (ctrlc()) {
- puts("abort\n");
- return 1;
- }
- udelay(1);
+ for (i = 0; i < chunk; i++) {
+ *rdata = readb(&ss->regs->spdr);
+ if (din != NULL)
+ rdata++;
}
- while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) {
- if (ctrlc()) {
- puts("abort\n");
- return 1;
- }
- udelay(10);
- }
-
- *rdata = readb((unsigned char *)(&ss->regs->spdr));
-
- if (dout != NULL)
- tdata++;
- if (din != NULL)
- rdata++;
-
- nbyte--;
+ nbyte -= chunk;
}
if (flags & SPI_XFER_END)
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index ef2b64e..558708a 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -16,7 +16,6 @@
#include <dm.h>
#include <errno.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_defs.h>
#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
index 3abce7f..22c602a 100644
--- a/drivers/sysreset/sysreset_syscon.c
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -15,8 +15,6 @@
#include <sysreset.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct syscon_reboot_priv {
struct regmap *regmap;
unsigned int offset;
@@ -55,10 +53,8 @@
return -ENODEV;
}
- priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "offset", 0);
- priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "mask", 0);
+ priv->offset = dev_read_u32_default(dev, "offset", 0);
+ priv->mask = dev_read_u32_default(dev, "mask", 0);
return 0;
}
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 3a1f831..2c96896 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -119,4 +119,11 @@
Select this to enable support for the timer found on
Rockchip devices.
+config STM32_TIMER
+ bool "STM32 timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ STM32 devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 15e5154..a6e7832 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -16,3 +16,4 @@
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
+obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
new file mode 100644
index 0000000..344e6fb
--- /dev/null
+++ b/drivers/timer/stm32_timer.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <timer.h>
+
+#include <asm/io.h>
+
+/* Timer control1 register */
+#define CR1_CEN BIT(0)
+#define CR1_ARPE BIT(7)
+
+/* Event Generation Register register */
+#define EGR_UG BIT(0)
+
+/* Auto reload register for free running config */
+#define GPT_FREE_RUNNING 0xFFFFFFFF
+
+struct stm32_timer_regs {
+ u32 cr1;
+ u32 cr2;
+ u32 smcr;
+ u32 dier;
+ u32 sr;
+ u32 egr;
+ u32 ccmr1;
+ u32 ccmr2;
+ u32 ccer;
+ u32 cnt;
+ u32 psc;
+ u32 arr;
+ u32 reserved;
+ u32 ccr1;
+ u32 ccr2;
+ u32 ccr3;
+ u32 ccr4;
+ u32 reserved1;
+ u32 dcr;
+ u32 dmar;
+ u32 tim2_5_or;
+};
+
+struct stm32_timer_priv {
+ struct stm32_timer_regs *base;
+};
+
+static int stm32_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct stm32_timer_priv *priv = dev_get_priv(dev);
+ struct stm32_timer_regs *regs = priv->base;
+
+ *count = readl(®s->cnt);
+
+ return 0;
+}
+
+static int stm32_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct stm32_timer_priv *priv = dev_get_priv(dev);
+ struct stm32_timer_regs *regs;
+ struct clk clk;
+ fdt_addr_t addr;
+ int ret;
+ u32 rate, psc;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = (struct stm32_timer_regs *)addr;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ regs = priv->base;
+
+ /* Stop the timer */
+ clrbits_le32(®s->cr1, CR1_CEN);
+
+ /* get timer clock */
+ rate = clk_get_rate(&clk);
+
+ /* we set timer prescaler to obtain a 1MHz timer counter frequency */
+ psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+ writel(psc, ®s->psc);
+
+ /* Set timer frequency to 1MHz */
+ uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+
+ /* Configure timer for auto-reload */
+ setbits_le32(®s->cr1, CR1_ARPE);
+
+ /* load value for auto reload */
+ writel(GPT_FREE_RUNNING, ®s->arr);
+
+ /* start timer */
+ setbits_le32(®s->cr1, CR1_CEN);
+
+ /* Update generation */
+ setbits_le32(®s->egr, EGR_UG);
+
+ return 0;
+}
+
+static const struct timer_ops stm32_timer_ops = {
+ .get_count = stm32_timer_get_count,
+};
+
+static const struct udevice_id stm32_timer_ids[] = {
+ { .compatible = "st,stm32-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(stm32_timer) = {
+ .name = "stm32_timer",
+ .id = UCLASS_TIMER,
+ .of_match = stm32_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct stm32_timer_priv),
+ .probe = stm32_timer_probe,
+ .ops = &stm32_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig
index 496a6d1..2f6bfa8 100644
--- a/drivers/usb/eth/Kconfig
+++ b/drivers/usb/eth/Kconfig
@@ -23,6 +23,7 @@
config USB_ETHER_LAN75XX
bool "Microchip LAN75XX support"
depends on USB_HOST_ETHER
+ depends on PHYLIB
---help---
Say Y here if you would like to support Microchip LAN75XX Hi-Speed
USB 2.0 to 10/100/1000 Gigabit Ethernet controller.
@@ -32,6 +33,7 @@
config USB_ETHER_LAN78XX
bool "Microchip LAN78XX support"
depends on USB_HOST_ETHER
+ depends on PHYLIB
---help---
Say Y here if you would like to support Microchip LAN78XX USB 3.1
Gen 1 to 10/100/1000 Gigabit Ethernet controller.
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 6825e6b..26b4d12 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -158,6 +158,7 @@
config USB_ETHER
bool "USB Ethernet Gadget"
+ depends on NET
default y if ARCH_SUNXI && USB_MUSB_GADGET
help
Creates an Ethernet network device through a USB peripheral
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index a80486e..386505d 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <console.h>
+#include <environment.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/usb/ch9.h>
diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c
index d5a10f1..ad3ae91 100644
--- a/drivers/usb/gadget/f_rockusb.c
+++ b/drivers/usb/gadget/f_rockusb.c
@@ -552,7 +552,6 @@
sizeof(struct fsg_bulk_cb_wrap));
struct f_rockusb *f_rkusb = get_rkusb();
- f_rkusb->reboot_flag = 0;
memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
f_rkusb->reboot_flag = cbw->CDB[1];
rockusb_func->in_req->complete = compl_do_reset;
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 90b2f78..6caa615 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -21,6 +21,13 @@
Say Y or if your system has a Dual Role SuperSpeed
USB controller based on the DesignWare USB3 IP Core.
+config USB_XHCI_DWC3_OF_SIMPLE
+ bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
+ select MISC
+ help
+ Support USB2/3 functionality in simple SoC integrations with
+ USB controller based on the DesignWare USB3 IP Core.
+
config USB_XHCI_MVEBU
bool "MVEBU USB 3.0 support"
default y
@@ -245,3 +252,15 @@
Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
operation is compliant to the controller Supplement. If you want to
enable this controller in host mode, say Y.
+
+if USB_DWC2
+config USB_DWC2_BUFFER_SIZE
+ int "Data buffer size in kB"
+ default 64
+ ---help---
+ By default 64 kB buffer is used but if amount of RAM avaialble on
+ the target is not enough to accommodate allocation of buffer of
+ that size it is possible to shrink it. Smaller sizes should be fine
+ because larger transactions could be split in smaller ones.
+
+endif # USB_DWC2
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7f9ba24..abe4f90 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -35,7 +35,6 @@
obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o
obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
-obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
@@ -50,6 +49,7 @@
# xhci
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 0efe645..4862ab0 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -25,7 +25,7 @@
#define DWC2_HC_CHANNEL 0
#define DWC2_STATUS_BUF_SIZE 64
-#define DWC2_DATA_BUF_SIZE (64 * 1024)
+#define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
#define MAX_DEVICE 16
#define MAX_ENDPOINT 16
@@ -34,6 +34,9 @@
#ifdef CONFIG_DM_USB
uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
+#ifdef CONFIG_DM_REGULATOR
+ struct udevice *vbus_supply;
+#endif
#else
uint8_t *aligned_buffer;
uint8_t *status_buffer;
@@ -111,7 +114,7 @@
ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
false, 1000, false);
if (ret)
- printf("%s: Timeout!\n", __func__);
+ dev_info(dev, "%s: Timeout!\n", __func__);
/* Wait for 3 PHY Clocks */
udelay(1);
@@ -130,7 +133,7 @@
ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
false, 1000, false);
if (ret)
- printf("%s: Timeout!\n", __func__);
+ dev_info(dev, "%s: Timeout!\n", __func__);
/* Wait for 3 PHY Clocks */
udelay(1);
@@ -148,14 +151,14 @@
ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
true, 1000, false);
if (ret)
- printf("%s: Timeout!\n", __func__);
+ dev_info(dev, "%s: Timeout!\n", __func__);
/* Core Soft Reset */
writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
false, 1000, false);
if (ret)
- printf("%s: Timeout!\n", __func__);
+ dev_info(dev, "%s: Timeout!\n", __func__);
/*
* Wait for core to come out of reset.
@@ -168,28 +171,52 @@
#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
static int dwc_vbus_supply_init(struct udevice *dev)
{
- struct udevice *vbus_supply;
+ struct dwc2_priv *priv = dev_get_priv(dev);
int ret;
- ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply);
+ ret = device_get_supply_regulator(dev, "vbus-supply",
+ &priv->vbus_supply);
if (ret) {
debug("%s: No vbus supply\n", dev->name);
return 0;
}
- ret = regulator_set_enable(vbus_supply, true);
+ ret = regulator_set_enable(priv->vbus_supply, true);
if (ret) {
- pr_err("Error enabling vbus supply\n");
+ dev_err(dev, "Error enabling vbus supply\n");
return ret;
}
return 0;
}
+
+static int dwc_vbus_supply_exit(struct udevice *dev)
+{
+ struct dwc2_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply, false);
+ if (ret) {
+ dev_err(dev, "Error disabling vbus supply\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
#else
static int dwc_vbus_supply_init(struct udevice *dev)
{
return 0;
}
+
+#if defined(CONFIG_DM_USB)
+static int dwc_vbus_supply_exit(struct udevice *dev)
+{
+ return 0;
+}
+#endif
#endif
/*
@@ -270,7 +297,7 @@
ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
DWC2_HCCHAR_CHEN, false, 1000, false);
if (ret)
- printf("%s: Timeout!\n", __func__);
+ dev_info("%s: Timeout!\n", __func__);
}
/* Turn on the vbus power. */
@@ -784,7 +811,7 @@
uint32_t hcint, hctsiz;
ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
- 1000, false);
+ 2000, false);
if (ret)
return ret;
@@ -1091,7 +1118,7 @@
timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
for (;;) {
if (get_timer(0) > timeout) {
- printf("Timeout poll on interrupt endpoint\n");
+ dev_err(dev, "Timeout poll on interrupt endpoint\n");
return -ETIMEDOUT;
}
ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
@@ -1107,11 +1134,13 @@
int i, j;
snpsid = readl(®s->gsnpsid);
- printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
+ dev_info(dev, "Core Release: %x.%03x\n",
+ snpsid >> 12 & 0xf, snpsid & 0xfff);
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
(snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
- printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
+ dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
+ snpsid);
return -ENODEV;
}
@@ -1269,6 +1298,11 @@
static int dwc2_usb_remove(struct udevice *dev)
{
struct dwc2_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dwc_vbus_supply_exit(dev);
+ if (ret)
+ return ret;
dwc2_uninit_common(priv->regs);
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
new file mode 100644
index 0000000..54a5f60
--- /dev/null
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -0,0 +1,109 @@
+/*
+ * dwc3-of-simple.c - OF glue layer for simple integrations
+ *
+ * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <reset.h>
+#include <clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dwc3_of_simple {
+ struct clk_bulk clks;
+ struct reset_ctl_bulk resets;
+};
+
+static int dwc3_of_simple_reset_init(struct udevice *dev,
+ struct dwc3_of_simple *simple)
+{
+ int ret;
+
+ ret = reset_get_bulk(dev, &simple->resets);
+ if (ret == -ENOTSUPP)
+ return 0;
+ else if (ret)
+ return ret;
+
+ ret = reset_deassert_bulk(&simple->resets);
+ if (ret) {
+ reset_release_bulk(&simple->resets);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dwc3_of_simple_clk_init(struct udevice *dev,
+ struct dwc3_of_simple *simple)
+{
+ int ret;
+
+ ret = clk_get_bulk(dev, &simple->clks);
+ if (ret == -ENOTSUPP)
+ return 0;
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_enable_bulk(&simple->clks);
+ if (ret) {
+ clk_release_bulk(&simple->clks);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static int dwc3_of_simple_probe(struct udevice *dev)
+{
+ struct dwc3_of_simple *simple = dev_get_platdata(dev);
+ int ret;
+
+ ret = dwc3_of_simple_clk_init(dev, simple);
+ if (ret)
+ return ret;
+
+ ret = dwc3_of_simple_reset_init(dev, simple);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int dwc3_of_simple_remove(struct udevice *dev)
+{
+ struct dwc3_of_simple *simple = dev_get_platdata(dev);
+
+ reset_release_bulk(&simple->resets);
+
+ clk_release_bulk(&simple->clks);
+
+ return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id dwc3_of_simple_ids[] = {
+ { .compatible = "amlogic,meson-gxl-dwc3" },
+ { }
+};
+
+U_BOOT_DRIVER(dwc3_of_simple) = {
+ .name = "dwc3-of-simple",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = dwc3_of_simple_ids,
+ .probe = dwc3_of_simple_probe,
+ .remove = dwc3_of_simple_remove,
+ .platdata_auto_alloc_size = sizeof(struct dwc3_of_simple),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 1cb92c0..b012d86 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -27,6 +27,56 @@
int reset_count;
};
+static int ehci_setup_phy(struct udevice *dev, int index)
+{
+ struct generic_ehci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = generic_phy_get_by_index(dev, index, &priv->phy);
+ if (ret) {
+ if (ret != -ENOENT) {
+ dev_err(dev, "failed to get usb phy\n");
+ return ret;
+ }
+ } else {
+ ret = generic_phy_init(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to init usb phy\n");
+ return ret;
+ }
+
+ ret = generic_phy_power_on(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power on usb phy\n");
+ return generic_phy_exit(&priv->phy);
+ }
+ }
+
+ return 0;
+}
+
+static int ehci_shutdown_phy(struct udevice *dev)
+{
+ struct generic_ehci *priv = dev_get_priv(dev);
+ int ret = 0;
+
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_power_off(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power off usb phy\n");
+ return ret;
+ }
+
+ ret = generic_phy_exit(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power off usb phy\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int ehci_usb_probe(struct udevice *dev)
{
struct generic_ehci *priv = dev_get_priv(dev);
@@ -51,7 +101,7 @@
break;
err = clk_enable(&priv->clocks[i]);
if (err) {
- pr_err("failed to enable clock %d\n", i);
+ dev_err(dev, "failed to enable clock %d\n", i);
clk_free(&priv->clocks[i]);
goto clk_err;
}
@@ -59,7 +109,8 @@
}
} else {
if (clock_nb != -ENOENT) {
- pr_err("failed to get clock phandle(%d)\n", clock_nb);
+ dev_err(dev, "failed to get clock phandle(%d)\n",
+ clock_nb);
return clock_nb;
}
}
@@ -80,7 +131,8 @@
break;
if (reset_deassert(&priv->resets[i])) {
- pr_err("failed to deassert reset %d\n", i);
+ dev_err(dev, "failed to deassert reset %d\n",
+ i);
reset_free(&priv->resets[i]);
goto reset_err;
}
@@ -88,25 +140,15 @@
}
} else {
if (reset_nb != -ENOENT) {
- pr_err("failed to get reset phandle(%d)\n", reset_nb);
+ dev_err(dev, "failed to get reset phandle(%d)\n",
+ reset_nb);
goto clk_err;
}
}
- err = generic_phy_get_by_index(dev, 0, &priv->phy);
- if (err) {
- if (err != -ENOENT) {
- pr_err("failed to get usb phy\n");
- goto reset_err;
- }
- } else {
-
- err = generic_phy_init(&priv->phy);
- if (err) {
- pr_err("failed to init usb phy\n");
- goto reset_err;
- }
- }
+ err = ehci_setup_phy(dev, 0);
+ if (err)
+ goto reset_err;
hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
@@ -119,20 +161,18 @@
return 0;
phy_err:
- if (generic_phy_valid(&priv->phy)) {
- ret = generic_phy_exit(&priv->phy);
- if (ret)
- pr_err("failed to release phy\n");
- }
+ ret = ehci_shutdown_phy(dev);
+ if (ret)
+ dev_err(dev, "failed to shutdown usb phy\n");
reset_err:
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
- pr_err("failed to assert all resets\n");
+ dev_err(dev, "failed to assert all resets\n");
clk_err:
ret = clk_release_all(priv->clocks, priv->clock_count);
if (ret)
- pr_err("failed to disable all clocks\n");
+ dev_err(dev, "failed to disable all clocks\n");
return err;
}
@@ -146,11 +186,9 @@
if (ret)
return ret;
- if (generic_phy_valid(&priv->phy)) {
- ret = generic_phy_exit(&priv->phy);
- if (ret)
- return ret;
- }
+ ret = ehci_shutdown_phy(dev);
+ if (ret)
+ return ret;
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
deleted file mode 100644
index 9d23577..0000000
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2010, Chris Zhang <chris@seamicro.com>
- *
- * Author: Chris Zhang <chris@seamicro.com>
- * This code is based on ehci freescale driver
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <usb.h>
-#include <asm/io.h>
-
-#include "ehci.h"
-
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- *hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
- *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
- HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
- return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
- return 0;
-}
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index bf55a71..5bdd799 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -25,6 +25,56 @@
int reset_count; /* number of reset in reset list */
};
+static int ohci_setup_phy(struct udevice *dev, int index)
+{
+ struct generic_ohci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = generic_phy_get_by_index(dev, index, &priv->phy);
+ if (ret) {
+ if (ret != -ENOENT) {
+ dev_err(dev, "failed to get usb phy\n");
+ return ret;
+ }
+ } else {
+ ret = generic_phy_init(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to init usb phy\n");
+ return ret;
+ }
+
+ ret = generic_phy_power_on(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power on usb phy\n");
+ return generic_phy_exit(&priv->phy);
+ }
+ }
+
+ return 0;
+}
+
+static int ohci_shutdown_phy(struct udevice *dev)
+{
+ struct generic_ohci *priv = dev_get_priv(dev);
+ int ret = 0;
+
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_power_off(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power off usb phy\n");
+ return ret;
+ }
+
+ ret = generic_phy_exit(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power off usb phy\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int ohci_usb_probe(struct udevice *dev)
{
struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
@@ -47,14 +97,14 @@
err = clk_enable(&priv->clocks[i]);
if (err) {
- pr_err("failed to enable clock %d\n", i);
+ dev_err(dev, "failed to enable clock %d\n", i);
clk_free(&priv->clocks[i]);
goto clk_err;
}
priv->clock_count++;
}
} else if (clock_nb != -ENOENT) {
- pr_err("failed to get clock phandle(%d)\n", clock_nb);
+ dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb);
return clock_nb;
}
@@ -74,31 +124,20 @@
err = reset_deassert(&priv->resets[i]);
if (err) {
- pr_err("failed to deassert reset %d\n", i);
+ dev_err(dev, "failed to deassert reset %d\n", i);
reset_free(&priv->resets[i]);
goto reset_err;
}
priv->reset_count++;
}
} else if (reset_nb != -ENOENT) {
- pr_err("failed to get reset phandle(%d)\n", reset_nb);
+ dev_err(dev, "failed to get reset phandle(%d)\n", reset_nb);
goto clk_err;
}
- err = generic_phy_get_by_index(dev, 0, &priv->phy);
- if (err) {
- if (err != -ENOENT) {
- pr_err("failed to get usb phy\n");
- goto reset_err;
- }
- } else {
-
- err = generic_phy_init(&priv->phy);
- if (err) {
- pr_err("failed to init usb phy\n");
- goto reset_err;
- }
- }
+ err = ohci_setup_phy(dev, 0);
+ if (err)
+ goto reset_err;
err = ohci_register(dev, regs);
if (err)
@@ -107,20 +146,18 @@
return 0;
phy_err:
- if (generic_phy_valid(&priv->phy)) {
- ret = generic_phy_exit(&priv->phy);
- if (ret)
- pr_err("failed to release phy\n");
- }
+ ret = ohci_shutdown_phy(dev);
+ if (ret)
+ dev_err(dev, "failed to shutdown usb phy\n");
reset_err:
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
- pr_err("failed to assert all resets\n");
+ dev_err(dev, "failed to assert all resets\n");
clk_err:
ret = clk_release_all(priv->clocks, priv->clock_count);
if (ret)
- pr_err("failed to disable all clocks\n");
+ dev_err(dev, "failed to disable all clocks\n");
return err;
}
@@ -134,11 +171,9 @@
if (ret)
return ret;
- if (generic_phy_valid(&priv->phy)) {
- ret = generic_phy_exit(&priv->phy);
- if (ret)
- return ret;
- }
+ ret = ohci_shutdown_phy(dev);
+ if (ret)
+ return ret;
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 258d1cd..c100735 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -22,7 +22,8 @@
DECLARE_GLOBAL_DATA_PTR;
struct xhci_dwc3_platdata {
- struct phy usb_phy;
+ struct phy *usb_phys;
+ int num_phys;
};
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
@@ -112,9 +113,89 @@
}
#ifdef CONFIG_DM_USB
-static int xhci_dwc3_probe(struct udevice *dev)
+static int xhci_dwc3_setup_phy(struct udevice *dev, int count)
{
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ int i, ret;
+
+ if (!count)
+ return 0;
+
+ plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
+ GFP_KERNEL);
+ if (!plat->usb_phys)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, dev->name);
+ return ret;
+ }
+
+ ++plat->num_phys;
+ }
+
+ for (i = 0; i < plat->num_phys; i++) {
+ ret = generic_phy_init(&plat->usb_phys[i]);
+ if (ret) {
+ pr_err("Can't init USB PHY%d for %s\n",
+ i, dev->name);
+ goto phys_init_err;
+ }
+ }
+
+ for (i = 0; i < plat->num_phys; i++) {
+ ret = generic_phy_power_on(&plat->usb_phys[i]);
+ if (ret) {
+ pr_err("Can't power USB PHY%d for %s\n",
+ i, dev->name);
+ goto phys_poweron_err;
+ }
+ }
+
+ return 0;
+
+
+phys_poweron_err:
+ for (; i >= 0; i--)
+ generic_phy_power_off(&plat->usb_phys[i]);
+
+ for (i = 0; i < plat->num_phys; i++)
+ generic_phy_exit(&plat->usb_phys[i]);
+
+ return ret;
+
+phys_init_err:
+ for (; i >= 0; i--)
+ generic_phy_exit(&plat->usb_phys[i]);
+
+ return ret;
+}
+
+static int xhci_dwc3_shutdown_phy(struct udevice *dev)
+{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ int i, ret;
+
+ for (i = 0; i < plat->num_phys; i++) {
+ if (!generic_phy_valid(&plat->usb_phys[i]))
+ continue;
+
+ ret = generic_phy_power_off(&plat->usb_phys[i]);
+ ret |= generic_phy_exit(&plat->usb_phys[i]);
+ if (ret) {
+ pr_err("Can't shutdown USB PHY%d for %s\n",
+ i, dev->name);
+ }
+ }
+
+ return 0;
+}
+
+static int xhci_dwc3_probe(struct udevice *dev)
+{
struct xhci_hcor *hcor;
struct xhci_hccr *hccr;
struct dwc3 *dwc3_reg;
@@ -125,19 +206,10 @@
hcor = (struct xhci_hcor *)((uintptr_t)hccr +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
- ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
- if (ret) {
- if (ret != -ENOENT) {
- pr_err("Failed to get USB PHY for %s\n", dev->name);
- return ret;
- }
- } else {
- ret = generic_phy_init(&plat->usb_phy);
- if (ret) {
- pr_err("Can't init USB PHY for %s\n", dev->name);
- return ret;
- }
- }
+ ret = xhci_dwc3_setup_phy(dev, dev_count_phandle_with_args(
+ dev, "phys", "#phy-cells"));
+ if (ret)
+ return ret;
dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
@@ -155,16 +227,7 @@
static int xhci_dwc3_remove(struct udevice *dev)
{
- struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- if (generic_phy_valid(&plat->usb_phy)) {
- ret = generic_phy_exit(&plat->usb_phy);
- if (ret) {
- pr_err("Can't deinit USB PHY for %s\n", dev->name);
- return ret;
- }
- }
+ xhci_dwc3_shutdown_phy(dev);
return xhci_deregister(dev);
}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..45a105d 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -38,7 +38,6 @@
config VIDEO_BPP8
bool "Support 8-bit-per-pixel displays"
depends on DM_VIDEO
- default n if ARCH_SUNXI
default y if DM_VIDEO
help
Support drawing text and bitmaps onto a 8-bit-per-pixel display.
@@ -49,7 +48,6 @@
config VIDEO_BPP16
bool "Support 16-bit-per-pixel displays"
depends on DM_VIDEO
- default n if ARCH_SUNXI
default y if DM_VIDEO
help
Support drawing text and bitmaps onto a 16-bit-per-pixel display.
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 0b25897..5b7795d 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -768,7 +768,7 @@
break;
case '\n': /* next line */
- if (console_col || (!console_col && nl))
+ if (console_col || nl)
console_newline(1);
nl = 1;
break;
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 6ec4f89..26db73b 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -853,9 +853,10 @@
do {
ret = lcdc_irq_handler();
udelay(1000);
- } while (!(ret & event));
+ --timeout;
+ } while (!(ret & event) && timeout);
- if (timeout <= 0) {
+ if (!(ret & event)) {
printf("%s: event %d not hit\n", __func__, event);
return -1;
}
diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 30e4020..3a6ef62 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -321,7 +321,7 @@
static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
exynos_dp_set_training_pattern(regs, DP_NONE);
@@ -339,7 +339,7 @@
struct exynos_dp *regs, unsigned char enable)
{
unsigned char data;
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
&data);
@@ -366,7 +366,7 @@
static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
unsigned char enhance_mode)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
if (ret != EXYNOS_DP_SUCCESS) {
@@ -416,7 +416,7 @@
static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
unsigned char lane_num, unsigned char *sw, unsigned char *em)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char buf;
unsigned int dpcd_addr;
unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
@@ -484,7 +484,7 @@
static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
struct exynos_dp_priv *priv)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char lane_stat;
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
unsigned int i;
@@ -594,7 +594,7 @@
static unsigned int exynos_dp_process_equalizer_training(
struct exynos_dp *regs, struct exynos_dp_priv *priv)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char lane_stat, adj_req_sw, adj_req_em, i;
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
unsigned char interlane_aligned = 0;
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index fbd7bf7..f40e57b 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -32,16 +32,18 @@
uint duty_cycle;
int ret;
- plat = dev_get_uclass_platdata(priv->reg);
- debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__, dev->name,
- priv->reg->name, plat->name);
- ret = regulator_set_enable(priv->reg, true);
- if (ret) {
- debug("%s: Cannot enable regulator for PWM '%s'\n", __func__,
- dev->name);
- return ret;
+ if (priv->reg) {
+ plat = dev_get_uclass_platdata(priv->reg);
+ debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__,
+ dev->name, priv->reg->name, plat->name);
+ ret = regulator_set_enable(priv->reg, true);
+ if (ret) {
+ debug("%s: Cannot enable regulator for PWM '%s'\n",
+ __func__, dev->name);
+ return ret;
+ }
+ mdelay(120);
}
- mdelay(120);
duty_cycle = priv->period_ns * (priv->default_level - priv->min_level) /
(priv->max_level - priv->min_level + 1);
@@ -68,10 +70,8 @@
debug("%s: start\n", __func__);
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
- if (ret) {
+ if (ret)
debug("%s: Cannot get power supply: ret=%d\n", __func__, ret);
- return ret;
- }
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index 953b47f..a7fa9c5 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -136,7 +136,7 @@
struct rk_mipi_priv *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- if (IS_ERR(priv->grf)) {
+ if (IS_ERR_OR_NULL(priv->grf)) {
debug("%s: Get syscon grf failed (ret=%p)\n",
__func__, priv->grf);
return -ENXIO;
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index 9ef202b..b936fce 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -128,7 +128,7 @@
struct rk_mipi_priv *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- if (priv->grf <= 0) {
+ if (IS_ERR_OR_NULL(priv->grf)) {
debug("%s: Get syscon grf failed (ret=%p)\n",
__func__, priv->grf);
return -ENXIO;
diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h
index 26e483c..5d00bff 100644
--- a/drivers/video/stb_truetype.h
+++ b/drivers/video/stb_truetype.h
@@ -1993,7 +1993,7 @@
STBTT_assert(fabs(area) <= 1.01f);
- scanline[x2] += area + sign * (1-((x2-x2)+(x_bottom-x2))/2) * (sy1-y_crossing);
+ scanline[x2] += area + sign * (1-(x_bottom-x2)/2) * (sy1-y_crossing);
scanline_fill[x2] += sign * (sy1-sy0);
}
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index b417ac2..e160c77 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -1,8 +1,7 @@
/*
- * Copyright (C) STMicroelectronics SA 2017
- *
- * Authors: Philippe Cornu <philippe.cornu@st.com>
- * Yannick Fertre <yannick.fertre@st.com>
+ * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -11,6 +10,7 @@
#include <clk.h>
#include <dm.h>
#include <panel.h>
+#include <reset.h>
#include <video.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
@@ -138,7 +138,9 @@
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
+#define BF1_CA 0x400 /* Constant Alpha */
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA 0x005 /* 1 - Constant Alpha */
enum stm32_ltdc_pix_fmt {
PF_ARGB8888 = 0,
@@ -161,11 +163,17 @@
pf = PF_RGB565;
break;
+ case VIDEO_BPP32:
+ pf = PF_ARGB8888;
+ break;
+
+ case VIDEO_BPP8:
+ pf = PF_L8;
+ break;
+
case VIDEO_BPP1:
case VIDEO_BPP2:
case VIDEO_BPP4:
- case VIDEO_BPP8:
- case VIDEO_BPP32:
default:
debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
@@ -178,6 +186,23 @@
return (u32)pf;
}
+static bool has_alpha(u32 fmt)
+{
+ switch (fmt) {
+ case PF_ARGB8888:
+ case PF_ARGB1555:
+ case PF_ARGB4444:
+ case PF_AL44:
+ case PF_AL88:
+ return true;
+ case PF_RGB888:
+ case PF_RGB565:
+ case PF_L8:
+ default:
+ return false;
+ }
+}
+
static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
{
/* Reload configuration immediately & enable LTDC */
@@ -219,6 +244,8 @@
val = (total_w << 16) | total_h;
clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+ setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
+
/* Signal polarities */
val = 0;
debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
@@ -245,6 +272,7 @@
u32 line_length;
u32 bus_width;
u32 val, tmp, bpp;
+ u32 format;
x0 = priv->crop_x;
x1 = priv->crop_x + priv->crop_w - 1;
@@ -275,15 +303,18 @@
clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
/* Pixel format */
- val = stm32_ltdc_get_pixel_format(priv->l2bpp);
- clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
+ format = stm32_ltdc_get_pixel_format(priv->l2bpp);
+ clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
/* Constant alpha value */
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
+ /* Specifies the blending factors : with or without pixel alpha */
+ /* Manage hw-specific capabilities */
+ val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
+
/* Blending factors */
- clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
- BF1_PAXCA | BF2_1PAXCA);
+ clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
/* Frame buffer line number */
clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
@@ -301,8 +332,9 @@
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *panel;
- struct clk pclk, pxclk;
- int ret;
+ struct clk pclk;
+ struct reset_ctl rst;
+ int rate, ret;
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
@@ -310,6 +342,28 @@
return -EINVAL;
}
+ ret = clk_get_by_index(dev, 0, &pclk);
+ if (ret) {
+ debug("%s: peripheral clock get error %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = clk_enable(&pclk);
+ if (ret) {
+ debug("%s: peripheral clock enable error %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = reset_get_by_index(dev, 0, &rst);
+ if (ret) {
+ debug("%s: missing ltdc hardware reset\n", __func__);
+ return -ENODEV;
+ }
+
+ /* Reset */
+ reset_deassert(&rst);
+
ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
debug("%s: panel device error %d\n", __func__, ret);
@@ -323,31 +377,24 @@
return ret;
}
- ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
- 0, &priv->timing);
+ ret = fdtdec_decode_display_timing(gd->fdt_blob,
+ dev_of_offset(dev), 0,
+ &priv->timing);
if (ret) {
- debug("%s: decode display timing error %d\n", __func__, ret);
+ debug("%s: decode display timing error %d\n",
+ __func__, ret);
return -EINVAL;
}
- ret = clk_get_by_name(dev, "pclk", &pclk);
- if (ret) {
- debug("%s: peripheral clock get error %d\n", __func__, ret);
- return ret;
+ rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
+ if (rate < 0) {
+ debug("%s: fail to set pixel clock %d hz %d hz\n",
+ __func__, priv->timing.pixelclock.typ, rate);
+ return rate;
}
- ret = clk_enable(&pclk);
- if (ret) {
- debug("%s: peripheral clock enable error %d\n", __func__, ret);
- return ret;
- }
-
- /* Verify pixel clock value if any & inform user accordingly */
- ret = clk_get_by_name(dev, "pxclk", &pxclk);
- if (!ret) {
- if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
- printf("Warning: please adjust ltdc pixel clock\n");
- }
+ debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
+ priv->timing.pixelclock.typ, rate);
/* TODO Below parameters are hard-coded for the moment... */
priv->l2bpp = VIDEO_BPP16;
@@ -397,10 +444,10 @@
};
U_BOOT_DRIVER(stm32_ltdc) = {
- .name = "stm32_ltdc",
- .id = UCLASS_VIDEO,
- .of_match = stm32_ltdc_ids,
- .probe = stm32_ltdc_probe,
- .bind = stm32_ltdc_bind,
+ .name = "stm32_display",
+ .id = UCLASS_VIDEO,
+ .of_match = stm32_ltdc_ids,
+ .probe = stm32_ltdc_probe,
+ .bind = stm32_ltdc_bind,
.priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),
};
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index f191ef1..4da169f 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <efi_loader.h>
#include <asm/arch/clock.h>
#include <asm/arch/display.h>
@@ -1207,6 +1208,13 @@
gd->bd->bi_dram[0].size - sunxi_display.fb_size;
sunxi_engines_init();
+#ifdef CONFIG_EFI_LOADER
+ efi_add_memory_map(gd->fb_base,
+ ALIGN(sunxi_display.fb_size, EFI_PAGE_SIZE) >>
+ EFI_PAGE_SHIFT,
+ EFI_RESERVED_MEMORY_TYPE, false);
+#endif
+
fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;
sunxi_display.fb_addr = gd->fb_base;
if (overscan_offset) {
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 5f63c12..5553d62 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -13,7 +13,16 @@
#include <dm.h>
#include <video.h>
#include <video_console.h>
-#include <video_font.h> /* Get font data, width and height */
+#include <video_font.h> /* Bitmap font for code page 437 */
+
+/*
+ * Structure to describe a console color
+ */
+struct vid_rgb {
+ u32 r;
+ u32 g;
+ u32 b;
+};
/* By default we scroll by a single line */
#ifndef CONFIG_CONSOLE_SCROLL_LINES
@@ -108,38 +117,45 @@
video_sync(dev->parent);
}
-static const struct {
- unsigned r;
- unsigned g;
- unsigned b;
-} colors[] = {
+static const struct vid_rgb colors[VID_COLOR_COUNT] = {
{ 0x00, 0x00, 0x00 }, /* black */
- { 0xff, 0x00, 0x00 }, /* red */
- { 0x00, 0xff, 0x00 }, /* green */
+ { 0xc0, 0x00, 0x00 }, /* red */
+ { 0x00, 0xc0, 0x00 }, /* green */
+ { 0xc0, 0x60, 0x00 }, /* brown */
+ { 0x00, 0x00, 0xc0 }, /* blue */
+ { 0xc0, 0x00, 0xc0 }, /* magenta */
+ { 0x00, 0xc0, 0xc0 }, /* cyan */
+ { 0xc0, 0xc0, 0xc0 }, /* light gray */
+ { 0x80, 0x80, 0x80 }, /* gray */
+ { 0xff, 0x00, 0x00 }, /* bright red */
+ { 0x00, 0xff, 0x00 }, /* bright green */
{ 0xff, 0xff, 0x00 }, /* yellow */
- { 0x00, 0x00, 0xff }, /* blue */
- { 0xff, 0x00, 0xff }, /* magenta */
- { 0x00, 0xff, 0xff }, /* cyan */
+ { 0x00, 0x00, 0xff }, /* bright blue */
+ { 0xff, 0x00, 0xff }, /* bright magenta */
+ { 0x00, 0xff, 0xff }, /* bright cyan */
{ 0xff, 0xff, 0xff }, /* white */
};
-static void set_color(struct video_priv *priv, unsigned idx, unsigned *c)
+u32 vid_console_color(struct video_priv *priv, unsigned int idx)
{
switch (priv->bpix) {
case VIDEO_BPP16:
- *c = ((colors[idx].r >> 3) << 0) |
- ((colors[idx].g >> 2) << 5) |
- ((colors[idx].b >> 3) << 11);
- break;
+ return ((colors[idx].r >> 3) << 11) |
+ ((colors[idx].g >> 2) << 5) |
+ ((colors[idx].b >> 3) << 0);
case VIDEO_BPP32:
- *c = 0xff000000 |
- (colors[idx].r << 0) |
- (colors[idx].g << 8) |
- (colors[idx].b << 16);
- break;
+ return (colors[idx].r << 16) |
+ (colors[idx].g << 8) |
+ (colors[idx].b << 0);
default:
- /* unsupported, leave current color in place */
- break;
+ /*
+ * For unknown bit arrangements just support
+ * black and white.
+ */
+ if (idx)
+ return 0xffffff; /* white */
+ else
+ return 0x000000; /* black */
}
}
@@ -270,18 +286,30 @@
s++;
switch (val) {
+ case 0:
+ /* all attributes off */
+ video_set_default_colors(vid_priv);
+ break;
+ case 1:
+ /* bold */
+ vid_priv->fg_col_idx |= 8;
+ vid_priv->colour_fg = vid_console_color(
+ vid_priv, vid_priv->fg_col_idx);
+ break;
case 30 ... 37:
- /* fg color */
- set_color(vid_priv, val - 30,
- (unsigned *)&vid_priv->colour_fg);
+ /* foreground color */
+ vid_priv->fg_col_idx &= ~7;
+ vid_priv->fg_col_idx |= val - 30;
+ vid_priv->colour_fg = vid_console_color(
+ vid_priv, vid_priv->fg_col_idx);
break;
case 40 ... 47:
- /* bg color */
- set_color(vid_priv, val - 40,
- (unsigned *)&vid_priv->colour_bg);
+ /* background color */
+ vid_priv->colour_bg = vid_console_color(
+ vid_priv, val - 40);
break;
default:
- /* unknown/unsupported */
+ /* ignore unsupported SGR parameter */
break;
}
}
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index dcaceed..b5bb8e0 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -91,15 +91,41 @@
{
struct video_priv *priv = dev_get_uclass_priv(dev);
- if (priv->bpix == VIDEO_BPP32) {
+ switch (priv->bpix) {
+ case VIDEO_BPP16: {
+ u16 *ppix = priv->fb;
+ u16 *end = priv->fb + priv->fb_size;
+
+ while (ppix < end)
+ *ppix++ = priv->colour_bg;
+ break;
+ }
+ case VIDEO_BPP32: {
u32 *ppix = priv->fb;
u32 *end = priv->fb + priv->fb_size;
while (ppix < end)
*ppix++ = priv->colour_bg;
- } else {
- memset(priv->fb, priv->colour_bg, priv->fb_size);
+ break;
}
+ default:
+ memset(priv->fb, priv->colour_bg, priv->fb_size);
+ break;
+ }
+}
+
+void video_set_default_colors(struct video_priv *priv)
+{
+#ifdef CONFIG_SYS_WHITE_ON_BLACK
+ /* White is used when switching to bold, use light gray here */
+ priv->fg_col_idx = VID_LIGHT_GRAY;
+ priv->colour_fg = vid_console_color(priv, VID_LIGHT_GRAY);
+ priv->colour_bg = vid_console_color(priv, VID_BLACK);
+#else
+ priv->fg_col_idx = VID_BLACK;
+ priv->colour_fg = vid_console_color(priv, VID_BLACK);
+ priv->colour_bg = vid_console_color(priv, VID_WHITE);
+#endif
}
/* Flush video activity to the caches */
@@ -191,12 +217,8 @@
priv->line_length = priv->xsize * VNBYTES(priv->bpix);
priv->fb_size = priv->line_length * priv->ysize;
- /* Set up colours - we could in future support other colours */
-#ifdef CONFIG_SYS_WHITE_ON_BLACK
- priv->colour_fg = 0xffffff;
-#else
- priv->colour_bg = 0xffffff;
-#endif
+ /* Set up colors */
+ video_set_default_colors(priv);
if (!CONFIG_IS_ENABLED(NO_FB_CLEAR))
video_clear(dev);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index fc46b67..dca2c90 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1,5 +1,13 @@
menu "Watchdog Timer Support"
+config WATCHDOG
+ bool "Enable U-Boot watchdog reset"
+ help
+ This option enables U-Boot watchdog support where U-Boot is using
+ watchdog_reset function to service watchdog device in U-Boot. Enable
+ this option if you want to service enabled watchdog by U-Boot. Disable
+ this option if you want U-Boot to start watchdog but never service it.
+
config HW_WATCHDOG
bool
@@ -48,9 +56,9 @@
bool "Enable Watchdog Timer support for Sandbox"
depends on SANDBOX && WDT
help
- Enable Watchdog Timer support in Sandbox. This is a dummy device that
- can be probed and supports all of the methods of WDT, but does not
- really do anything.
+ Enable Watchdog Timer support in Sandbox. This is a dummy device that
+ can be probed and supports all of the methods of WDT, but does not
+ really do anything.
config WDT_ASPEED
bool "Aspeed ast2400/ast2500 watchdog timer support"
@@ -78,4 +86,12 @@
Select this to enable Orion watchdog timer, which can be found on some
Marvell Armada chips.
+config WDT_CDNS
+ bool "Cadence watchdog timer support"
+ depends on WDT
+ imply WATCHDOG
+ help
+ Select this to enable Cadence watchdog timer, which can be found on some
+ Xilinx Microzed Platform.
+
endmenu
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index ab6a6b7..4fee6db 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,3 +22,5 @@
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
+obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
+obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o
diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c
new file mode 100644
index 0000000..71733cf
--- /dev/null
+++ b/drivers/watchdog/cdns_wdt.c
@@ -0,0 +1,276 @@
+/*
+ * Cadence WDT driver - Used by Xilinx Zynq
+ * Reference: Linux kernel Cadence watchdog driver.
+ *
+ * Author(s): Shreenidhi Shedi <yesshedi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <clk.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cdns_regs {
+ u32 zmr; /* WD Zero mode register, offset - 0x0 */
+ u32 ccr; /* Counter Control Register offset - 0x4 */
+ u32 restart; /* Restart key register, offset - 0x8 */
+ u32 status; /* Status Register, offset - 0xC */
+};
+
+struct cdns_wdt_priv {
+ bool rst;
+ u32 timeout;
+ void __iomem *reg;
+ struct cdns_regs *regs;
+};
+
+#define CDNS_WDT_DEFAULT_TIMEOUT 10
+
+/* Supports 1 - 516 sec */
+#define CDNS_WDT_MIN_TIMEOUT 1
+#define CDNS_WDT_MAX_TIMEOUT 516
+
+/* Restart key */
+#define CDNS_WDT_RESTART_KEY 0x00001999
+
+/* Counter register access key */
+#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000
+
+/* Counter value divisor */
+#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000
+
+/* Clock prescaler value and selection */
+#define CDNS_WDT_PRESCALE_64 64
+#define CDNS_WDT_PRESCALE_512 512
+#define CDNS_WDT_PRESCALE_4096 4096
+#define CDNS_WDT_PRESCALE_SELECT_64 1
+#define CDNS_WDT_PRESCALE_SELECT_512 2
+#define CDNS_WDT_PRESCALE_SELECT_4096 3
+
+/* Input clock frequency */
+#define CDNS_WDT_CLK_75MHZ 75000000
+
+/* Counter maximum value */
+#define CDNS_WDT_COUNTER_MAX 0xFFF
+
+/********************* Register Map **********************************/
+
+/*
+ * Zero Mode Register - This register controls how the time out is indicated
+ * and also contains the access code to allow writes to the register (0xABC).
+ */
+#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
+#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */
+#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */
+#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */
+#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */
+
+/*
+ * Counter Control register - This register controls how fast the timer runs
+ * and the reset value and also contains the access code to allow writes to
+ * the register.
+ */
+#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */
+
+/* Write access to Registers */
+static inline void cdns_wdt_writereg(u32 *addr, u32 val)
+{
+ writel(val, addr);
+}
+
+/**
+ * cdns_wdt_reset - Reload the watchdog timer (i.e. pat the watchdog).
+ *
+ * @dev: Watchdog device
+ *
+ * Write the restart key value (0x00001999) to the restart register.
+ *
+ * Return: Always 0
+ */
+static int cdns_wdt_reset(struct udevice *dev)
+{
+ struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+ debug("%s\n", __func__);
+
+ cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
+
+ return 0;
+}
+
+/**
+ * cdns_wdt_start - Enable and start the watchdog.
+ *
+ * @dev: Watchdog device
+ * @timeout: Timeout value
+ * @flags: Driver flags
+ *
+ * The counter value is calculated according to the formula:
+ * count = (timeout * clock) / prescaler + 1.
+ *
+ * The calculated count is divided by 0x1000 to obtain the field value
+ * to write to counter control register.
+ *
+ * Clears the contents of prescaler and counter reset value. Sets the
+ * prescaler to 4096 and the calculated count and access key
+ * to write to CCR Register.
+ *
+ * Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit)
+ * or Interrupt signal(IRQEN) with a specified cycles and the access
+ * key to write to ZMR Register.
+ *
+ * Return: Upon success 0, failure -1.
+ */
+static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ ulong clk_f;
+ u32 count, prescaler, ctrl_clksel, data = 0;
+ struct clk clock;
+ struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+ if (clk_get_by_index(dev, 0, &clock) < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return -1;
+ }
+
+ clk_f = clk_get_rate(&clock);
+ if (IS_ERR_VALUE(clk_f)) {
+ dev_err(dev, "failed to get rate\n");
+ return -1;
+ }
+
+ debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout);
+
+ if ((timeout < CDNS_WDT_MIN_TIMEOUT) ||
+ (timeout > CDNS_WDT_MAX_TIMEOUT)) {
+ timeout = priv->timeout;
+ }
+
+ if (clk_f <= CDNS_WDT_CLK_75MHZ) {
+ prescaler = CDNS_WDT_PRESCALE_512;
+ ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512;
+ } else {
+ prescaler = CDNS_WDT_PRESCALE_4096;
+ ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096;
+ }
+
+ /*
+ * Counter value divisor to obtain the value of
+ * counter reset to be written to control register.
+ */
+ count = (timeout * (clk_f / prescaler)) /
+ CDNS_WDT_COUNTER_VALUE_DIVISOR + 1;
+
+ if (count > CDNS_WDT_COUNTER_MAX)
+ count = CDNS_WDT_COUNTER_MAX;
+
+ cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL);
+
+ count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
+
+ /* Write counter access key first to be able write to register */
+ data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel;
+ cdns_wdt_writereg(&priv->regs->ccr, data);
+
+ data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 |
+ CDNS_WDT_ZMR_ZKEY_VAL;
+
+ /* Reset on timeout if specified in device tree. */
+ if (priv->rst) {
+ data |= CDNS_WDT_ZMR_RSTEN_MASK;
+ data &= ~CDNS_WDT_ZMR_IRQEN_MASK;
+ } else {
+ data &= ~CDNS_WDT_ZMR_RSTEN_MASK;
+ data |= CDNS_WDT_ZMR_IRQEN_MASK;
+ }
+
+ cdns_wdt_writereg(&priv->regs->zmr, data);
+ cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
+
+ return 0;
+}
+
+/**
+ * cdns_wdt_stop - Stop the watchdog.
+ *
+ * @dev: Watchdog device
+ *
+ * Read the contents of the ZMR register, clear the WDEN bit in the register
+ * and set the access key for successful write.
+ *
+ * Return: Always 0
+ */
+static int cdns_wdt_stop(struct udevice *dev)
+{
+ struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+ cdns_wdt_writereg(&priv->regs->zmr,
+ CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK));
+
+ return 0;
+}
+
+/**
+ * cdns_wdt_probe - Probe call for the device.
+ *
+ * @dev: Handle to the udevice structure.
+ *
+ * Return: Always 0.
+ */
+static int cdns_wdt_probe(struct udevice *dev)
+{
+ struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+ debug("%s: Probing wdt%u\n", __func__, dev->seq);
+
+ priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs));
+
+ cdns_wdt_stop(dev);
+
+ return 0;
+}
+
+static int cdns_wdt_ofdata_to_platdata(struct udevice *dev)
+{
+ int node = dev_of_offset(dev);
+ struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->regs = devfdt_get_addr_ptr(dev);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+
+ priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec",
+ CDNS_WDT_DEFAULT_TIMEOUT);
+
+ priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout");
+
+ debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst);
+
+ return 0;
+}
+
+static const struct wdt_ops cdns_wdt_ops = {
+ .start = cdns_wdt_start,
+ .reset = cdns_wdt_reset,
+ .stop = cdns_wdt_stop,
+};
+
+static const struct udevice_id cdns_wdt_ids[] = {
+ { .compatible = "cdns,wdt-r1p2" },
+ {}
+};
+
+U_BOOT_DRIVER(cdns_wdt) = {
+ .name = "cdns_wdt",
+ .id = UCLASS_WDT,
+ .of_match = cdns_wdt_ids,
+ .probe = cdns_wdt_probe,
+ .priv_auto_alloc_size = sizeof(struct cdns_wdt_priv),
+ .ofdata_to_platdata = cdns_wdt_ofdata_to_platdata,
+ .ops = &cdns_wdt_ops,
+};
diff --git a/drivers/watchdog/mpc8xx_wdt.c b/drivers/watchdog/mpc8xx_wdt.c
new file mode 100644
index 0000000..ded80c4
--- /dev/null
+++ b/drivers/watchdog/mpc8xx_wdt.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2017 CS Systemes d'Information
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/cpm_8xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void hw_watchdog_reset(void)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ out_be16(&immap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
+ out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
+}
+
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 7b1f429..d724c96 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -53,16 +53,25 @@
{
struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
- /* wait for posted write to complete */
- while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
- ;
+ /*
+ * Somebody just triggered watchdog reset and write to WTGR register
+ * is in progress. It is resetting right now, no need to trigger it
+ * again
+ */
+ if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
+ return;
wdt_trgr_pattern = ~wdt_trgr_pattern;
writel(wdt_trgr_pattern, &wdt->wdtwtgr);
- /* wait for posted write to complete */
- while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR))
- ;
+ /*
+ * Don't wait for posted write to complete, i.e. don't check
+ * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
+ * WTGR register outside of this func, and if entering it
+ * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
+ * was just triggered. This prevents us from wasting time in busy
+ * polling of WDT_WWPS_PEND_WTGR bit.
+ */
}
static int omap_wdt_set_timeout(unsigned int timeout)
diff --git a/env/Kconfig b/env/Kconfig
index a3c6298..f403906 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -152,7 +152,6 @@
bool "Environment in an MMC device"
depends on !CHAIN_OF_TRUST
depends on MMC
- default y if ARCH_SUNXI
default y if ARCH_EXYNOS4
default y if MX6SX || MX7D
default y if TEGRA30 || TEGRA124
@@ -360,12 +359,6 @@
the environment in. This will enable redundant environments in UBI.
It is assumed that both volumes are in the same MTD partition.
- - CONFIG_UBI_SILENCE_MSG
- - CONFIG_UBIFS_SILENCE_MSG
-
- You will probably want to define these to avoid a really noisy system
- when storing the env in UBI.
-
config ENV_FAT_INTERFACE
string "Name of the block device for the environment"
depends on ENV_IS_IN_FAT
@@ -486,4 +479,29 @@
endif
+config USE_DEFAULT_ENV_FILE
+ bool "Create default environment from file"
+ help
+ Normally, the default environment is automatically generated
+ based on the settings of various CONFIG_* options, as well
+ as the CONFIG_EXTRA_ENV_SETTINGS. By selecting this option,
+ you can instead define the entire default environment in an
+ external file.
+
+config DEFAULT_ENV_FILE
+ string "Path to default environment file"
+ depends on USE_DEFAULT_ENV_FILE
+ help
+ The path containing the default environment. The format is
+ the same as accepted by the mkenvimage tool: lines
+ containing key=value pairs, blank lines and lines beginning
+ with # are ignored.
+
+config ENV_VARS_UBOOT_RUNTIME_CONFIG
+ bool "Add run-time information to the environment"
+ help
+ Enable this in order to add variables describing certain
+ run-time determined information about the hardware to the
+ environment. These will be named board_name, board_rev.
+
endmenu
diff --git a/env/embedded.c b/env/embedded.c
index 43694db..9b0a6a3 100644
--- a/env/embedded.c
+++ b/env/embedded.c
@@ -35,11 +35,11 @@
* a seperate section.
*/
#if defined(USE_HOSTCC) /* Native for 'tools/envcrc' */
-# define __UBOOT_ENV_SECTION__ /*XXX DO_NOT_DEL_THIS_COMMENT*/
+# define __UBOOT_ENV_SECTION__(name) /*XXX DO_NOT_DEL_THIS_COMMENT*/
#else /* Environment is embedded in U-Boot's .text section */
/* XXX - This only works with GNU C */
-# define __UBOOT_ENV_SECTION__ __attribute__ ((section(".text")))
+# define __UBOOT_ENV_SECTION__(name) __attribute__ ((section(".text."#name)))
#endif
/*
@@ -70,7 +70,7 @@
#include <env_default.h>
#ifdef CONFIG_ENV_ADDR_REDUND
-env_t redundand_environment __UBOOT_ENV_SECTION__ = {
+env_t redundand_environment __UBOOT_ENV_SECTION__(redundand_environment) = {
0, /* CRC Sum: invalid */
0, /* Flags: invalid */
{
@@ -87,7 +87,7 @@
* .data/.sdata section.
*
*/
-unsigned long env_size __UBOOT_ENV_SECTION__ = sizeof(env_t);
+unsigned long env_size __UBOOT_ENV_SECTION__(env_size) = sizeof(env_t);
/*
* Add in absolutes.
diff --git a/env/mmc.c b/env/mmc.c
index 6f11dec..bf7015c 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -158,7 +158,7 @@
if (!mmc)
return "!No MMC card found";
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct udevice *dev;
if (blk_get_from_parent(mmc->dev, &dev))
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 4140e2b..b01b111 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -221,7 +221,3 @@
#endif
return -ENOSYS;
}
-
-/*
- btrfs_list_subvols();
-*/
diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c
index b13ecb9..c15fca3 100644
--- a/fs/btrfs/ctree.c
+++ b/fs/btrfs/ctree.c
@@ -45,16 +45,6 @@
int low = 0, high = max, mid, ret;
struct btrfs_key *tmp;
- if (0) {
- int i;
- printf("\tsearching %llu %i\n", key->objectid, key->type);
- for (i = 0; i < max; ++i) {
- tmp = (struct btrfs_key *) ((u8 *) addr + i*item_size);
- printf("\t\t%llu %i\n", tmp->objectid, tmp->type);
- }
- printf("\n");
- }
-
while (low < high) {
mid = (low + high) / 2;
diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
index 6e1107d..46da8f1 100644
--- a/fs/cbfs/cbfs.c
+++ b/fs/cbfs/cbfs.c
@@ -168,9 +168,9 @@
struct cbfs_header *header)
{
struct cbfs_header *header_in_rom;
+ int32_t offset = *(u32 *)(end_of_rom - 3);
- header_in_rom = (struct cbfs_header *)(uintptr_t)
- *(u32 *)(end_of_rom - 3);
+ header_in_rom = (struct cbfs_header *)(end_of_rom + offset + 1);
swap_header(header, header_in_rom);
if (header->magic != good_magic || header->offset >
diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig
index e69de29..9da35b8 100644
--- a/fs/ubifs/Kconfig
+++ b/fs/ubifs/Kconfig
@@ -0,0 +1,6 @@
+config UBIFS_SILENCE_MSG
+ bool "UBIFS silence verbose messages"
+ default ENV_IS_IN_UBI
+ help
+ Make the verbose messages from UBIFS stop printing. This leaves
+ warnings and errors enabled.
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index effa8d9..2c478cb 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -1334,7 +1334,10 @@
static int mount_ubifs(struct ubifs_info *c)
{
int err;
- long long x, y;
+ long long x;
+#ifndef CONFIG_UBIFS_SILENCE_MSG
+ long long y;
+#endif
size_t sz;
c->ro_mount = !!(c->vfs_sb->s_flags & MS_RDONLY);
@@ -1613,7 +1616,9 @@
c->vi.ubi_num, c->vi.vol_id, c->vi.name,
c->ro_mount ? ", R/O mode" : "");
x = (long long)c->main_lebs * c->leb_size;
+#ifndef CONFIG_UBIFS_SILENCE_MSG
y = (long long)c->log_lebs * c->leb_size + c->max_bud_bytes;
+#endif
ubifs_msg(c, "LEB size: %d bytes (%d KiB), min./max. I/O unit sizes: %d bytes/%d bytes",
c->leb_size, c->leb_size >> 10, c->min_io_size,
c->max_write_size);
diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 1d89465..cbc4cb2 100644
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -611,16 +611,20 @@
/* misc.h */
#define mutex_lock_nested(...)
#define mutex_unlock_nested(...)
-#define mutex_is_locked(...) 0
+#define mutex_is_locked(...) 1
#endif
/* Version of this UBIFS implementation */
#define UBIFS_VERSION 1
/* Normal UBIFS messages */
+#ifdef CONFIG_UBIFS_SILENCE_MSG
+#define ubifs_msg(c, fmt, ...)
+#else
#define ubifs_msg(c, fmt, ...) \
pr_notice("UBIFS (ubi%d:%d): " fmt "\n", \
(c)->vi.ubi_num, (c)->vi.vol_id, ##__VA_ARGS__)
+#endif
/* UBIFS error messages */
#ifndef __UBOOT__
#define ubifs_err(c, fmt, ...) \
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index d3049d8..f734d53 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -37,7 +37,7 @@
unsigned long bi_dsp_freq; /* dsp core frequency */
unsigned long bi_ddr_freq; /* ddr frequency */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_M68K)
diff --git a/include/clk.h b/include/clk.h
index a7d95d3..b3a9fce 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -60,6 +60,23 @@
unsigned long id;
};
+/**
+ * struct clk_bulk - A handle to (allowing control of) a bulk of clocks.
+ *
+ * Clients provide storage for the clock bulk. The content of the structure is
+ * managed solely by the clock API. A clock bulk struct is
+ * initialized by "get"ing the clock bulk struct.
+ * The clock bulk struct is passed to all other bulk clock APIs to apply
+ * the API to all the clock in the bulk struct.
+ *
+ * @clks: An array of clock handles.
+ * @count: The number of clock handles in the clks array.
+ */
+struct clk_bulk {
+ struct clk *clks;
+ unsigned int count;
+};
+
#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
struct phandle_1_arg;
int clk_get_by_index_platdata(struct udevice *dev, int index,
@@ -83,6 +100,21 @@
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
/**
+ * clock_get_bulk - Get/request all clocks of a device.
+ *
+ * This looks up and requests all clocks of the client device; each device is
+ * assumed to have n clocks associated with it somehow, and this function finds
+ * and requests all of them in a separate structure. The mapping of client
+ * device clock indices to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev: The client device.
+ * @bulk A pointer to a clock bulk struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk);
+
+/**
* clock_get_by_name - Get/request a clock by name.
*
* This looks up and requests a clock. The name is relative to the client
@@ -120,6 +152,11 @@
return -ENOSYS;
}
+static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+ return -ENOSYS;
+}
+
static inline int clk_get_by_name(struct udevice *dev, const char *name,
struct clk *clk)
{
@@ -130,7 +167,6 @@
{
return -ENOSYS;
}
-
#endif
#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
@@ -151,6 +187,22 @@
#endif
/**
+ * clk_release_bulk() - Disable (turn off)/Free an array of previously
+ * requested clocks in a clock bulk struct.
+ *
+ * For each clock contained in the clock bulk struct, this function will check
+ * if clock has been previously requested and then will disable and free it.
+ *
+ * @clk: A clock bulk struct that was previously successfully
+ * requested by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+static inline int clk_release_bulk(struct clk_bulk *bulk)
+{
+ return clk_release_all(bulk->clks, bulk->count);
+}
+
+/**
* clk_request - Request a clock by provider-specific ID.
*
* This requests a clock using a provider-specific ID. Generally, this function
@@ -215,6 +267,15 @@
int clk_enable(struct clk *clk);
/**
+ * clk_enable_bulk() - Enable (turn on) all clocks in a clock bulk struct.
+ *
+ * @bulk: A clock bulk struct that was previously successfully requested
+ * by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+int clk_enable_bulk(struct clk_bulk *bulk);
+
+/**
* clk_disable() - Disable (turn off) a clock.
*
* @clk: A clock struct that was previously successfully requested by
@@ -223,6 +284,15 @@
*/
int clk_disable(struct clk *clk);
+/**
+ * clk_disable_bulk() - Disable (turn off) all clocks in a clock bulk struct.
+ *
+ * @bulk: A clock bulk struct that was previously successfully requested
+ * by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+int clk_disable_bulk(struct clk_bulk *bulk);
+
int soc_clk_dump(void);
#endif
diff --git a/include/command.h b/include/command.h
index 767cabb..56499b8 100644
--- a/include/command.h
+++ b/include/command.h
@@ -111,6 +111,8 @@
extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+ char * const argv[]);
/*
* Error codes that commands return to cmd_process(). We use the standard 0
* and 1 for success and failure, but add one more case - failure with a
diff --git a/include/common.h b/include/common.h
index 0fe9439..3087505 100644
--- a/include/common.h
+++ b/include/common.h
@@ -62,31 +62,19 @@
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#endif
+/* startup functions, used in:
+ * common/board_f.c
+ * common/init/board_init.c
+ * common/board_r.c
+ * common/board_info.c
+ */
+#include <init.h>
+
/*
* Function Prototypes
*/
-int dram_init(void);
-
-/**
- * dram_init_banksize() - Set up DRAM bank sizes
- *
- * This can be implemented by boards to set up the DRAM bank information in
- * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
- * is called.
- *
- * If this is not provided, a default implementation will try to set up a
- * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
- * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
- * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
- * get_effective_memsize().
- *
- * @return 0 if OK, -ve on error
- */
-int dram_init_banksize(void);
-
void hang (void) __attribute__ ((noreturn));
-int timer_init(void);
int cpu_init(void);
#include <display_options.h>
@@ -109,105 +97,11 @@
*/
int run_command_list(const char *cmd, int len, int flag);
-/* arch/$(ARCH)/lib/board.c */
-void board_init_f(ulong);
-void board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
-
-/**
- * ulong board_init_f_alloc_reserve - allocate reserved area
- *
- * This function is called by each architecture very early in the start-up
- * code to allow the C runtime to reserve space on the stack for writable
- * 'globals' such as GD and the malloc arena.
- *
- * @top: top of the reserve area, growing down.
- * @return: bottom of reserved area
- */
-ulong board_init_f_alloc_reserve(ulong top);
-
-/**
- * board_init_f_init_reserve - initialize the reserved area(s)
- *
- * This function is called once the C runtime has allocated the reserved
- * area on the stack. It must initialize the GD at the base of that area.
- *
- * @base: top from which reservation was done
- */
-void board_init_f_init_reserve(ulong base);
-
-/**
- * arch_setup_gd() - Set up the global_data pointer
- *
- * This pointer is special in some architectures and cannot easily be assigned
- * to. For example on x86 it is implemented by adding a specific record to its
- * Global Descriptor Table! So we we provide a function to carry out this task.
- * For most architectures this can simply be:
- *
- * gd = gd_ptr;
- *
- * @gd_ptr: Pointer to global data
- */
-void arch_setup_gd(gd_t *gd_ptr);
-
-int checkboard(void);
-int show_board_info(void);
int checkflash(void);
int checkdram(void);
-int last_stage_init(void);
-extern ulong monitor_flash_len;
-int mac_read_from_eeprom(void);
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */
-int set_cpu_clk_info(void);
int mdm_init(void);
-int print_cpuinfo(void);
-int update_flash_size(int flash_size);
-int arch_early_init_r(void);
-
-/*
- * setup_board_extra() - Fill in extra details in the bd_t structure
- *
- * @return 0 if OK, -ve on error
- */
-int setup_board_extra(void);
-
-/**
- * arch_fsp_init() - perform firmware support package init
- *
- * Where U-Boot relies on binary blobs to handle part of the system init, this
- * function can be used to set up the blobs. This is used on some Intel
- * platforms.
- */
-int arch_fsp_init(void);
-
-/**
- * arch_cpu_init_dm() - init CPU after driver model is available
- *
- * This is called immediately after driver model is available before
- * relocation. This is similar to arch_cpu_init() but is able to reference
- * devices
- *
- * @return 0 if OK, -ve on error
- */
-int arch_cpu_init_dm(void);
-
-/**
- * Reserve all necessary stacks
- *
- * This is used in generic board init sequence in common/board_f.c. Each
- * architecture could provide this function to tailor the required stacks.
- *
- * On entry gd->start_addr_sp is pointing to the suggested top of the stack.
- * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures
- * require only this can leave it untouched.
- *
- * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective
- * positions of the stack. The stack pointer(s) will be set to this later.
- * gd->irq_sp is only required, if the architecture needs it.
- *
- * @return 0 if no error
- */
-__weak int arch_reserve_stacks(void);
/**
* Show the DRAM size in a board-specific way
@@ -228,7 +122,6 @@
*/
int arch_fixup_fdt(void *blob);
-int reserve_mmu(void);
/* common/flash.c */
void flash_perror (int);
@@ -355,19 +248,8 @@
#endif
int get_env_id (void);
-void pci_init (void);
void pci_init_board(void);
-#if defined(CONFIG_DTB_RESELECT)
-int embedded_dtb_select(void);
-#endif
-
-int misc_init_f (void);
-int misc_init_r (void);
-#if defined(CONFIG_VID)
-int init_func_vid(void);
-#endif
-
/* common/exports.c */
void jumptable_init(void);
@@ -422,7 +304,6 @@
int board_late_init (void);
int board_postclk_init (void); /* after clocks/timebase, before env/serial */
int board_early_init_r (void);
-void board_poweroff (void);
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram(void);
@@ -464,16 +345,6 @@
u32 cpu_dsp_mask(void);
int is_core_valid (unsigned int);
-/**
- * arch_cpu_init() - basic cpu-dependent setup for an architecture
- *
- * This is called after early malloc is available. It should handle any
- * CPU- or SoC- specific init needed to continue the init sequence. See
- * board_f.c for where it is called. If this is not provided, a default
- * version (which does nothing) will be used.
- */
-int arch_cpu_init(void);
-
void s_init(void);
int checkcpu (void);
@@ -503,8 +374,6 @@
ulong get_bus_freq (ulong);
int get_serial_clock(void);
-int cpu_init_r (void);
-
/* $(CPU)/interrupts.c */
int interrupt_init (void);
void timer_interrupt (struct pt_regs *);
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index c9742f3..b737e46 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -12,7 +12,6 @@
/*
* BOARD/CPU
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* SERIAL
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index afd6488..e64f6d8 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -12,7 +12,6 @@
/*
* BOARD/CPU
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* SERIAL
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index d28e003..3bbb18a 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -167,7 +167,6 @@
#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -407,7 +406,6 @@
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -441,7 +439,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 56e6e14..f81f0de 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -45,7 +45,6 @@
/* High Level Configuration Options */
-#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
@@ -204,7 +203,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -326,7 +324,7 @@
#define CONFIG_HAS_ETH0
#endif
-#define CONFIG_HOSTNAME BSC9131rdb
+#define CONFIG_HOSTNAME "BSC9131rdb"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 96a92f1..fb4762d 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -88,7 +88,6 @@
#endif
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_TSEC_ENET /* ethernet */
#if defined(CONFIG_SYS_CLK_100_DDR_100)
#define CONFIG_SYS_CLK_FREQ 100000000
@@ -356,8 +355,6 @@
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
@@ -370,7 +367,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -458,7 +454,6 @@
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
@@ -533,7 +528,7 @@
#define CONFIG_HAS_ETH1
#endif
-#define CONFIG_HOSTNAME BSC9132qds
+#define CONFIG_HOSTNAME "BSC9132qds"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin"
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 125a26b..9c4d2d1 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -89,7 +89,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
-#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DDR_CLK_FREQ 100000000
@@ -283,8 +282,6 @@
#define CONFIG_SYS_EXTRA_ENV_RELOC
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
@@ -334,7 +331,6 @@
#endif
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 3385dcb..4a1a8ff 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -64,7 +64,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* CONFIG_MCFFEC */
-#define CONFIG_HOSTNAME M5208EVBe
+#define CONFIG_HOSTNAME "M5208EVBe"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 7798b06..2e2e512 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -31,7 +31,7 @@
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_HOSTNAME M52277EVB
+#define CONFIG_HOSTNAME "M52277EVB"
#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index d221f71..e507ad9 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -76,7 +76,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
-#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_HOSTNAME "M5235EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index cf10f30..b9f30cc 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -77,7 +77,7 @@
""
#endif
-#define CONFIG_HOSTNAME M5253DEMO
+#define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */
#define CONFIG_SYS_I2C
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 936a91e..ab5ebbd 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -80,7 +80,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* CONFIG_MCFFEC */
-#define CONFIG_HOSTNAME M5272C3
+#define CONFIG_HOSTNAME "M5272C3"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index b295150..26b9ef3 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -72,7 +72,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* CONFIG_MCFFEC */
-#define CONFIG_HOSTNAME M5282EVB
+#define CONFIG_HOSTNAME "M5282EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 96fb87b..69b7d86 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -81,7 +81,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
-#define CONFIG_HOSTNAME M53017
+#define CONFIG_HOSTNAME "M53017"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 5a99485..6dcd41a 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -73,7 +73,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
-#define CONFIG_HOSTNAME M5329EVB
+#define CONFIG_HOSTNAME "M5329EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 7b2d1bb..faf098e 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -73,7 +73,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
-#define CONFIG_HOSTNAME M5373EVB
+#define CONFIG_HOSTNAME "M5373EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index ba9ba00..c614193 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -85,7 +85,7 @@
#endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
-#define CONFIG_HOSTNAME M54418TWR
+#define CONFIG_HOSTNAME "M54418TWR"
#if defined(CONFIG_CF_SBF)
/* ST Micro serial flash */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index b144332..bec0ca0 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -64,7 +64,7 @@
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
-#define CONFIG_HOSTNAME M54451EVB
+#define CONFIG_HOSTNAME "M54451EVB"
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 14dd2a5..fb3fee6 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -67,7 +67,7 @@
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
-#define CONFIG_HOSTNAME M54455EVB
+#define CONFIG_HOSTNAME "M54455EVB"
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_SYS_LOAD_ADDR2 0x40010013
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 566f24e..5c53e82 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -110,7 +110,7 @@
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
-#define CONFIG_HOSTNAME M547xEVB
+#define CONFIG_HOSTNAME "M547xEVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 3156474..bc10284 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -98,7 +98,7 @@
#define CONFIG_UDP_CHECKSUM
-#define CONFIG_HOSTNAME M548xEVB
+#define CONFIG_HOSTNAME "M548xEVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
index 6b03873..aeda474 100644
--- a/include/configs/MCR3000.h
+++ b/include/configs/MCR3000.h
@@ -9,7 +9,6 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -55,25 +54,14 @@
"${ofl_args}; " \
"bootm ${loadaddr} - 0xf00000\0"
-#define CONFIG_BOOTDELAY 5
-
#define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
/* Miscellaneous configurable options */
-#ifdef CONFIG_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "S3K> "
-#endif
-
#define CONFIG_SYS_MEMTEST_START 0x00002000
#define CONFIG_SYS_MEMTEST_END 0x00800000
@@ -82,16 +70,11 @@
#define CONFIG_SYS_HZ 1000
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00
-#define CONFIG_SYS_GBL_DATA_SIZE 64
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
+#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
@@ -108,37 +91,24 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_SYS_MONITOR_LEN (320 << 10)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
/* Environment Configuration */
/* environment is in FLASH */
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_OVERWRITE 1
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
/* Ethernet configuration part */
#define CONFIG_SYS_DISCOVER_PHY 1
-#ifdef CONFIG_MPC8XX_FEC
#define CONFIG_MII_INIT 1
-#endif
/* NAND configuration part */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x0C000000
-/* Internal Definitions */
-
-/* Boot Flags*/
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 0f94d4d..b62b11c 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -19,7 +19,6 @@
#define CONFIG_MISC_INIT_R
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_USE_PIO
#endif
@@ -297,7 +296,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -366,7 +364,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index a1b5ad6..ef6d820 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -73,8 +73,6 @@
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
-
#define CONFIG_SYS_IMMR 0xE0000000
#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
@@ -347,7 +345,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -387,7 +384,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_GMII /* MII PHY management */
@@ -608,7 +604,7 @@
#define CONFIG_NETDEV "eth1"
-#define CONFIG_HOSTNAME mpc8313erdb
+#define CONFIG_HOSTNAME "mpc8313erdb"
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_BOOTFILE "uImage"
/* U-Boot image on TFTP server */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index b0dade5..9e01ae4 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -279,7 +279,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
@@ -364,7 +363,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index b00306f..85ea171 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -205,7 +205,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -449,7 +448,7 @@
#define CONFIG_NETDEV "eth1"
-#define CONFIG_HOSTNAME mpc8323erdb
+#define CONFIG_HOSTNAME "mpc8323erdb"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "uImage"
/* U-Boot image on TFTP server */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 0892000..617e527 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -70,8 +70,6 @@
*/
#define CONFIG_SYS_SICRL 0x00000000
-#define CONFIG_BOARD_EARLY_INIT_R
-
/*
* IMMR new address
*/
@@ -286,7 +284,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index c496b23..c40ba46 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -304,7 +304,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -395,7 +394,6 @@
/*
* TSEC configuration
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
@@ -687,7 +685,7 @@
#define CONFIG_HAS_ETH0
#endif
-#define CONFIG_HOSTNAME mpc8349emds
+#define CONFIG_HOSTNAME "mpc8349emds"
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 37dcde3..0948d0d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -68,7 +68,6 @@
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C
-#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
/*
* Device configurations
@@ -340,7 +339,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 182f558..69e8a1d 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -95,7 +95,6 @@
*/
#define CONFIG_SYS_OBIR 0x31100000
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_HWCONFIG
/*
@@ -301,7 +300,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -384,7 +382,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
@@ -460,7 +457,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 772ce6d..7ebd617 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -22,7 +22,6 @@
/*
* On-board devices
*/
-#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
#define CONFIG_VSC7385_ENET
/*
@@ -322,7 +321,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -474,7 +472,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#endif
@@ -625,7 +622,7 @@
#define CONFIG_NETDEV "eth1"
-#define CONFIG_HOSTNAME mpc837x_rdb
+#define CONFIG_HOSTNAME "mpc837x_rdb"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 9f0039c..6843ef2 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -41,7 +41,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
@@ -193,8 +192,6 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
@@ -340,7 +337,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -571,7 +567,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
@@ -617,7 +612,7 @@
#define CONFIG_IPADDR 192.168.1.254
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index d44de9a..a43210f 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -29,7 +29,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
/*
@@ -204,7 +203,6 @@
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -342,7 +340,7 @@
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 238dd67..d4753c4 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -18,7 +18,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_VIA
@@ -229,7 +228,6 @@
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -365,7 +363,7 @@
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 64e0aa1..b2943fa 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -20,7 +20,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
@@ -175,7 +174,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -372,7 +370,7 @@
#define CONFIG_IPADDR 192.168.1.251
-#define CONFIG_HOSTNAME 8544ds_unknown
+#define CONFIG_HOSTNAME "8544ds_unknown"
#define CONFIG_ROOTPATH "/nfs/mpc85xx"
#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index cdd70a1..0c44c16 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -24,7 +24,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
@@ -299,7 +298,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -480,7 +478,7 @@
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index bcef1e7..a74b24c 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -18,7 +18,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_VIA
@@ -227,7 +226,6 @@
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -361,7 +359,7 @@
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 7f854c5..13567e4 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -28,7 +28,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
@@ -205,7 +204,6 @@
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
@@ -378,7 +376,7 @@
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 6d9a964..7fb4054 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -19,7 +19,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
@@ -207,7 +206,6 @@
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -379,7 +377,7 @@
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index ae92c37..6d09705 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -48,7 +48,6 @@
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
@@ -214,7 +213,6 @@
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -439,7 +437,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
@@ -472,7 +469,7 @@
/*
* Environment Configuration
*/
-#define CONFIG_HOSTNAME mpc8569mds
+#define CONFIG_HOSTNAME "mpc8569mds"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 303922a..c04b3a2 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -32,7 +32,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
@@ -180,8 +179,6 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
@@ -338,7 +335,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -573,7 +569,7 @@
#define CONFIG_IPADDR 192.168.1.254
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index fb5dc9a..3fd432e 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -201,7 +201,6 @@
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -440,7 +439,7 @@
*/
#define CONFIG_IPADDR 192.168.1.100
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 954896c..9ede6dd 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -44,7 +44,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
@@ -246,7 +245,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -604,7 +602,7 @@
#define CONFIG_IPADDR 192.168.1.100
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 84c364c..4b880e1 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -33,7 +33,6 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
/* Enable alternate, more extensive, memory test */
-#undef CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 344d99d..9d07742 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -180,7 +180,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
-#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
@@ -478,8 +477,6 @@
#endif
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
@@ -529,7 +526,6 @@
#endif
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -637,7 +633,6 @@
#endif /* #ifdef CONFIG_FSL_SATA */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 62165df..8dd4f91 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -264,7 +264,6 @@
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -338,7 +337,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -489,11 +487,9 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
-#define CONFIG_TSEC_ENET
#ifdef CONFIG_TSEC_ENET
#define CONFIG_TSECV2
@@ -591,7 +587,7 @@
* Environment Configuration
*/
-#define CONFIG_HOSTNAME p1022ds
+#define CONFIG_HOSTNAME "p1022ds"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 8dbfb06..aa12863 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -102,8 +102,6 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
@@ -143,7 +141,6 @@
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index bf9b1c4..3901a72 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -111,7 +111,6 @@
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -259,7 +258,6 @@
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -293,7 +291,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -573,7 +570,6 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 8001e70..ea9be7d 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -189,7 +189,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -423,7 +422,6 @@
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -454,7 +452,6 @@
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -629,7 +626,6 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index e80ba14..e2dcca7 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -212,7 +212,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -432,7 +431,6 @@
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -463,7 +461,6 @@
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -636,7 +633,6 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index c0a1bb4..df5b0f5 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -122,7 +122,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -339,7 +338,6 @@
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -367,7 +365,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -519,7 +516,6 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index a8f7885..e1f911a 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -219,7 +219,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -445,7 +444,6 @@
#endif
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -473,7 +471,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -629,7 +626,6 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 50413eb..492d12b 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -395,7 +395,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -419,7 +418,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -693,7 +691,6 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index ca1916a..5fe4c96 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -111,7 +111,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
@@ -343,7 +342,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -367,7 +365,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -644,7 +641,6 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 597ba2e..56f0a4e 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -489,7 +489,6 @@
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 87d65e4..5f743a9 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -89,7 +89,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -133,7 +132,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -161,7 +159,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -645,7 +642,6 @@
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index f4d8012..b90f1cf 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -40,7 +40,6 @@
/* board pre init: do not call, nothing to do */
/* detect the number of flash banks */
-#define CONFIG_BOARD_EARLY_INIT_R
/*
* DDR Setup
@@ -151,7 +150,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -184,7 +182,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MII
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 499319f..489e4e3 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -27,7 +27,6 @@
#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
-#define CONFIG_TSEC_ENET
#define CONFIG_TSEC1
#define CONFIG_TSEC3
#define CONFIG_HAS_ETH0
@@ -46,8 +45,6 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_LAST_STAGE_INIT
-
#endif
#if defined(CONFIG_TARGET_UCP1020)
@@ -57,7 +54,6 @@
#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
-#define CONFIG_TSEC_ENET
#define CONFIG_TSEC1
#define CONFIG_TSEC2
#define CONFIG_TSEC3
@@ -81,8 +77,6 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_LAST_STAGE_INIT
-
#endif
#ifdef CONFIG_SDCARD
@@ -237,8 +231,6 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
/* Initial L1 address */
@@ -274,7 +266,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -419,7 +410,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_MMC_SPI
#endif
@@ -479,7 +469,7 @@
#endif
-#define CONFIG_HOSTNAME UCP1020
+#define CONFIG_HOSTNAME "UCP1020"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h
index f95b1ff..1ebbc4c 100644
--- a/include/configs/adp-ae3xx.h
+++ b/include/configs/adp-ae3xx.h
@@ -73,7 +73,6 @@
*/
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
@@ -82,12 +81,6 @@
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
/*
- * SD (MMC) controller
- */
-#define CONFIG_FTSDC010_NUMBER 1
-#define CONFIG_FTSDC010_SDIO
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index fb5fa21..ff365c4 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -75,7 +75,6 @@
*/
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
@@ -84,12 +83,6 @@
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
/*
- * SD (MMC) controller
- */
-#define CONFIG_FTSDC010_NUMBER 1
-#define CONFIG_FTSDC010_SDIO
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index aba2fc6..bcc7a6d 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -44,7 +44,6 @@
#define CONFIG_LBA48
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_BOUNCE_BUFFER
@@ -76,7 +75,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_LOADADDR 0x12000000
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 158b7d4..ff87adc 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -56,8 +56,6 @@
#define NANDARGS ""
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"setenv mmcdev " #instance"; "\
@@ -74,14 +72,26 @@
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
#devtypel #instance " "
+#if CONFIG_IS_ENABLED(CMD_PXE)
+# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DHCP(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(LEGACY_MMC, legacy_mmc, 0) \
func(MMC, mmc, 1) \
func(LEGACY_MMC, legacy_mmc, 1) \
func(NAND, nand, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func)
#include <config_distro_bootcmd.h>
@@ -133,6 +143,8 @@
"setenv fdtfile am335x-bone.dtb; fi; " \
"if test $board_name = A335BNLT; then " \
"setenv fdtfile am335x-boneblack.dtb; fi; " \
+ "if test $board_name = A335PBGL; then " \
+ "setenv fdtfile am335x-pocketbeagle.dtb; fi; " \
"if test $board_name = BBBW; then " \
"setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \
"if test $board_name = BBG1; then " \
@@ -268,7 +280,6 @@
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index d5b63e6..a429dd9 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -22,12 +22,6 @@
#define CONFIG_ENV_SIZE (96 << 10) /* 96 KiB */
-/* Make the verbose messages from UBI stop printing */
-#define CONFIG_UBI_SILENCE_MSG
-#define CONFIG_UBIFS_SILENCE_MSG
-
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
@@ -107,7 +101,6 @@
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_CONS_INDEX 1
/* Ethernet support */
#define CONFIG_PHY_SMSC
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index 55e803b..e29de0e 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -16,7 +16,6 @@
#include <configs/ti_am335x_common.h>
/* settings we don;t want on this board */
-#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#undef CONFIG_CMD_SPI
#define CONFIG_CMD_CACHE
@@ -65,8 +64,6 @@
# define CONFIG_RESET_TO_RETRY
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
@@ -236,7 +233,6 @@
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_CONS_INDEX 1
/* PMIC support */
#define CONFIG_POWER_TPS65217
@@ -252,13 +248,11 @@
#undef CONFIG_TIMER
#endif
-#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
/* I2C configuration */
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 739a998..9687f37 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -26,8 +26,6 @@
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifndef CONFIG_SPL_BUILD
#define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 03b7c26..b97a761 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -58,7 +58,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 663f861..d2c1810 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -62,8 +62,6 @@
/* Always 64 KiB env size */
#define CONFIG_ENV_SIZE (64 << 10)
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -221,7 +219,6 @@
#define CONFIG_NET_RETRY_COUNT 10
#endif
-#define CONFIG_DRIVER_TI_CPSW
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define CONFIG_SYS_RX_ETH_BUFFER 64
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index c079a3a..d1f73f7 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -78,7 +78,6 @@
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
@@ -112,7 +111,6 @@
/* SPI SPL */
#define CONFIG_TI_EDMA3
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* SPI */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 569fd98..58c77de 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -9,7 +9,7 @@
#ifndef __AMCORE_CONFIG_H
#define __AMCORE_CONFIG_H
-#define CONFIG_HOSTNAME AMCORE
+#define CONFIG_HOSTNAME "AMCORE"
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index e1a192d..247f44b 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -43,6 +43,5 @@
*/
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x83f00000
-#define CONFIG_CMD_MEMTEST
#endif /* __CONFIG_H */
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 94b5332..00588ab 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -47,6 +47,5 @@
*/
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x83f00000
-#define CONFIG_CMD_MEMTEST
#endif /* __CONFIG_H */
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index b749826..098bafe 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -37,7 +37,6 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
/* Enable alternate, more extensive, memory test */
-#undef CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index d46a588..6df2ff9 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -44,7 +44,6 @@
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE)
/* Enable alternate, more extensive, memory test */
-#undef CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 5f53a52..f9970b8 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -16,7 +16,6 @@
#define CONFIG_ARCH_MISC_INIT
/* High-level configuration options */
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 21a79e1..eb8ffda 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -12,7 +12,6 @@
#include "mx6_common.h"
#undef CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
#define CONFIG_MACH_TYPE 4886
@@ -39,10 +38,6 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-/* Make the HW version stuff available in U-Boot env */
-#define CONFIG_VERSION_VARIABLE /* ver environment variable */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
@@ -57,7 +52,6 @@
#endif
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
@@ -117,7 +111,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Command definition */
#undef CONFIG_CMD_LOADB
@@ -254,7 +247,6 @@
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 48
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 16dce4a..9d59e69 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -14,7 +14,6 @@
#include "tegra30-common.h"
/* High-level configuration options */
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index 1b52cc3..ceca5ba 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -42,7 +42,7 @@
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS2
-#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
+#define CONFIG_HOSTNAME "apf27"
#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
/*
@@ -155,7 +155,6 @@
* Serial Driver
*/
#define CONFIG_MXC_UART
-#define CONFIG_CONS_INDEX 1
#define CONFIG_MXC_UART_BASE UART1_BASE
/*
diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h
index 1799cc1..a671611 100644
--- a/include/configs/aristainetos.h
+++ b/include/configs/aristainetos.h
@@ -14,7 +14,7 @@
#define __ARISTAINETOS_CONFIG_H
#define CONFIG_SYS_BOARD_VERSION 1
-#define CONFIG_HOSTNAME aristainetos
+#define CONFIG_HOSTNAME "aristainetos"
#define CONFIG_BOARDNAME "aristainetos"
#define CONFIG_MXC_UART_BASE UART5_BASE
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 9cd40a7..3584c27 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -13,7 +13,7 @@
#define __ARISTAINETOS2_CONFIG_H
#define CONFIG_SYS_BOARD_VERSION 2
-#define CONFIG_HOSTNAME aristainetos2
+#define CONFIG_HOSTNAME "aristainetos2"
#define CONFIG_BOARDNAME "aristainetos2"
#define CONFIG_MXC_UART_BASE UART2_BASE
diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h
index a680e76..9befb89 100644
--- a/include/configs/aristainetos2b.h
+++ b/include/configs/aristainetos2b.h
@@ -13,7 +13,7 @@
#define __ARISTAINETOS2B_CONFIG_H
#define CONFIG_SYS_BOARD_VERSION 3
-#define CONFIG_HOSTNAME aristainetos2
+#define CONFIG_HOSTNAME "aristainetos2"
#define CONFIG_BOARDNAME "aristainetos2-revB"
#define CONFIG_MXC_UART_BASE UART2_BASE
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 9aca91a..6e7ac0a 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -47,7 +47,6 @@
#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
504 * 1024 * 1024)
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 0758902..90dbc0e 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -170,7 +170,6 @@
#elif CONFIG_SYS_USE_NANDFLASH
#elif CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
#elif CONFIG_NAND_BOOT
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 95e327a..0af0127 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -143,7 +143,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
#elif CONFIG_NAND_BOOT
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 5766a36..03559bd 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -69,8 +69,6 @@
#define NANDARGS ""
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
@@ -231,11 +229,6 @@
/* SPL */
#ifndef CONFIG_NOR_BOOT
-/* USB gadget RNDIS */
-
-/* General network SPL, both CPSW and USB gadget RNDIS */
-#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/
-
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
@@ -273,16 +266,7 @@
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_OTG
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
-/* disable host part of MUSB in SPL */
-/* disable EFI partitions and partition UUID support */
-/*
- * Disable CPSW SPL support so we fit within the 101KiB limit.
- */
-#endif
-
/* Network. */
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#define CONFIG_MII
#define CONFIG_PHY_ATHEROS
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index e7f65d6..fb896fe 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -56,8 +56,6 @@
#define NANDARGS ""
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
@@ -452,7 +450,6 @@
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
index 9c23c9b..2062e9a 100644
--- a/include/configs/bcm23550_w1d.h
+++ b/include/configs/bcm23550_w1d.h
@@ -76,7 +76,6 @@
/* Post pad 3 bytes after each reg addr */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 13000000
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 0x3e000000
/* must fit into GPT:u-boot-env partition */
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index bd6d9ae..f15b94c 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -75,7 +75,6 @@
/* Post pad 3 bytes after each reg addr */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 13000000
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 0x3e000000
/* must fit into GPT:u-boot-env partition */
diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h
index 634186a..f0eba6b 100644
--- a/include/configs/bcm_northstar2.h
+++ b/include/configs/bcm_northstar2.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
-#define CONFIG_HOSTNAME northstar2
+#define CONFIG_HOSTNAME "northstar2"
/* Physical Memory Map */
#define V2M_BASE 0x80000000
@@ -33,7 +33,6 @@
#define CONFIG_SYS_NS16550_COM2 0x66110000
#define CONFIG_SYS_NS16550_COM3 0x66120000
#define CONFIG_SYS_NS16550_COM4 0x66130000
-#define CONFIG_CONS_INDEX 4
#define CONFIG_BAUDRATE 115200
#define CONFIG_ENV_SIZE SZ_8K
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index 506b783..8c1959d 100755
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -32,7 +32,6 @@
#define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
index 454a7b7..5541cc5 100644
--- a/include/configs/bmips_bcm6318.h
+++ b/include/configs/bmips_bcm6318.h
@@ -14,6 +14,13 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
index ac0a670..042479b 100644
--- a/include/configs/bmips_bcm63268.h
+++ b/include/configs/bmips_bcm63268.h
@@ -14,6 +14,13 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index 41c7838..2cb9b55 100644
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h
@@ -14,6 +14,13 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
index e9f53d6..6c9c33b 100644
--- a/include/configs/bmips_bcm6348.h
+++ b/include/configs/bmips_bcm6348.h
@@ -14,6 +14,11 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* USB */
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
index 5d018a3..e3113ee 100644
--- a/include/configs/bmips_bcm6358.h
+++ b/include/configs/bmips_bcm6358.h
@@ -14,6 +14,13 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
new file mode 100644
index 0000000..2f92ac1
--- /dev/null
+++ b/include/configs/bmips_bcm6362.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6362_H
+#define __CONFIG_BMIPS_BCM6362_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6362_H */
diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
index ce35fae..ad8877b 100644
--- a/include/configs/bmips_bcm6368.h
+++ b/include/configs/bmips_bcm6368.h
@@ -14,6 +14,13 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index 02e989a..457f55b 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -216,7 +216,6 @@
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 24000000
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index e8abe53..37d6aa5 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -17,7 +17,6 @@
/* Timer information */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */
#define CONFIG_POWER_TPS65217
#include <asm/arch/omap.h>
@@ -29,7 +28,6 @@
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
/* Network defines */
-#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_NATSEMI
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 364066f..d55ef3e 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -133,7 +133,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index afc0bae..a0a9ec8 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -19,7 +19,6 @@
#ifdef CONFIG_SPL
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#define CONFIG_SPL_SPI_LOAD
#include "imx6_spl.h"
#endif
@@ -99,7 +98,6 @@
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index 92e0479..5a69f3c 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -9,8 +9,6 @@
#include <configs/ti_am335x_common.h>
-#define CONFIG_CONS_INDEX 1
-
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
#endif
diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h
index eaf2754..9c70cf0 100644
--- a/include/configs/cl-som-am57x.h
+++ b/include/configs/cl-som-am57x.h
@@ -15,7 +15,6 @@
#define CONSOLEDEV "ttyO2"
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_OMAP_ABE_SYSCK
@@ -37,8 +36,6 @@
/* Offsets: 0K - SPL1, 64K - SPL2, 128K - SPL3, 192K - SPL4, 256K - U-Boot */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
/* SD/MMC RAW/FS boot */
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
@@ -46,7 +43,6 @@
/* Environment */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
@@ -82,7 +78,6 @@
/* USB Networking options */
/* CPSW Ethernet */
-#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 7d6f39f..36cf576 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -184,7 +184,6 @@
/* SPL */
#include "imx7_spl.h"
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index 7089bc4..059c302 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -11,8 +11,6 @@
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
@@ -66,8 +64,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_SYS_ALT_MEMTEST
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
@@ -102,7 +98,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 4f36930..35328b1 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -63,7 +63,6 @@
#define CONFIG_ENV_OFFSET (768 * 1024)
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
@@ -228,7 +227,6 @@
/* SPL */
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#define CONFIG_SPL_SPI_LOAD
/* Display */
#define CONFIG_VIDEO_IPUV3
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index bd41a56..0609cca 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -16,7 +16,6 @@
#include <configs/ti_am335x_common.h>
#undef CONFIG_SPI
-#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
@@ -83,7 +82,6 @@
#define CONFIG_SYS_AUTOLOAD "no"
/* Serial console configuration */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SERIAL1 1 /* UART0 */
/* NS16550 Configuration */
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 400edf0..e464e40 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -62,7 +62,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 19117a0..a57715e 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -66,7 +66,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 1b057ef..a118f0e 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -45,7 +45,6 @@
50, 51, 52, 53, 54, 55, 56, 57, }
/* CPSW Ethernet support */
-#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_SEND_HOSTNAME
@@ -84,7 +83,6 @@
#undef CONFIG_SYS_MONITOR_LEN
#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -128,14 +126,11 @@
"run emmcboot; " \
"fi;"
-#define CONFIG_CONS_INDEX 1
-
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SPL_SPI_LOAD
/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 1351eb8..6123cd3 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -25,7 +25,6 @@
#define OMAP_HSMMC_USE_GPIO
/* UART setup */
-#define CONFIG_CONS_INDEX 4
#define CONFIG_SYS_NS16550_COM4 UART4_BASE
/* MMC ENV related defines */
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index b810384..0c372c5 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -12,7 +12,6 @@
#include "mx6_common.h"
#undef CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
#define CONFIG_SYS_GENERIC_BOARD
@@ -37,10 +36,6 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-/* Make the HW version stuff available in U-Boot env */
-#define CONFIG_VERSION_VARIABLE /* ver environment variable */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
@@ -55,7 +50,6 @@
#endif
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
@@ -105,7 +99,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Command definition */
#undef CONFIG_CMD_LOADB
@@ -229,7 +222,6 @@
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 48
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 27f44ac..daa0859 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -17,10 +17,6 @@
/*#define CONFIG_DBG_MONITOR*/
#define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
-
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 484483d..f5f648d 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -20,13 +20,10 @@
/* We will never enable dcache because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
-
/*
* Environment settings
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index e7f9405..4bd825e 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -12,7 +12,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 8a4ab6a..3ec91d6 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -14,7 +14,6 @@
#include "tegra30-common.h"
/* High-level configuration options */
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 1078480..4d55c01 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -16,8 +16,6 @@
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
-
#define CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_CMD_FUSE
@@ -39,7 +37,6 @@
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* NAND support */
#define CONFIG_SYS_NAND_ONFI_DETECTION
@@ -50,7 +47,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 276c733..1fe6f2f 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -155,7 +155,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -199,7 +198,6 @@
/*
* MMC
*/
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#ifndef CONFIG_TRAILBLAZER
@@ -256,7 +254,6 @@
/*
* Ethernet
*/
-#define CONFIG_TSEC_ENET
#define CONFIG_TSECV2
@@ -318,15 +315,7 @@
/*
* Board initialisation callbacks
*/
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#else /* CONFIG_TRAILBLAZER */
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
#endif /* CONFIG_TRAILBLAZER */
/*
@@ -354,7 +343,7 @@
#else
-#define CONFIG_HOSTNAME controlcenterd
+#define CONFIG_HOSTNAME "controlcenterd"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
index e34b08e..b6d15f6 100644
--- a/include/configs/controlcenterdc.h
+++ b/include/configs/controlcenterdc.h
@@ -14,9 +14,7 @@
#define CONFIG_CUSTOMER_BOARD_SUPPORT
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_LAST_STAGE_INIT
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
@@ -73,8 +71,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_SYS_ALT_MEMTEST
-
/*
* Software (bit-bang) MII driver configuration
*/
@@ -121,7 +117,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
@@ -145,7 +140,7 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HOSTNAME ccdc
+#define CONFIG_HOSTNAME "ccdc"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "ccdc.img"
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 83c2642..2f3c497 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -123,7 +123,6 @@
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -268,7 +267,6 @@
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -301,7 +299,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -582,7 +579,6 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index dde0dc3..f0844a4 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -82,7 +82,6 @@
#undef CONFIG_POST
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -153,7 +152,6 @@
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -186,7 +184,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -405,7 +402,6 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index a58a54e..a914564 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -126,7 +126,6 @@
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#endif
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
@@ -137,7 +136,6 @@
#endif
#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif
@@ -293,7 +291,6 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT 32768
@@ -301,9 +298,6 @@
#endif
/* Load U-Boot Image From MMC */
-#ifdef CONFIG_SPL_MMC_LOAD
-#undef CONFIG_SPL_SPI_LOAD
-#endif
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index 25ce0ce..a0eab2d 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -10,7 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
@@ -46,8 +45,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_ALT_MEMTEST
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@@ -83,7 +80,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index f039f0b..cc54efe 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -11,8 +11,6 @@
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
@@ -51,8 +49,6 @@
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_ALT_MEMTEST
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
@@ -88,7 +84,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index db7346a..8ea039e 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -11,8 +11,6 @@
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
@@ -66,8 +64,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_SYS_ALT_MEMTEST
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
@@ -102,7 +98,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 115b593..f69d997 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -12,8 +12,6 @@
*/
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
@@ -44,8 +42,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_ALT_MEMTEST
-
/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
@@ -95,7 +91,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 40dee67..23841e0 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -71,7 +71,6 @@
#define CONFIG_RMII
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
-#define CONFIG_PHY_ADDR 0x1F
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index abe393e..9fce261 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -25,7 +25,6 @@
/* SPL */
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
/* Miscellaneous configurable options */
@@ -66,7 +65,6 @@
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
@@ -91,7 +89,6 @@
/* UART */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* USB Configs */
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 9c8a836..cda03d9 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -49,7 +49,6 @@
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@@ -92,7 +91,6 @@
#endif
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index e82de2a..917a05d 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -97,7 +97,6 @@
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_TI
@@ -131,7 +130,6 @@
/* SPI SPL */
#define CONFIG_TI_EDMA3
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/draco.h b/include/configs/draco.h
index c181640..02e935e 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -18,7 +18,6 @@
#include "siemens-am33x-common.h"
#define DDR_PLL_FREQ 303
-#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */
#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 6921714..1ac6cca 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -10,7 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
@@ -40,11 +39,8 @@
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x1, 0x0 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
-#define CONFIG_SYS_ALT_MEMTEST
-
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_MVEBU
@@ -104,7 +100,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
/* DS414 bus width is 32bits */
diff --git a/include/configs/duovero.h b/include/configs/duovero.h
index 96644b1..1fecac2 100644
--- a/include/configs/duovero.h
+++ b/include/configs/duovero.h
@@ -34,6 +34,4 @@
/* ENV related config options */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#endif /* __CONFIG_DUOVERO_H */
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index d27323a..ce1ed5b 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -54,7 +54,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
@@ -152,7 +151,7 @@
* to update uboot and load kernel
*/
-#define CONFIG_HOSTNAME ea20
+#define CONFIG_HOSTNAME "ea20"
#define CONFIG_EXTRA_ENV_SETTINGS \
"as=3\0" \
"netdev=eth0\0" \
@@ -189,9 +188,9 @@
"loadaddr=c0000014\0" \
"memory=32M\0" \
"kernel_addr_r=c0700000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/image.ext2\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
+ "ramdisk_file=" CONFIG_HOSTNAME "/image.ext2\0" \
"flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
"bootm ${kernel_addr_r}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
@@ -220,7 +219,7 @@
"net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \
" addip addtty addmtd addmisc addmem;" \
"clrlogo;bootm ${kernel_addr_r}\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"load_magic=if sf probe 0;then sf " \
"read c0000000 0x10000 0x60000;fi\0" \
"load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h
index 3c4ec17..16382f6 100644
--- a/include/configs/eco5pk.h
+++ b/include/configs/eco5pk.h
@@ -16,11 +16,9 @@
#include "tam3517-common.h"
/* Our console port is port3 */
-#undef CONFIG_CONS_INDEX
#undef CONFIG_SYS_NS16550_COM1
#undef CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3
@@ -28,6 +26,8 @@
#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_HOSTNAME "eco5pk"
+
/*
* Set its own mtdparts, different from common
*/
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 991cee5..35eaec6 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -79,7 +79,6 @@
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
/* Enable alternate, more extensive, memory test */
-#undef CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 18ec6cb..7eff616 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -78,7 +78,6 @@
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
/* Serial port hardware configuration */
-#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
115200, 230400}
#define CONFIG_SYS_SERIAL0 0x808C0000
@@ -95,7 +94,6 @@
#define CONFIG_DRIVER_EP93XX_MAC
#define CONFIG_MII_SUPPRESS_PREAMBLE
#define CONFIG_MII
-#define CONFIG_PHY_ADDR 1
#undef CONFIG_NETCONSOLE
/* SDRAM configuration */
diff --git a/include/configs/edison.h b/include/configs/edison.h
index dcfd311..3233f66 100644
--- a/include/configs/edison.h
+++ b/include/configs/edison.h
@@ -10,7 +10,6 @@
#include <asm/ibmpc.h>
/* ACPI */
-#define CONFIG_LAST_STAGE_INIT
/* Boot */
#define CONFIG_BOOTCOMMAND "run bootcmd"
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index b262b37..6a92e7f 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -84,7 +84,6 @@
* for your console driver.
*/
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index 94e0bdf..9c14520 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -22,7 +22,6 @@
#ifdef CONFIG_SPL
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#define CONFIG_SPL_SPI_LOAD
#include "imx6_spl.h"
#endif
@@ -56,7 +55,6 @@
#define CONFIG_BOARD_NAME EL6Q
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"board="__stringify(CONFIG_BOARD_NAME)"\0" \
"cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \
@@ -82,8 +80,6 @@
#define CONFIG_ARP_TIMEOUT 200UL
-#define CONFIG_CMD_MEMTEST
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10800000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index ef9f330..a605f8d 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -70,7 +70,6 @@
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define DDR_PLL_FREQ 303
-#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
/* FWD Button = 27
* SRV Button = 87 */
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 067d836..6ca69fb 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -55,7 +55,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/*
* Command definition
@@ -156,7 +155,7 @@
* to update uboot and load kernel
*/
-#define CONFIG_HOSTNAME flea3
+#define CONFIG_HOSTNAME "flea3"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -174,9 +173,9 @@
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
+ "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
@@ -190,7 +189,7 @@
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +80000;" \
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 925507f..44c92f9 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -48,8 +48,6 @@
#define CONFIG_IMX_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
-#define CONFIG_LAST_STAGE_INIT
-
#define CONFIG_MXC_UART
#define CONFIG_MXC_OCOTP
@@ -63,7 +61,6 @@
#endif
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_BOUNCE_BUFFER
@@ -100,7 +97,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_LOADADDR 0x12000000
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 4845c9f..a470bd8 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -24,7 +24,6 @@
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
-#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 4b380be..a657db9 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -100,7 +100,6 @@
* Serial port
*/
#define CONFIG_FFUART
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 785cad7..038ffcd 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -22,7 +22,6 @@
#define CONFIG_PL011_CLOCK 150000000
#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
-#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index a8afb15..d6761dd 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -18,10 +18,6 @@
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_HRCON 1 /* HRCON board specific */
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
/*
@@ -277,7 +273,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -470,7 +465,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
@@ -584,7 +578,7 @@
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#define CONFIG_HOSTNAME hrcon
+#define CONFIG_HOSTNAME "hrcon"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h
index fb4829a..f476f5b 100644
--- a/include/configs/hsdk.h
+++ b/include/configs/hsdk.h
@@ -12,6 +12,7 @@
/*
* CPU configuration
*/
+#define NR_CPUS 4
#define ARC_PERIPHERAL_BASE 0xF0000000
#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
@@ -61,6 +62,50 @@
*/
#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "core_dccm_0=0x10\0" \
+ "core_dccm_1=0x6\0" \
+ "core_dccm_2=0x10\0" \
+ "core_dccm_3=0x6\0" \
+ "core_iccm_0=0x10\0" \
+ "core_iccm_1=0x6\0" \
+ "core_iccm_2=0x10\0" \
+ "core_iccm_3=0x6\0" \
+ "core_mask=0xF\0" \
+ "dcache_ena=0x1\0" \
+ "icache_ena=0x1\0" \
+ "non_volatile_limit=0xE\0" \
+ "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
+ "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+ "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+ "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+ "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+ "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
+ "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
+ "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
+setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
+
/*
* Environment configuration
*/
@@ -68,12 +113,16 @@
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
- * Console configuration
- */
-
-/*
* Misc utility configuration
*/
#define CONFIG_BOUNCE_BUFFER
+/* Cli configuration */
+#define CONFIG_SYS_CBSIZE SZ_2K
+
+/*
+ * Callback configuration
+ */
+#define CONFIG_BOARD_LATE_INIT
+
#endif /* _CONFIG_HSDK_H_ */
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index a4acaa6..a10dc12 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -162,7 +162,6 @@
*/
#define CONFIG_TSEC1
#define CONFIG_TSEC2
-#define CONFIG_TSEC_ENET
#define CONFIG_HARD_SPI
/*
@@ -315,7 +314,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -428,7 +426,7 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#define CONFIG_NETDEV eth1
-#define CONFIG_HOSTNAME ids8313
+#define CONFIG_HOSTNAME "ids8313"
#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
#define CONFIG_BOOTFILE "ids8313/uImage"
#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index dca910f..ad9aca4 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -82,7 +82,6 @@
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
/*
* Flash & Environment
@@ -151,9 +150,9 @@
" console=ttymxc0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"kernel_addr_r=a0800000\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
"rootpath=/opt/eldk-4.2-arm/arm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addtty addmtd addmisc;" \
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 1bc7f2a..bfc9b33 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -28,8 +28,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 63aa8df..cf74052 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -13,8 +13,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
-#define CONFIG_CONS_INDEX 0
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index c8e9951..28e5d53 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -114,7 +114,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
/*
* Flash & Environment
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index f00ca1c..b14f6c5 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -16,8 +16,6 @@
/* Platform type */
#define CONFIG_SOC_K2G
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_MMC_TI_ARGS \
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index d8bcbde..87639df 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -15,9 +15,18 @@
/* Platform type */
#define CONFIG_SOC_K2L
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV \
+ DEFAULT_FIT_TI_ARGS \
+ "findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
+ DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 061303d..b7d510e 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -97,7 +97,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
115200 }
diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h
index 9d99bc5..f44b388 100644
--- a/include/configs/khadas-vim.h
+++ b/include/configs/khadas-vim.h
@@ -12,8 +12,6 @@
#define CONFIG_MISC_INIT_R
-#define CONFIG_PHY_ADDR 8
-
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
#include <configs/meson-gxbb-common.h>
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 61890d3..cf3fc43 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -23,8 +23,6 @@
#define CONFIG_HUSH_INIT_VAR
-#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_LOADS_ECHO
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index 64c1d2f..c4d4b0c 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -9,8 +9,6 @@
#define __CONFIG_KEYMILE_POWERPC_H
/* Do boardspecific init for all boards */
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
#define CONFIG_JFFS2_CMDLINE
@@ -67,7 +65,7 @@
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
#define CONFIG_KM_DEF_ENV_CPU \
- "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot="CONFIG_HOSTNAME "/u-boot.bin\0" \
"update=" \
"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
"erase " __stringify(BOOTFLASH_START) " +${filesize} && "\
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index f0ec5cf..f315062 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -128,7 +128,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index cc36a68..c676192 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -69,7 +69,7 @@
" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
#define CONFIG_KM_DEF_ENV_CPU \
- "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
+ "u-boot="CONFIG_HOSTNAME "/u-boot.kwb\0" \
CONFIG_KM_UPDATE_UBOOT \
"set_fdthigh=setenv fdt_high ${kernelmem}\0" \
"checkfdt=" \
@@ -98,8 +98,6 @@
* for your console driver.
*/
-#define CONFIG_CONS_INDEX 1 /* Console on UART0 */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index f49f436..05a4e86 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -188,10 +188,8 @@
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
#define CONFIG_HWCONFIG
@@ -219,7 +217,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@ -394,7 +391,7 @@
"cramfsload ${fdt_addr_r} " \
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
- "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
+ "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0" \
"update=" \
"sf probe 0;sf erase 0 +${filesize};" \
"sf write ${load_addr_r} 0 ${filesize};\0" \
diff --git a/include/configs/km8360.h b/include/configs/km8360.h
index 7d4b430..280da9d 100644
--- a/include/configs/km8360.h
+++ b/include/configs/km8360.h
@@ -14,11 +14,11 @@
#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
#if defined CONFIG_KMETER1
-#define CONFIG_HOSTNAME kmeter1
+#define CONFIG_HOSTNAME "kmeter1"
#define CONFIG_KM_BOARD_NAME "kmeter1"
#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
#elif defined CONFIG_KMCOGE5NE
-#define CONFIG_HOSTNAME kmcoge5ne
+#define CONFIG_HOSTNAME "kmcoge5ne"
#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
#define CONFIG_NAND_ECC_BCH
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 0d78cfa..15e4b46 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -23,13 +23,13 @@
/* KM_KIRKWOOD */
#if defined(CONFIG_KM_KIRKWOOD)
-#define CONFIG_HOSTNAME km_kirkwood
+#define CONFIG_HOSTNAME "km_kirkwood"
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/* KM_KIRKWOOD_PCI */
#elif defined(CONFIG_KM_KIRKWOOD_PCI)
-#define CONFIG_HOSTNAME km_kirkwood_pci
+#define CONFIG_HOSTNAME "km_kirkwood_pci"
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
@@ -37,7 +37,7 @@
/* KM_KIRKWOOD_128M16 */
#elif defined(CONFIG_KM_KIRKWOOD_128M16)
-#define CONFIG_HOSTNAME km_kirkwood_128m16
+#define CONFIG_HOSTNAME "km_kirkwood_128m16"
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_DISABLE_PCIE
@@ -48,9 +48,9 @@
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
# if defined(CONFIG_KM_NUSA)
-#define CONFIG_HOSTNAME kmnusa
+#define CONFIG_HOSTNAME "kmnusa"
# elif defined(CONFIG_KM_SUGP1)
-#define CONFIG_HOSTNAME kmsugp1
+#define CONFIG_HOSTNAME "kmsugp1"
#define KM_PCIE_RESET_MPP7
#endif
@@ -64,7 +64,7 @@
/* KM_MGCOGE3UN */
#elif defined(CONFIG_KM_MGCOGE3UN)
-#define CONFIG_HOSTNAME mgcoge3un
+#define CONFIG_HOSTNAME "mgcoge3un"
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
@@ -80,20 +80,20 @@
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
-#define CONFIG_HOSTNAME kmcoge5un
+#define CONFIG_HOSTNAME "kmcoge5un"
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_PIGGY4_88E6352
/* KM_PORTL2 */
#elif defined(CONFIG_KM_PORTL2)
-#define CONFIG_HOSTNAME portl2
+#define CONFIG_HOSTNAME "portl2"
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_PIGGY4_88E6061
/* KM_SUV31 */
#elif defined(CONFIG_KM_SUV31)
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
-#define CONFIG_HOSTNAME kmsuv31
+#define CONFIG_HOSTNAME "kmsuv31"
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
index 8bb3571..37a33e5 100644
--- a/include/configs/kmp204x.h
+++ b/include/configs/kmp204x.h
@@ -10,12 +10,12 @@
/* KMLION1 */
#if defined(CONFIG_KMLION1)
-#define CONFIG_HOSTNAME kmlion1
+#define CONFIG_HOSTNAME "kmlion1"
#define CONFIG_KM_BOARD_NAME "kmlion1"
/* KMCOGE4 */
#elif defined(CONFIG_KMCOGE4)
-#define CONFIG_HOSTNAME kmcoge4
+#define CONFIG_HOSTNAME "kmcoge4"
#define CONFIG_KM_BOARD_NAME "kmcoge4"
#else
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 82984f4..179c760 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -47,7 +47,6 @@
#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END \
(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 1d3fd96..3e5689a 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -102,7 +102,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h
index ffaca26..08dfb30 100644
--- a/include/configs/libretech-cc.h
+++ b/include/configs/libretech-cc.h
@@ -12,8 +12,6 @@
#define CONFIG_MISC_INIT_R
-#define CONFIG_PHY_ADDR 8
-
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
#include <configs/meson-gxbb-common.h>
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 25df103..7664b96 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -9,28 +9,17 @@
#include "ls1012a_common.h"
-/* PFE Ethernet */
-#ifdef CONFIG_FSL_PFE
-#define EMAC1_PHY_ADDR 0x2
-#define EMAC2_PHY_ADDR 0x1
-#define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_AQUANTIA
-#endif
-
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
@@ -48,7 +37,6 @@
#define CONFIG_NET_MULTI
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
@@ -110,7 +98,7 @@
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
#endif
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 73cd049..35ecb3c 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -13,8 +13,6 @@
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
#define CONFIG_SYS_CLK_FREQ 125000000
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -78,7 +76,6 @@
/* I2C */
#define CONFIG_SYS_I2C
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
@@ -110,9 +107,9 @@
"kernel_size=0x2800000\0" \
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
- "$kernel_start $kernel_size && "\
- "bootm $kernel_load"
+#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 297c057..6bb6927 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -16,7 +16,6 @@
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
@@ -68,10 +67,9 @@
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index e1767ef..3829f1a 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -15,7 +15,6 @@
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
@@ -109,7 +108,6 @@
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
@@ -118,7 +116,6 @@
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 97ed909..e24d261 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -15,7 +15,6 @@
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
@@ -25,6 +24,7 @@
*/
#define I2C_MUX_IO_ADDR 0x24
+#define I2C_MUX_IO2_ADDR 0x25
#define I2C_MUX_IO_0 0
#define I2C_MUX_IO_1 1
#define SW_BOOT_MASK 0x03
@@ -39,10 +39,12 @@
#define SW_REV_C2 0xD8
#define SW_REV_D 0xD0
#define SW_REV_E 0xC8
+#define __PHY_MASK 0xF9
+#define __PHY_ETH2_MASK 0xFB
+#define __PHY_ETH1_MASK 0xFD
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
@@ -52,7 +54,6 @@
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
@@ -113,7 +114,7 @@
"bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
#include <asm/fsl_secure_boot.h>
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 20c50ff..f2a6837 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -92,7 +92,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
@@ -118,7 +117,6 @@
* MMC
*/
#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
@@ -154,7 +152,6 @@
/*
* eTSEC
*/
-#define CONFIG_TSEC_ENET
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d1c0acb..d092410 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -336,7 +336,6 @@
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -363,7 +362,6 @@
/*
* MMC
*/
-#define CONFIG_FSL_ESDHC
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
@@ -397,7 +395,6 @@
/*
* eTSEC
*/
-#define CONFIG_TSEC_ENET
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 8f27d9e..c11f454 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -209,7 +209,6 @@
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -238,7 +237,6 @@
/*
* MMC
*/
-#define CONFIG_FSL_ESDHC
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
@@ -270,7 +268,6 @@
/*
* eTSEC
*/
-#define CONFIG_TSEC_ENET
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 9e1b81a..5ab29a1 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -54,7 +54,6 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
@@ -165,7 +164,6 @@
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 2494d9d..b9424e6 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -52,7 +52,6 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
@@ -153,7 +152,6 @@
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 393ce4f..814760e 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -69,7 +69,6 @@
#define CONFIG_SYS_I2C
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 897a049..88c5816 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -10,9 +10,6 @@
#include "ls1088a_common.h"
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
-
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
@@ -27,7 +24,6 @@
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
@@ -41,6 +37,8 @@
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#else
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
@@ -89,13 +87,14 @@
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TAVDS(0x6) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1a) |\
+ FTIM1_NOR_TRAD_NOR(0x1a) | \
FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
+ FTIM2_NOR_TCH(0x8) | \
+ FTIM2_NOR_TWPH(0xe) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x04000000
#define CONFIG_SYS_IFC_CCR 0x01000000
@@ -197,7 +196,7 @@
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
+#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
#else
@@ -226,7 +225,7 @@
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
@@ -262,13 +261,13 @@
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3
+#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
@@ -346,7 +345,6 @@
#endif
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
@@ -359,7 +357,6 @@
#define CONFIG_FSL_MEMAC
/* MMC */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 3f2a008..c92cb72 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -9,10 +9,6 @@
#include "ls1088a_common.h"
-#ifndef SPL_NO_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#endif
-
#define CONFIG_MISC_INIT_R
#if defined(CONFIG_QSPI_BOOT)
@@ -292,7 +288,6 @@
#endif
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
@@ -457,7 +452,6 @@
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 3e05b27..258a6f1 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -79,7 +79,6 @@
#define CONFIG_SYS_I2C
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 103ebec..d4da91f 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -130,7 +130,6 @@
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 815d8ad..213a5a5 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -343,7 +343,6 @@
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 3f9794f..012c24f 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -10,9 +10,6 @@
#include "ls2080a_common.h"
-#undef CONFIG_CONS_INDEX
-#define CONFIG_CONS_INDEX 2
-
#ifdef CONFIG_FSL_QSPI
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_QIXIS_I2C_ACCESS
@@ -325,7 +322,6 @@
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
@@ -372,7 +368,7 @@
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
- "kernel_addr=0x65000000\0" \
+ "kernel_addr=0x581000000\0" \
"kernel_start=0x1000000\0" \
"kernelheader_start=0x800000\0" \
"scriptaddr=0x80000000\0" \
@@ -442,8 +438,8 @@
"&& esbc_validate 0x20780000; " \
"env exists mcinitcmd && " \
"fsl_mc lazyapply dpl 0x20d00000; " \
- "run distro_bootcmd;env exists secureboot " \
- " && esbc_halt;run qspi_bootcmd; "
+ "run distro_bootcmd;run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
/* Try to boot an on-SD kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
@@ -453,16 +449,16 @@
"env exists mcinitcmd && run mcinitcmd " \
"&& mmc read 0x88000000 0x6800 0x800 " \
"&& fsl_mc lazyapply dpl 0x88000000; " \
- "run distro_bootcmd;env exists secureboot " \
- "&& esbc_halt;run sd_bootcmd;"
+ "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#else
/* Try to boot an on-NOR kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
"env exists mcinitcmd && env exists secureboot "\
"&& esbc_validate 0x580780000; env exists mcinitcmd "\
"&& fsl_mc lazyapply dpl 0x580d00000;" \
- "run distro_bootcmd; env exists secureboot " \
- "&& esbc_halt; run nor_bootcmd;"
+ "run distro_bootcmd;run nor_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#endif
/* MAC/PHY configuration */
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index d44cf78..9c4d01e 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -97,7 +97,7 @@
/* Extra Environment */
#define CONFIG_PREBOOT "run try_bootscript"
-#define CONFIG_HOSTNAME m28evk
+#define CONFIG_HOSTNAME "m28evk"
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyAMA0\0" \
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index bd36a8d..0ef9929 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -50,13 +50,11 @@
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONS_INDEX 1
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#endif
@@ -186,7 +184,7 @@
* Extra Environments
*/
#define CONFIG_PREBOOT "run try_bootscript"
-#define CONFIG_HOSTNAME m53evk
+#define CONFIG_HOSTNAME "m53evk"
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttymxc1\0" \
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index ed95e58..1781db8 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -86,7 +86,6 @@
* SPI NOR (boot memory)
*/
#ifdef CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
@@ -119,7 +118,7 @@
* Extra Environments
*/
#define CONFIG_PREBOOT "run try_bootscript"
-#define CONFIG_HOSTNAME ma5d4evk
+#define CONFIG_HOSTNAME "ma5d4evk"
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyS3\0" \
@@ -206,7 +205,6 @@
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#define CONFIG_SYS_USE_MMC
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 4593145..0f97b4c 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -10,7 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
@@ -42,8 +41,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_ALT_MEMTEST
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@@ -79,7 +76,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 8eb248a..0aa797a 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -94,7 +94,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200 quiet\0" \
"fdtfile=imx6q-mccmon6.dtb\0" \
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index a624671..27098ec 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -60,7 +60,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
@@ -107,7 +106,7 @@
/* Setup MTD for NAND on the SOM */
-#define CONFIG_HOSTNAME mcx
+#define CONFIG_HOSTNAME "mcx"
#define CONFIG_EXTRA_ENV_SETTINGS \
"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
@@ -126,13 +125,13 @@
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"baudrate=115200\0" \
"consoledev=ttyO2\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
"loadaddr=0x82000000\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"load_k=tftp ${loadaddr} ${bootfile}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
- "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
+ "mlo=" CONFIG_HOSTNAME "/MLO\0" \
"mmcargs=root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"mmcboot=echo Booting from mmc ...; " \
@@ -146,7 +145,7 @@
"bootm ${loadaddr}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
"uboot_addr=0x80000\0" \
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 73c3c2a..1a02ff5 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -179,7 +179,7 @@
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0
-#define CONFIG_HOSTNAME XILINX_BOARD_NAME
+#define CONFIG_HOSTNAME "microblaze-generic"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
/* architecture dependent code */
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index dfed513..2b7b600 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -283,7 +283,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -331,7 +330,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 5ba10b8..687f8ff 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -32,7 +32,6 @@
#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-#undef CONFIG_SYS_ALT_MEMTEST /* Enable alternate, more extensive, memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index 7109949..3810fd9 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -23,7 +23,7 @@
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_HOSTNAME mt_ventoux
+#define CONFIG_HOSTNAME "mt_ventoux"
/*
* Set its own mtdparts, different from common
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 3035a11..62a303c 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -49,7 +49,6 @@
* for your console driver.
*/
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200,230400, 460800, 921600 }
/* auto boot */
diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h
index a2f68ad..f6ac035 100644
--- a/include/configs/mv-plug-common.h
+++ b/include/configs/mv-plug-common.h
@@ -45,6 +45,4 @@
#define CONFIG_RTC_MV
#endif /* CONFIG_CMD_DATE */
-#define CONFIG_SYS_ALT_MEMTEST
-
#endif /* _CONFIG_MARVELL_PLUG_H */
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 52f8c5d..f4647b0 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -10,7 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
@@ -49,8 +48,6 @@
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_ALT_MEMTEST
-
/* End of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index f288cf5..44ec702 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -12,8 +12,6 @@
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
@@ -51,8 +49,6 @@
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_ALT_MEMTEST
-
/* End of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
@@ -106,4 +102,23 @@
#define CONFIG_E1000
#endif
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(SCSI, scsi, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x4d00000\0" \
+ "pxefile_addr_r=0x4e00000\0" \
+ "fdt_addr_r=0x4f00000\0" \
+ "kernel_addr_r=0x5000000\0" \
+ "ramdisk_addr_r=0x8000000\0" \
+ "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ BOOTENV
+
#endif /* _CONFIG_MVEBU_ARMADA_8K_H */
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 74346cf..a929d9f 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -49,7 +49,6 @@
/* Serial Info */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
/* No NOR flash present */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
@@ -68,7 +67,6 @@
#define CONFIG_ENV_OVERWRITE
/* ESDHC driver */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
#define CONFIG_SYS_FSL_ESDHC_NUM 1
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index bc58ca5..79d4c9b 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -65,6 +65,7 @@
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE
#define CONFIG_MX28_FEC_MAC_IN_OCOTP
#endif
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index fe04ca7..899f477 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -63,7 +63,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 0ec28ff..3aefe5b 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -65,7 +65,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/*
* Command definition
@@ -181,7 +180,6 @@
#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
/* mmc driver */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
@@ -209,9 +207,9 @@
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
+ "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
@@ -221,7 +219,7 @@
"bootm ${kernel_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +80000;" \
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index e3b33a0..173cb5c 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -50,7 +50,6 @@
/*
* MMC Configs
* */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 2
@@ -79,7 +78,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_ETHPRIME "FEC0"
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 1214ffd..733f59c 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -42,7 +42,6 @@
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
@@ -52,7 +51,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Command definition */
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index 7965125..0914439 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -31,7 +31,6 @@
#define CONFIG_FPGA_COUNT 1
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
@@ -51,7 +50,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Command definition */
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 9fa8031..087fc5f 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -42,7 +42,6 @@
#define CONFIG_RTC_MC13XXX
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
@@ -55,7 +54,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Command definition */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index e1aa7b8..b96483b 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -29,7 +29,6 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
@@ -64,7 +63,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Command definition */
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index 00132d1..e2ce796 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -35,7 +35,6 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
@@ -77,7 +76,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Command definition */
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 8de89c7..0a3578f 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -34,7 +34,6 @@
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
@@ -48,7 +47,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Command definition */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 2dc10c6..fadadb3 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -51,7 +51,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Filesystems and image support */
@@ -61,7 +60,6 @@
/* MMC */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
/* Fuses */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 0e1d18c..9fbd162 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -71,7 +71,6 @@
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdtfile=undefined\0" \
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h
index 5be8ce4..5325ec1 100644
--- a/include/configs/mx6memcal.h
+++ b/include/configs/mx6memcal.h
@@ -14,7 +14,6 @@
#include "mx6_common.h"
#include "imx6_spl.h"
-#undef CONFIG_FSL_ESDHC
#undef CONFIG_MMC
#undef CONFIG_SPL_MMC_SUPPORT
#undef CONFIG_GENERIC_MMC
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index d976e77..6f970a4 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -57,8 +57,6 @@
#define EMMC_ENV ""
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eaaf01..713ebf6 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -43,7 +43,6 @@
#define UPDATE_M4_ENV ""
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
UPDATE_M4_ENV \
"script=boot.scr\0" \
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 1c1671e..733538f 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -18,8 +18,6 @@
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 2142913..cf9f8ab 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -22,8 +22,6 @@
#define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 6ebf2e1..3544ffc 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -32,7 +32,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512
@@ -46,7 +45,6 @@
/* MMC */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
/* Fuses */
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 31b6d3e..c2223bd 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -29,7 +29,6 @@
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
@@ -65,7 +64,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CACHELINE_SIZE 64
@@ -86,7 +84,6 @@
#define CONFIG_LOADADDR 0x60800000
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_END 0x9E000000
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 5d07c9f..f07f81c 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -105,7 +105,6 @@
*/
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
-#define CONFIG_CONS_INDEX 0
/* Default baudrate can be overridden by board! */
/* FEC Ethernet on SoC */
diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h
new file mode 100644
index 0000000..0c3823b
--- /dev/null
+++ b/include/configs/netgear_dgnd3700v2.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6362.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index c73cfb7..7d2cf0b 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -268,8 +268,6 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
-#define CONFIG_SYS_ALT_MEMTEST
-
/*
* PCI express
*/
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index c853e8d..3cf78d4 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -73,7 +73,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 on RX-51 */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 977b2c3..121d339 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -37,7 +37,7 @@
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_HOSTNAME novena
+#define CONFIG_HOSTNAME "novena"
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
diff --git a/include/configs/nx25-ae250.h b/include/configs/nx25-ae250.h
index a357d71..0e4c431 100644
--- a/include/configs/nx25-ae250.h
+++ b/include/configs/nx25-ae250.h
@@ -11,18 +11,9 @@
/*
* CPU and Board Configuration Options
*/
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#ifdef CONFIG_OF_CONTROL
-#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
-#endif
-#endif
-
/*
* Miscellaneous configurable options
*/
@@ -50,6 +41,9 @@
*/
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE 0x000f0000
+
/*
* Physical Memory Map
*/
@@ -64,19 +58,12 @@
/*
* Serial console configuration
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#endif
#define CONFIG_SYS_NS16550_CLK 19660800
-/*
- * SD (MMC) controller
- */
-#define CONFIG_FTSDC010_NUMBER 1
-#define CONFIG_FTSDC010_SDIO
-
/* Init Stack Pointer */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
GENERATED_GBL_DATA_SIZE)
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index 3b67382..ddc36df 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -19,8 +19,6 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index 117c0e4..ff30a8a 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -11,7 +11,6 @@
#define CONFIG_MISC_INIT_R
/* Serial setup */
-#define CONFIG_CONS_INDEX 0
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0"
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 2c8ee7a..8faa7a3 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -185,7 +185,6 @@
* TODO: Add Odroid X support
*/
#define CONFIG_MISC_COMMON
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_BOARD_TYPES
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 9067ba6..53edd23 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -88,7 +88,6 @@
#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K)
/* Set soc_rev, soc_id, board_rev, boardname, fdtfile */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_ODROID_REV_AIN 9
#define CONFIG_REVISION_TAG
#define CONFIG_BOARD_TYPES
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index ff4e601..85b8352 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -12,7 +12,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <configs/ti_omap3_common.h>
@@ -45,22 +45,17 @@
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_NAND */
-/* MUSB */
-#define CONFIG_USB_OMAP3
-
/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
@@ -73,88 +68,75 @@
/* TWL4030 LED Support */
#define CONFIG_TWL4030_LED
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0)
+/* Environment */
+#define CONFIG_ENV_SIZE SZ_128K
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "run distro_bootcmd; " \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run userbutton; then " \
- "setenv bootenv uEnv.txt;" \
- "else " \
- "setenv bootenv user.txt;" \
- "fi;" \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcboot;" \
- "fi;" \
- "fi; " \
- "fi;" \
- "run nandboot;" \
- "setenv bootfile zImage;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcbootz; " \
- "fi; " \
+#define CONFIG_PREBOOT "usb start"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV
+
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance "; " \
+ "run mmcboot\0"
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#if defined(CONFIG_NAND)
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \
+ "echo NAND boot disabled: No mtdids and/or mtdparts; " \
+ "else " \
+ "run nandboot; " \
+ "fi\0"
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0) \
+ func(UBIFS, ubifs, 0) \
+ func(NAND, nand, 0)
+
+#else /* !CONFIG_NAND */
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0)
+
+#endif /* CONFIG_NAND */
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_high=0xffffffff\0" \
- "usbtty=cdc_acm\0" \
- "bootfile=uImage\0" \
- "ramdisk=ramdisk.gz\0" \
- "bootdir=/boot\0" \
- "bootpart=0:2\0" \
"console=ttyO2,115200n8\0" \
+ "bootdir=/boot\0" \
+ "bootenv=uEnv.txt\0" \
+ "bootfile=zImage\0" \
+ "bootpart=0:2\0" \
+ "bootubivol=rootfs\0" \
+ "bootubipart=rootfs\0" \
+ "usbtty=cdc_acm\0" \
"mpurate=auto\0" \
"buddy=none\0" \
- "optargs=\0" \
"camera=none\0" \
"vram=12M\0" \
"dvimode=640x480MR-16@60\0" \
"defaultdisplay=dvi\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "nandroot=ubi0:rootfs ubi.mtd=4\0" \
- "nandrootfstype=ubifs\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
- "ramrootfstype=ext2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
+ "defaultargs=setenv defargs " \
"mpurate=${mpurate} " \
"buddy=${buddy} "\
"camera=${camera} "\
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "mpurate=${mpurate} " \
- "buddy=${buddy} "\
- "camera=${camera} "\
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
+ "omapdss.def_disp=${defaultdisplay}\0" \
+ "optargs=\0" \
"findfdt=" \
"if test $beaglerev = AxBx; then " \
"setenv fdtfile omap3-beagle.dtb; fi; " \
@@ -167,49 +149,92 @@
"if test $beaglerev = xMC; then " \
"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
"if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine device tree to use; fi; \0" \
+ "echo WARNING: Could not determine device tree to use; fi\0" \
+ "mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "mmcargs=run defaultargs; setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${defargs} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "userbutton_xm=gpio input 4;\0" \
+ "userbutton_nonxm=gpio input 7;\0" \
+ "userbutton=if gpio input 173; then " \
+ "run userbutton_xm; " \
+ "else " \
+ "run userbutton_nonxm; " \
+ "fi;\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+ "env import -t ${loadaddr} ${filesize}\0" \
+ "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "if run userbutton; then " \
+ "setenv bootenv uEnv.txt;" \
+ "else " \
+ "setenv bootenv user.txt;" \
+ "fi;" \
+ "run loadbootenv && run importbootenv; " \
+ "run ext4bootenv && run importbootenv; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...; " \
+ "run uenvcmd; " \
+ "fi; " \
+ "fi\0" \
"validatefdt=" \
"if test $beaglerev = xMAB; then " \
"if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
"setenv fdtfile omap3-beagle-xm.dtb; " \
"fi; " \
"fi; \0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t -r $loadaddr $filesize\0" \
- "ramargs=setenv bootargs console=${console} " \
+ "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loaddtb=run validatefdt; ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "mmcboot=run mmcbootenv; " \
+ "if run loadimage && run loaddtb; then " \
+ "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \
+ "run mmcargs; " \
+ "if test ${bootfile} = uImage; then " \
+ "bootm ${loadaddr} - ${fdtaddr}; " \
+ "fi; " \
+ "if test ${bootfile} = zImage; then " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi; " \
+ "fi\0" \
+ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw\0" \
+ "nandrootfstype=ubifs rootwait\0" \
+ "nandargs=run defaultargs; setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${defargs} " \
"${optargs} " \
- "mpurate=${mpurate} " \
- "buddy=${buddy} "\
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr} - ${fdtaddr}\0" \
- "mmcbootz=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
- "ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootm ${loadaddr}\0" \
- "userbutton=if gpio input 173; then run userbutton_xm; " \
- "else run userbutton_nonxm; fi;\0" \
- "userbutton_xm=gpio input 4;\0" \
- "userbutton_nonxm=gpio input 7;\0" \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
+ "echo Booting uImage from NAND MTD 'kernel' partition ...; " \
+ "run nandargs; " \
+ "bootm ${loadaddr} - ${fdtaddr}; " \
+ "fi\0" \
+ "loadramdisk=ext4load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
+ "ramdisk=rootfs.ext2.gz.uboot\0" \
+ "ramdisk_size=16384\0" \
+ "ramroot=/dev/ram rw\0" \
+ "ramrootfstype=ext2\0" \
+ "ramargs=run defaultargs; setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${defargs} " \
+ "${optargs} " \
+ "root=${ramroot} ramdisk_size=${ramdisk_size} " \
+ "rootfstype=${ramrootfstype}\0" \
+ "ramboot=run mmcbootenv; " \
+ "if run loadimage && run loaddtb && run loadramdisk; then " \
+ "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \
+ "run ramargs; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}; " \
+ "fi\0" \
BOOTENV
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index b1f957b..1fa02a5 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -203,8 +203,6 @@
* are needed and peripheral clocks for UART2 must be enabled in
* function per_clocks_enable().
*/
-#undef CONFIG_CONS_INDEX
-#define CONFIG_CONS_INDEX 2
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_SYS_NS16550_COM3
#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 1392593..048c830 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -35,8 +35,6 @@
#define CONFIG_REVISION_TAG
/* Override OMAP3 serial console configuration */
-#undef CONFIG_CONS_INDEX
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
/* NAND */
@@ -54,51 +52,58 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_NAND */
-/* MUSB */
-
-/* USB EHCI */
-#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
-
/* Environment */
+#define CONFIG_ENV_SIZE SZ_128K
+
#define CONFIG_PREBOOT "usb start"
#define MEM_LAYOUT_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
-#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "run nandboot\0"
-#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"setenv mmcdev " #instance "; " \
- "setenv bootpart " #instance ":${mmcpart} ; " \
"run mmcboot\0"
#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
#devtypel #instance " "
+#if defined(CONFIG_NAND)
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \
+ "echo NAND boot disabled: No mtdids and/or mtdparts; " \
+ "else " \
+ "run nandboot; " \
+ "fi\0"
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(LEGACY_MMC, legacy_mmc, 0) \
func(UBIFS, ubifs, 0) \
func(NAND, nand, 0)
+#else /* !CONFIG_NAND */
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0)
+
+#endif /* CONFIG_NAND */
+
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -107,31 +112,29 @@
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"fdt_high=0xffffffff\0" \
+ "console=ttyO0,115200n8\0" \
"bootdir=/boot\0" \
"bootenv=uEnv.txt\0" \
"bootfile=zImage\0" \
+ "bootpart=0:2\0" \
"bootubivol=rootfs\0" \
"bootubipart=rootfs\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
- "bootpart=${mmcdev}:${mmcpart}\0" \
- "console=ttyO0,115200n8\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"${mtdparts} " \
"${optargs} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext4 rootwait\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "${optargs} " \
- "root=ubi0:rootfs rw ubi.mtd=rootfs noinitrd " \
- "rootfstype=ubifs rootwait\0" \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
+ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
- "mmcbootenv=mmc dev ${mmcdev}; " \
+ "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
+ "mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"run loadbootenv && run importbootenv; " \
"run ext4bootenv && run importbootenv; " \
@@ -153,8 +156,14 @@
"bootz ${loadaddr} - ${fdtaddr}; " \
"fi; " \
"fi\0" \
- "nandboot=" \
- "if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
+ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \
+ "nandrootfstype=ubifs rootwait\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
"echo Booting uImage from NAND MTD 'kernel' partition ...; " \
"run nandargs; " \
"bootm ${loadaddr} - ${fdtaddr}; " \
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 76d8e13..e2a7f63 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -136,8 +136,6 @@
#define CONFIG_ENV_UBI_PART "UBI"
#define CONFIG_ENV_UBI_VOLUME "config"
#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
-#define CONFIG_UBI_SILENCE_MSG 1
-#define CONFIG_UBIFS_SILENCE_MSG 1
#define CONFIG_ENV_SIZE (32*1024)
#endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 7ffc4f7..162b05d 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -19,8 +19,6 @@
#ifdef CONFIG_SPL_BUILD
/* select serial console configuration for SPL */
-#undef CONFIG_CONS_INDEX
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
#endif
@@ -155,10 +153,10 @@
"run loadramdisk\0" \
"mmcramboot=setenv bootfile uImage; " \
"run mmcrambootcommon; " \
- "bootm ${loadaddr} ${rdaddr} ${fdtimage}\0" \
+ "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
"mmcrambootz=setenv bootfile zImage; " \
"run mmcrambootcommon; " \
- "bootz ${loadaddr} ${rdaddr} ${fdtimage}\0" \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
"run ramargs; " \
"run common_bootargs; " \
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 75203b2..8cded99 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -30,7 +30,6 @@
/* ENV related config options */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_ENV_OVERWRITE
#endif /* __CONFIG_PANDA_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 38a0055..266dac9 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -29,7 +29,6 @@
#include <configs/ti_omap5_common.h>
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index ea7bdf1..d67a619 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -20,6 +20,14 @@
#define CONFIG_USE_NAND
/*
+* Disable DM_* for SPL build and can be re-enabled after adding
+* DM support in SPL
+*/
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_I2C
+#undef CONFIG_DM_I2C_COMPAT
+#endif
+/*
* SoC Configuration
*/
#define CONFIG_MACH_OMAPL138_LCDK
@@ -57,7 +65,8 @@
* PLL configuration
*/
-#define CONFIG_SYS_DA850_PLL0_PLLM 37
+/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
+#define CONFIG_SYS_DA850_PLL0_PLLM 18
#define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
@@ -104,12 +113,14 @@
/*
* Serial Driver info
*/
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#if !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#endif
#define CONFIG_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
@@ -118,7 +129,6 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
#endif
@@ -126,7 +136,6 @@
/*
* I2C Configuration
*/
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index b2cbf91..62b48bc 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -68,7 +68,6 @@
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#define CONFIG_SPL_SPI_LOAD
#endif
#define CONFIG_FEC_MXC
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index d0f5529..a9752ad 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -233,7 +233,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_SATA_MAX_DEVICE 2
@@ -427,8 +426,6 @@
#endif
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
@@ -554,7 +551,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -780,7 +776,6 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
@@ -806,7 +801,7 @@
/*
* Environment Configuration
*/
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index e02c31d..623b238 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -42,7 +42,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_SATA_MAX_DEVICE 2
@@ -166,8 +165,6 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
/* Initial L1 address */
@@ -191,7 +188,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -373,7 +369,6 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
@@ -395,7 +390,7 @@
/*
* Environment Configuration
*/
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
diff --git a/include/configs/p212.h b/include/configs/p212.h
index 793b556..a087d86 100644
--- a/include/configs/p212.h
+++ b/include/configs/p212.h
@@ -12,10 +12,7 @@
#define CONFIG_MISC_INIT_R
-#define CONFIG_PHY_ADDR 8
-
/* Serial setup */
-#define CONFIG_CONS_INDEX 0
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0"
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index c6ff1e1..a59e881 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -25,7 +25,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
/* set to negative value for no autoboot */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80007fc0\0" \
"fdtaddr=0x80000000\0" \
@@ -98,7 +97,6 @@
#define CONFIG_SF_DEFAULT_SPEED 24000000
-#define CONFIG_CONS_INDEX 1
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
@@ -118,7 +116,6 @@
/* CPU */
#ifdef CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 94f580d..17600f5 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -37,7 +37,6 @@
#endif
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index 0bd19b6..3b82390 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h
@@ -9,7 +9,6 @@
#define __PCM058_CONFIG_H
#ifdef CONFIG_SPL
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
#endif
@@ -27,7 +26,6 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
/* Early setup */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/* Size of malloc() pool */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index d9a50ca..863b6e7 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -12,7 +12,6 @@
#define __CONFIG_PENGWYN_H
#define CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX 1
#include <configs/ti_am335x_common.h>
@@ -23,8 +22,6 @@
/* set env size */
#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
@@ -168,16 +165,9 @@
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-#if defined(CONFIG_SPL_BUILD)
-/* disable host part of MUSB in SPL */
-/* Disable CPSW SPL support so we fit within the 101KiB limit. */
-#endif
-
/* Network */
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_REALTEK
-/* CPSW support */
-
#endif /* ! __CONFIG_PENGWYN_H */
diff --git a/include/configs/pepper.h b/include/configs/pepper.h
index 7ef2529..44dcfba 100644
--- a/include/configs/pepper.h
+++ b/include/configs/pepper.h
@@ -20,7 +20,6 @@
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"bootdir=/boot\0" \
@@ -72,12 +71,10 @@
"fi;" \
/* Serial console configuration */
-#define CONFIG_CONS_INDEX 1 /* UART0 */
#define CONFIG_SERIAL1 1
#define CONFIG_SYS_NS16550_COM1 0x44e09000
/* Ethernet support */
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_RESET_DELAY 1000
/* SPL */
diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h
index 86d875d..072cd34 100644
--- a/include/configs/pfla02.h
+++ b/include/configs/pfla02.h
@@ -9,7 +9,6 @@
#define __PCM058_CONFIG_H
#ifdef CONFIG_SPL
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
#endif
@@ -25,7 +24,6 @@
#define CONSOLE_DEV "ttymxc3"
/* Early setup */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/* Size of malloc() pool */
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 4b18b2c..88c74bd 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -30,7 +30,6 @@
/* MMC Configs */
#define CONFIG_FSL_USDHC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h
index 2031554..148e561 100644
--- a/include/configs/platinum_picon.h
+++ b/include/configs/platinum_picon.h
@@ -16,7 +16,7 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_HOSTNAME picon
+#define CONFIG_HOSTNAME "picon"
#define CONFIG_PLATFORM_ENV_SETTINGS "\0"
diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h
index 09b9bd3..362d3a4 100644
--- a/include/configs/platinum_titanium.h
+++ b/include/configs/platinum_titanium.h
@@ -21,7 +21,7 @@
#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_HOSTNAME titanium
+#define CONFIG_HOSTNAME "titanium"
#define CONFIG_PLATFORM_ENV_SETTINGS "\0"
diff --git a/include/configs/porter.h b/include/configs/porter.h
index eb28d1a..b1a4c25 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -54,10 +54,13 @@
"initrd_high=0xffffffff\0"
/* SPL support */
-#define CONFIG_SPL_TEXT_BASE 0xe6304000
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
#define CONFIG_SPL_STACK 0xe6340000
-#define CONFIG_SPL_MAX_SIZE 0x40000
-#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __PORTER_H */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 58895a8..c133a33 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -44,7 +44,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
#define CONFIG_SYS_NS16550_COM1 0xb40003f8
-#define CONFIG_CONS_INDEX 1
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CONFIG_IDE_SWAP_IO
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 382c580..24ddfe0 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -44,7 +44,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8
-#define CONFIG_CONS_INDEX 1
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CONFIG_IDE_SWAP_IO
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index f718704..7b97ad5 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -27,7 +27,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/* Needed to fill the ccsrbar pointer */
@@ -83,7 +82,6 @@
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
@@ -114,8 +112,6 @@
#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_LAST_STAGE_INIT
-
/*
* Command line configuration.
*/
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index c14b4d2..c5cb657 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -42,7 +42,6 @@
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
/* Enable alternate, more extensive, memory test */
-#undef CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef CONFIG_SYS_MEMTEST_SCRATCH
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index 116728f..a9304e8 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -16,7 +16,6 @@
#include "siemens-am33x-common.h"
#define DDR_PLL_FREQ 303
-#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
/* FWD Button = 27
* SRV Button = 87 */
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index bbaab80..da82e44 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -51,6 +51,7 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* ENV setting */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 7018668..517d058 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -42,7 +42,7 @@
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
- "kernel_addr_r=0x02000000\0" \
+ "kernel_addr_r=0x02080000\0" \
"ramdisk_addr_r=0x04000000\0"
#include <config_distro_bootcmd.h>
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index d700bf2..bdba19e 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -13,9 +13,6 @@
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#if defined(CONFIG_SPL_SPI_SUPPORT)
-#define CONFIG_SPL_SPI_LOAD
-#endif
#define COUNTER_FREQUENCY 24000000
@@ -53,12 +50,13 @@
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
- "kernel_addr_r=0x02000000\0" \
+ "kernel_addr_r=0x02080000\0" \
"ramdisk_addr_r=0x04000000\0"
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
+ "fdtfile=rockchip/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"partitions=" PARTS_DEFAULT \
BOOTENV
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 26d41b5..2c94319 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -58,6 +58,4 @@
#endif
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
#endif /* _ROCKCHIP_COMMON_H_ */
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 17cdecd..325e52a 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -86,7 +86,6 @@
#define CONFIG_INITRD_TAG
/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define ENV_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
index 4dc098b..34e8441 100644
--- a/include/configs/s32v234evb.h
+++ b/include/configs/s32v234evb.h
@@ -69,7 +69,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_UART_PORT (1)
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 1
@@ -156,7 +155,6 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "=> "
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START (DDR_BASE_ADDR)
#define CONFIG_SYS_MEMTEST_END (DDR_BASE_ADDR + 0x7C00000)
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 1b40c29..40f037e 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -103,7 +103,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_UPDATEB \
"updatek=" \
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 841dedd..410d20b 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -71,8 +71,6 @@
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"updateb=" \
"onenand erase 0x0 0x100000;" \
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 24fa027..71dbc10 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -82,7 +82,6 @@
#endif
#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index f06556f..7f27f7a 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -61,7 +61,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 843aaa6..51db135 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -15,8 +15,6 @@
#include "at91-sama5_common.h"
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
@@ -104,7 +102,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#elif CONFIG_NAND_BOOT
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index 007a4f6..fb1e740 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -63,7 +63,6 @@
#elif CONFIG_SYS_USE_NANDFLASH
#elif CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#elif CONFIG_NAND_BOOT
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index dec3b52..2ac47fd 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -60,7 +60,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#elif CONFIG_NAND_BOOT
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 2b90231..4961301 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -34,7 +34,6 @@
#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/* turn on command-line edit/c/auto */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 5b5689a..73a2d19 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -259,7 +259,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -339,7 +338,6 @@
/*
* TSEC configuration
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
@@ -599,7 +597,7 @@
#define CONFIG_HAS_ETH1
#endif
-#define CONFIG_HOSTNAME SBC8349
+#define CONFIG_HOSTNAME "SBC8349"
#define CONFIG_ROOTPATH "/tftpboot/rootfs"
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index e52b3a9..51c0ad6 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -53,7 +53,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#endif
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
@@ -386,7 +385,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
@@ -522,7 +520,7 @@
#define CONFIG_IPADDR 192.168.0.55
-#define CONFIG_HOSTNAME sbc8548
+#define CONFIG_HOSTNAME "sbc8548"
#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
#define CONFIG_BOOTFILE "/uImage"
#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 1d31d3a..5f0a955 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -44,7 +44,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
@@ -232,7 +231,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -481,7 +479,7 @@
#define CONFIG_IPADDR 192.168.0.50
-#define CONFIG_HOSTNAME sbc8641d
+#define CONFIG_HOSTNAME "sbc8641d"
#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index 9d59509..e192de0 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -27,7 +27,6 @@
#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
480 * 1024 * 1024)
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index fee8059..c17bc31 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -27,7 +27,6 @@
#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
480 * 1024 * 1024)
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index c750666..6ca13aa 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -30,7 +30,6 @@
#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
224 * 1024 * 1024)
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index b175a6f..8d36262 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -47,7 +47,6 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(SH7785LCR_SDRAM_SIZE) - \
4 * 1024 * 1024)
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 0e77ccb..13c3dc8 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -87,7 +87,6 @@
#define CONFIG_SYS_NS16550_COM4 0x481a6000
#define CONFIG_SERIAL1 1
-#define CONFIG_CONS_INDEX 1
/* I2C Configuration */
#define CONFIG_I2C
@@ -104,7 +103,6 @@
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SPL_NAND_BASE
@@ -193,7 +191,6 @@
# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
#endif /* SPI support */
-#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS2
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index a3b1773..0da3b3b 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -64,8 +64,6 @@
#define CONFIG_ATMEL_LCD
#define CONFIG_GURNARD_SPLASH
-#define CONFIG_ATMEL_SPI
-
/* GPIOs and IO expander */
#define CONFIG_ATMEL_LEGACY
#define CONFIG_AT91_GPIO
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 2322326..29b5e6e 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -95,7 +95,6 @@
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
115200 }
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 6644ef6..cf1f2b1 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -12,7 +12,6 @@
/*
* High level configuration
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_CLOCKS
#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
@@ -192,7 +191,6 @@
#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
#define CONFIG_SYS_NS16550_CLK 50000000
#endif
-#define CONFIG_CONS_INDEX 1
/*
* USB
@@ -271,7 +269,6 @@
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif
@@ -295,7 +292,7 @@
#define BOOT_TARGET_DEVICES_DHCP(func)
#endif
-#ifdef CONFIG_CMD_PXE
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
index 1197b40..1d8aed9 100644
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -41,7 +41,7 @@
#endif
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_vining_fpga
+#define CONFIG_HOSTNAME "socfpga_vining_fpga"
/*
* Active LOW GPIO buttons:
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 3491944..2ec55c1 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -22,10 +22,7 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
@@ -174,7 +171,6 @@
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 45e226d..ae6a216 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -76,7 +76,6 @@
* CONFIG_PL01x_PORTS is defined in specific files
*/
#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
-#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
57600, 115200 }
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 801980e..8b8a73d 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -79,4 +79,14 @@
#endif
/* For SPL ends */
+/* For splashcreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h
index aa2871d..d6d3547 100644
--- a/include/configs/stm32h743-disco.h
+++ b/include/configs/stm32h743-disco.h
@@ -24,8 +24,7 @@
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ_CLOCK 250000000
+#define CONFIG_SYS_HZ_CLOCK 1000000
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h
index aa2871d..d6d3547 100644
--- a/include/configs/stm32h743-eval.h
+++ b/include/configs/stm32h743-eval.h
@@ -24,8 +24,7 @@
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ_CLOCK 250000000
+#define CONFIG_SYS_HZ_CLOCK 1000000
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
new file mode 100644
index 0000000..da0e259
--- /dev/null
+++ b/include/configs/stm32mp1.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP15x CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+#define CONFIG_PREBOOT
+
+/*
+ * Number of clock ticks in 1 sec
+ */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_ARCH_TIMER
+
+/*
+ * malloc() pool size
+ */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/*
+ * Console I/O buffer size
+ */
+#define CONFIG_SYS_CBSIZE SZ_1K
+
+/*
+ * Needed by "loadb"
+ */
+#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE
+
+/*
+ * Env parameters
+ */
+#define CONFIG_ENV_SIZE SZ_4K
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* SPL support */
+#ifdef CONFIG_SPL
+/* BOOTROM load address */
+#define CONFIG_SPL_TEXT_BASE 0x2FFC2500
+/* SPL use DDR */
+#define CONFIG_SPL_BSS_START_ADDR 0xC0200000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START 0xC0300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+/* limit SYSRAM usage to first 128 KB */
+#define CONFIG_SPL_MAX_SIZE 0x00020000
+#define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \
+ STM32_SYSRAM_SIZE)
+#endif /* #ifdef CONFIG_SPL */
+
+/*MMC SD*/
+#define CONFIG_SYS_MMC_MAX_DEVICE 3
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+#if !defined(CONFIG_SPL) || !defined(CONFIG_SPL_BUILD)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+#define STM32MP_PREBOOT \
+ "echo \"Boot over ${boot_device}${boot_instance}!\"; " \
+ "if test \"${boot_device}\" = \"mmc\"; then " \
+ "env set boot_targets \"mmc${boot_instance}\"; "\
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0xC0000000\0" \
+ "pxefile_addr_r=0xC0000000\0" \
+ "kernel_addr_r=0xC1000000\0" \
+ "fdt_addr_r=0xC4000000\0" \
+ "ramdisk_addr_r=0xC4100000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "preboot=" STM32MP_PREBOOT "\0" \
+ BOOTENV
+
+#endif /* ifndef CONFIG_SPL_BUILD */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index d20dd9c..c02fe2a 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -9,7 +9,7 @@
#ifndef __STMARK2_CONFIG_H
#define __STMARK2_CONFIG_H
-#define CONFIG_HOSTNAME stmark2
+#define CONFIG_HOSTNAME "stmark2"
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
diff --git a/include/configs/stout.h b/include/configs/stout.h
index b81103e..228cb55 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -17,14 +17,9 @@
#include "rcar-gen2-common.h"
-/* STACK */
-#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
-#endif
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
+#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
@@ -43,47 +38,31 @@
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_RCAR
-#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
-#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
-#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
-#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_SYS_TMU_CLK_DIV 4
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF, SCIFA0 */
-#define CONFIG_SMSTP2_ENA 0x00002010
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIFA0
+#define CONFIG_SH_SCIF_CLK_FREQ 52000000
+#endif
#endif /* __STOUT_H */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 9ba52d1..b56a03e 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -18,14 +18,8 @@
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_STRIDER 1 /* STRIDER board specific */
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_ALT_MEMTEST
-
/*
* System Clock Setup
*/
@@ -278,7 +272,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -504,7 +497,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
@@ -618,7 +610,7 @@
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#define CONFIG_HOSTNAME hrcon
+#define CONFIG_HOSTNAME "hrcon"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index e4e7c22..9d9e9ce 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -288,12 +288,10 @@
/* Ethernet support */
#ifdef CONFIG_SUN4I_EMAC
-#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
#endif
#ifdef CONFIG_SUN7I_GMAC
-#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
#define CONFIG_PHY_REALTEK
#endif
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 606a4fc..a1d03ac 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -24,13 +24,13 @@
/* This needs to be set prior to including km/km83xx-common.h */
#if defined(CONFIG_SUVD3) /* SUVD3 board specific */
-#define CONFIG_HOSTNAME suvd3
+#define CONFIG_HOSTNAME "suvd3"
#define CONFIG_KM_BOARD_NAME "suvd3"
/* include common defines/options for all 8321 Keymile boards */
#include "km/km8321-common.h"
#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */
-#define CONFIG_HOSTNAME kmvect1
+#define CONFIG_HOSTNAME "kmvect1"
#define CONFIG_KM_BOARD_NAME "kmvect1"
/* at end of uboot partition, before env */
#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
@@ -38,7 +38,7 @@
#include "km/km8309-common.h"
#elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */
-#define CONFIG_HOSTNAME kmtegr1
+#define CONFIG_HOSTNAME "kmtegr1"
#define CONFIG_KM_BOARD_NAME "kmtegr1"
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 0e735be..aed72ff 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -49,7 +49,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
@@ -93,7 +92,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -121,7 +119,6 @@
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 02bfca1..7f5a3ca 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -53,7 +53,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
#define CONFIG_SERIAL1 /* UART1 */
@@ -215,8 +214,8 @@
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=82000000\0" \
"kernel_addr_r=82000000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
@@ -231,10 +230,10 @@
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
- "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
+ "mlo=" CONFIG_HOSTNAME "/MLO\0" \
"uboot_addr=0x80000\0" \
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 5a7f207..6e04e6b 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -53,7 +53,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
/* allow to overwrite serial and ethaddr */
@@ -140,7 +139,6 @@
/* turn on command-line edit/hist/auto */
-#define CONFIG_SYS_ALT_MEMTEST 1
#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
/* defaults */
#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 51e3987..2fa0ded 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -118,13 +118,11 @@
/* SPI EEPROM */
#define CONFIG_SPI
-#define CONFIG_ATMEL_SPI
#define TAURUS_SPI_MASK (1 << 4)
#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
#if defined(CONFIG_SPL_BUILD)
/* SPL related */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SF_DEFAULT_BUS 0
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index abd0e18..18208b1 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -42,8 +42,6 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
-#define CONFIG_CONS_INDEX 1
-
/* Filesystems / image support */
/* MMC */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 3ead2e4..cd3db1a 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -43,7 +43,6 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index e4ec2c0..c487642 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -10,7 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
@@ -54,7 +53,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT
/* Keep device tree and initrd in lower memory so the kernel can access them */
@@ -120,7 +118,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index 78674a1..88dce54 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -16,7 +16,6 @@
#include "siemens-am33x-common.h"
#define DDR_PLL_FREQ 303
-#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */
#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 51e1e4e..67b00eb 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -35,7 +35,6 @@
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_CONS_INDEX 1
/* Generic Interrupt Controller Definitions */
#define GICD_BASE (0x801000000000)
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 61d0b80..a81f3b8 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -28,7 +28,6 @@
/* commands to include */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
@@ -122,7 +121,6 @@
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x40300000
@@ -156,7 +154,6 @@
#endif
/* Ethernet */
-#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 35c7a91..e424983 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -56,7 +56,6 @@
#define CONFIG_SERIAL1
#define CONFIG_SERIAL2
#define CONFIG_SERIAL3
-#define CONFIG_CONS_INDEX 1
/*
* GPMC NAND block. We support 1 device and the physical address to
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 8251ceb..83e26db 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -15,7 +15,6 @@
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#include <asm/arch/omap.h>
@@ -36,7 +35,6 @@
#define CONFIG_MII /* Required in net/eth.c */
#endif
-#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 2fe8d9d..e87acca 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -48,7 +48,6 @@
CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
KEYSTONE_SPL_STACK_SIZE - 4)
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* SRAM scratch space entries */
@@ -66,7 +65,6 @@
#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
-#define CONFIG_CONS_INDEX 1
#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index cd6a9c2..3439a27 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -38,7 +38,6 @@
115200}
/* Select serial console configuration */
-#define CONFIG_CONS_INDEX 3
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 844a9e5..3a87192 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -53,7 +53,6 @@
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#endif
-#define CONFIG_CONS_INDEX 3
/* TWL6030 */
#ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 5391641..d6ea17b 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -58,7 +58,6 @@
#include <environment/ti/boot.h>
#include <environment/ti/mmc.h>
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index 0fe40ee..b53ddac 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -54,17 +54,17 @@
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20))
-#define CONFIG_HOSTNAME titanium
+#define CONFIG_HOSTNAME "titanium"
#define CONFIG_UBI_PART ubi
#define CONFIG_UBIFS_VOLUME rootfs0
#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "kernel=" CONFIG_HOSTNAME "/uImage\0" \
"kernel_fs=/boot/uImage\0" \
"kernel_addr=11000000\0" \
- "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
- __stringify(CONFIG_HOSTNAME) ".dtb\0" \
- "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb=" CONFIG_HOSTNAME "/" \
+ CONFIG_HOSTNAME ".dtb\0" \
+ "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
"dtb_addr=12800000\0" \
"script=boot.scr\0" \
"uimage=uImage\0" \
@@ -93,7 +93,7 @@
"rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
+ "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
"part=" __stringify(CONFIG_UBI_PART) "\0" \
"boot_vol=0\0" \
"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 9e8409b..38be086 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -43,7 +43,6 @@
/* FPGA commands that we don't use */
/* Extras */
-#define CONFIG_CMD_MEMTEST
#undef CONFIG_SYS_MEMTEST_START
#define CONFIG_SYS_MEMTEST_START 0
#undef CONFIG_SYS_MEMTEST_END
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 15b4ada..ad90bee 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -57,7 +57,6 @@
*/
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x83f00000
-#define CONFIG_CMD_MEMTEST
#define CONFIG_CMD_MII
diff --git a/include/configs/trats.h b/include/configs/trats.h
index e6649ff..e892b59 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -57,8 +57,6 @@
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Tizen - partitions definitions */
#define PARTS_CSA "csa-mmc"
#define PARTS_BOOT "boot"
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index c3eb7c9..aecac07 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -52,8 +52,6 @@
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Tizen - partitions definitions */
#define PARTS_CSA "csa-mmc"
#define PARTS_BOOT "boot"
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 80dfe12..9e7fadb 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -49,7 +49,6 @@
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
/* select serial console configuration */
-#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
@@ -265,6 +264,5 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
#endif /* __CONFIG_H */
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index d71baab..2a8663f 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -51,7 +51,6 @@
/*
* MMC Configs
* */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
/*
@@ -67,7 +66,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */
-#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */
/***********************************************************
* Command definition
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 94a3be6..1df806b 100644
--- a/include/configs/turris_omnia.h
+++ b/include/configs/turris_omnia.h
@@ -13,7 +13,6 @@
*/
#define CONFIG_MISC_INIT_R
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
@@ -75,8 +74,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_SYS_ALT_MEMTEST
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
@@ -100,7 +97,6 @@
#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
/* SPL related SPI defines */
-# define CONFIG_SPL_SPI_LOAD
# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index b63bdf1..bb1d1db 100644
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -26,19 +26,19 @@
*/
#if defined(CONFIG_KMSUPX5)
#define CONFIG_KM_BOARD_NAME "kmsupx5"
-#define CONFIG_HOSTNAME kmsupx5
+#define CONFIG_HOSTNAME "kmsupx5"
#elif defined(CONFIG_TUGE1)
#define CONFIG_KM_BOARD_NAME "tuge1"
-#define CONFIG_HOSTNAME tuge1
+#define CONFIG_HOSTNAME "tuge1"
#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */
#define CONFIG_KM_BOARD_NAME "tuxx1"
-#define CONFIG_HOSTNAME tuxx1
+#define CONFIG_HOSTNAME "tuxx1"
#elif defined(CONFIG_KMOPTI2)
#define CONFIG_KM_BOARD_NAME "kmopti2"
-#define CONFIG_HOSTNAME kmopti2
+#define CONFIG_HOSTNAME "kmopti2"
#elif defined(CONFIG_KMTEPR2)
#define CONFIG_KM_BOARD_NAME "kmtepr2"
-#define CONFIG_HOSTNAME kmtepr2
+#define CONFIG_HOSTNAME "kmtepr2"
#else
#error ("Board not supported")
#endif
diff --git a/include/configs/twister.h b/include/configs/twister.h
index 5626eb1..0325596 100644
--- a/include/configs/twister.h
+++ b/include/configs/twister.h
@@ -22,7 +22,7 @@
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_HOSTNAME twister
+#define CONFIG_HOSTNAME "twister"
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"bootcmd=run nandboot\0"
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 989014a..dd86dee 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -46,8 +46,6 @@
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index 35a6eca..7e6b980 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -27,7 +27,6 @@
#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/
/* Linux only */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200\0" \
"fdt_high=0xffffffff\0" \
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 8aeda4e..1b4140d 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -52,8 +52,6 @@
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-#define CONFIG_CONS_INDEX 1
-
#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_SIZE 0x2000
/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
@@ -87,7 +85,7 @@
#define CONFIG_GATEWAYIP 192.168.11.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 0x84000000
+#define CONFIG_LOADADDR 0x85000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_BOOTM_LEN (32 << 20)
@@ -115,7 +113,7 @@
#define CONFIG_BOOTFILE "fitImage"
#define LINUXBOOT_ENV_SETTINGS \
"fit_addr=0x00100000\0" \
- "fit_addr_r=0x84100000\0" \
+ "fit_addr_r=0x85100000\0" \
"fit_size=0x00f00000\0" \
"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
"bootm $fit_addr\0" \
@@ -128,7 +126,7 @@
#ifdef CONFIG_ARM64
#define CONFIG_BOOTFILE "Image.gz"
#define LINUXBOOT_CMD "booti"
-#define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0"
+#define KERNEL_ADDR_LOAD "kernel_addr_load=0x85200000\0"
#define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0"
#else
#define CONFIG_BOOTFILE "zImage"
@@ -138,15 +136,15 @@
#endif
#define LINUXBOOT_ENV_SETTINGS \
"fdt_addr=0x00100000\0" \
- "fdt_addr_r=0x84100000\0" \
+ "fdt_addr_r=0x85100000\0" \
"fdt_size=0x00008000\0" \
"kernel_addr=0x00200000\0" \
KERNEL_ADDR_LOAD \
KERNEL_ADDR_R \
- "kernel_size=0x00800000\0" \
- "ramdisk_addr=0x00a00000\0" \
- "ramdisk_addr_r=0x84a00000\0" \
- "ramdisk_size=0x00600000\0" \
+ "kernel_size=0x00e00000\0" \
+ "ramdisk_addr=0x01000000\0" \
+ "ramdisk_addr_r=0x86000000\0" \
+ "ramdisk_size=0x00800000\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
"if test $kernel_addr_load = $kernel_addr_r; then " \
@@ -192,17 +190,17 @@
"tftpboot $second_image && " \
"mmc write $loadaddr 0 100 && " \
"tftpboot $third_image && " \
- "mmc write $loadaddr 100 700\0" \
+ "mmc write $loadaddr 100 f00\0" \
"nandupdate=nand erase 0 0x00100000 &&" \
"tftpboot $second_image && " \
"nand write $loadaddr 0 0x00020000 && " \
"tftpboot $third_image && " \
- "nand write $loadaddr 0x00020000 0x000e0000\0" \
+ "nand write $loadaddr 0x00020000 0x001e0000\0" \
"usbupdate=usb start &&" \
"tftpboot $second_image && " \
"usb write $loadaddr 0 100 && " \
"tftpboot $third_image && " \
- "usb write $loadaddr 100 700\0" \
+ "usb write $loadaddr 100 f00\0" \
BOOT_IMAGES \
LINUXBOOT_ENV_SETTINGS
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 836dbb7..1c44f76 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -26,10 +26,8 @@
/* UART */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1
/* SD/MMC */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
@@ -53,7 +51,7 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Linux boot */
-#define CONFIG_HOSTNAME usbarmory
+#define CONFIG_HOSTNAME "usbarmory"
#define CONFIG_BOOTCOMMAND \
"run distro_bootcmd; " \
"setenv bootargs console=${console} ${bootargs_default}; " \
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 2168279..4780c2c 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -52,7 +52,6 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_CLK 921600
/*
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 580a08b..bbd8ec5 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -234,7 +234,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -266,7 +265,6 @@
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
@@ -439,7 +437,7 @@
#define CONFIG_NETDEV eth0
-#define CONFIG_HOSTNAME ve8313
+#define CONFIG_HOSTNAME "ve8313"
#define CONFIG_UBOOTPATH ve8313/u-boot.bin
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index d3422a5..208a315 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -105,7 +105,6 @@
#endif
/* PL011 Serial Configuration */
-#define CONFIG_CONS_INDEX 0
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7273800
#else
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 6a10edb..3e2d410 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -134,7 +134,6 @@
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
-#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_SERIAL0 V2M_UART0
diff --git a/include/configs/veyron.h b/include/configs/veyron.h
index 3a5fc06..4952255 100644
--- a/include/configs/veyron.h
+++ b/include/configs/veyron.h
@@ -14,7 +14,6 @@
#include <configs/rk3288_common.h>
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_KEYBOARD
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 80a501e..267b274 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -42,7 +42,6 @@
#define CONFIG_MTD_DEVICE
#endif
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index ca39589..9a63b3f 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -38,7 +38,6 @@
/* SerialFlash */
#ifdef CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 0
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index f054c99..45d1c35 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -92,7 +92,6 @@
#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K)
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 6bbf364..9559b50 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -194,7 +194,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -279,10 +278,6 @@
/*
* TSEC configuration
*/
-#ifdef VME_CADDY2
-#else
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-#endif
#if defined(CONFIG_TSEC_ENET)
@@ -500,7 +495,7 @@
#define CONFIG_HAS_ETH1
#endif
-#define CONFIG_HOSTNAME VME8349
+#define CONFIG_HOSTNAME "VME8349"
#define CONFIG_ROOTPATH "/tftpboot/rootfs"
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 487cb1f..7b50284 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -12,7 +12,6 @@
#include "mx6_common.h"
#include "imx6_spl.h"
-#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6
@@ -79,7 +78,6 @@
#define CONFIG_IMX_VIDEO_SKIP
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200\0" \
"splashpos=m,m\0" \
diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h
index c61865f..028e3ff 100644
--- a/include/configs/wb50n.h
+++ b/include/configs/wb50n.h
@@ -23,7 +23,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_IMAGE_FORMAT_LEGACY
/* general purpose I/O */
@@ -53,7 +52,6 @@
#define CONFIG_SYS_MEMTEST_START 0x21000000
#define CONFIG_SYS_MEMTEST_END 0x22000000
-#define CONFIG_SYS_ALT_MEMTEST
/* NAND flash */
#define CONFIG_NAND_ATMEL
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index af06548..7e993b8 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -53,7 +53,6 @@
#define CONFIG_RTC_MC13XXX
/* mmc driver */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
@@ -65,7 +64,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
/*
* Command definition
@@ -166,7 +164,7 @@
* to update uboot and load kernel
*/
-#define CONFIG_HOSTNAME woodburn
+#define CONFIG_HOSTNAME "woodburn"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -184,9 +182,9 @@
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
+ "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
@@ -200,7 +198,7 @@
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +80000;" \
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index cabd815..ee82816 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -25,7 +25,6 @@
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
/* generate LPC32XX-specific SPL image */
#define CONFIG_LPC32XX_SPL
@@ -56,7 +55,6 @@
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
-#define CONFIG_PHY_ADDR 0
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index bfa6f5e..a6fb988 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -38,7 +38,6 @@
#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
-#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
57600, 115200 }
#define CONFIG_SYS_LOADS_BAUD_CHANGE
@@ -70,7 +69,6 @@
/* Ethernet config options */
#define CONFIG_MII
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_SPEAR_GPIO
@@ -115,13 +113,13 @@
#define CONFIG_SYS_MALLOC_LEN (8 << 20)
#define CONFIG_SYS_LOAD_ADDR 0x00800000
-#define CONFIG_HOSTNAME x600
+#define CONFIG_HOSTNAME "x600"
#define CONFIG_UBI_PART ubi0
#define CONFIG_UBIFS_VOLUME rootfs
#define CONFIG_EXTRA_ENV_SETTINGS \
"u-boot_addr=1000000\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \
"load=tftp ${u-boot_addr} ${u-boot}\0" \
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize};" \
@@ -131,7 +129,7 @@
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
"upd=run load update\0" \
- "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
+ "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
"part=" __stringify(CONFIG_UBI_PART) "\0" \
"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
"load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
@@ -156,12 +154,12 @@
"saveenv;boot\0" \
"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
"root=ubi0:rootfs rootfstype=ubifs\0" \
- "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "kernel=" CONFIG_HOSTNAME "/uImage\0" \
"kernel_fs=/boot/uImage \0" \
"kernel_addr=1000000\0" \
- "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
- __stringify(CONFIG_HOSTNAME) ".dtb\0" \
- "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb=" CONFIG_HOSTNAME "/" \
+ CONFIG_HOSTNAME ".dtb\0" \
+ "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
"dtb_addr=1800000\0" \
"load_kernel=tftp ${kernel_addr} ${kernel}\0" \
"load_dtb=tftp ${dtb_addr} ${dtb}\0" \
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 8d8c689..6d650b7 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -17,8 +17,6 @@
*/
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_PHYSMEM
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_LAST_STAGE_INIT
#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_LMB
@@ -112,7 +110,7 @@
/* Default environment */
#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_HOSTNAME x86
+#define CONFIG_HOSTNAME "x86"
#define CONFIG_BOOTFILE "bzImage"
#define CONFIG_LOADADDR 0x1000000
#define CONFIG_RAMDISK_ADDR 0x4000000
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index f5fc245..5827911 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -20,8 +20,9 @@
#define GICD_BASE 0xF9010000
#define GICC_BASE 0xF9020000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
+#ifndef CONFIG_SYS_MEMTEST_SCRATCH
+# define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+#endif
#ifndef CONFIG_NR_DRAM_BANKS
# define CONFIG_NR_DRAM_BANKS 2
@@ -43,7 +44,6 @@
#define CONFIG_ARM_DCC
#define CONFIG_CPU_ARMV8
-#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
@@ -143,7 +143,6 @@
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_CLOCKS
#define ENV_MEM_LAYOUT_SETTINGS \
@@ -173,12 +172,24 @@
# define BOOT_TARGET_DEVICES_USB(func)
#endif
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
+ BOOT_TARGET_DEVICES_PXE(func) \
+ BOOT_TARGET_DEVICES_DHCP(func)
#include <config_distro_bootcmd.h>
@@ -210,7 +221,6 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
-# define CONFIG_SPL_SPI_LOAD
# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000
# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000
# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
deleted file mode 100644
index a26377a..0000000
--- a/include/configs/xilinx_zynqmp_ep.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Configuration for Xilinx ZynqMP emulation platforms
- *
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- *
- * Based on Configuration for Versatile Express
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQMP_EP_H
-#define __CONFIG_ZYNQMP_EP_H
-
-#define CONFIG_ZYNQ_EEPROM
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
- ZYNQMP_USB1_XHCI_BASEADDR}
-
-#define COUNTER_FREQUENCY 4000000
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_EP_H */
diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h
index 00f4c1c..4fbf85a 100644
--- a/include/configs/xilinx_zynqmp_mini.h
+++ b/include/configs/xilinx_zynqmp_mini.h
@@ -11,6 +11,8 @@
#ifndef __CONFIG_ZYNQMP_MINI_H
#define __CONFIG_ZYNQMP_MINI_H
+#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
+
#include <configs/xilinx_zynqmp.h>
/* Undef unneeded configs */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h b/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h
new file mode 100644
index 0000000..cdc0062
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h
@@ -0,0 +1,20 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM017 DC3
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H
+#define __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H
+
+#define CONFIG_ZYNQ_SDHCI1
+
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
+ ZYNQMP_USB1_XHCI_BASEADDR}
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H */
diff --git a/include/configs/xilinx_zynqmp_zcu100.h b/include/configs/xilinx_zynqmp_zcu100.h
new file mode 100644
index 0000000..bfb85d6
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zcu100.h
@@ -0,0 +1,36 @@
+/*
+ * Configuration for Xilinx ZynqMP zcu100
+ *
+ * (C) Copyright 2015 - 2016 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU100_H
+#define __CONFIG_ZYNQMP_ZCU100_H
+
+/* FIXME Will go away soon */
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 9
+#define CONFIG_SYS_I2C_BUSES { \
+ {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
+ }
+
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
+ ZYNQMP_USB1_XHCI_BASEADDR}
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU100_H */
diff --git a/include/configs/xilinx_zynqmp_zcu104.h b/include/configs/xilinx_zynqmp_zcu104.h
new file mode 100644
index 0000000..f8cdade
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zcu104.h
@@ -0,0 +1,36 @@
+/*
+ * Configuration for Xilinx ZynqMP zcu104
+ *
+ * (C) Copyright 2017 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU104_H
+#define __CONFIG_ZYNQMP_ZCU104_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 9
+#define CONFIG_SYS_I2C_BUSES { \
+ {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 5} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 6} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 7} } }, \
+ }
+
+#define CONFIG_PCA953X
+
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU104_H */
diff --git a/include/configs/xilinx_zynqmp_zcu106.h b/include/configs/xilinx_zynqmp_zcu106.h
new file mode 100644
index 0000000..0f0d8c6
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zcu106.h
@@ -0,0 +1,47 @@
+/*
+ * Configuration for Xilinx ZynqMP zcu106
+ *
+ * (C) Copyright 2016 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU106_H
+#define __CONFIG_ZYNQMP_ZCU106_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 18
+#define CONFIG_SYS_I2C_BUSES { \
+ {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
+ {1, {I2C_NULL_HOP} }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
+ }
+
+#define CONFIG_PCA953X
+
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_ZYNQ_EEPROM_BUS 5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU106_H */
diff --git a/include/configs/xilinx_zynqmp_zcu111.h b/include/configs/xilinx_zynqmp_zcu111.h
new file mode 100644
index 0000000..c488c21
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zcu111.h
@@ -0,0 +1,50 @@
+/*
+ * Configuration for Xilinx ZynqMP zcu111
+ *
+ * (C) Copyright 2017 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU111_H
+#define __CONFIG_ZYNQMP_ZCU111_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 21
+#define CONFIG_SYS_I2C_BUSES { \
+ {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 3} } }, \
+ {1, {I2C_NULL_HOP} }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 5} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 6} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
+ }
+
+#define CONFIG_PCA953X
+
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_ZYNQ_EEPROM_BUS 5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU111_H */
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index de10d8c..e05ec54 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -17,7 +17,6 @@
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1
@@ -79,7 +78,6 @@
/*
* Diagnostics
*/
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
@@ -191,7 +189,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -300,7 +297,6 @@
/*
* Networking options
*/
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_ETHPRIME "eTSEC1"
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index dfacd2a..6347953 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -16,7 +16,6 @@
*/
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC 1
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI1 1 /* PCI controller 1 */
@@ -55,7 +54,6 @@
/*
* Diagnostics
*/
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
@@ -162,7 +160,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -239,7 +236,6 @@
/*
* Networking options
*/
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_ETHPRIME "eTSEC1"
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index ea4773c..d0d21c4 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -16,7 +16,6 @@
*/
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
#define CONFIG_SYS_FORM_3U_VPX 1
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controller 1 */
@@ -72,7 +71,6 @@
/*
* Diagnostics
*/
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
@@ -187,7 +185,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -299,7 +296,6 @@
/*
* Networking options
*/
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_TSEC_TBI
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 883843a..f7ac2f4 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -17,7 +17,6 @@
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
@@ -70,7 +69,6 @@
/*
* Diagnostics
*/
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
@@ -188,7 +186,6 @@
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@ -283,7 +280,6 @@
/*
* Networking options
*/
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_TSEC_TBI
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index 691adda..8a920fa 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -182,7 +182,6 @@
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*======================*/
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index b5a326b..0860a50 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -43,7 +43,6 @@
* STUART - the lower serial port on Colibri board
*/
#define CONFIG_STUART 1
-#define CONFIG_CONS_INDEX 2
/*
* Bootloader Components Configuration
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 124431b..1dafda3 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -40,7 +40,6 @@
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
/*
* Ethernet
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 554fb66..ae82a7a 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -162,7 +162,7 @@
#define BOOT_TARGET_DEVICES_USB(func)
#endif
-#if defined(CONFIG_CMD_PXE)
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
@@ -298,7 +298,6 @@
/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
diff --git a/include/dm/platform_data/pfe_dm_eth.h b/include/dm/platform_data/pfe_dm_eth.h
new file mode 100644
index 0000000..7943c67
--- /dev/null
+++ b/include/dm/platform_data/pfe_dm_eth.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include <net.h>
+
+struct pfe_ddr_address {
+ void *ddr_pfe_baseaddr;
+ unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+ struct eth_pdata pfe_eth_pdata_mac;
+ struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 07fabc3..d28fb3e 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -19,6 +19,7 @@
UCLASS_TEST_FDT,
UCLASS_TEST_BUS,
UCLASS_TEST_PROBE,
+ UCLASS_TEST_DUMMY,
UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 3a01abc..a5bf3eb 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -211,6 +211,22 @@
struct udevice **devp);
/**
+ * uclass_get_device_by_phandle_id() - Get a uclass device by phandle id
+ *
+ * This searches the devices in the uclass for one with the given phandle id.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: uclass ID to look up
+ * @phandle_id: the phandle id to look up
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ENODEV if there is no device match the phandle, other
+ * -ve on error
+ */
+int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id,
+ struct udevice **devp);
+
+/**
* uclass_get_device_by_phandle() - Get a uclass device by phandle
*
* This searches the devices in the uclass for one with the given phandle.
diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h
new file mode 100644
index 0000000..6b11a9f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6362-clock.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
+#define __DT_BINDINGS_CLOCK_BCM6362_H
+
+#define BCM6362_CLK_GLESS 0
+#define BCM6362_CLK_ADSL_QPROC 1
+#define BCM6362_CLK_ADSL_AFE 2
+#define BCM6362_CLK_ADSL 3
+#define BCM6362_CLK_MIPS 4
+#define BCM6362_CLK_WLAN_OCP 5
+#define BCM6362_CLK_SWPKT_USB 7
+#define BCM6362_CLK_SWPKT_SAR 8
+#define BCM6362_CLK_SAR 9
+#define BCM6362_CLK_ROBOSW 10
+#define BCM6362_CLK_PCM 11
+#define BCM6362_CLK_USBD 12
+#define BCM6362_CLK_USBH 13
+#define BCM6362_CLK_IPSEC 14
+#define BCM6362_CLK_SPI 15
+#define BCM6362_CLK_HSSPI 16
+#define BCM6362_CLK_PCIE 17
+#define BCM6362_CLK_FAP 18
+#define BCM6362_CLK_PHYMIPS 19
+#define BCM6362_CLK_NAND 20
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644
index 0000000..1643158
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+/* OSCILLATOR clocks */
+#define CK_HSE 0
+#define CK_CSI 1
+#define CK_LSI 2
+#define CK_LSE 3
+#define CK_HSI 4
+#define CK_HSE_DIV2 5
+
+/* Bus clocks */
+#define TIM2 6
+#define TIM3 7
+#define TIM4 8
+#define TIM5 9
+#define TIM6 10
+#define TIM7 11
+#define TIM12 12
+#define TIM13 13
+#define TIM14 14
+#define LPTIM1 15
+#define SPI2 16
+#define SPI3 17
+#define USART2 18
+#define USART3 19
+#define UART4 20
+#define UART5 21
+#define UART7 22
+#define UART8 23
+#define I2C1 24
+#define I2C2 25
+#define I2C3 26
+#define I2C5 27
+#define SPDIF 28
+#define CEC 29
+#define DAC12 30
+#define MDIO 31
+#define TIM1 32
+#define TIM8 33
+#define TIM15 34
+#define TIM16 35
+#define TIM17 36
+#define SPI1 37
+#define SPI4 38
+#define SPI5 39
+#define USART6 40
+#define SAI1 41
+#define SAI2 42
+#define SAI3 43
+#define DFSDM 44
+#define FDCAN 45
+#define LPTIM2 46
+#define LPTIM3 47
+#define LPTIM4 48
+#define LPTIM5 49
+#define SAI4 50
+#define SYSCFG 51
+#define VREF 52
+#define TMPSENS 53
+#define PMBCTRL 54
+#define HDP 55
+#define LTDC 56
+#define DSI 57
+#define IWDG2 58
+#define USBPHY 59
+#define STGENRO 60
+#define SPI6 61
+#define I2C4 62
+#define I2C6 63
+#define USART1 64
+#define RTCAPB 65
+#define TZC 66
+#define TZPC 67
+#define IWDG1 68
+#define BSEC 69
+#define STGEN 70
+#define DMA1 71
+#define DMA2 72
+#define DMAMUX 73
+#define ADC12 74
+#define USBO 75
+#define SDMMC3 76
+#define DCMI 77
+#define CRYP2 78
+#define HASH2 79
+#define RNG2 80
+#define CRC2 81
+#define HSEM 82
+#define IPCC 83
+#define GPIOA 84
+#define GPIOB 85
+#define GPIOC 86
+#define GPIOD 87
+#define GPIOE 88
+#define GPIOF 89
+#define GPIOG 90
+#define GPIOH 91
+#define GPIOI 92
+#define GPIOJ 93
+#define GPIOK 94
+#define GPIOZ 95
+#define CRYP1 96
+#define HASH1 97
+#define RNG1 98
+#define BKPSRAM 99
+#define MDMA 100
+#define DMA2D 101
+#define GPU 102
+#define ETHCK 103
+#define ETHTX 104
+#define ETHRX 105
+#define ETHMAC 106
+#define FMC 107
+#define QSPI 108
+#define SDMMC1 109
+#define SDMMC2 110
+#define CRC1 111
+#define USBH 112
+#define ETHSTP 113
+
+/* Kernel clocks */
+#define SDMMC1_K 114
+#define SDMMC2_K 115
+#define SDMMC3_K 116
+#define FMC_K 117
+#define QSPI_K 118
+#define ETHMAC_K 119
+#define RNG1_K 120
+#define RNG2_K 121
+#define GPU_K 122
+#define USBPHY_K 123
+#define STGEN_K 124
+#define SPDIF_K 125
+#define SPI1_K 126
+#define SPI2_K 127
+#define SPI3_K 128
+#define SPI4_K 129
+#define SPI5_K 130
+#define SPI6_K 131
+#define CEC_K 132
+#define I2C1_K 133
+#define I2C2_K 134
+#define I2C3_K 135
+#define I2C4_K 136
+#define I2C5_K 137
+#define I2C6_K 138
+#define LPTIM1_K 139
+#define LPTIM2_K 140
+#define LPTIM3_K 141
+#define LPTIM4_K 142
+#define LPTIM5_K 143
+#define USART1_K 144
+#define USART2_K 145
+#define USART3_K 146
+#define UART4_K 147
+#define UART5_K 148
+#define USART6_K 149
+#define UART7_K 150
+#define UART8_K 151
+#define DFSDM_K 152
+#define FDCAN_K 153
+#define SAI1_K 154
+#define SAI2_K 155
+#define SAI3_K 156
+#define SAI4_K 157
+#define ADC12_K 158
+#define DSI_K 159
+#define ADFSDM_K 160
+#define USBO_K 161
+#define LTDC_K 162
+
+/* PLL */
+#define PLL1 163
+#define PLL2 164
+#define PLL3 165
+#define PLL4 166
+
+/* ODF */
+#define PLL1_P 167
+#define PLL1_Q 168
+#define PLL1_R 169
+#define PLL2_P 170
+#define PLL2_Q 171
+#define PLL2_R 172
+#define PLL3_P 173
+#define PLL3_Q 174
+#define PLL3_R 175
+#define PLL4_P 176
+#define PLL4_Q 177
+#define PLL4_R 178
+
+/* AUX */
+#define RTC 179
+
+/* MCLK */
+#define CK_PER 180
+#define CK_MPU 181
+#define CK_AXI 182
+#define CK_MCU 183
+
+/* Time base */
+#define TIM2_K 184
+#define TIM3_K 185
+#define TIM4_K 186
+#define TIM5_K 187
+#define TIM6_K 188
+#define TIM7_K 189
+#define TIM12_K 190
+#define TIM13_K 191
+#define TIM14_K 192
+#define TIM1_K 193
+#define TIM8_K 194
+#define TIM15_K 195
+#define TIM16_K 196
+#define TIM17_K 197
+
+/* MCO clocks */
+#define CK_MCO1 198
+#define CK_MCO2 199
+
+/* TRACE & DEBUG clocks */
+#define DBG 200
+#define CK_DBG 201
+#define CK_TRACE 202
+
+/* DDR */
+#define DDRC1 203
+#define DDRC1LP 204
+#define DDRC2 205
+#define DDRC2LP 206
+#define DDRPHYC 207
+#define DDRPHYCLP 208
+#define DDRCAPB 209
+#define DDRCAPBLP 210
+#define AXIDCG 211
+#define DDRPHYCAPB 212
+#define DDRPHYCAPBLP 213
+#define DDRPERFM 214
+
+#define STM32MP1_LAST_CLK 215
diff --git a/include/dt-bindings/clock/stm32mp1-clksrc.h b/include/dt-bindings/clock/stm32mp1-clksrc.h
new file mode 100644
index 0000000..19fd959
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clksrc.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+
+/* PLL output is enable when x=1, with x=p,q or r */
+#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
+
+/* st,clksrc: mandatory clock source */
+
+#define CLK_MPU_HSI 0x00000200
+#define CLK_MPU_HSE 0x00000201
+#define CLK_MPU_PLL1P 0x00000202
+#define CLK_MPU_PLL1P_DIV 0x00000203
+
+#define CLK_AXI_HSI 0x00000240
+#define CLK_AXI_HSE 0x00000241
+#define CLK_AXI_PLL2P 0x00000242
+
+#define CLK_MCU_HSI 0x00000480
+#define CLK_MCU_HSE 0x00000481
+#define CLK_MCU_CSI 0x00000482
+#define CLK_MCU_PLL3P 0x00000483
+
+#define CLK_PLL12_HSI 0x00000280
+#define CLK_PLL12_HSE 0x00000281
+
+#define CLK_PLL3_HSI 0x00008200
+#define CLK_PLL3_HSE 0x00008201
+#define CLK_PLL3_CSI 0x00008202
+
+#define CLK_PLL4_HSI 0x00008240
+#define CLK_PLL4_HSE 0x00008241
+#define CLK_PLL4_CSI 0x00008242
+#define CLK_PLL4_I2SCKIN 0x00008243
+
+#define CLK_RTC_DISABLED 0x00001400
+#define CLK_RTC_LSE 0x00001401
+#define CLK_RTC_LSI 0x00001402
+#define CLK_RTC_HSE 0x00001403
+
+#define CLK_MCO1_HSI 0x00008000
+#define CLK_MCO1_HSE 0x00008001
+#define CLK_MCO1_CSI 0x00008002
+#define CLK_MCO1_LSI 0x00008003
+#define CLK_MCO1_LSE 0x00008004
+#define CLK_MCO1_DISABLED 0x0000800F
+
+#define CLK_MCO2_MPU 0x00008040
+#define CLK_MCO2_AXI 0x00008041
+#define CLK_MCO2_MCU 0x00008042
+#define CLK_MCO2_PLL4P 0x00008043
+#define CLK_MCO2_HSE 0x00008044
+#define CLK_MCO2_HSI 0x00008045
+#define CLK_MCO2_DISABLED 0x0000804F
+
+/* st,pkcs: peripheral kernel clock source */
+
+#define CLK_I2C12_PCLK1 0x00008C00
+#define CLK_I2C12_PLL4R 0x00008C01
+#define CLK_I2C12_HSI 0x00008C02
+#define CLK_I2C12_CSI 0x00008C03
+#define CLK_I2C12_DISABLED 0x00008C07
+
+#define CLK_I2C35_PCLK1 0x00008C40
+#define CLK_I2C35_PLL4R 0x00008C41
+#define CLK_I2C35_HSI 0x00008C42
+#define CLK_I2C35_CSI 0x00008C43
+#define CLK_I2C35_DISABLED 0x00008C47
+
+#define CLK_I2C46_PCLK5 0x00000C00
+#define CLK_I2C46_PLL3Q 0x00000C01
+#define CLK_I2C46_HSI 0x00000C02
+#define CLK_I2C46_CSI 0x00000C03
+#define CLK_I2C46_DISABLED 0x00000C07
+
+#define CLK_SAI1_PLL4Q 0x00008C80
+#define CLK_SAI1_PLL3Q 0x00008C81
+#define CLK_SAI1_I2SCKIN 0x00008C82
+#define CLK_SAI1_CKPER 0x00008C83
+#define CLK_SAI1_PLL3R 0x00008C84
+#define CLK_SAI1_DISABLED 0x00008C87
+
+#define CLK_SAI2_PLL4Q 0x00008CC0
+#define CLK_SAI2_PLL3Q 0x00008CC1
+#define CLK_SAI2_I2SCKIN 0x00008CC2
+#define CLK_SAI2_CKPER 0x00008CC3
+#define CLK_SAI2_SPDIF 0x00008CC4
+#define CLK_SAI2_PLL3R 0x00008CC5
+#define CLK_SAI2_DISABLED 0x00008CC7
+
+#define CLK_SAI3_PLL4Q 0x00008D00
+#define CLK_SAI3_PLL3Q 0x00008D01
+#define CLK_SAI3_I2SCKIN 0x00008D02
+#define CLK_SAI3_CKPER 0x00008D03
+#define CLK_SAI3_PLL3R 0x00008D04
+#define CLK_SAI3_DISABLED 0x00008D07
+
+#define CLK_SAI4_PLL4Q 0x00008D40
+#define CLK_SAI4_PLL3Q 0x00008D41
+#define CLK_SAI4_I2SCKIN 0x00008D42
+#define CLK_SAI4_CKPER 0x00008D43
+#define CLK_SAI4_PLL3R 0x00008D44
+#define CLK_SAI4_DISABLED 0x00008D47
+
+#define CLK_SPI2S1_PLL4P 0x00008D80
+#define CLK_SPI2S1_PLL3Q 0x00008D81
+#define CLK_SPI2S1_I2SCKIN 0x00008D82
+#define CLK_SPI2S1_CKPER 0x00008D83
+#define CLK_SPI2S1_PLL3R 0x00008D84
+#define CLK_SPI2S1_DISABLED 0x00008D87
+
+#define CLK_SPI2S23_PLL4P 0x00008DC0
+#define CLK_SPI2S23_PLL3Q 0x00008DC1
+#define CLK_SPI2S23_I2SCKIN 0x00008DC2
+#define CLK_SPI2S23_CKPER 0x00008DC3
+#define CLK_SPI2S23_PLL3R 0x00008DC4
+#define CLK_SPI2S23_DISABLED 0x00008DC7
+
+#define CLK_SPI45_PCLK2 0x00008E00
+#define CLK_SPI45_PLL4Q 0x00008E01
+#define CLK_SPI45_HSI 0x00008E02
+#define CLK_SPI45_CSI 0x00008E03
+#define CLK_SPI45_HSE 0x00008E04
+#define CLK_SPI45_DISABLED 0x00008E07
+
+#define CLK_SPI6_PCLK5 0x00000C40
+#define CLK_SPI6_PLL4Q 0x00000C41
+#define CLK_SPI6_HSI 0x00000C42
+#define CLK_SPI6_CSI 0x00000C43
+#define CLK_SPI6_HSE 0x00000C44
+#define CLK_SPI6_PLL3Q 0x00000C45
+#define CLK_SPI6_DISABLED 0x00000C47
+
+#define CLK_UART6_PCLK2 0x00008E40
+#define CLK_UART6_PLL4Q 0x00008E41
+#define CLK_UART6_HSI 0x00008E42
+#define CLK_UART6_CSI 0x00008E43
+#define CLK_UART6_HSE 0x00008E44
+#define CLK_UART6_DISABLED 0x00008E47
+
+#define CLK_UART24_PCLK1 0x00008E80
+#define CLK_UART24_PLL4Q 0x00008E81
+#define CLK_UART24_HSI 0x00008E82
+#define CLK_UART24_CSI 0x00008E83
+#define CLK_UART24_HSE 0x00008E84
+#define CLK_UART24_DISABLED 0x00008E87
+
+#define CLK_UART35_PCLK1 0x00008EC0
+#define CLK_UART35_PLL4Q 0x00008EC1
+#define CLK_UART35_HSI 0x00008EC2
+#define CLK_UART35_CSI 0x00008EC3
+#define CLK_UART35_HSE 0x00008EC4
+#define CLK_UART35_DISABLED 0x00008EC7
+
+#define CLK_UART78_PCLK1 0x00008F00
+#define CLK_UART78_PLL4Q 0x00008F01
+#define CLK_UART78_HSI 0x00008F02
+#define CLK_UART78_CSI 0x00008F03
+#define CLK_UART78_HSE 0x00008F04
+#define CLK_UART78_DISABLED 0x00008F07
+
+#define CLK_UART1_PCLK5 0x00000C80
+#define CLK_UART1_PLL3Q 0x00000C81
+#define CLK_UART1_HSI 0x00000C82
+#define CLK_UART1_CSI 0x00000C83
+#define CLK_UART1_PLL4Q 0x00000C84
+#define CLK_UART1_HSE 0x00000C85
+#define CLK_UART1_DISABLED 0x00000C87
+
+#define CLK_SDMMC12_HCLK6 0x00008F40
+#define CLK_SDMMC12_PLL3R 0x00008F41
+#define CLK_SDMMC12_PLL4P 0x00008F42
+#define CLK_SDMMC12_HSI 0x00008F43
+#define CLK_SDMMC12_DISABLED 0x00008F47
+
+#define CLK_SDMMC3_HCLK2 0x00008F80
+#define CLK_SDMMC3_PLL3R 0x00008F81
+#define CLK_SDMMC3_PLL4P 0x00008F82
+#define CLK_SDMMC3_HSI 0x00008F83
+#define CLK_SDMMC3_DISABLED 0x00008F87
+
+#define CLK_ETH_PLL4P 0x00008FC0
+#define CLK_ETH_PLL3Q 0x00008FC1
+#define CLK_ETH_DISABLED 0x00008FC3
+
+#define CLK_QSPI_ACLK 0x00009000
+#define CLK_QSPI_PLL3R 0x00009001
+#define CLK_QSPI_PLL4P 0x00009002
+#define CLK_QSPI_CKPER 0x00009003
+
+#define CLK_FMC_ACLK 0x00009040
+#define CLK_FMC_PLL3R 0x00009041
+#define CLK_FMC_PLL4P 0x00009042
+#define CLK_FMC_CKPER 0x00009043
+
+#define CLK_FDCAN_HSE 0x000090C0
+#define CLK_FDCAN_PLL3Q 0x000090C1
+#define CLK_FDCAN_PLL4Q 0x000090C2
+#define CLK_FDCAN_PLL4R 0x000090C3
+
+#define CLK_SPDIF_PLL4P 0x00009140
+#define CLK_SPDIF_PLL3Q 0x00009141
+#define CLK_SPDIF_HSI 0x00009142
+#define CLK_SPDIF_DISABLED 0x00009143
+
+#define CLK_CEC_LSE 0x00009180
+#define CLK_CEC_LSI 0x00009181
+#define CLK_CEC_CSI_DIV122 0x00009182
+#define CLK_CEC_DISABLED 0x00009183
+
+#define CLK_USBPHY_HSE 0x000091C0
+#define CLK_USBPHY_PLL4R 0x000091C1
+#define CLK_USBPHY_HSE_DIV2 0x000091C2
+#define CLK_USBPHY_DISABLED 0x000091C3
+
+#define CLK_USBO_PLL4R 0x800091C0
+#define CLK_USBO_USBPHY 0x800091C1
+
+#define CLK_RNG1_CSI 0x00000CC0
+#define CLK_RNG1_PLL4R 0x00000CC1
+#define CLK_RNG1_LSE 0x00000CC2
+#define CLK_RNG1_LSI 0x00000CC3
+
+#define CLK_RNG2_CSI 0x00009200
+#define CLK_RNG2_PLL4R 0x00009201
+#define CLK_RNG2_LSE 0x00009202
+#define CLK_RNG2_LSI 0x00009203
+
+#define CLK_CKPER_HSI 0x00000D00
+#define CLK_CKPER_CSI 0x00000D01
+#define CLK_CKPER_HSE 0x00000D02
+#define CLK_CKPER_DISABLED 0x00000D03
+
+#define CLK_STGEN_HSI 0x00000D40
+#define CLK_STGEN_HSE 0x00000D41
+#define CLK_STGEN_DISABLED 0x00000D43
+
+#define CLK_DSI_DSIPLL 0x00009240
+#define CLK_DSI_PLL4P 0x00009241
+
+#define CLK_ADC_PLL4R 0x00009280
+#define CLK_ADC_CKPER 0x00009281
+#define CLK_ADC_PLL3Q 0x00009282
+#define CLK_ADC_DISABLED 0x00009283
+
+#define CLK_LPTIM45_PCLK3 0x000092C0
+#define CLK_LPTIM45_PLL4P 0x000092C1
+#define CLK_LPTIM45_PLL3Q 0x000092C2
+#define CLK_LPTIM45_LSE 0x000092C3
+#define CLK_LPTIM45_LSI 0x000092C4
+#define CLK_LPTIM45_CKPER 0x000092C5
+#define CLK_LPTIM45_DISABLED 0x000092C7
+
+#define CLK_LPTIM23_PCLK3 0x00009300
+#define CLK_LPTIM23_PLL4Q 0x00009301
+#define CLK_LPTIM23_CKPER 0x00009302
+#define CLK_LPTIM23_LSE 0x00009303
+#define CLK_LPTIM23_LSI 0x00009304
+#define CLK_LPTIM23_DISABLED 0x00009307
+
+#define CLK_LPTIM1_PCLK1 0x00009340
+#define CLK_LPTIM1_PLL4P 0x00009341
+#define CLK_LPTIM1_PLL3Q 0x00009342
+#define CLK_LPTIM1_LSE 0x00009343
+#define CLK_LPTIM1_LSI 0x00009344
+#define CLK_LPTIM1_CKPER 0x00009345
+#define CLK_LPTIM1_DISABLED 0x00009347
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD 0
+#define SSCG_MODE_DOWN_SPREAD 1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST 0
+#define LSEDRV_MEDIUM_LOW 1
+#define LSEDRV_MEDIUM_HIGH 2
+#define LSEDRV_HIGHEST 3
+
+#endif
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
index 44c0914..c9087f5 100644
--- a/include/dt-bindings/mfd/stm32f7-rcc.h
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -106,6 +106,7 @@
#define STM32F7_RCC_APB2_SAI1 22
#define STM32F7_RCC_APB2_SAI2 23
#define STM32F7_RCC_APB2_LTDC 26
+#define STM32F7_RCC_APB2_DSI 27
#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
deleted file mode 100644
index e1b81fe..0000000
--- a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * MIO pin configuration defines for Xilinx ZynqMP
- *
- * Copyright (C) 2017 Xilinx, Inc.
- * Author: Chirag Parekh <chirag.parekh@xilinx.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
-#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
-
-/* Bit value for IO standards */
-#define IO_STANDARD_LVCMOS33 0
-#define IO_STANDARD_LVCMOS18 1
-
-/* Bit values for Slew Rates */
-#define SLEW_RATE_FAST 0
-#define SLEW_RATE_SLOW 1
-
-/* Bit values for Pin inputs */
-#define PIN_INPUT_TYPE_CMOS 0
-#define PIN_INPUT_TYPE_SCHMITT 1
-
-#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h
new file mode 100644
index 0000000..3178b00
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+
+#define BCM6362_PWR_SAR 0
+#define BCM6362_PWR_IPSEC 1
+#define BCM6362_PWR_MIPS 2
+#define BCM6362_PWR_DECT 3
+#define BCM6362_PWR_USBH 4
+#define BCM6362_PWR_USBD 5
+#define BCM6362_PWR_ROBOSW 6
+#define BCM6362_PWR_PCM 7
+#define BCM6362_PWR_PERIPH 8
+#define BCM6362_PWR_ADSL_PHY 9
+#define BCM6362_PWR_GMII_PADS 10
+#define BCM6362_PWR_FAP 11
+#define BCM6362_PWR_PCIE 12
+#define BCM6362_PWR_WLAN_PADS 13
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */
diff --git a/include/dt-bindings/reset-controller/stm32mp1-resets.h b/include/dt-bindings/reset-controller/stm32mp1-resets.h
new file mode 100644
index 0000000..f279f8f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stm32mp1-resets.h
@@ -0,0 +1,97 @@
+#define LTDC_R 3072
+#define DSI_R 3076
+#define DDRPERFM_R 3080
+#define USBPHY_R 3088
+#define SPI6_R 3136
+#define I2C4_R 3138
+#define I2C6_R 3139
+#define USART1_R 3140
+#define STGEN_R 3156
+#define GPIOZ_R 3200
+#define CRYP1_R 3204
+#define HASH1_R 3205
+#define RNG1_R 3206
+#define AXIM_R 3216
+#define GPU_R 3269
+#define ETHMAC_R 3274
+#define FMC_R 3276
+#define QSPI_R 3278
+#define SDMMC1_R 3280
+#define SDMMC2_R 3281
+#define CRC1_R 3284
+#define USBH_R 3288
+#define MDMA_R 3328
+#define MCU_R 8225
+#define TIM2_R 19456
+#define TIM3_R 19457
+#define TIM4_R 19458
+#define TIM5_R 19459
+#define TIM6_R 19460
+#define TIM7_R 19461
+#define TIM12_R 16462
+#define TIM13_R 16463
+#define TIM14_R 16464
+#define LPTIM1_R 19465
+#define SPI2_R 19467
+#define SPI3_R 19468
+#define USART2_R 19470
+#define USART3_R 19471
+#define UART4_R 19472
+#define UART5_R 19473
+#define UART7_R 19474
+#define UART8_R 19475
+#define I2C1_R 19477
+#define I2C2_R 19478
+#define I2C3_R 19479
+#define I2C5_R 19480
+#define SPDIF_R 19482
+#define CEC_R 19483
+#define DAC12_R 19485
+#define MDIO_R 19847
+#define TIM1_R 19520
+#define TIM8_R 19521
+#define TIM15_R 19522
+#define TIM16_R 19523
+#define TIM17_R 19524
+#define SPI1_R 19528
+#define SPI4_R 19529
+#define SPI5_R 19530
+#define USART6_R 19533
+#define SAI1_R 19536
+#define SAI2_R 19537
+#define SAI3_R 19538
+#define DFSDM_R 19540
+#define FDCAN_R 19544
+#define LPTIM2_R 19584
+#define LPTIM3_R 19585
+#define LPTIM4_R 19586
+#define LPTIM5_R 19587
+#define SAI4_R 19592
+#define SYSCFG_R 19595
+#define VREF_R 19597
+#define TMPSENS_R 19600
+#define PMBCTRL_R 19601
+#define DMA1_R 19648
+#define DMA2_R 19649
+#define DMAMUX_R 19650
+#define ADC12_R 19653
+#define USBO_R 19656
+#define SDMMC3_R 19664
+#define CAMITF_R 19712
+#define CRYP2_R 19716
+#define HASH2_R 19717
+#define RNG2_R 19718
+#define CRC2_R 19719
+#define HSEM_R 19723
+#define MBOX_R 19724
+#define GPIOA_R 19776
+#define GPIOB_R 19777
+#define GPIOC_R 19778
+#define GPIOD_R 19779
+#define GPIOE_R 19780
+#define GPIOF_R 19781
+#define GPIOG_R 19782
+#define GPIOH_R 19783
+#define GPIOI_R 19784
+#define GPIOJ_R 19785
+#define GPIOK_R 19786
diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h
new file mode 100644
index 0000000..ffa46a6
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6362-reset.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6362_H
+#define __DT_BINDINGS_RESET_BCM6362_H
+
+#define BCM6362_RST_SPI 0
+#define BCM6362_RST_IPSEC 1
+#define BCM6362_RST_EPHY 2
+#define BCM6362_RST_SAR 3
+#define BCM6362_RST_ENETSW 4
+#define BCM6362_RST_USBD 5
+#define BCM6362_RST_USBH 6
+#define BCM6362_RST_PCM 7
+#define BCM6362_RST_PCIE_CORE 8
+#define BCM6362_RST_PCIE 9
+#define BCM6362_RST_PCIE_EXT 10
+#define BCM6362_RST_WLAN_SHIM 11
+#define BCM6362_RST_DDR_PHY 12
+#define BCM6362_RST_FAP 13
+#define BCM6362_RST_WLAN_UBUS 14
+
+#endif /* __DT_BINDINGS_RESET_BCM6362_H */
diff --git a/include/efi_api.h b/include/efi_api.h
index 3ba650e..ae93061 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -107,7 +107,7 @@
efi_status_t (EFIAPI *load_image)(bool boot_policiy,
efi_handle_t parent_image,
struct efi_device_path *file_path, void *source_buffer,
- unsigned long source_size, efi_handle_t *image);
+ efi_uintn_t source_size, efi_handle_t *image);
efi_status_t (EFIAPI *start_image)(efi_handle_t handle,
unsigned long *exitdata_size,
s16 **exitdata);
@@ -180,7 +180,8 @@
enum efi_reset_type {
EFI_RESET_COLD = 0,
EFI_RESET_WARM = 1,
- EFI_RESET_SHUTDOWN = 2
+ EFI_RESET_SHUTDOWN = 2,
+ EFI_RESET_PLATFORM_SPECIFIC = 3,
};
/* EFI Runtime Services table */
@@ -243,6 +244,27 @@
u64 maximum_variable_size);
};
+/* EFI event group GUID definitions */
+#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
+ EFI_GUID(0x27abf055, 0xb1b8, 0x4c26, 0x80, 0x48, \
+ 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf)
+
+#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \
+ EFI_GUID(0x13fa7698, 0xc831, 0x49c7, 0x87, 0xea, \
+ 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96)
+
+#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \
+ EFI_GUID(0x78bee926, 0x692f, 0x48fd, 0x9e, 0xdb, \
+ 0x01, 0x42, 0x2e, 0xf0, 0xd7, 0xab)
+
+#define EFI_EVENT_GROUP_READY_TO_BOOT \
+ EFI_GUID(0x7ce88fb3, 0x4bd7, 0x4679, 0x87, 0xa8, \
+ 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b)
+
+#define EFI_EVENT_GROUP_RESET_SYSTEM \
+ EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \
+ 0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b)
+
/* EFI Configuration Table and GUID definitions */
#define NULL_GUID \
EFI_GUID(0x00000000, 0x0000, 0x0000, 0x00, 0x00, \
@@ -296,8 +318,8 @@
u32 revision;
void *parent_handle;
struct efi_system_table *system_table;
- void *device_handle;
- void *file_path;
+ efi_handle_t device_handle;
+ struct efi_device_path *file_path;
void *reserved;
u32 load_options_size;
void *load_options;
@@ -309,6 +331,8 @@
/* Below are efi loader private fields */
#ifdef CONFIG_EFI_LOADER
+ void *reloc_base;
+ aligned_u64 reloc_size;
efi_status_t exit_status;
struct jmp_buf_data exit_jmp;
#endif
@@ -571,24 +595,6 @@
struct efi_event *wait_for_key;
};
-#define CONSOLE_CONTROL_GUID \
- EFI_GUID(0xf42f7782, 0x12e, 0x4c12, \
- 0x99, 0x56, 0x49, 0xf9, 0x43, 0x4, 0xf7, 0x21)
-#define EFI_CONSOLE_MODE_TEXT 0
-#define EFI_CONSOLE_MODE_GFX 1
-
-struct efi_console_control_protocol
-{
- efi_status_t (EFIAPI *get_mode)(
- struct efi_console_control_protocol *this, int *mode,
- char *uga_exists, char *std_in_locked);
- efi_status_t (EFIAPI *set_mode)(
- struct efi_console_control_protocol *this, int mode);
- efi_status_t (EFIAPI *lock_std_in)(
- struct efi_console_control_protocol *this,
- uint16_t *password);
-};
-
#define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \
EFI_GUID(0x8b843e20, 0x8132, 0x4852, \
0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c)
@@ -605,6 +611,35 @@
bool allow_shortcuts);
};
+#define EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID \
+ EFI_GUID(0x0379be4e, 0xd706, 0x437d, \
+ 0xb0, 0x37, 0xed, 0xb8, 0x2f, 0xb7, 0x72, 0xa4)
+
+struct efi_device_path_utilities_protocol {
+ efi_uintn_t (EFIAPI *get_device_path_size)(
+ const struct efi_device_path *device_path);
+ struct efi_device_path *(EFIAPI *duplicate_device_path)(
+ const struct efi_device_path *device_path);
+ struct efi_device_path *(EFIAPI *append_device_path)(
+ const struct efi_device_path *src1,
+ const struct efi_device_path *src2);
+ struct efi_device_path *(EFIAPI *append_device_node)(
+ const struct efi_device_path *device_path,
+ const struct efi_device_path *device_node);
+ struct efi_device_path *(EFIAPI *append_device_path_instance)(
+ const struct efi_device_path *device_path,
+ const struct efi_device_path *device_path_instance);
+ struct efi_device_path *(EFIAPI *get_next_device_path_instance)(
+ struct efi_device_path **device_path_instance,
+ efi_uintn_t *device_path_instance_size);
+ bool (EFIAPI *is_device_path_multi_instance)(
+ const struct efi_device_path *device_path);
+ struct efi_device_path *(EFIAPI *create_device_node)(
+ uint8_t node_type,
+ uint8_t node_sub_type,
+ uint16_t node_length);
+};
+
#define EFI_GOP_GUID \
EFI_GUID(0x9042a9de, 0x23dc, 0x4a38, \
0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a)
@@ -633,6 +668,13 @@
unsigned long fb_size;
};
+struct efi_gop_pixel {
+ u8 blue;
+ u8 green;
+ u8 red;
+ u8 reserved;
+};
+
#define EFI_BLT_VIDEO_FILL 0
#define EFI_BLT_VIDEO_TO_BLT_BUFFER 1
#define EFI_BLT_BUFFER_TO_VIDEO 2
@@ -644,7 +686,8 @@
efi_uintn_t *size_of_info,
struct efi_gop_mode_info **info);
efi_status_t (EFIAPI *set_mode)(struct efi_gop *this, u32 mode_number);
- efi_status_t (EFIAPI *blt)(struct efi_gop *this, void *buffer,
+ efi_status_t (EFIAPI *blt)(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
u32 operation, efi_uintn_t sx,
efi_uintn_t sy, efi_uintn_t dx,
efi_uintn_t dy, efi_uintn_t width,
@@ -662,7 +705,7 @@
struct efi_ip_address {
u8 ip_addr[16];
-};
+} __attribute__((aligned(4)));
enum efi_simple_network_state {
EFI_NETWORK_STOPPED,
@@ -756,7 +799,28 @@
struct efi_pxe_mode
{
- u8 unused[52];
+ u8 started;
+ u8 ipv6_available;
+ u8 ipv6_supported;
+ u8 using_ipv6;
+ u8 bis_supported;
+ u8 bis_detected;
+ u8 auto_arp;
+ u8 send_guid;
+ u8 dhcp_discover_valid;
+ u8 dhcp_ack_received;
+ u8 proxy_offer_received;
+ u8 pxe_discover_valid;
+ u8 pxe_reply_received;
+ u8 pxe_bis_reply_received;
+ u8 icmp_error_received;
+ u8 tftp_error_received;
+ u8 make_callbacks;
+ u8 ttl;
+ u8 tos;
+ u8 pad;
+ struct efi_ip_address station_ip;
+ struct efi_ip_address subnet_mask;
struct efi_pxe_packet dhcp_discover;
struct efi_pxe_packet dhcp_ack;
struct efi_pxe_packet proxy_offer;
@@ -794,17 +858,19 @@
efi_status_t (EFIAPI *close)(struct efi_file_handle *file);
efi_status_t (EFIAPI *delete)(struct efi_file_handle *file);
efi_status_t (EFIAPI *read)(struct efi_file_handle *file,
- u64 *buffer_size, void *buffer);
+ efi_uintn_t *buffer_size, void *buffer);
efi_status_t (EFIAPI *write)(struct efi_file_handle *file,
- u64 *buffer_size, void *buffer);
+ efi_uintn_t *buffer_size, void *buffer);
efi_status_t (EFIAPI *getpos)(struct efi_file_handle *file,
- u64 *pos);
+ efi_uintn_t *pos);
efi_status_t (EFIAPI *setpos)(struct efi_file_handle *file,
- u64 pos);
+ efi_uintn_t pos);
efi_status_t (EFIAPI *getinfo)(struct efi_file_handle *file,
- efi_guid_t *info_type, u64 *buffer_size, void *buffer);
+ const efi_guid_t *info_type, efi_uintn_t *buffer_size,
+ void *buffer);
efi_status_t (EFIAPI *setinfo)(struct efi_file_handle *file,
- efi_guid_t *info_type, u64 buffer_size, void *buffer);
+ const efi_guid_t *info_type, efi_uintn_t buffer_size,
+ void *buffer);
efi_status_t (EFIAPI *flush)(struct efi_file_handle *file);
};
@@ -823,6 +889,10 @@
EFI_GUID(0x9576e92, 0x6d3f, 0x11d2, \
0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+#define EFI_FILE_SYSTEM_INFO_GUID \
+ EFI_GUID(0x09576e93, 0x6d3f, 0x11d2, \
+ 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
#define EFI_FILE_MODE_READ 0x0000000000000001
#define EFI_FILE_MODE_WRITE 0x0000000000000002
#define EFI_FILE_MODE_CREATE 0x8000000000000000
@@ -846,6 +916,15 @@
s16 file_name[0];
};
+struct efi_file_system_info {
+ u64 size;
+ u8 read_only;
+ u64 volume_size;
+ u64 free_space;
+ u32 block_size;
+ u16 volume_label[0];
+};
+
#define EFI_DRIVER_BINDING_PROTOCOL_GUID \
EFI_GUID(0x18a031ab, 0xb443, 0x4d1a,\
0xa5, 0xc0, 0x0c, 0x09, 0x26, 0x1e, 0x9f, 0x71)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 07730c3..17f9d3d 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -83,6 +83,9 @@
extern struct efi_simple_input_interface efi_con_in;
extern struct efi_console_control_protocol efi_console_control;
extern const struct efi_device_path_to_text_protocol efi_device_path_to_text;
+/* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */
+extern const struct efi_device_path_utilities_protocol
+ efi_device_path_utilities;
uint16_t *efi_dp_str(struct efi_device_path *dp);
@@ -93,10 +96,25 @@
extern const efi_guid_t efi_guid_device_path;
/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
extern const efi_guid_t efi_guid_driver_binding_protocol;
+/* event group ExitBootServices() invoked */
+extern const efi_guid_t efi_guid_event_group_exit_boot_services;
+/* event group SetVirtualAddressMap() invoked */
+extern const efi_guid_t efi_guid_event_group_virtual_address_change;
+/* event group memory map changed */
+extern const efi_guid_t efi_guid_event_group_memory_map_change;
+/* event group boot manager about to boot */
+extern const efi_guid_t efi_guid_event_group_ready_to_boot;
+/* event group ResetSystem() invoked (before ExitBootServices) */
+extern const efi_guid_t efi_guid_event_group_reset_system;
+/* GUID of the device tree table */
+extern const efi_guid_t efi_guid_fdt;
extern const efi_guid_t efi_guid_loaded_image;
extern const efi_guid_t efi_guid_device_path_to_text_protocol;
extern const efi_guid_t efi_simple_file_system_protocol_guid;
extern const efi_guid_t efi_file_info_guid;
+/* GUID for file system information */
+extern const efi_guid_t efi_file_system_info_guid;
+extern const efi_guid_t efi_guid_device_path_utilities_protocol;
extern unsigned int __efi_runtime_start, __efi_runtime_stop;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
@@ -144,21 +162,25 @@
/**
* struct efi_event
*
+ * @link: Link to list of all events
* @type: Type of event, see efi_create_event
* @notify_tpl: Task priority level of notifications
- * @trigger_time: Period of the timer
- * @trigger_next: Next time to trigger the timer
* @nofify_function: Function to call when the event is triggered
* @notify_context: Data to be passed to the notify function
+ * @group: Event group
+ * @trigger_time: Period of the timer
+ * @trigger_next: Next time to trigger the timer
* @trigger_type: Type of timer, see efi_set_timer
- * @queued: The notification function is queued
- * @signaled: The event occurred. The event is in the signaled state.
+ * @is_queued: The notification function is queued
+ * @is_signaled: The event occurred. The event is in the signaled state.
*/
struct efi_event {
+ struct list_head link;
uint32_t type;
efi_uintn_t notify_tpl;
void (EFIAPI *notify_function)(struct efi_event *event, void *context);
void *notify_context;
+ const efi_guid_t *group;
u64 trigger_next;
u64 trigger_time;
enum efi_timer_delay trigger_type;
@@ -166,9 +188,10 @@
bool is_signaled;
};
-
/* This list contains all UEFI objects we know of */
extern struct list_head efi_obj_list;
+/* List of all events */
+extern struct list_head efi_events;
/* Called by bootefi to make console interface available */
int efi_console_register(void);
@@ -179,13 +202,13 @@
const char *if_typename, int diskid,
const char *pdevname);
/* Called by bootefi to make GOP (graphical) interface available */
-int efi_gop_register(void);
+efi_status_t efi_gop_register(void);
/* Called by bootefi to make the network interface available */
-int efi_net_register(void);
+efi_status_t efi_net_register(void);
/* Called by bootefi to make the watchdog available */
-int efi_watchdog_register(void);
+efi_status_t efi_watchdog_register(void);
/* Called by bootefi to make SMBIOS tables available */
-void efi_smbios_register(void);
+efi_status_t efi_smbios_register(void);
struct efi_simple_file_system_protocol *
efi_fs_from_path(struct efi_device_path *fp);
@@ -235,7 +258,8 @@
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
- void *notify_context, struct efi_event **event);
+ void *notify_context, efi_guid_t *group,
+ struct efi_event **event);
/* Call this to set a timer */
efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
uint64_t trigger_time);
@@ -284,6 +308,10 @@
struct efi_device_path *file_path);
efi_status_t efi_load_image_from_path(struct efi_device_path *file_path,
void **buffer);
+/* Print information about a loaded image */
+efi_status_t efi_print_image_info(struct efi_loaded_image *image, void *pc);
+/* Print information about all loaded images */
+void efi_print_image_infos(void *pc);
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
extern void *efi_bounce_buffer;
@@ -330,6 +358,7 @@
{
while (*ascii)
*(unicode++) = *(ascii++);
+ *unicode = 0;
}
static inline int guidcmp(const efi_guid_t *g1, const efi_guid_t *g2)
@@ -346,7 +375,7 @@
/* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region
* to make it available at runtime */
-void efi_add_runtime_mmio(void *mmio_ptr, u64 len);
+efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len);
/* Boards may provide the functions below to implement RTS functionality */
@@ -354,12 +383,14 @@
enum efi_reset_type reset_type,
efi_status_t reset_status,
unsigned long data_size, void *reset_data);
-void efi_reset_system_init(void);
+
+/* Architecture specific initialization of the EFI subsystem */
+efi_status_t efi_reset_system_init(void);
efi_status_t __efi_runtime EFIAPI efi_get_time(
struct efi_time *time,
struct efi_time_cap *capabilities);
-void efi_get_time_init(void);
+efi_status_t efi_get_time_init(void);
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
/*
@@ -388,13 +419,17 @@
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
#define __efi_runtime_data
#define __efi_runtime
-static inline void efi_add_runtime_mmio(void *mmio_ptr, u64 len) { }
+static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len)
+{
+ return EFI_SUCCESS;
+}
/* No loader configured, stub out EFI_ENTRY */
static inline void efi_restore_gd(void) { }
static inline void efi_set_bootdev(const char *dev, const char *devnr,
const char *path) { }
static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
+static inline void efi_print_image_infos(void *pc) { }
#endif /* CONFIG_EFI_LOADER && !CONFIG_SPL_BUILD */
diff --git a/include/env_default.h b/include/env_default.h
index b574345..7d5988a 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -11,7 +11,7 @@
#include <env_callback.h>
#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
-env_t environment __UBOOT_ENV_SECTION__ = {
+env_t environment __UBOOT_ENV_SECTION__(environment) = {
ENV_CRC, /* CRC Sum */
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
1, /* Flags: valid */
@@ -22,6 +22,7 @@
#else
const uchar default_environment[] = {
#endif
+#ifndef CONFIG_USE_DEFAULT_ENV_FILE
#ifdef CONFIG_ENV_CALLBACK_LIST_DEFAULT
ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0"
#endif
@@ -74,7 +75,7 @@
"netmask=" __stringify(CONFIG_NETMASK) "\0"
#endif
#ifdef CONFIG_HOSTNAME
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
+ "hostname=" CONFIG_HOSTNAME "\0"
#endif
#ifdef CONFIG_BOOTFILE
"bootfile=" CONFIG_BOOTFILE "\0"
@@ -108,6 +109,9 @@
CONFIG_EXTRA_ENV_SETTINGS
#endif
"\0"
+#else /* CONFIG_USE_DEFAULT_ENV_FILE */
+#include "generated/defaultenv_autogenerated.h"
+#endif
#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
}
#endif
diff --git a/include/environment.h b/include/environment.h
index 7986a24..1b52353 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -314,6 +314,10 @@
*/
int env_save(void);
+void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr);
+int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr);
+int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr);
+
#endif /* DO_DEPS_ONLY */
#endif /* _ENVIRONMENT_H_ */
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index 0a23420..24b7783 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -40,15 +40,13 @@
"setenv eval_bootargs setenv bootargs $bootargs; " \
"run eval_bootargs; " \
"setenv mmcdev 1; " \
- "setenv fdt_part 3; " \
- "setenv boot_part 9; " \
"setenv machid fe6; " \
"mmc dev $mmcdev; " \
"mmc rescan; " \
- "part start mmc ${mmcdev} ${fdt_part} fdt_start; " \
- "part size mmc ${mmcdev} ${fdt_part} fdt_size; " \
- "part start mmc ${mmcdev} ${boot_part} boot_start; " \
- "part size mmc ${mmcdev} ${boot_part} boot_size; " \
+ "part start mmc ${mmcdev} environment fdt_start; " \
+ "part size mmc ${mmcdev} environment fdt_size; " \
+ "part start mmc ${mmcdev} boot boot_start; " \
+ "part size mmc ${mmcdev} boot boot_size; " \
"mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
"mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
"bootm $loadaddr $loadaddr $fdtaddr;\0"
diff --git a/include/image.h b/include/image.h
index dbdaecb..a579c5f 100644
--- a/include/image.h
+++ b/include/image.h
@@ -21,6 +21,7 @@
/* Define this to avoid #ifdefs later on */
struct lmb;
+struct fdt_region;
#ifdef USE_HOSTCC
#include <sys/types.h>
@@ -153,6 +154,7 @@
IH_OS_PLAN9, /* Plan 9 */
IH_OS_OPENRTOS, /* OpenRTOS */
IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */
+ IH_OS_TEE, /* Trusted Execution Environment */
IH_OS_COUNT,
};
@@ -272,6 +274,7 @@
IH_TYPE_TEE, /* Trusted Execution Environment OS Image */
IH_TYPE_FIRMWARE_IVT, /* Firmware Image with HABv4 IVT */
IH_TYPE_PMMC, /* TI Power Management Micro-Controller Firmware */
+ IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
IH_TYPE_COUNT, /* Number of image types */
};
@@ -917,6 +920,7 @@
#define FIT_DEFAULT_PROP "default"
#define FIT_SETUP_PROP "setup"
#define FIT_FPGA_PROP "fpga"
+#define FIT_FIRMWARE_PROP "firmware"
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
@@ -1013,6 +1017,8 @@
const char *comment, int require_keys,
const char *engine_id);
+int fit_image_verify_with_data(const void *fit, int image_noffset,
+ const void *data, size_t size);
int fit_image_verify(const void *fit, int noffset);
int fit_config_verify(const void *fit, int conf_noffset);
int fit_all_image_verify(const void *fit);
diff --git a/include/init.h b/include/init.h
new file mode 100644
index 0000000..147ae6b
--- /dev/null
+++ b/include/init.h
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copy the startup prototype, previously defined in common.h
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __INIT_H_
+#define __INIT_H_ 1
+
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+
+/*
+ * Function Prototypes
+ */
+
+/* common/board_f.c */
+void board_init_f(ulong dummy);
+
+/**
+ * arch_cpu_init() - basic cpu-dependent setup for an architecture
+ *
+ * This is called after early malloc is available. It should handle any
+ * CPU- or SoC- specific init needed to continue the init sequence. See
+ * board_f.c for where it is called. If this is not provided, a default
+ * version (which does nothing) will be used.
+ *
+ * @return: 0 on success, otherwise error
+ */
+int arch_cpu_init(void);
+
+/**
+ * arch_cpu_init_dm() - init CPU after driver model is available
+ *
+ * This is called immediately after driver model is available before
+ * relocation. This is similar to arch_cpu_init() but is able to reference
+ * devices
+ *
+ * @return 0 if OK, -ve on error
+ */
+int arch_cpu_init_dm(void);
+
+/**
+ * mach_cpu_init() - SoC/machine dependent CPU setup
+ *
+ * This is called after arch_cpu_init(). It should handle any
+ * SoC or machine specific init needed to continue the init sequence. See
+ * board_f.c for where it is called. If this is not provided, a default
+ * version (which does nothing) will be used.
+ *
+ * @return: 0 on success, otherwise error
+ */
+int mach_cpu_init(void);
+
+/**
+ * arch_fsp_init() - perform firmware support package init
+ *
+ * Where U-Boot relies on binary blobs to handle part of the system init, this
+ * function can be used to set up the blobs. This is used on some Intel
+ * platforms.
+ */
+int arch_fsp_init(void);
+
+int dram_init(void);
+
+/**
+ * dram_init_banksize() - Set up DRAM bank sizes
+ *
+ * This can be implemented by boards to set up the DRAM bank information in
+ * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
+ * is called.
+ *
+ * If this is not provided, a default implementation will try to set up a
+ * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
+ * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * get_effective_memsize().
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dram_init_banksize(void);
+
+/**
+ * Reserve all necessary stacks
+ *
+ * This is used in generic board init sequence in common/board_f.c. Each
+ * architecture could provide this function to tailor the required stacks.
+ *
+ * On entry gd->start_addr_sp is pointing to the suggested top of the stack.
+ * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures
+ * require only this can leave it untouched.
+ *
+ * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective
+ * positions of the stack. The stack pointer(s) will be set to this later.
+ * gd->irq_sp is only required, if the architecture needs it.
+ *
+ * @return 0 if no error
+ */
+int arch_reserve_stacks(void);
+
+/**
+ * init_cache_f_r() - Turn on the cache in preparation for relocation
+ *
+ * @return 0 if OK, -ve on error
+ */
+int init_cache_f_r(void);
+
+int print_cpuinfo(void);
+int timer_init(void);
+int reserve_mmu(void);
+int misc_init_f(void);
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void);
+#endif
+
+/* common/init/board_init.c */
+extern ulong monitor_flash_len;
+
+/**
+ * ulong board_init_f_alloc_reserve - allocate reserved area
+ *
+ * This function is called by each architecture very early in the start-up
+ * code to allow the C runtime to reserve space on the stack for writable
+ * 'globals' such as GD and the malloc arena.
+ *
+ * @top: top of the reserve area, growing down.
+ * @return: bottom of reserved area
+ */
+ulong board_init_f_alloc_reserve(ulong top);
+
+/**
+ * board_init_f_init_reserve - initialize the reserved area(s)
+ *
+ * This function is called once the C runtime has allocated the reserved
+ * area on the stack. It must initialize the GD at the base of that area.
+ *
+ * @base: top from which reservation was done
+ */
+void board_init_f_init_reserve(ulong base);
+
+/**
+ * arch_setup_gd() - Set up the global_data pointer
+ *
+ * This pointer is special in some architectures and cannot easily be assigned
+ * to. For example on x86 it is implemented by adding a specific record to its
+ * Global Descriptor Table! So we we provide a function to carry out this task.
+ * For most architectures this can simply be:
+ *
+ * gd = gd_ptr;
+ *
+ * @gd_ptr: Pointer to global data
+ */
+void arch_setup_gd(gd_t *gd_ptr);
+
+/* common/board_r.c */
+void board_init_r(gd_t *id, ulong dest_addr) __attribute__ ((noreturn));
+
+int cpu_init_r(void);
+int last_stage_init(void);
+int mac_read_from_eeprom(void);
+int set_cpu_clk_info(void);
+int update_flash_size(int flash_size);
+int arch_early_init_r(void);
+void pci_init(void);
+int misc_init_r(void);
+#if defined(CONFIG_VID)
+int init_func_vid(void);
+#endif
+
+/* common/board_info.c */
+int checkboard(void);
+int show_board_info(void);
+
+#endif /* __ASSEMBLY__ */
+/* Put only stuff here that the assembler can digest */
+
+#endif /* __INIT_H_ */
diff --git a/include/init_helpers.h b/include/init_helpers.h
deleted file mode 100644
index 3efcfdd..0000000
--- a/include/init_helpers.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _INIT_HELPERS_H_
-#define _INIT_HELPERS_H_
-
-/**
- * init_cache_f_r() - Turn on the cache in preparation for relocation
- *
- * @return 0 if OK, -ve on error
- */
-int init_cache_f_r(void);
-
-#endif /* _INIT_HELPERS_H_ */
diff --git a/include/keyboard.h b/include/keyboard.h
index 9b51e20..7561954 100644
--- a/include/keyboard.h
+++ b/include/keyboard.h
@@ -1,7 +1,6 @@
#ifndef __KEYBOARD_H
#define __KEYBOARD_H
-#ifdef CONFIG_DM_KEYBOARD
#include <input.h>
#include <stdio_dev.h>
@@ -77,30 +76,4 @@
#define keyboard_get_ops(dev) ((struct keyboard_ops *)(dev)->driver->ops)
-#else
-
-#ifdef CONFIG_PS2MULT
-#include <ps2mult.h>
-#endif
-
-#if !defined(kbd_request_region) || \
- !defined(kbd_request_irq) || \
- !defined(kbd_read_input) || \
- !defined(kbd_read_status) || \
- !defined(kbd_write_output) || \
- !defined(kbd_write_command)
-#error PS/2 low level routines not defined
-#endif
-
-extern int kbd_init (void);
-extern void handle_scancode(unsigned char scancode);
-extern int kbd_init_hw(void);
-extern void pckbd_leds(unsigned char leds);
-#endif /* !CONFIG_DM_KEYBOARD */
-
-#if defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
-int ps2ser_check(void);
-#endif
-
#endif /* __KEYBOARD_H */
diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h
index 9e6eead..eeb2344 100644
--- a/include/linux/libfdt.h
+++ b/include/linux/libfdt.h
@@ -309,7 +309,4 @@
extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
-/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
-#define FDT_RAMDISK_OVERHEAD 0x80
-
#endif /* _INCLUDE_LIBFDT_H_ */
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index fc081ab..daa874c 100644
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -81,7 +81,7 @@
#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */
#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */
#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */
-#if 0 /* already in asm/8xx_immap.h */
+#if 0 /* already in asm/immap_8xx.h */
#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */
#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */
#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */
@@ -95,7 +95,7 @@
*/
#undef PISCR_PIRQ /* TBD */
#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
-#if 0 /* already in asm/8xx_immap.h */
+#if 0 /* already in asm/immap_8xx.h */
#define PISCR_PS 0x0080 /* Periodic interrupt Status */
#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
diff --git a/include/net.h b/include/net.h
index 455b48f..3469811 100644
--- a/include/net.h
+++ b/include/net.h
@@ -238,9 +238,6 @@
void eth_set_current(void); /* set nterface to ethcur var */
int eth_get_dev_index(void); /* get the device index */
-void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
-int eth_env_get_enetaddr(const char *name, uchar *enetaddr);
-int eth_env_set_enetaddr(const char *name, const uchar *enetaddr);
/**
* eth_env_set_enetaddr_by_index() - set the MAC address environment variable
@@ -676,7 +673,7 @@
/* Processes a received packet */
void net_process_received_packet(uchar *in_packet, int len);
-#ifdef CONFIG_NETCONSOLE
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
void nc_start(void);
int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
unsigned src_port, unsigned len);
@@ -684,7 +681,7 @@
static __always_inline int eth_is_on_demand_init(void)
{
-#ifdef CONFIG_NETCONSOLE
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
extern enum proto_t net_loop_last_protocol;
return net_loop_last_protocol != NETCONS;
@@ -695,7 +692,7 @@
static inline void eth_set_last_protocol(int protocol)
{
-#ifdef CONFIG_NETCONSOLE
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
extern enum proto_t net_loop_last_protocol;
net_loop_last_protocol = protocol;
diff --git a/include/net/pfe_eth/pfe/cbus.h b/include/net/pfe_eth/pfe/cbus.h
new file mode 100644
index 0000000..002041c
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
+#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
+#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
+#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
+#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
+#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
+#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
+#define LMEM_SIZE 0x10000
+#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
+#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
+#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
+
+/*
+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
+ * XXX_MEM_ACCESS_ADDR register bit definitions.
+ */
+/* Internal Memory Write. */
+#define PE_MEM_ACCESS_WRITE BIT(31)
+/* Internal Memory Read. */
+#define PE_MEM_ACCESS_READ (0 << 31)
+
+#define PE_MEM_ACCESS_IMEM BIT(15)
+#define PE_MEM_ACCESS_DMEM BIT(16)
+
+/* Byte Enables of the Internal memory access. These are interpred in BE */
+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) (((((1 << (size)) - 1) << (4 \
+ - (offset) - (size)))\
+ & 0xf) << 24)
+
+/* PFE cores states */
+#define CORE_DISABLE 0x00000000
+#define CORE_ENABLE 0x00000001
+#define CORE_SW_RESET 0x00000002
+
+/* LMEM defines */
+#define LMEM_HDR_SIZE 0x0010
+#define LMEM_BUF_SIZE_LN2 0x7
+#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
+
+/* DDR defines */
+#define DDR_HDR_SIZE 0x0100
+#define DDR_BUF_SIZE_LN2 0xb
+#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)
+
+/* Clock generation through PLL */
+#define PLL_CLK_EN 1
+
+#endif /* _CBUS_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/bmu.h b/include/net/pfe_eth/pfe/cbus/bmu.h
new file mode 100644
index 0000000..f707cc3
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/bmu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BMU_H_
+#define _BMU_H_
+
+#define BMU_VERSION 0x000
+#define BMU_CTRL 0x004
+#define BMU_UCAST_CONFIG 0x008
+#define BMU_UCAST_BASE_ADDR 0x00c
+#define BMU_BUF_SIZE 0x010
+#define BMU_BUF_CNT 0x014
+#define BMU_THRES 0x018
+#define BMU_INT_SRC 0x020
+#define BMU_INT_ENABLE 0x024
+#define BMU_ALLOC_CTRL 0x030
+#define BMU_FREE_CTRL 0x034
+#define BMU_FREE_ERR_ADDR 0x038
+#define BMU_CURR_BUF_CNT 0x03c
+#define BMU_MCAST_CNT 0x040
+#define BMU_MCAST_ALLOC_CTRL 0x044
+#define BMU_REM_BUF_CNT 0x048
+#define BMU_LOW_WATERMARK 0x050
+#define BMU_HIGH_WATERMARK 0x054
+#define BMU_INT_MEM_ACCESS 0x100
+
+struct bmu_cfg {
+ u32 baseaddr;
+ u32 count;
+ u32 size;
+};
+
+#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
+#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
+
+#endif /* _BMU_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/class_csr.h b/include/net/pfe_eth/pfe/cbus/class_csr.h
new file mode 100644
index 0000000..eeca751
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/class_csr.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CLASS_CSR_H_
+#define _CLASS_CSR_H_
+
+/*
+ * @file class_csr.h.
+ * class_csr - block containing all the classifier control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
+#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
+#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
+#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
+/* LMEM header size for the Classifier block.
+ * Data in the LMEM is written from this offset.
+ */
+#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
+/* DDR header size for the Classifier block.
+ * Data in the DDR is written from this offset.
+ */
+#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
+
+/*
+ * @name Class PE memory access. Allows external PE's and HOST to
+ * read/write PMEM/DMEM memory ranges for each classifier PE.
+ */
+#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
+/* Internal Memory Access Write Data [31:0] */
+#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
+/* Internal Memory Access Read Data [31:0] */
+#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
+#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
+#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
+
+#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
+#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
+#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
+#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
+#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
+#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
+#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
+#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
+#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
+#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
+
+#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
+/* bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR */
+#define CLASS_BUS_ACCESS_ADDR_MASK (0x0001FFFF)
+
+#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
+#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
+
+/*
+ * (route_entry_size[9:0], route_hash_size[23:16]
+ * (this is actually ln2(size)))
+ */
+#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
+#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
+
+#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
+#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
+#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
+#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
+#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
+#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
+#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
+#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
+
+#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
+#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000)
+
+#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
+
+#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
+#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
+#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
+#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
+#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
+#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
+#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
+#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
+#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
+#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
+#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
+#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
+
+#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
+#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
+
+#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
+#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
+
+#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
+
+#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
+#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
+#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
+#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
+#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
+#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
+
+#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
+#define CLASS_AXI_CTRL (CLASS_CSR_BASE_ADDR + 0x2d0)
+
+/* CLASS defines */
+#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
+#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
+
+#define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */
+/* Can be configured */
+#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
+
+#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+
+#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) |\
+ CLASS_PBUF0_BASE_ADDR)
+#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) |\
+ CLASS_PBUF2_BASE_ADDR)
+
+#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16)\
+ | CLASS_PBUF0_HEADER_BASE_ADDR)
+#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16)\
+ | CLASS_PBUF2_HEADER_BASE_ADDR)
+
+#define CLASS_ROUTE_SIZE 128
+#define CLASS_ROUTE_HASH_BITS 20
+#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1)
+
+#define TWO_LEVEL_ROUTE BIT(0)
+#define PHYNO_IN_HASH BIT(1)
+#define HW_ROUTE_FETCH BIT(3)
+#define HW_BRIDGE_FETCH BIT(5)
+#define IP_ALIGNED BIT(6)
+#define ARC_HIT_CHECK_EN BIT(7)
+#define CLASS_TOE BIT(11)
+#define HASH_CRC_PORT BIT(12)
+#define HASH_CRC_IP BIT(13)
+#define HASH_CRC_PORT_IP GENMASK(13, 12)
+#define QB2BUS_LE BIT(15)
+
+#define TCP_CHKSUM_DROP BIT(0)
+#define UDP_CHKSUM_DROP BIT(1)
+#define IPV4_CHKSUM_DROP BIT(9)
+
+struct class_cfg {
+ u32 route_table_baseaddr;
+ u32 route_table_hash_bits;
+};
+
+#endif /* _CLASS_CSR_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/emac.h b/include/net/pfe_eth/pfe/cbus/emac.h
new file mode 100644
index 0000000..f74bd96
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/emac.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EMAC_H_
+#define _EMAC_H_
+
+#define EMAC_IEVENT_REG 0x004
+#define EMAC_IMASK_REG 0x008
+#define EMAC_R_DES_ACTIVE_REG 0x010
+#define EMAC_X_DES_ACTIVE_REG 0x014
+#define EMAC_ECNTRL_REG 0x024
+#define EMAC_MII_DATA_REG 0x040
+#define EMAC_MII_CTRL_REG 0x044
+#define EMAC_MIB_CTRL_STS_REG 0x064
+#define EMAC_RCNTRL_REG 0x084
+#define EMAC_TCNTRL_REG 0x0C4
+#define EMAC_PHY_ADDR_LOW 0x0E4
+#define EMAC_PHY_ADDR_HIGH 0x0E8
+#define EMAC_TFWR_STR_FWD 0x144
+#define EMAC_RX_SECTIOM_FULL 0x190
+#define EMAC_TX_SECTION_EMPTY 0x1A0
+#define EMAC_TRUNC_FL 0x1B0
+
+/* GEMAC definitions and settings */
+#define EMAC_PORT_0 0
+#define EMAC_PORT_1 1
+
+/* GEMAC Bit definitions */
+#define EMAC_IEVENT_HBERR BIT(31)
+#define EMAC_IEVENT_BABR BIT(30)
+#define EMAC_IEVENT_BABT BIT(29)
+#define EMAC_IEVENT_GRA BIT(28)
+#define EMAC_IEVENT_TXF BIT(27)
+#define EMAC_IEVENT_TXB BIT(26)
+#define EMAC_IEVENT_RXF BIT(25)
+#define EMAC_IEVENT_RXB BIT(24)
+#define EMAC_IEVENT_MII BIT(23)
+#define EMAC_IEVENT_EBERR BIT(22)
+#define EMAC_IEVENT_LC BIT(21)
+#define EMAC_IEVENT_RL BIT(20)
+#define EMAC_IEVENT_UN BIT(19)
+
+#define EMAC_IMASK_HBERR BIT(31)
+#define EMAC_IMASK_BABR BIT(30)
+#define EMAC_IMASKT_BABT BIT(29)
+#define EMAC_IMASK_GRA BIT(28)
+#define EMAC_IMASKT_TXF BIT(27)
+#define EMAC_IMASK_TXB BIT(26)
+#define EMAC_IMASKT_RXF BIT(25)
+#define EMAC_IMASK_RXB BIT(24)
+#define EMAC_IMASK_MII BIT(23)
+#define EMAC_IMASK_EBERR BIT(22)
+#define EMAC_IMASK_LC BIT(21)
+#define EMAC_IMASKT_RL BIT(20)
+#define EMAC_IMASK_UN BIT(19)
+
+#define EMAC_RCNTRL_MAX_FL_SHIFT 16
+#define EMAC_RCNTRL_LOOP BIT(0)
+#define EMAC_RCNTRL_DRT BIT(1)
+#define EMAC_RCNTRL_MII_MODE BIT(2)
+#define EMAC_RCNTRL_PROM BIT(3)
+#define EMAC_RCNTRL_BC_REJ BIT(4)
+#define EMAC_RCNTRL_FCE BIT(5)
+#define EMAC_RCNTRL_RGMII BIT(6)
+#define EMAC_RCNTRL_SGMII BIT(7)
+#define EMAC_RCNTRL_RMII BIT(8)
+#define EMAC_RCNTRL_RMII_10T BIT(9)
+#define EMAC_RCNTRL_CRC_FWD BIT(10)
+
+#define EMAC_TCNTRL_GTS BIT(0)
+#define EMAC_TCNTRL_HBC BIT(1)
+#define EMAC_TCNTRL_FDEN BIT(2)
+#define EMAC_TCNTRL_TFC_PAUSE BIT(3)
+#define EMAC_TCNTRL_RFC_PAUSE BIT(4)
+
+#define EMAC_ECNTRL_RESET BIT(0) /* reset the EMAC */
+#define EMAC_ECNTRL_ETHER_EN BIT(1) /* enable the EMAC */
+#define EMAC_ECNTRL_SPEED BIT(5)
+#define EMAC_ECNTRL_DBSWAP BIT(8)
+
+#define EMAC_X_WMRK_STRFWD BIT(8)
+
+#define EMAC_X_DES_ACTIVE_TDAR BIT(24)
+#define EMAC_R_DES_ACTIVE_RDAR BIT(24)
+
+#define EMAC_TFWR (0x4)
+#define EMAC_RX_SECTION_FULL_32 (0x5)
+#define EMAC_TRUNC_FL_16K (0x3FFF)
+#define EMAC_TX_SECTION_EMPTY_30 (0x30)
+#define EMAC_MIBC_NO_CLR_NO_DIS (0x0)
+
+/*
+ * The possible operating speeds of the MAC, currently supporting 10, 100 and
+ * 1000Mb modes.
+ */
+enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M,
+ PFE_MAC_SPEED_1000M_PCS};
+
+/* MII-related definitios */
+#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
+#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */
+#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */
+#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
+#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
+#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
+#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
+
+#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
+#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
+#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
+#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
+
+#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+ EMAC_MII_DATA_RA_SHIFT)
+#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+ EMAC_MII_DATA_PA_SHIFT)
+#define EMAC_MII_DATA(v) (v & 0xffff)
+
+#define EMAC_MII_SPEED_SHIFT 1
+#define EMAC_HOLDTIME_SHIFT 8
+#define EMAC_HOLDTIME_MASK 0x7
+#define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET 0x8000
+#define PHY_SGMII_CR_RESET_AN 0x0200
+#define PHY_SGMII_CR_DEF_VAL 0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN 0x0002
+#define PHY_SGMII_IF_MODE_SGMII 0x0001
+#define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008
+#define PHY_SGMII_ENABLE_AN 0x1000
+
+#endif /* _EMAC_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/gpi.h b/include/net/pfe_eth/pfe/cbus/gpi.h
new file mode 100644
index 0000000..f86f3f9
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/gpi.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _GPI_H_
+#define _GPI_H_
+
+#define GPI_VERSION 0x00
+#define GPI_CTRL 0x04
+#define GPI_RX_CONFIG 0x08
+#define GPI_HDR_SIZE 0x0c
+#define GPI_BUF_SIZE 0x10
+#define GPI_LMEM_ALLOC_ADDR 0x14
+#define GPI_LMEM_FREE_ADDR 0x18
+#define GPI_DDR_ALLOC_ADDR 0x1c
+#define GPI_DDR_FREE_ADDR 0x20
+#define GPI_CLASS_ADDR 0x24
+#define GPI_DRX_FIFO 0x28
+#define GPI_TRX_FIFO 0x2c
+#define GPI_INQ_PKTPTR 0x30
+#define GPI_DDR_DATA_OFFSET 0x34
+#define GPI_LMEM_DATA_OFFSET 0x38
+#define GPI_TMLF_TX 0x4c
+#define GPI_DTX_ASEQ 0x50
+#define GPI_FIFO_STATUS 0x54
+#define GPI_FIFO_DEBUG 0x58
+#define GPI_TX_PAUSE_TIME 0x5c
+#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
+#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
+#define GPI_TOE_CHKSUM_EN 0x68
+#define GPI_OVERRUN_DROPCNT 0x6c
+#define GPI_AXI_CTRL 0x70
+
+struct gpi_cfg {
+ u32 lmem_rtry_cnt;
+ u32 tmlf_txthres;
+ u32 aseq_len;
+};
+
+/* GPI commons defines */
+#define GPI_LMEM_BUF_EN 0x1
+#define GPI_DDR_BUF_EN 0x1
+
+/* EGPI 1 defines */
+#define EGPI1_LMEM_RTRY_CNT 0x40
+#define EGPI1_TMLF_TXTHRES 0xBC
+#define EGPI1_ASEQ_LEN 0x50
+
+/* EGPI 2 defines */
+#define EGPI2_LMEM_RTRY_CNT 0x40
+#define EGPI2_TMLF_TXTHRES 0xBC
+#define EGPI2_ASEQ_LEN 0x40
+
+/* HGPI defines */
+#define HGPI_LMEM_RTRY_CNT 0x40
+#define HGPI_TMLF_TXTHRES 0xBC
+#define HGPI_ASEQ_LEN 0x40
+
+#endif /* _GPI_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/hif.h b/include/net/pfe_eth/pfe/cbus/hif.h
new file mode 100644
index 0000000..4b5cb3c
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/hif.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _HIF_H_
+#define _HIF_H_
+
+/*
+ * @file hif.h.
+ * hif - PFE hif block control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
+#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
+#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
+#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
+#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
+#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
+#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
+#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
+#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
+#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
+#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
+#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
+#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
+#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
+#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
+#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
+#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
+#define HIF_AXI_CTRL (HIF_BASE_ADDR + 0x54)
+
+/* HIF_TX_CTRL bits */
+#define HIF_CTRL_DMA_EN BIT(0)
+#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1)
+#define HIF_CTRL_BDP_CH_START_WSTB BIT(2)
+
+/* HIF_RX_STATUS bits */
+#define BDP_CSR_RX_DMA_ACTV BIT(16)
+
+/* HIF_INT_ENABLE bits */
+#define HIF_INT_EN BIT(0)
+#define HIF_RXBD_INT_EN BIT(1)
+#define HIF_RXPKT_INT_EN BIT(2)
+#define HIF_TXBD_INT_EN BIT(3)
+#define HIF_TXPKT_INT_EN BIT(4)
+
+/* HIF_POLL_CTRL bits*/
+#define HIF_RX_POLL_CTRL_CYCLE 0x0400
+#define HIF_TX_POLL_CTRL_CYCLE 0x0400
+
+/* Buffer descriptor control bits */
+#define BD_CTRL_BUFLEN_MASK (0xffff)
+#define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK)
+#define BD_CTRL_CBD_INT_EN BIT(16)
+#define BD_CTRL_PKT_INT_EN BIT(17)
+#define BD_CTRL_LIFM BIT(18)
+#define BD_CTRL_LAST_BD BIT(19)
+#define BD_CTRL_DIR BIT(20)
+#define BD_CTRL_PKT_XFER BIT(24)
+#define BD_CTRL_DESC_EN BIT(31)
+#define BD_CTRL_PARSE_DISABLE BIT(25)
+#define BD_CTRL_BRFETCH_DISABLE BIT(26)
+#define BD_CTRL_RTFETCH_DISABLE BIT(27)
+
+#endif /* _HIF_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/hif_nocpy.h b/include/net/pfe_eth/pfe/cbus/hif_nocpy.h
new file mode 100644
index 0000000..c2d6f6d
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/hif_nocpy.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _HIF_NOCPY_H_
+#define _HIF_NOCPY_H_
+
+#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
+#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
+#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
+#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
+#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
+#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
+#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
+#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
+#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
+#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
+#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
+#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
+#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
+#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
+#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
+#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
+#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
+#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
+#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
+#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
+#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
+#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
+#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
+#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
+#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
+#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
+#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
+#define HIF_NOCPY_AXI_CTRL (HIF_NOCPY_BASE_ADDR + 0x94)
+
+#endif /* _HIF_NOCPY_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/tmu_csr.h b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
new file mode 100644
index 0000000..e810b79
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TMU_CSR_H_
+#define _TMU_CSR_H_
+
+#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
+#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
+#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
+#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
+#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
+#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
+#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
+#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
+#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
+#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
+#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
+#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
+#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
+#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
+#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
+#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
+#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
+#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
+#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
+#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
+#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
+#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
+#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
+#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
+#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
+#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
+#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
+#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
+#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
+#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
+#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
+#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
+#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
+#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
+#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
+#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
+#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
+#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
+#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
+#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
+#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
+#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
+#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
+#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
+#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
+#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY0
+ */
+#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8)
+#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
+#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
+#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
+#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
+#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
+#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
+#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
+#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
+#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
+#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
+
+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal
+ * memory Write [27:24] Byte Enables of the Internal memory access [23:0]
+ * Address of the internal memory. This address is used to access both the
+ * PM and DM of all the PE's
+ */
+#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4)
+
+/* Internal Memory Access Write Data */
+#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8)
+/* Internal Memory Access Read Data. The commands are blocked at the
+ * mem_access only
+ */
+#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec)
+
+/* [31:0] PHY0 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0)
+/* [31:0] PHY1 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4)
+/* [31:0] PHY3 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc)
+#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
+#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
+
+#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
+#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
+#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
+
+/* [31:0] PHY4 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134)
+
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY1
+ */
+#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY3
+ */
+#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
+
+#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
+/* [31:0] PHY5 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148)
+
+#define TMU_AXI_CTRL (TMU_CSR_BASE_ADDR + 0x17c)
+
+#define SW_RESET BIT(0) /* Global software reset */
+#define INQ_RESET BIT(2)
+#define TEQ_RESET BIT(3)
+#define TDQ_RESET BIT(4)
+#define PE_RESET BIT(5)
+#define MEM_INIT BIT(6)
+#define MEM_INIT_DONE BIT(7)
+#define LLM_INIT BIT(8)
+#define LLM_INIT_DONE BIT(9)
+#define ECC_MEM_INIT_DONE BIT(10)
+
+struct tmu_cfg {
+ u32 llm_base_addr;
+ u32 llm_queue_len;
+};
+
+/* Not HW related for pfe_ctrl/pfe common defines */
+#define DEFAULT_MAX_QDEPTH 80
+#define DEFAULT_Q0_QDEPTH 511 /* We keep 1 large queue for host tx qos */
+#define DEFAULT_TMU3_QDEPTH 127
+
+#endif /* _TMU_CSR_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/util_csr.h b/include/net/pfe_eth/pfe/cbus/util_csr.h
new file mode 100644
index 0000000..bac4114
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/util_csr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _UTIL_CSR_H_
+#define _UTIL_CSR_H_
+
+#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
+#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
+#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
+
+#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
+
+#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
+#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
+#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
+#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
+
+#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
+#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
+#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
+
+#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
+#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
+
+#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
+#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
+#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
+#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
+#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
+#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
+#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
+#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
+#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
+#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
+
+#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
+#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
+#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
+
+#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
+#define UTIL_AXI_CTRL (UTIL_CSR_BASE_ADDR + 0x240)
+
+#endif /* _UTIL_CSR_H_ */
diff --git a/include/net/pfe_eth/pfe/pfe_hw.h b/include/net/pfe_eth/pfe/pfe_hw.h
new file mode 100644
index 0000000..992454f
--- /dev/null
+++ b/include/net/pfe_eth/pfe/pfe_hw.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PFE_H_
+#define _PFE_H_
+
+#include <elf.h>
+#include "cbus.h"
+
+#define PFE_RESET_WA
+
+#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
+/* Only valid for mem access register interface */
+#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
+#define CLASS_DMEM_SIZE 0x00002000
+#define CLASS_IMEM_SIZE 0x00008000
+
+#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
+/* Only valid for mem access register interface */
+#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
+#define TMU_DMEM_SIZE 0x00000800
+#define TMU_IMEM_SIZE 0x00002000
+
+#define UTIL_DMEM_BASE_ADDR 0x00000000
+#define UTIL_DMEM_SIZE 0x00002000
+
+#define PE_LMEM_BASE_ADDR 0xc3010000
+#define PE_LMEM_SIZE 0x8000
+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
+
+#define DMEM_BASE_ADDR 0x00000000
+#define DMEM_SIZE 0x2000 /* TMU has less... */
+#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
+
+#define PMEM_BASE_ADDR 0x00010000
+#define PMEM_SIZE 0x8000 /* TMU has less... */
+#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
+
+/* Memory ranges check from PE point of view/memory map */
+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
+ (((unsigned long)(addr) +\
+ (len)) <= DMEM_END))
+#define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
+ (((unsigned long)(addr) +\
+ (len)) <= PMEM_END))
+#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
+ ) && (((unsigned long)(addr)\
+ + (len)) <= PE_LMEM_END))
+
+#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\
+ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
+ (((unsigned long)(addr) + (len)) <=\
+ CBUS_VIRT_TO_PFE(LMEM_END)))
+#define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\
+ PFE_DDR_PHYS_BASE_ADDR) &&\
+ (((unsigned long)(addr) + (len)) <=\
+ PFE_DDR_PHYS_END))
+
+/* Host View Address */
+extern void *ddr_pfe_base_addr;
+
+/* PFE View Address */
+/* DDR physical base address as seen by PE's. */
+#define PFE_DDR_PHYS_BASE_ADDR 0x03800000
+#define PFE_DDR_PHYS_SIZE 0xC000000
+#define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
+/* CBUS physical base address as seen by PE's. */
+#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000
+
+/* Host<->PFE Mapping */
+#define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p) + 0x80000000))
+#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\
+ PFE_CBUS_PHYS_BASE_ADDR)
+#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
+ CBUS_BASE_ADDR)
+
+enum {
+ CLASS0_ID = 0,
+ CLASS1_ID,
+ CLASS2_ID,
+ CLASS3_ID,
+ CLASS4_ID,
+ CLASS5_ID,
+
+ TMU0_ID,
+ TMU1_ID,
+ TMU2_ID,
+ TMU3_ID,
+ MAX_PE
+};
+
+#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
+ | BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
+ BIT(CLASS5_ID))
+#define CLASS_MAX_ID CLASS5_ID
+
+#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
+#define TMU_MAX_ID TMU3_ID
+
+/*
+ * PE information.
+ * Structure containing PE's specific information. It is used to create
+ * generic C functions common to all PEs.
+ * Before using the library functions this structure needs to be
+ * initialized with the different registers virtual addresses
+ * (according to the ARM MMU mmaping). The default initialization supports a
+ * virtual == physical mapping.
+ *
+ */
+struct pe_info {
+ u32 dmem_base_addr; /* PE's dmem base address */
+ u32 pmem_base_addr; /* PE's pmem base address */
+ u32 pmem_size; /* PE's pmem size */
+
+ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA
+ * register address
+ */
+ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR
+ * register address
+ */
+ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA
+ * register address
+ */
+};
+
+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
+void pe_lmem_write(u32 *src, u32 len, u32 offset);
+
+u32 pe_pmem_read(int id, u32 addr, u8 size);
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
+u32 pe_dmem_read(int id, u32 addr, u8 size);
+
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
+
+void pfe_lib_init(void);
+
+void bmu_init(void *base, struct bmu_cfg *cfg);
+void bmu_enable(void *base);
+
+void gpi_init(void *base, struct gpi_cfg *cfg);
+void gpi_enable(void *base);
+void gpi_disable(void *base);
+
+void class_init(struct class_cfg *cfg);
+void class_enable(void);
+void class_disable(void);
+
+void tmu_init(struct tmu_cfg *cfg);
+void tmu_enable(u32 pe_mask);
+void tmu_disable(u32 pe_mask);
+
+void hif_init(void);
+void hif_tx_enable(void);
+void hif_tx_disable(void);
+void hif_rx_enable(void);
+void hif_rx_disable(void);
+void hif_rx_desc_disable(void);
+
+#endif /* _PFE_H_ */
diff --git a/include/net/pfe_eth/pfe_driver.h b/include/net/pfe_eth/pfe_driver.h
new file mode 100644
index 0000000..da7d247
--- /dev/null
+++ b/include/net/pfe_eth/pfe_driver.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFE_DRIVER_H__
+#define __PFE_DRIVER_H__
+
+#include <net/pfe_eth/pfe/pfe_hw.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define HIF_RX_DESC_NT 64
+#define HIF_TX_DESC_NT 64
+
+#define RX_BD_BASEADDR (HIF_DESC_BASEADDR)
+#define TX_BD_BASEADDR (HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
+
+#define MIN_PKT_SIZE 56
+#define MAX_FRAME_SIZE 2048
+
+struct __packed hif_header_s {
+ u8 port_no; /* Carries input port no for host rx packets and
+ * output port no for tx pkts
+ */
+ u8 reserved0;
+ u32 reserved2;
+};
+
+struct __packed buf_desc {
+ u32 ctrl;
+ u32 status;
+ u32 data;
+ u32 next;
+};
+
+struct rx_desc_s {
+ struct buf_desc *rx_base;
+ unsigned int rx_base_pa;
+ int rx_to_read;
+ int rx_ring_size;
+};
+
+struct tx_desc_s {
+ struct buf_desc *tx_base;
+ unsigned int tx_base_pa;
+ int tx_to_send;
+ int tx_ring_size;
+};
+
+int pfe_send(int phy_port, void *data, int length);
+int pfe_recv(uchar **pkt_ptr, int *phy_port);
+int pfe_tx_done(void);
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length);
+int pfe_drv_init(struct pfe_ddr_address *pfe_addr);
+int pfe_eth_remove(struct udevice *dev);
+
+#endif
diff --git a/include/net/pfe_eth/pfe_eth.h b/include/net/pfe_eth/pfe_eth.h
new file mode 100644
index 0000000..f319365
--- /dev/null
+++ b/include/net/pfe_eth/pfe_eth.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFE_ETH_H__
+#define __PFE_ETH_H__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include "pfe_driver.h"
+
+#define BMU2_DDR_BASEADDR 0
+#define BMU2_BUF_COUNT (3 * SZ_1K)
+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
+
+#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
+
+#define HIF_DESC_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
+#define HIF_RX_DESC_SIZE (16 * HIF_RX_DESC_NT)
+#define HIF_TX_DESC_SIZE (16 * HIF_TX_DESC_NT)
+
+#define UTIL_CODE_BASEADDR 0x780000
+#define UTIL_CODE_SIZE (128 * SZ_1K)
+
+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
+
+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
+
+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
+
+#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define TMU_LLM_QUEUE_LEN (16 * 256)
+ /* Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN)
+ /* (4 TMU's x 16 queues x queue_len) */
+
+#define ROUTE_TABLE_BASEADDR 0x800000
+#define ROUTE_TABLE_HASH_BITS_MAX 15 /* 32K entries */
+#define ROUTE_TABLE_HASH_BITS 8 /* 256 entries */
+#define ROUTE_TABLE_SIZE (BIT(ROUTE_TABLE_HASH_BITS_MAX) \
+ * CLASS_ROUTE_SIZE)
+
+#define PFE_TOTAL_DATA_SIZE (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+
+#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
+#error DDR mapping above 12MiB
+#endif
+
+/* LMEM Mapping */
+#define BMU1_LMEM_BASEADDR 0
+#define BMU1_BUF_COUNT 256
+#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
+
+struct gemac_s {
+ void *gemac_base;
+ void *egpi_base;
+
+ /* GEMAC config */
+ int gemac_mode;
+ int gemac_speed;
+ int gemac_duplex;
+ int flags;
+ /* phy iface */
+ int phy_address;
+ int phy_mode;
+ struct mii_dev *bus;
+
+};
+
+struct pfe_mdio_info {
+ void *reg_base;
+ char *name;
+};
+
+struct pfe_eth_dev {
+ int gemac_port;
+ struct gemac_s *gem;
+ struct pfe_ddr_address pfe_addr;
+ struct udevice *dev;
+#ifdef CONFIG_PHYLIB
+ struct phy_device *phydev;
+#endif
+};
+
+int pfe_remove(struct pfe_ddr_address *pfe_addr);
+struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info);
+void pfe_set_mdio(int dev_id, struct mii_dev *bus);
+void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
+int gemac_initialize(bd_t *bis, int dev_id, char *devname);
+int pfe_init(struct pfe_ddr_address *pfe_addr);
+int pfe_eth_board_init(struct udevice *dev);
+
+#endif /* __PFE_ETH_H__ */
diff --git a/include/net/pfe_eth/pfe_firmware.h b/include/net/pfe_eth/pfe_firmware.h
new file mode 100644
index 0000000..588b2ae
--- /dev/null
+++ b/include/net/pfe_eth/pfe_firmware.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/** @file
+ * Contains all the defines to handle parsing and loading of PE firmware files.
+ */
+#ifndef __PFE_FIRMWARE_H__
+#define __PFE_FIRMWARE_H__
+
+int pfe_firmware_init(void);
+void pfe_firmware_exit(void);
+
+#endif
diff --git a/include/net/pfe_eth/pfe_mdio.h b/include/net/pfe_eth/pfe_mdio.h
new file mode 100644
index 0000000..ab27ec3
--- /dev/null
+++ b/include/net/pfe_eth/pfe_mdio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PFE_MDIO_H_
+#define _PFE_MDIO_H_
+
+int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id);
+
+#endif /* _PFE_MDIO_H_ */
diff --git a/include/netdev.h b/include/netdev.h
index 3958a4c..68c6d49 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -39,8 +39,6 @@
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
-int enc28j60_initialize(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
int eth_3com_initialize (bd_t * bis);
int ethoc_initialize(u8 dev_num, int base_addr);
@@ -119,11 +117,7 @@
return num;
}
-#ifdef CONFIG_DM_ETH
-struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id);
-#else
-struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
-#endif
+struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id);
#ifdef CONFIG_PHYLIB
struct phy_device;
diff --git a/include/pc_keyb.h b/include/pc_keyb.h
deleted file mode 100644
index 5ba99e3..0000000
--- a/include/pc_keyb.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * include/linux/pc_keyb.h
- *
- * PC Keyboard And Keyboard Controller
- *
- * (c) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
- */
-
-/*
- * Configuration Switches
- */
-#undef KBD_REPORT_ERR /* Report keyboard errors */
-#define KBD_REPORT_UNKN /* Report unknown scan codes */
-#define KBD_REPORT_TIMEOUTS /* Report keyboard timeouts */
-#undef KBD_IS_FOCUS_9000 /* We have the brain-damaged FOCUS-9000 keyboard */
-#undef INITIALIZE_MOUSE /* Define if your PS/2 mouse needs initialization. */
-
-#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
-#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
-#define KBD_TIMEOUT 1000 /* Timeout in ms for keyboard command acknowledge */
-
-/*
- * Internal variables of the driver
- */
-extern unsigned char pckbd_read_mask;
-extern unsigned char aux_device_present;
-
-/*
- * Keyboard Controller Registers on normal PCs.
- */
-#define KBD_STATUS_REG 0x64 /* Status register (R) */
-#define KBD_CNTL_REG 0x64 /* Controller command register (W) */
-#define KBD_DATA_REG 0x60 /* Keyboard data register (R/W) */
-
-/*
- * Keyboard Controller Commands
- */
-#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
-#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
-#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
-#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
-#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
-#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
-#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
- initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
-
-/*
- * Keyboard Commands
- */
-#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
-#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
-#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
-#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
-#define KBD_CMD_RESET 0xFF /* Reset */
-
-/*
- * Keyboard Replies
- */
-#define KBD_REPLY_POR 0xAA /* Power on reset */
-#define KBD_REPLY_ACK 0xFA /* Command ACK */
-#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
-
-/*
- * Status Register Bits
- */
-#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
-#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
-#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
-#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
-#define KBD_STAT_PERR 0x80 /* Parity error */
-
-#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
-
-/*
- * Controller Mode Register Bits
- */
-#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 0x04 /* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
-#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
-#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
-#define KBD_MODE_RFU 0x80
-
-/*
- * Mouse Commands
- */
-#define AUX_SET_RES 0xE8 /* Set resolution */
-#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
-#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
-#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
-#define AUX_SET_STREAM 0xEA /* Set stream mode */
-#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
-#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
-#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
-#define AUX_RESET 0xFF /* Reset aux device */
-#define AUX_ACK 0xFA /* Command byte ACK. */
-
-#define AUX_BUF_SIZE 2048 /* This might be better divisible by
- three to make overruns stay in sync
- but then the read function would need
- a lock etc - ick */
-
-#if 0
-struct aux_queue {
- unsigned long head;
- unsigned long tail;
- wait_queue_head_t proc_list;
- struct fasync_struct *fasync;
- unsigned char buf[AUX_BUF_SIZE];
-};
-#endif
diff --git a/include/pci.h b/include/pci.h
index 7adc043..31dc760 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -585,8 +585,6 @@
/* Used by auto config */
struct pci_region *pci_mem, *pci_io, *pci_prefetch;
- /* Used by ppc405 autoconfig*/
- struct pci_region *pci_fb;
#ifndef CONFIG_DM_PCI
int current_busno;
diff --git a/include/pe.h b/include/pe.h
index c3a19ce..e7845bb 100644
--- a/include/pe.h
+++ b/include/pe.h
@@ -38,11 +38,15 @@
#define IMAGE_DOS_SIGNATURE 0x5A4D /* MZ */
#define IMAGE_NT_SIGNATURE 0x00004550 /* PE00 */
+#define IMAGE_FILE_MACHINE_I386 0x014c
#define IMAGE_FILE_MACHINE_ARM 0x01c0
#define IMAGE_FILE_MACHINE_THUMB 0x01c2
#define IMAGE_FILE_MACHINE_ARMNT 0x01c4
#define IMAGE_FILE_MACHINE_AMD64 0x8664
#define IMAGE_FILE_MACHINE_ARM64 0xaa64
+#define IMAGE_FILE_MACHINE_RISCV32 0x5032
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064
+
#define IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
#define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10
diff --git a/include/power/stpmu1.h b/include/power/stpmu1.h
new file mode 100644
index 0000000..697e245
--- /dev/null
+++ b/include/power/stpmu1.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __PMIC_STPMU1_H_
+#define __PMIC_STPMU1_H_
+
+#define STPMU1_MASK_RESET_BUCK 0x18
+#define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
+#define STPMU1_VREF_CTRL_REG 0x24
+#define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
+#define STPMU1_USB_CTRL_REG 0x40
+#define STPMU1_NVM_USER_STATUS_REG 0xb8
+#define STPMU1_NVM_USER_CONTROL_REG 0xb9
+
+#define STPMU1_MASK_RESET_BUCK3 BIT(2)
+
+#define STPMU1_BUCK_EN BIT(0)
+#define STPMU1_BUCK_MODE BIT(1)
+#define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2)
+#define STPMU1_BUCK_OUTPUT_SHIFT 2
+#define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT)
+#define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT)
+#define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT)
+
+#define STPMU1_VREF_EN BIT(0)
+
+#define STPMU1_LDO_EN BIT(0)
+#define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
+#define STPMU1_LDO12356_OUTPUT_SHIFT 2
+#define STPMU1_LDO3_MODE BIT(7)
+#define STPMU1_LDO3_DDR_SEL 31
+#define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
+#define STPMU1_LDO4_UV 3300000
+
+#define STPMU1_USB_BOOST_EN BIT(0)
+#define STPMU1_USB_PWR_SW_EN GENMASK(2, 1)
+
+#define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0)
+#define STPMU1_NVM_USER_CONTROL_READ BIT(1)
+
+#define STPMU1_NVM_USER_STATUS_BUSY BIT(0)
+#define STPMU1_NVM_USER_STATUS_ERROR BIT(1)
+
+#define STPMU1_DEFAULT_START_UP_DELAY_MS 1
+#define STPMU1_USB_BOOST_START_UP_DELAY_MS 10
+
+enum {
+ STPMU1_BUCK1,
+ STPMU1_BUCK2,
+ STPMU1_BUCK3,
+ STPMU1_BUCK4,
+ STPMU1_MAX_BUCK,
+};
+
+enum {
+ STPMU1_BUCK_MODE_HP,
+ STPMU1_BUCK_MODE_LP,
+};
+
+enum {
+ STPMU1_LDO1,
+ STPMU1_LDO2,
+ STPMU1_LDO3,
+ STPMU1_LDO4,
+ STPMU1_LDO5,
+ STPMU1_LDO6,
+ STPMU1_MAX_LDO,
+};
+
+enum {
+ STPMU1_LDO_MODE_NORMAL,
+ STPMU1_LDO_MODE_BYPASS,
+ STPMU1_LDO_MODE_SINK_SOURCE,
+};
+
+enum {
+ STPMU1_PWR_SW1,
+ STPMU1_PWR_SW2,
+ STPMU1_MAX_PWR_SW,
+};
+
+#endif
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 1878334..4947c77 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -81,7 +81,7 @@
#define r30 30
#define r31 31
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
/* Some special registers */
@@ -93,10 +93,10 @@
#define LCTRL2 157 /* Load/Store Support (37-41) */
#define ICTRL 158
-#endif /* CONFIG_8xx */
+#endif /* CONFIG_MPC8xx */
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
/* Registers in the processor's internal memory map that we use.
*/
diff --git a/include/ps2mult.h b/include/ps2mult.h
deleted file mode 100644
index 1a38733..0000000
--- a/include/ps2mult.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef __LINUX_PS2MULT_H
-#define __LINUX_PS2MULT_H
-
-#define kbd_request_region() ps2mult_init()
-#define kbd_request_irq(handler) ps2mult_request_irq(handler)
-
-#define kbd_read_input() ps2mult_read_input()
-#define kbd_read_status() ps2mult_read_status()
-#define kbd_write_output(val) ps2mult_write_output(val)
-#define kbd_write_command(val) ps2mult_write_command(val)
-
-#define aux_request_irq(hand, dev_id) 0
-#define aux_free_irq(dev_id)
-
-#define PS2MULT_KB_SELECTOR 0xA0
-#define PS2MULT_MS_SELECTOR 0xA1
-#define PS2MULT_ESCAPE 0x7D
-#define PS2MULT_BSYNC 0x7E
-#define PS2MULT_SESSION_START 0x55
-#define PS2MULT_SESSION_END 0x56
-
-#define PS2BUF_SIZE 512 /* power of 2, please */
-
-#ifndef CONFIG_PS2MULT_DELAY
-#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
-#endif
-
- /* PS/2 controller interface (include/asm/keyboard.h)
- */
-extern int ps2mult_init (void);
-extern int ps2mult_request_irq(void (*handler)(void *));
-extern u_char ps2mult_read_input(void);
-extern u_char ps2mult_read_status(void);
-extern void ps2mult_write_output(u_char val);
-extern void ps2mult_write_command(u_char val);
-
-extern void ps2mult_early_init (void);
-extern void ps2mult_callback (int in_cnt);
-
- /* Simple serial interface
- */
-extern int ps2ser_init(void);
-extern void ps2ser_putc(int chr);
-extern int ps2ser_getc(void);
-extern int ps2ser_check(void);
-
-
- /* Serial related stuff
- */
-struct serial_state {
- int baud_base;
- int irq;
- u8 *iomem_base;
-};
-
-#endif /* __LINUX_PS2MULT_H */
diff --git a/include/reset.h b/include/reset.h
index 7185ade..d38f176 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -60,6 +60,24 @@
unsigned long id;
};
+/**
+ * struct reset_ctl_bulk - A handle to (allowing control of) a bulk of reset
+ * signals.
+ *
+ * Clients provide storage for the reset control bulk. The content of the
+ * structure is managed solely by the reset API. A reset control bulk struct is
+ * initialized by "get"ing the reset control bulk struct.
+ * The reset control bulk struct is passed to all other bulk reset APIs to apply
+ * the API to all the reset signals in the bulk struct.
+ *
+ * @resets: An array of reset signal handles handles.
+ * @count: The number of reset signal handles in the reset array.
+ */
+struct reset_ctl_bulk {
+ struct reset_ctl *resets;
+ unsigned int count;
+};
+
#ifdef CONFIG_DM_RESET
/**
* reset_get_by_index - Get/request a reset signal by integer index.
@@ -81,6 +99,22 @@
struct reset_ctl *reset_ctl);
/**
+ * reset_get_bulk - Get/request all reset signals of a device.
+ *
+ * This looks up and requests all reset signals of the client device; each
+ * device is assumed to have n reset signals associated with it somehow,
+ * and this function finds and requests all of them in a separate structure.
+ * The mapping of client device reset signals indices to provider reset signals
+ * may be via device-tree properties, board-provided mapping tables, or some
+ * other mechanism.
+ *
+ * @dev: The client device.
+ * @bulk A pointer to a reset control bulk struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
+
+/**
* reset_get_by_name - Get/request a reset signal by name.
*
* This looks up and requests a reset signal. The name is relative to the
@@ -132,6 +166,21 @@
int reset_assert(struct reset_ctl *reset_ctl);
/**
+ * reset_assert_bulk - Assert all reset signals in a reset control bulk struct.
+ *
+ * This function will assert the specified reset signals in a reset control
+ * bulk struct, thus resetting the affected HW module(s). Depending on the
+ * reset controller hardware, the reset signals will either stay asserted
+ * until reset_deassert_bulk() is called, or the hardware may autonomously
+ * clear the reset signals itself.
+ *
+ * @bulk: A reset control bulk struct that was previously successfully
+ * requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_assert_bulk(struct reset_ctl_bulk *bulk);
+
+/**
* reset_deassert - Deassert a reset signal.
*
* This function will deassert the specified reset signal, thus releasing the
@@ -145,6 +194,20 @@
int reset_deassert(struct reset_ctl *reset_ctl);
/**
+ * reset_deassert_bulk - Deassert all reset signals in a reset control bulk
+ * struct.
+ *
+ * This function will deassert the specified reset signals in a reset control
+ * bulk struct, thus releasing the affected HW modules() from reset, and
+ * allowing them to continue normal operation.
+ *
+ * @bulk: A reset control bulk struct that was previously successfully
+ * requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_deassert_bulk(struct reset_ctl_bulk *bulk);
+
+/**
* reset_release_all - Assert/Free an array of previously requested resets.
*
* For each reset contained in the reset array, this function will check if
@@ -156,6 +219,23 @@
* @return 0 if OK, or a negative error code.
*/
int reset_release_all(struct reset_ctl *reset_ctl, int count);
+
+/**
+ * reset_release_bulk - Assert/Free an array of previously requested reset
+ * signals in a reset control bulk struct.
+ *
+ * For each reset contained in the reset control bulk struct, this function
+ * will check if reset has been previously requested and then will assert
+ * and free it.
+ *
+ * @bulk: A reset control bulk struct that was previously successfully
+ * requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
+{
+ return reset_release_all(bulk->resets, bulk->count);
+}
#else
static inline int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl)
@@ -163,6 +243,11 @@
return -ENOTSUPP;
}
+static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+ return -ENOTSUPP;
+}
+
static inline int reset_get_by_name(struct udevice *dev, const char *name,
struct reset_ctl *reset_ctl)
{
@@ -179,16 +264,30 @@
return 0;
}
+static inline int reset_assert_bulk(struct reset_ctl_bulk *bulk)
+{
+ return 0;
+}
+
static inline int reset_deassert(struct reset_ctl *reset_ctl)
{
return 0;
}
+static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
+{
+ return 0;
+}
+
static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
{
return 0;
}
+static inline int reset_release_bulk(struct clk_bulk *bulk)
+{
+ return 0;
+}
#endif
#endif
diff --git a/include/serial.h b/include/serial.h
index d87f010..384df94 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -165,46 +165,15 @@
/* Access the serial operations for a device */
#define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops)
-void amirix_serial_initialize(void);
-void arc_serial_initialize(void);
-void arm_dcc_initialize(void);
-void asc_serial_initialize(void);
void atmel_serial_initialize(void);
void au1x00_serial_initialize(void);
-void bfin_jtag_initialize(void);
-void bfin_serial_initialize(void);
-void bmw_serial_initialize(void);
-void clps7111_serial_initialize(void);
-void cogent_serial_initialize(void);
-void cpci750_serial_initialize(void);
-void evb64260_serial_initialize(void);
-void imx_serial_initialize(void);
-void iop480_serial_initialize(void);
-void jz_serial_initialize(void);
-void leon2_serial_initialize(void);
-void leon3_serial_initialize(void);
-void lh7a40x_serial_initialize(void);
-void lpc32xx_serial_initialize(void);
-void marvell_serial_initialize(void);
-void max3100_serial_initialize(void);
void mcf_serial_initialize(void);
-void ml2_serial_initialize(void);
void mpc85xx_serial_initialize(void);
void mpc8xx_serial_initialize(void);
void mxc_serial_initialize(void);
-void mxs_auart_initialize(void);
void ns16550_serial_initialize(void);
-void oc_serial_initialize(void);
-void p3mx_serial_initialize(void);
void pl01x_serial_initialize(void);
void pxa_serial_initialize(void);
-void s3c24xx_serial_initialize(void);
-void s5p_serial_initialize(void);
-void sa1100_serial_initialize(void);
-void sandbox_serial_initialize(void);
-void sconsole_serial_initialize(void);
void sh_serial_initialize(void);
-void uartlite_serial_initialize(void);
-void zynq_serial_initialize(void);
#endif
diff --git a/include/spl.h b/include/spl.h
index c14448b..5754012 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -82,6 +82,7 @@
void preloader_console_init(void);
u32 spl_boot_device(void);
u32 spl_boot_mode(const u32 boot_device);
+int spl_boot_partition(const u32 boot_device);
void spl_set_bd(void);
/**
diff --git a/include/st_logo_data.h b/include/st_logo_data.h
new file mode 100644
index 0000000..4d3a26e
--- /dev/null
+++ b/include/st_logo_data.h
@@ -0,0 +1,3267 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * file generated from picture
+ * tools/logos/stmicroelectronics_uboot_logo_8bit_rle.bmp
+ */
+
+unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = {
+0x42, 0x4d, 0x5c, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x04,
+0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x60, 0x01,
+0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe2, 0x93,
+0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x01,
+0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x42, 0x47, 0x52, 0x73, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xae, 0x82, 0x3a, 0x00, 0xa5, 0x7b,
+0x37, 0x00, 0xfe, 0xfe, 0xfe, 0x00, 0xac, 0x80, 0x39, 0x00, 0x4e, 0x1b,
+0x02, 0x00, 0xb7, 0x88, 0x3b, 0x00, 0x4f, 0x1c, 0x02, 0x00, 0xb3, 0x85,
+0x3a, 0x00, 0xe1, 0xaa, 0x35, 0x00, 0x86, 0x62, 0x1f, 0x00, 0x65, 0x4a,
+0x13, 0x00, 0xa9, 0x7e, 0x38, 0x00, 0xff, 0xfe, 0xff, 0x00, 0x77, 0x55,
+0x13, 0x00, 0xbe, 0x91, 0x47, 0x00, 0xbc, 0x8d, 0x3d, 0x00, 0xfe, 0xfd,
+0xfd, 0x00, 0xa3, 0x7a, 0x38, 0x00, 0xbd, 0x8e, 0x42, 0x00, 0xa7, 0x7d,
+0x39, 0x00, 0x72, 0x52, 0x14, 0x00, 0xbc, 0x8d, 0x40, 0x00, 0x84, 0x60,
+0x1e, 0x00, 0xba, 0x8a, 0x3c, 0x00, 0x75, 0x53, 0x13, 0x00, 0x87, 0x62,
+0x11, 0x00, 0x85, 0x60, 0x10, 0x00, 0x7e, 0x5b, 0x12, 0x00, 0xb4, 0x86,
+0x3a, 0x00, 0x8c, 0x6a, 0x35, 0x00, 0xb1, 0x84, 0x3b, 0x00, 0xaa, 0x7f,
+0x3a, 0x00, 0xbc, 0x8c, 0x3c, 0x00, 0x85, 0x64, 0x34, 0x00, 0xb9, 0x89,
+0x3b, 0x00, 0x93, 0x69, 0x0e, 0x00, 0x8d, 0x65, 0x0e, 0x00, 0xfd, 0xfd,
+0xfc, 0x00, 0xa0, 0x78, 0x37, 0x00, 0x81, 0x5d, 0x12, 0x00, 0x9e, 0x76,
+0x36, 0x00, 0xbe, 0x90, 0x45, 0x00, 0x94, 0x6a, 0x0b, 0x00, 0x8b, 0x64,
+0x10, 0x00, 0x68, 0x4c, 0x14, 0x00, 0x8b, 0x69, 0x35, 0x00, 0x82, 0x5e,
+0x11, 0x00, 0x90, 0x6c, 0x35, 0x00, 0x89, 0x63, 0x0f, 0x00, 0xaf, 0x83,
+0x39, 0x00, 0xa2, 0x75, 0x06, 0x00, 0x96, 0x6b, 0x0d, 0x00, 0x7b, 0x59,
+0x12, 0x00, 0x9c, 0x70, 0x08, 0x00, 0x99, 0x73, 0x37, 0x00, 0xb0, 0x83,
+0x39, 0x00, 0x84, 0x60, 0x11, 0x00, 0x80, 0x5c, 0x14, 0x00, 0x91, 0x68,
+0x0c, 0x00, 0x6a, 0x4d, 0x14, 0x00, 0xc3, 0x99, 0x54, 0x00, 0x92, 0x6e,
+0x36, 0x00, 0x9a, 0x6e, 0x0b, 0x00, 0x8a, 0x68, 0x34, 0x00, 0xc0, 0x94,
+0x4b, 0x00, 0x98, 0x6c, 0x09, 0x00, 0x8f, 0x67, 0x0f, 0x00, 0x82, 0x62,
+0x34, 0x00, 0x7d, 0x5a, 0x15, 0x00, 0xc5, 0x9f, 0x5f, 0x00, 0xbb, 0x8b,
+0x3b, 0x00, 0xc8, 0xa7, 0x6a, 0x00, 0xc0, 0x95, 0x4e, 0x00, 0x87, 0x66,
+0x34, 0x00, 0x9f, 0x72, 0x06, 0x00, 0xbf, 0x93, 0x49, 0x00, 0xfd, 0xfb,
+0xfc, 0x00, 0xc7, 0xa4, 0x66, 0x00, 0x7a, 0x57, 0x13, 0x00, 0xc4, 0x9d,
+0x5a, 0x00, 0x83, 0x5f, 0x13, 0x00, 0x9c, 0x75, 0x36, 0x00, 0x7f, 0x60,
+0x32, 0x00, 0xb5, 0x87, 0x3c, 0x00, 0xc3, 0x9b, 0x57, 0x00, 0xc8, 0xa5,
+0x69, 0x00, 0x72, 0x55, 0x25, 0x00, 0xb9, 0x8a, 0x3a, 0x00, 0x94, 0x70,
+0x36, 0x00, 0xa2, 0x79, 0x36, 0x00, 0x7f, 0x5c, 0x12, 0x00, 0x97, 0x72,
+0x37, 0x00, 0x6c, 0x4e, 0x14, 0x00, 0xc5, 0x9e, 0x5d, 0x00, 0xca, 0xa9,
+0x6c, 0x00, 0xc5, 0xa3, 0x64, 0x00, 0x9e, 0x72, 0x0b, 0x00, 0xad, 0x81,
+0x3a, 0x00, 0x8e, 0x6b, 0x36, 0x00, 0xc6, 0xa1, 0x62, 0x00, 0x7c, 0x5f,
+0x31, 0x00, 0x6f, 0x50, 0x14, 0x00, 0xc1, 0x96, 0x50, 0x00, 0xd9, 0xc4,
+0x9f, 0x00, 0xcd, 0xbe, 0xa9, 0x00, 0xaa, 0x98, 0x7f, 0x00, 0xf6, 0xf3,
+0xf1, 0x00, 0xb9, 0x9b, 0x62, 0x00, 0x6a, 0x4c, 0x19, 0x00, 0x76, 0x59,
+0x29, 0x00, 0x79, 0x57, 0x15, 0x00, 0x6e, 0x4f, 0x13, 0x00, 0xfb, 0xf9,
+0xf9, 0x00, 0xae, 0x8d, 0x53, 0x00, 0x78, 0x5c, 0x2e, 0x00, 0xb2, 0x91,
+0x55, 0x00, 0xe8, 0xe1, 0xdc, 0x00, 0x8b, 0x69, 0x2e, 0x00, 0xc0, 0x9f,
+0x62, 0x00, 0xc1, 0x97, 0x52, 0x00, 0x52, 0x20, 0x06, 0x00, 0xbe, 0x9c,
+0x60, 0x00, 0xa1, 0x79, 0x38, 0x00, 0xed, 0xe8, 0xe5, 0x00, 0xdc, 0xc8,
+0xa6, 0x00, 0xd6, 0xca, 0xb9, 0x00, 0x80, 0x5e, 0x1d, 0x00, 0xb6, 0x95,
+0x58, 0x00, 0xb5, 0x97, 0x60, 0x00, 0x92, 0x75, 0x41, 0x00, 0x6f, 0x51,
+0x1d, 0x00, 0xc9, 0xba, 0xb2, 0x00, 0xa2, 0x88, 0x7b, 0x00, 0x82, 0x5e,
+0x1a, 0x00, 0x89, 0x67, 0x56, 0x00, 0xb0, 0x93, 0x5d, 0x00, 0x67, 0x4a,
+0x00, 0x00, 0xad, 0x9c, 0x81, 0x00, 0xd1, 0xbc, 0x9a, 0x00, 0x84, 0x64,
+0x2c, 0x00, 0x6e, 0x53, 0x25, 0x00, 0xf2, 0xee, 0xeb, 0x00, 0xbe, 0xa0,
+0x69, 0x00, 0xd5, 0xbf, 0x9b, 0x00, 0xba, 0x99, 0x5c, 0x00, 0x5a, 0x2a,
+0x12, 0x00, 0x7d, 0x5e, 0x29, 0x00, 0xbc, 0xa9, 0x9f, 0x00, 0x56, 0x24,
+0x0b, 0x00, 0xd0, 0xc2, 0xba, 0x00, 0x64, 0x37, 0x21, 0x00, 0x6a, 0x3f,
+0x29, 0x00, 0xd6, 0xcb, 0xc4, 0x00, 0xe4, 0xdc, 0xd7, 0x00, 0x6f, 0x45,
+0x30, 0x00, 0x6d, 0x4e, 0x03, 0x00, 0xca, 0xab, 0x72, 0x00, 0x64, 0x49,
+0x13, 0x00, 0xa5, 0x8c, 0x7f, 0x00, 0xed, 0xcc, 0x86, 0x00, 0xf8, 0xea,
+0xcd, 0x00, 0xfc, 0xf7, 0xec, 0x00, 0xfc, 0xf9, 0xf3, 0x00, 0x77, 0x4f,
+0x3b, 0x00, 0x8e, 0x71, 0x3c, 0x00, 0x92, 0x73, 0x3b, 0x00, 0xc6, 0xa8,
+0x6f, 0x00, 0xa8, 0x8a, 0x53, 0x00, 0x97, 0x79, 0x6a, 0x00, 0xa9, 0x80,
+0x3e, 0x00, 0xb2, 0x7e, 0x04, 0x00, 0x7b, 0x56, 0x0d, 0x00, 0xee, 0xe7,
+0xde, 0x00, 0x74, 0x51, 0x02, 0x00, 0xa4, 0x84, 0x4a, 0x00, 0xf6, 0xe4,
+0xbf, 0x00, 0xdc, 0xd2, 0xc8, 0x00, 0xe0, 0xd7, 0xd0, 0x00, 0xe9, 0xbf,
+0x68, 0x00, 0x9d, 0x7d, 0x43, 0x00, 0x5f, 0x31, 0x19, 0x00, 0xb3, 0x9d,
+0x92, 0x00, 0xb8, 0x8a, 0x40, 0x00, 0x9e, 0x82, 0x4f, 0x00, 0x92, 0x6d,
+0x2e, 0x00, 0x65, 0x4a, 0x11, 0x00, 0x97, 0x7b, 0x48, 0x00, 0xbf, 0x93,
+0x41, 0x00, 0x7d, 0x57, 0x44, 0x00, 0x80, 0x5c, 0x02, 0x00, 0x83, 0x5f,
+0x4e, 0x00, 0x97, 0x71, 0x30, 0x00, 0xab, 0x89, 0x4d, 0x00, 0x9d, 0x81,
+0x73, 0x00, 0x87, 0x64, 0x24, 0x00, 0x90, 0x70, 0x61, 0x00, 0xc6, 0xb5,
+0xac, 0x00, 0xab, 0x7e, 0x2d, 0x00, 0xa7, 0x7b, 0x1b, 0x00, 0xb8, 0x89,
+0x26, 0x00, 0xe3, 0xb1, 0x45, 0x00, 0x9c, 0x74, 0x2e, 0x00, 0x7a, 0x57,
+0x01, 0x00, 0xc2, 0xa4, 0x6e, 0x00, 0x86, 0x60, 0x01, 0x00, 0x60, 0x41,
+0x00, 0x00, 0xba, 0xa5, 0x83, 0x00, 0xce, 0xb8, 0x93, 0x00, 0xb6, 0x84,
+0x17, 0x00, 0xf8, 0xf1, 0xe4, 0x00, 0x73, 0x53, 0x0c, 0x00, 0xa7, 0x91,
+0x6b, 0x00, 0xa9, 0x78, 0x04, 0x00, 0xc1, 0xaf, 0xa6, 0x00, 0xac, 0x93,
+0x87, 0x00, 0xf2, 0xda, 0xa8, 0x00, 0xe3, 0xd2, 0xb7, 0x00, 0xeb, 0xc5,
+0x75, 0x00, 0xb8, 0xa5, 0x96, 0x00, 0x93, 0x68, 0x01, 0x00, 0xbb, 0x8d,
+0x32, 0x00, 0xc5, 0x9c, 0x55, 0x00, 0x9c, 0x72, 0x22, 0x00, 0xa5, 0x78,
+0x29, 0x00, 0xb3, 0x83, 0x2d, 0x00, 0xe7, 0xbd, 0x61, 0x00, 0xf0, 0xd4,
+0x99, 0x00, 0x9a, 0x6d, 0x02, 0x00, 0x78, 0x58, 0x1f, 0x00, 0xf9, 0xef,
+0xd8, 0x00, 0xeb, 0xe0, 0xd1, 0x00, 0xf4, 0xdf, 0xb3, 0x00, 0xe2, 0xad,
+0x3d, 0x00, 0xc3, 0xae, 0x8c, 0x00, 0xcf, 0xb1, 0x7e, 0x00, 0xe8, 0xd9,
+0xc2, 0x00, 0x89, 0x6d, 0x3c, 0x00, 0x85, 0x69, 0x37, 0x00, 0x8d, 0x64,
+0x01, 0x00, 0x90, 0x69, 0x23, 0x00, 0xc4, 0xb3, 0x99, 0x00, 0xc2, 0x9c,
+0x50, 0x00, 0xb9, 0x8d, 0x44, 0x00, 0xa0, 0x87, 0x5e, 0x00, 0xa8, 0x8f,
+0x82, 0x00, 0xaf, 0x98, 0x8d, 0x00, 0xb1, 0x9a, 0x73, 0x00, 0xb3, 0x8a,
+0x48, 0x00, 0xe5, 0xb5, 0x4f, 0x00, 0xd6, 0xbb, 0x8e, 0x00, 0xbb, 0x92,
+0x4c, 0x00, 0x86, 0x62, 0x19, 0x00, 0xe1, 0xa9, 0x35, 0x00, 0xe6, 0xb9,
+0x59, 0x00, 0xdb, 0xb3, 0x61, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00,
+0xdb, 0x00, 0x01, 0x4d, 0x01, 0x4d, 0x0a, 0x00, 0x00, 0x03, 0x26, 0x4d,
+0x03, 0x00, 0xf6, 0x00, 0x00, 0x00, 0xd9, 0x00, 0x01, 0x03, 0x03, 0x00,
+0x00, 0x0a, 0x4d, 0x9a, 0x96, 0xc5, 0x94, 0xb6, 0xd6, 0x96, 0xb2, 0x8e,
+0x03, 0x00, 0x01, 0x26, 0xf5, 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x0e,
+0x9a, 0xb6, 0x87, 0x9b, 0x79, 0x07, 0x07, 0x05, 0x05, 0x07, 0x97, 0xbd,
+0x85, 0x96, 0xf7, 0x00, 0x00, 0x00, 0xd6, 0x00, 0x00, 0x06, 0x03, 0x00,
+0x00, 0x8e, 0xc2, 0x98, 0x05, 0x07, 0x01, 0x05, 0x06, 0x07, 0x00, 0x03,
+0x95, 0x87, 0xb1, 0x00, 0xf5, 0x00, 0x00, 0x00, 0xd5, 0x00, 0x00, 0x05,
+0x03, 0x00, 0x00, 0x96, 0x9b, 0x00, 0x04, 0x05, 0x03, 0x07, 0x00, 0x03,
+0x05, 0x07, 0x07, 0x00, 0x04, 0x05, 0x00, 0x07, 0x07, 0x07, 0x92, 0xf6,
+0x00, 0x00, 0x03, 0x00, 0xf1, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x07,
+0x26, 0x00, 0x00, 0xb6, 0x79, 0x07, 0x05, 0x00, 0x03, 0x07, 0x00, 0x12,
+0x97, 0x87, 0xf5, 0xdb, 0x94, 0xb6, 0xa9, 0x9b, 0x95, 0x05, 0x05, 0x07,
+0x07, 0x05, 0xa9, 0x4d, 0x00, 0x4d, 0xf0, 0x00, 0x00, 0x00, 0xd6, 0x00,
+0x01, 0xdb, 0x05, 0x07, 0x00, 0x03, 0x9b, 0xb6, 0x8e, 0x00, 0x06, 0x00,
+0x00, 0x0c, 0x03, 0x99, 0xc4, 0x79, 0x07, 0x07, 0x05, 0x05, 0x9f, 0x00,
+0x00, 0x03, 0xef, 0x00, 0x00, 0x00, 0xd5, 0x00, 0x01, 0x99, 0x01, 0x95,
+0x03, 0x07, 0x00, 0x03, 0x05, 0xa9, 0x6b, 0x00, 0x0b, 0x00, 0x01, 0xc5,
+0x01, 0xb5, 0x03, 0x07, 0x01, 0x05, 0x01, 0x84, 0xf1, 0x00, 0x00, 0x00,
+0xd2, 0x00, 0x00, 0x04, 0x03, 0x00, 0x6b, 0xa4, 0x03, 0x07, 0x01, 0x05,
+0x01, 0xf5, 0x0e, 0x00, 0x01, 0x96, 0x01, 0x95, 0x03, 0x07, 0x01, 0xa4,
+0x01, 0x8e, 0xf0, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x09, 0xd6, 0x05,
+0x07, 0x05, 0x05, 0xc4, 0x00, 0x00, 0x03, 0x00, 0x0d, 0x00, 0x01, 0xdb,
+0x04, 0x07, 0x01, 0xc5, 0xf0, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x01, 0x03,
+0x06, 0x00, 0x01, 0x03, 0x4e, 0x00, 0x00, 0x09, 0x26, 0x9b, 0x05, 0x07,
+0x05, 0x98, 0x7c, 0x00, 0x03, 0x00, 0x0e, 0x00, 0x00, 0x06, 0x6b, 0xa4,
+0x07, 0x07, 0x05, 0x87, 0x93, 0x00, 0x01, 0x03, 0x5c, 0x00, 0x00, 0x00,
+0x1f, 0x00, 0x01, 0x03, 0x0f, 0x00, 0x00, 0x03, 0x03, 0x00, 0x03, 0x00,
+0x0f, 0x00, 0x01, 0x03, 0x01, 0x03, 0x0f, 0x00, 0x01, 0x03, 0x0a, 0x00,
+0x01, 0x03, 0x01, 0x26, 0x03, 0x00, 0x01, 0x26, 0x04, 0xa2, 0x01, 0xa3,
+0x04, 0x00, 0x01, 0x26, 0x0f, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x00, 0xa2,
+0xd2, 0xd2, 0xa2, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x01, 0x03, 0x01, 0x4d,
+0x03, 0x00, 0x00, 0x07, 0x03, 0x8e, 0x7c, 0xad, 0xad, 0x7c, 0x6b, 0x00,
+0x03, 0x00, 0x00, 0x04, 0x4d, 0x26, 0x00, 0x26, 0x06, 0x00, 0x01, 0x03,
+0x0a, 0x00, 0x01, 0x26, 0x01, 0x4d, 0x03, 0x00, 0x00, 0x06, 0x8e, 0x7c,
+0x75, 0x9a, 0x75, 0x8e, 0x03, 0x00, 0x01, 0x4d, 0x01, 0x26, 0x06, 0x00,
+0x01, 0x26, 0x03, 0x00, 0x00, 0x06, 0x99, 0x07, 0x07, 0x05, 0x05, 0x94,
+0x05, 0x00, 0x00, 0x07, 0x4d, 0x8e, 0x7c, 0xad, 0x7c, 0x8e, 0x71, 0x00,
+0x03, 0x00, 0x00, 0x09, 0x4d, 0x00, 0x00, 0xd6, 0x07, 0x07, 0x05, 0x92,
+0x6b, 0x00, 0x03, 0x00, 0x01, 0x03, 0x01, 0x03, 0x06, 0x00, 0x01, 0x03,
+0x0b, 0x00, 0x01, 0x26, 0x05, 0x00, 0x01, 0x26, 0x0c, 0x00, 0x01, 0x03,
+0x06, 0x00, 0x01, 0x03, 0x09, 0x00, 0x01, 0x26, 0x01, 0x4d, 0x03, 0x00,
+0x00, 0x07, 0x6b, 0x8e, 0xad, 0xad, 0x7c, 0x8e, 0x71, 0x00, 0x03, 0x00,
+0x01, 0x4d, 0x01, 0x03, 0x0a, 0x00, 0x01, 0x03, 0x06, 0x00, 0x01, 0x03,
+0x0d, 0x00, 0x01, 0x03, 0x06, 0x00, 0x01, 0x03, 0x06, 0x00, 0x01, 0x03,
+0x06, 0x00, 0x01, 0x03, 0x01, 0x03, 0x0d, 0x00, 0x01, 0x03, 0x01, 0x4d,
+0x03, 0x00, 0x00, 0x07, 0x4d, 0x8e, 0x7c, 0xad, 0xad, 0x7c, 0x6b, 0x00,
+0x03, 0x00, 0x01, 0x4d, 0x01, 0x03, 0x12, 0x00, 0x01, 0x4d, 0x04, 0x00,
+0x00, 0x06, 0x8e, 0x7c, 0xad, 0xad, 0x7c, 0x8e, 0x03, 0x00, 0x00, 0x04,
+0x26, 0x4d, 0x00, 0x03, 0x06, 0x00, 0x01, 0x03, 0x24, 0x00, 0x00, 0x00,
+0x20, 0x00, 0x01, 0x4d, 0x0d, 0xb0, 0x01, 0xa2, 0x03, 0x00, 0x01, 0x4d,
+0x01, 0xa1, 0x0c, 0xb0, 0x00, 0x05, 0xa2, 0x00, 0x00, 0x4d, 0xa1, 0x00,
+0x0b, 0xb0, 0x00, 0x04, 0xe8, 0xd2, 0x00, 0x03, 0x08, 0x00, 0x00, 0x0f,
+0x03, 0x00, 0x00, 0x71, 0xa1, 0xd8, 0xa0, 0xb3, 0xf9, 0xf9, 0xfe, 0xda,
+0xa0, 0xe8, 0xd2, 0x00, 0x03, 0x00, 0x01, 0x03, 0x0c, 0x00, 0x00, 0x0a,
+0x03, 0x00, 0x26, 0xd8, 0xe2, 0xe9, 0xe9, 0xe2, 0xd8, 0x71, 0x0f, 0x00,
+0x01, 0x03, 0x03, 0x00, 0x00, 0x11, 0xb2, 0x94, 0xc2, 0xbd, 0x9b, 0x98,
+0x97, 0x9b, 0x87, 0x9f, 0x84, 0x8e, 0x00, 0x00, 0x26, 0x00, 0x8e, 0x00,
+0x03, 0xc5, 0x01, 0x84, 0x01, 0x4d, 0x0a, 0x00, 0x00, 0x17, 0x26, 0x00,
+0x00, 0x7c, 0xc5, 0xc2, 0xbd, 0x98, 0xb5, 0x92, 0x97, 0xbd, 0xc2, 0x84,
+0x6b, 0x00, 0x00, 0x6b, 0x96, 0xc5, 0xc5, 0x84, 0x6b, 0x00, 0x04, 0x00,
+0x01, 0x99, 0x03, 0x85, 0x01, 0xf6, 0x01, 0x8e, 0x03, 0x00, 0x00, 0x0c,
+0xb2, 0x94, 0xa9, 0xa4, 0x98, 0x97, 0x98, 0xa4, 0xc4, 0xdb, 0xb1, 0x03,
+0x03, 0x00, 0x01, 0x9a, 0x01, 0x92, 0x03, 0x07, 0x01, 0xb1, 0x05, 0x00,
+0x01, 0x9a, 0x03, 0xc5, 0x01, 0xb2, 0x0c, 0x00, 0x00, 0x07, 0x03, 0x00,
+0x9a, 0xc5, 0x84, 0xd6, 0xb1, 0x00, 0x0e, 0x00, 0x01, 0xad, 0x03, 0xc5,
+0x01, 0x99, 0x01, 0x71, 0x09, 0x00, 0x00, 0x08, 0x26, 0x00, 0x00, 0x6b,
+0x99, 0xf6, 0x87, 0xa4, 0x03, 0x98, 0x00, 0x04, 0xa4, 0xc4, 0xb6, 0xb1,
+0x03, 0x00, 0x01, 0x03, 0x0a, 0x00, 0x00, 0x06, 0x7c, 0x84, 0xc5, 0xc5,
+0x99, 0x71, 0x0f, 0x00, 0x00, 0x08, 0x71, 0x96, 0xc5, 0xc5, 0x84, 0x8e,
+0x00, 0x03, 0x07, 0x00, 0x00, 0x05, 0x9a, 0xd6, 0xc5, 0xc5, 0xb1, 0x00,
+0x0e, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x0f, 0xb2, 0x94, 0xa9, 0xbd,
+0x98, 0x98, 0x97, 0xa4, 0x87, 0xf6, 0x99, 0x6b, 0x00, 0x00, 0x26, 0x00,
+0x0f, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x16, 0x9a, 0xd6, 0xc2, 0xbd,
+0x98, 0x97, 0x98, 0x98, 0xbd, 0x85, 0x84, 0x7c, 0x00, 0x00, 0x4d, 0x00,
+0x8e, 0x96, 0xc5, 0xc5, 0x96, 0x6b, 0x25, 0x00, 0x00, 0x00, 0x20, 0x00,
+0x01, 0xa2, 0x0d, 0x09, 0x01, 0xd8, 0x03, 0x00, 0x01, 0xa2, 0x01, 0xc9,
+0x03, 0x09, 0x01, 0xfd, 0x01, 0xfd, 0x07, 0x09, 0x00, 0x05, 0xe8, 0x00,
+0x00, 0xa2, 0xfe, 0x00, 0x0c, 0x09, 0x00, 0x03, 0xd8, 0x00, 0x26, 0x00,
+0x0a, 0x00, 0x00, 0x03, 0xb0, 0xda, 0xe9, 0x00, 0x09, 0x09, 0x00, 0x06,
+0xf9, 0xa0, 0xe6, 0x00, 0x00, 0x03, 0x0a, 0x00, 0x00, 0x04, 0x03, 0x00,
+0x26, 0xa0, 0x06, 0x09, 0x01, 0xda, 0x01, 0x26, 0x10, 0x00, 0x00, 0x09,
+0x99, 0xc4, 0xb5, 0x07, 0x07, 0x05, 0x05, 0x07, 0x07, 0x00, 0x04, 0x05,
+0x00, 0x0b, 0xa4, 0xb6, 0x6b, 0x00, 0x00, 0x96, 0x07, 0x05, 0x07, 0x07,
+0x6b, 0x00, 0x0b, 0x00, 0x00, 0x06, 0x71, 0xb6, 0x9b, 0x07, 0x07, 0x05,
+0x07, 0x07, 0x00, 0x05, 0xbd, 0x84, 0x00, 0x7c, 0x92, 0x00, 0x03, 0x07,
+0x01, 0x75, 0x03, 0x00, 0x01, 0x03, 0x07, 0x00, 0x00, 0x03, 0x84, 0xc4,
+0x92, 0x00, 0x03, 0x07, 0x01, 0x05, 0x01, 0x05, 0x04, 0x07, 0x00, 0x07,
+0x92, 0xc4, 0x84, 0x00, 0x00, 0x7c, 0xa4, 0x00, 0x03, 0x07, 0x01, 0xc5,
+0x05, 0x00, 0x00, 0x05, 0xc2, 0x05, 0x05, 0x07, 0xc4, 0x00, 0x0c, 0x00,
+0x00, 0x03, 0x4d, 0x00, 0x9f, 0x00, 0x03, 0x07, 0x01, 0xbd, 0x0e, 0x00,
+0x01, 0xdb, 0x03, 0x07, 0x01, 0xa4, 0x01, 0x8e, 0x0b, 0x00, 0x00, 0x06,
+0xd6, 0xbf, 0x79, 0x07, 0x07, 0x05, 0x03, 0x07, 0x03, 0x05, 0x00, 0x03,
+0x92, 0xc4, 0x96, 0x00, 0x0c, 0x00, 0x01, 0xc5, 0x03, 0x07, 0x01, 0x9b,
+0x01, 0x7c, 0x0d, 0x00, 0x00, 0x04, 0x03, 0x00, 0x7c, 0xb5, 0x03, 0x07,
+0x00, 0x03, 0x84, 0x00, 0x4d, 0x00, 0x07, 0x00, 0x00, 0x05, 0xc2, 0x05,
+0x07, 0x07, 0xbd, 0x00, 0x10, 0x00, 0x00, 0x09, 0x96, 0xc4, 0x92, 0x07,
+0x07, 0x05, 0x07, 0x07, 0x05, 0x00, 0x03, 0x07, 0x00, 0x07, 0x79, 0xbf,
+0x94, 0x71, 0x00, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x00, 0x04, 0x99, 0xa9,
+0x97, 0x05, 0x03, 0x07, 0x00, 0x11, 0x05, 0x05, 0x07, 0x05, 0x07, 0x07,
+0x9b, 0xd7, 0x7c, 0x00, 0x00, 0x99, 0x95, 0x05, 0x05, 0x95, 0x9a, 0x00,
+0x25, 0x00, 0x00, 0x00, 0x20, 0x00, 0x01, 0xa2, 0x01, 0xe9, 0x0c, 0x09,
+0x01, 0xe8, 0x03, 0x00, 0x01, 0xa2, 0x01, 0xf9, 0x0c, 0x09, 0x00, 0x05,
+0xb0, 0x00, 0x00, 0xa2, 0xe2, 0x00, 0x0c, 0x09, 0x00, 0x03, 0xd8, 0x00,
+0x26, 0x00, 0x05, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0xd2, 0xda, 0x00,
+0x0e, 0x09, 0x00, 0x06, 0xc9, 0xe3, 0x4d, 0x00, 0x00, 0x03, 0x0a, 0x00,
+0x01, 0xe8, 0x08, 0x09, 0x01, 0xd8, 0x0b, 0x00, 0x00, 0x06, 0x03, 0x00,
+0x00, 0x7c, 0xa9, 0x92, 0x04, 0x07, 0x00, 0x0e, 0x05, 0x07, 0x07, 0x05,
+0x07, 0x07, 0x05, 0x07, 0x07, 0x05, 0xa4, 0x99, 0x00, 0x99, 0x03, 0x07,
+0x01, 0x95, 0x01, 0x6b, 0x0a, 0x00, 0x00, 0x07, 0x75, 0xbf, 0x05, 0x07,
+0x07, 0x05, 0x05, 0x00, 0x04, 0x07, 0x01, 0x05, 0x01, 0x05, 0x03, 0x07,
+0x00, 0x07, 0xd6, 0x6b, 0x98, 0x05, 0x07, 0x05, 0x75, 0x00, 0x09, 0x00,
+0x00, 0x06, 0x8e, 0xa9, 0x79, 0x07, 0x07, 0x05, 0x04, 0x07, 0x01, 0x05,
+0x06, 0x07, 0x00, 0x04, 0xc2, 0x26, 0x00, 0x87, 0x03, 0x05, 0x01, 0xdb,
+0x05, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x07, 0xa9, 0x00, 0x0c, 0x00,
+0x00, 0x07, 0x4d, 0x00, 0xd7, 0x07, 0x07, 0x05, 0x87, 0x00, 0x0e, 0x00,
+0x01, 0x94, 0x03, 0x07, 0x01, 0xbf, 0x01, 0x6b, 0x06, 0x00, 0x00, 0x05,
+0x03, 0x00, 0x00, 0x9a, 0x87, 0x00, 0x04, 0x07, 0x01, 0x05, 0x01, 0x05,
+0x03, 0x07, 0x01, 0x05, 0x01, 0x05, 0x03, 0x07, 0x00, 0x06, 0x95, 0xa9,
+0x8e, 0x00, 0x00, 0x03, 0x07, 0x00, 0x01, 0x84, 0x03, 0x07, 0x01, 0xa4,
+0x01, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x7c, 0x98, 0x07, 0x07,
+0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x01, 0x85, 0x03, 0x07, 0x01, 0x87,
+0x0b, 0x00, 0x00, 0x08, 0x03, 0x00, 0x00, 0x6b, 0x85, 0x95, 0x07, 0x05,
+0x08, 0x07, 0x01, 0x05, 0x03, 0x07, 0x00, 0x05, 0xbf, 0xb1, 0x00, 0x00,
+0x03, 0x00, 0x09, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x71, 0x9f, 0x92,
+0x04, 0x07, 0x01, 0x05, 0x04, 0x07, 0x01, 0x05, 0x01, 0x05, 0x03, 0x07,
+0x00, 0x09, 0x9b, 0x84, 0x00, 0xb2, 0xb5, 0x07, 0x07, 0x97, 0x9a, 0x00,
+0x25, 0x00, 0x00, 0x00, 0x20, 0x00, 0x01, 0xa2, 0x01, 0xe9, 0x0c, 0x09,
+0x01, 0xe8, 0x03, 0x00, 0x01, 0xa2, 0x01, 0xf9, 0x03, 0x09, 0x01, 0xfd,
+0x08, 0x09, 0x00, 0x05, 0xb0, 0x00, 0x00, 0xa2, 0xe2, 0x00, 0x0c, 0x09,
+0x00, 0x03, 0xd8, 0x00, 0x26, 0x00, 0x04, 0x00, 0x00, 0x05, 0x03, 0x00,
+0x00, 0xa1, 0xf9, 0x00, 0x04, 0x09, 0x00, 0x03, 0xfd, 0x09, 0xfe, 0x00,
+0x03, 0xb3, 0x01, 0xf9, 0x06, 0x09, 0x01, 0xda, 0x01, 0xa2, 0x0b, 0x00,
+0x01, 0xa3, 0x01, 0xb3, 0x03, 0x09, 0x01, 0xfd, 0x04, 0x09, 0x01, 0xfe,
+0x01, 0x4d, 0x09, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0xb1, 0x9b, 0x05,
+0x07, 0x05, 0x05, 0x07, 0x07, 0x79, 0x98, 0x9b, 0x9b, 0x97, 0x06, 0x07,
+0x00, 0x03, 0x92, 0x99, 0xb2, 0x00, 0x03, 0x07, 0x01, 0x95, 0x01, 0x6b,
+0x09, 0x00, 0x01, 0x9a, 0x01, 0x98, 0x03, 0x07, 0x00, 0x09, 0x05, 0x07,
+0x07, 0x98, 0xbd, 0xbf, 0x9b, 0x95, 0x05, 0x00, 0x03, 0x07, 0x00, 0x03,
+0x92, 0x85, 0x9b, 0x00, 0x03, 0x07, 0x01, 0x75, 0x05, 0x00, 0x00, 0x05,
+0x03, 0x00, 0x00, 0x99, 0x9b, 0x00, 0x05, 0x07, 0x00, 0x07, 0x05, 0x95,
+0x98, 0x9b, 0x9b, 0x92, 0x05, 0x00, 0x05, 0x07, 0x00, 0x07, 0x87, 0x8e,
+0xa9, 0x05, 0x07, 0x05, 0xf6, 0x00, 0x05, 0x00, 0x00, 0x05, 0x85, 0x05,
+0x07, 0x07, 0xa9, 0x00, 0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x07,
+0x07, 0x05, 0x87, 0x00, 0x0e, 0x00, 0x01, 0x94, 0x03, 0x07, 0x01, 0xbf,
+0x01, 0x6b, 0x05, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0x84, 0x97, 0x00,
+0x04, 0x07, 0x00, 0x09, 0x05, 0x07, 0x92, 0x9b, 0x9b, 0x98, 0x95, 0x05,
+0x05, 0x00, 0x04, 0x07, 0x01, 0x9b, 0x01, 0x9a, 0x09, 0x00, 0x00, 0x06,
+0x84, 0x79, 0x07, 0x05, 0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00,
+0x7c, 0x9b, 0x07, 0x07, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x01, 0x85,
+0x03, 0x07, 0x01, 0x87, 0x0a, 0x00, 0x00, 0x07, 0x03, 0x00, 0x00, 0x75,
+0xbd, 0x07, 0x05, 0x00, 0x04, 0x07, 0x00, 0x05, 0x95, 0x98, 0x9b, 0x9b,
+0x92, 0x00, 0x03, 0x07, 0x00, 0x08, 0x05, 0x07, 0x07, 0xb5, 0x84, 0x00,
+0x00, 0x03, 0x07, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0x75, 0xbd, 0x00,
+0x05, 0x07, 0x00, 0x14, 0x05, 0x79, 0x97, 0xbd, 0xbd, 0x98, 0x95, 0x07,
+0x07, 0x05, 0x07, 0x07, 0x79, 0xd6, 0x9a, 0x97, 0x07, 0x07, 0x97, 0x75,
+0x25, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x0b, 0xa3, 0xe8, 0xd8, 0xd8,
+0xe8, 0xa0, 0xe9, 0x09, 0x09, 0xf9, 0xe3, 0x00, 0x03, 0xd8, 0x01, 0xd2,
+0x03, 0x00, 0x00, 0x06, 0x71, 0xe8, 0xd8, 0xd8, 0xe8, 0xa0, 0x03, 0x09,
+0x00, 0x0e, 0xe2, 0xd8, 0xe8, 0xd8, 0xd8, 0xd2, 0x00, 0x00, 0x71, 0xb0,
+0xd8, 0xd8, 0xe8, 0xe3, 0x03, 0x09, 0x00, 0x08, 0xfe, 0xd8, 0xe8, 0xd8,
+0xe3, 0xe6, 0x00, 0x03, 0x03, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0xb0,
+0xe9, 0x00, 0x04, 0x09, 0x00, 0x04, 0xfe, 0xd8, 0xd2, 0xa2, 0x03, 0xa3,
+0x00, 0x04, 0xa2, 0xe6, 0xe3, 0xc9, 0x04, 0x09, 0x01, 0xe2, 0x01, 0xa2,
+0x0a, 0x00, 0x01, 0xd2, 0x01, 0xf9, 0x08, 0x09, 0x01, 0xe9, 0x01, 0xa2,
+0x08, 0x00, 0x00, 0x0d, 0x03, 0x00, 0x00, 0x99, 0x97, 0x07, 0x79, 0x07,
+0x07, 0x95, 0x87, 0xd6, 0x9a, 0x00, 0x04, 0x8e, 0x00, 0x09, 0xb2, 0xb6,
+0x9b, 0x07, 0x07, 0x05, 0x05, 0x98, 0x85, 0x00, 0x03, 0x07, 0x01, 0x95,
+0x01, 0x6b, 0x06, 0x00, 0x00, 0x04, 0x03, 0x00, 0x6b, 0xa4, 0x04, 0x07,
+0x00, 0x13, 0x92, 0x85, 0x9a, 0x8e, 0x6b, 0x6b, 0x8e, 0x75, 0x94, 0x9b,
+0x05, 0x07, 0x07, 0x79, 0x95, 0x07, 0x07, 0x05, 0x75, 0x00, 0x04, 0x00,
+0x00, 0x06, 0x03, 0x00, 0x00, 0x96, 0xb5, 0x05, 0x03, 0x07, 0x00, 0x04,
+0x95, 0x87, 0xc5, 0x7c, 0x03, 0x8e, 0x00, 0x05, 0x7c, 0x96, 0xa9, 0xb5,
+0x05, 0x00, 0x03, 0x07, 0x01, 0x87, 0x01, 0x87, 0x03, 0x07, 0x01, 0xb6,
+0x05, 0x00, 0x01, 0x85, 0x03, 0x07, 0x01, 0xa9, 0x0c, 0x00, 0x00, 0x03,
+0x4d, 0x00, 0xd7, 0x00, 0x03, 0x07, 0x01, 0x87, 0x0e, 0x00, 0x01, 0x94,
+0x03, 0x07, 0x01, 0xbf, 0x01, 0x6b, 0x04, 0x00, 0x00, 0x0d, 0x03, 0x00,
+0x00, 0xc5, 0x95, 0x07, 0x79, 0x05, 0x07, 0x92, 0xc4, 0x84, 0xad, 0x00,
+0x03, 0x8e, 0x00, 0x0a, 0x75, 0x84, 0xc4, 0x95, 0x07, 0x07, 0x05, 0x05,
+0x97, 0xb1, 0x08, 0x00, 0x00, 0x06, 0x84, 0x07, 0x05, 0x07, 0xa4, 0x7c,
+0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x7c, 0x98, 0x07, 0x05, 0x92, 0x96,
+0x00, 0x4d, 0x07, 0x00, 0x00, 0x05, 0x85, 0x07, 0x07, 0x05, 0x87, 0x00,
+0x09, 0x00, 0x00, 0x0d, 0x03, 0x00, 0x00, 0x9a, 0x9b, 0x07, 0x07, 0x05,
+0x07, 0x07, 0xbd, 0x94, 0x9a, 0x00, 0x03, 0x8e, 0x00, 0x0d, 0x7c, 0x96,
+0xa9, 0xb5, 0x07, 0x07, 0x79, 0x07, 0x92, 0xc5, 0x00, 0x00, 0x03, 0x00,
+0x05, 0x00, 0x00, 0x06, 0x03, 0x03, 0x00, 0xb2, 0x98, 0x05, 0x04, 0x07,
+0x00, 0x0a, 0xbd, 0x94, 0x75, 0x8e, 0x8e, 0x6b, 0x8e, 0x75, 0x94, 0xbd,
+0x04, 0x07, 0x00, 0x07, 0x92, 0xc4, 0x98, 0x05, 0x07, 0x97, 0x75, 0x00,
+0x25, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x01, 0x03, 0x05, 0x00, 0x00, 0x06,
+0xe6, 0xc9, 0x09, 0x09, 0xb3, 0xa3, 0x04, 0x00, 0x00, 0x03, 0x03, 0x00,
+0x03, 0x00, 0x05, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x05, 0x00,
+0x01, 0x03, 0x01, 0x03, 0x05, 0x00, 0x01, 0xd2, 0x03, 0x09, 0x01, 0xda,
+0x01, 0x11, 0x04, 0x00, 0x01, 0x03, 0x06, 0x00, 0x01, 0xa1, 0x01, 0xe9,
+0x03, 0x09, 0x00, 0x03, 0xc9, 0xd8, 0x03, 0x00, 0x09, 0x00, 0x01, 0xa2,
+0x01, 0xa0, 0x04, 0x09, 0x00, 0x04, 0xb3, 0xa3, 0x00, 0x03, 0x07, 0x00,
+0x00, 0x05, 0xd2, 0xf9, 0x09, 0x09, 0xfd, 0x00, 0x05, 0x09, 0x01, 0xe9,
+0x01, 0xa2, 0x0a, 0x00, 0x00, 0x08, 0xb1, 0x92, 0x05, 0x07, 0x05, 0x07,
+0xbf, 0xb2, 0x09, 0x00, 0x00, 0x03, 0x4d, 0x94, 0x97, 0x00, 0x07, 0x07,
+0x01, 0x95, 0x01, 0x6b, 0x08, 0x00, 0x01, 0xc2, 0x03, 0x05, 0x00, 0x03,
+0x07, 0xbf, 0x7c, 0x00, 0x08, 0x00, 0x00, 0x0a, 0x71, 0x85, 0x07, 0x07,
+0x05, 0x07, 0x07, 0x05, 0x05, 0x75, 0x06, 0x00, 0x00, 0x08, 0x99, 0x92,
+0x07, 0x05, 0x07, 0x05, 0xbf, 0xb1, 0x09, 0x00, 0x01, 0x7c, 0x01, 0xc4,
+0x03, 0x07, 0x00, 0x06, 0x05, 0x79, 0x05, 0x07, 0x07, 0xb6, 0x05, 0x00,
+0x01, 0x85, 0x03, 0x07, 0x01, 0xa9, 0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00,
+0xd7, 0x05, 0x07, 0x07, 0x87, 0x00, 0x0e, 0x00, 0x01, 0x94, 0x03, 0x07,
+0x01, 0xbf, 0x01, 0x6b, 0x06, 0x00, 0x01, 0x96, 0x01, 0x79, 0x04, 0x07,
+0x01, 0x87, 0x01, 0x9a, 0x09, 0x00, 0x00, 0x03, 0xb2, 0x87, 0x07, 0x00,
+0x03, 0x05, 0x00, 0x04, 0x98, 0x75, 0x00, 0x26, 0x05, 0x00, 0x00, 0x06,
+0x84, 0x07, 0x05, 0x07, 0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00,
+0x7c, 0x98, 0x05, 0x07, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x00, 0x05,
+0x85, 0x07, 0x07, 0x05, 0x87, 0x00, 0x0b, 0x00, 0x00, 0x08, 0x75, 0x9b,
+0x07, 0x05, 0x05, 0x07, 0xa4, 0x96, 0x09, 0x00, 0x00, 0x03, 0x8e, 0x85,
+0x95, 0x00, 0x03, 0x07, 0x00, 0x04, 0x79, 0x84, 0x00, 0x26, 0x07, 0x00,
+0x00, 0x08, 0x75, 0x9b, 0x05, 0x05, 0x07, 0x07, 0xbd, 0x99, 0x0a, 0x00,
+0x01, 0x96, 0x01, 0xa4, 0x04, 0x07, 0x00, 0x05, 0x79, 0x05, 0x07, 0x97,
+0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x06, 0xe6, 0xc9,
+0x09, 0x09, 0xb3, 0xa3, 0x0c, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0,
+0x01, 0x03, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0x71,
+0x0a, 0x00, 0x01, 0xa3, 0x01, 0xfe, 0x03, 0x09, 0x01, 0xf9, 0x01, 0xa1,
+0x0d, 0x00, 0x01, 0xd8, 0x04, 0x09, 0x01, 0xe3, 0x09, 0x00, 0x01, 0xa3,
+0x01, 0xda, 0x08, 0x09, 0x01, 0xfe, 0x01, 0x26, 0x09, 0x00, 0x00, 0x03,
+0x6b, 0xa4, 0x05, 0x00, 0x03, 0x07, 0x01, 0xf5, 0x0d, 0x00, 0x01, 0x75,
+0x01, 0xbd, 0x06, 0x07, 0x01, 0x95, 0x01, 0x6b, 0x05, 0x00, 0x00, 0x09,
+0x26, 0x00, 0xb2, 0xb5, 0x05, 0x79, 0x05, 0xbd, 0x6b, 0x00, 0x0b, 0x00,
+0x01, 0x9f, 0x04, 0x07, 0x00, 0x03, 0x05, 0x05, 0x75, 0x00, 0x05, 0x00,
+0x00, 0x07, 0x7c, 0x9b, 0x07, 0x07, 0x05, 0x07, 0x85, 0x00, 0x0d, 0x00,
+0x01, 0xb6, 0x03, 0x07, 0x00, 0x05, 0x05, 0x05, 0x07, 0x07, 0xb6, 0x00,
+0x05, 0x00, 0x01, 0x85, 0x03, 0x07, 0x01, 0xa9, 0x0c, 0x00, 0x00, 0x07,
+0x4d, 0x00, 0xd7, 0x05, 0x07, 0x05, 0x87, 0x00, 0x0e, 0x00, 0x00, 0x06,
+0x94, 0x07, 0x07, 0x05, 0xbf, 0x6b, 0x05, 0x00, 0x00, 0x07, 0x8e, 0x98,
+0x07, 0x05, 0x07, 0x05, 0xd7, 0x00, 0x0d, 0x00, 0x01, 0xf6, 0x04, 0x07,
+0x00, 0x04, 0xbf, 0x71, 0x00, 0x26, 0x04, 0x00, 0x01, 0x84, 0x03, 0x07,
+0x01, 0xa4, 0x01, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x7c, 0x98,
+0x05, 0x07, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x01, 0x85, 0x03, 0x07,
+0x01, 0x87, 0x0b, 0x00, 0x01, 0x87, 0x04, 0x05, 0x01, 0xc4, 0x01, 0x6b,
+0x0c, 0x00, 0x00, 0x09, 0x84, 0x92, 0x05, 0x07, 0x07, 0x97, 0x9a, 0x00,
+0x03, 0x00, 0x05, 0x00, 0x00, 0x08, 0x4d, 0x87, 0x07, 0x07, 0x05, 0x07,
+0xc2, 0x4d, 0x0c, 0x00, 0x00, 0x04, 0x6b, 0xc4, 0x07, 0x05, 0x03, 0x07,
+0x00, 0x03, 0x05, 0x97, 0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00,
+0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00,
+0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6,
+0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x0a, 0x00, 0x01, 0xe3, 0x03, 0x09,
+0x01, 0xc9, 0x01, 0xa1, 0x0c, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0xe3,
+0x04, 0x09, 0x00, 0x03, 0xa1, 0x00, 0x11, 0x00, 0x07, 0x00, 0x01, 0xe8,
+0x08, 0x09, 0x01, 0xe8, 0x0a, 0x00, 0x00, 0x06, 0xf5, 0x07, 0x05, 0x05,
+0x07, 0xd7, 0x0f, 0x00, 0x00, 0x09, 0x8e, 0xa4, 0x07, 0x07, 0x05, 0x05,
+0x07, 0x95, 0x6b, 0x00, 0x05, 0x00, 0x00, 0x03, 0x4d, 0x00, 0xd7, 0x00,
+0x03, 0x07, 0x00, 0x04, 0xb5, 0xb1, 0x00, 0x26, 0x0b, 0x00, 0x00, 0x07,
+0xbf, 0x05, 0x07, 0x07, 0x05, 0x07, 0x75, 0x00, 0x05, 0x00, 0x00, 0x06,
+0xc2, 0x07, 0x05, 0x05, 0x07, 0xc2, 0x0f, 0x00, 0x00, 0x04, 0xb6, 0x05,
+0x05, 0x07, 0x03, 0x05, 0x01, 0xb6, 0x05, 0x00, 0x00, 0x05, 0x85, 0x05,
+0x07, 0x07, 0xa9, 0x00, 0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x05,
+0x07, 0x07, 0x87, 0x00, 0x0e, 0x00, 0x00, 0x06, 0x94, 0x07, 0x07, 0x05,
+0xbf, 0x6b, 0x05, 0x00, 0x00, 0x06, 0xc2, 0x07, 0x05, 0x07, 0x07, 0xf6,
+0x0f, 0x00, 0x01, 0xd7, 0x04, 0x07, 0x00, 0x03, 0xdb, 0x00, 0x4d, 0x00,
+0x04, 0x00, 0x00, 0x06, 0x84, 0x79, 0x07, 0x07, 0xa4, 0x7c, 0x0d, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0x7c, 0x9b, 0x07, 0x07, 0x92, 0x96, 0x00, 0x4d,
+0x07, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x05, 0x87, 0x00, 0x0a, 0x00,
+0x01, 0xc5, 0x01, 0x05, 0x03, 0x07, 0x01, 0xc4, 0x0f, 0x00, 0x01, 0x84,
+0x01, 0x95, 0x03, 0x05, 0x01, 0xa9, 0x07, 0x00, 0x01, 0x94, 0x04, 0x07,
+0x01, 0xc2, 0x10, 0x00, 0x01, 0x87, 0x05, 0x07, 0x01, 0x97, 0x01, 0x75,
+0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09,
+0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0,
+0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3,
+0x09, 0x00, 0x01, 0xd2, 0x01, 0xf9, 0x03, 0x09, 0x00, 0x04, 0xd8, 0x00,
+0x03, 0x03, 0x0b, 0x00, 0x00, 0x08, 0x03, 0x00, 0x00, 0xda, 0x09, 0xe9,
+0xfd, 0xa0, 0x07, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0xe3, 0x06, 0x09,
+0x01, 0xa0, 0x01, 0x03, 0x09, 0x00, 0x01, 0xad, 0x01, 0x97, 0x03, 0x07,
+0x00, 0x04, 0xc4, 0x00, 0x00, 0x03, 0x0e, 0x00, 0x00, 0x08, 0xb2, 0x92,
+0x07, 0x07, 0x05, 0x05, 0x95, 0x6b, 0x06, 0x00, 0x01, 0x26, 0x01, 0x87,
+0x03, 0x07, 0x01, 0xc4, 0x0e, 0x00, 0x00, 0x07, 0xb2, 0x07, 0x07, 0x05,
+0x07, 0x07, 0x75, 0x00, 0x04, 0x00, 0x00, 0x07, 0x75, 0x92, 0x05, 0x05,
+0x07, 0xbf, 0x71, 0x00, 0x10, 0x00, 0x00, 0x07, 0xc4, 0x05, 0x07, 0x05,
+0x05, 0x07, 0xb6, 0x00, 0x05, 0x00, 0x00, 0x05, 0x85, 0x05, 0x07, 0x07,
+0xa9, 0x00, 0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x07, 0x07, 0x05,
+0x87, 0x00, 0x0e, 0x00, 0x00, 0x06, 0x94, 0x07, 0x05, 0x05, 0xbf, 0x6b,
+0x04, 0x00, 0x00, 0x09, 0xb2, 0x92, 0x05, 0x05, 0x07, 0xa9, 0x00, 0x00,
+0x03, 0x00, 0x0b, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x87, 0x03, 0x07,
+0x01, 0x98, 0x01, 0xad, 0x05, 0x00, 0x00, 0x06, 0x84, 0x79, 0x07, 0x07,
+0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x7c, 0x9b, 0x07, 0x05,
+0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x00, 0x05, 0x85, 0x05, 0x07, 0x05,
+0x87, 0x00, 0x09, 0x00, 0x01, 0x4d, 0x01, 0xa4, 0x03, 0x07, 0x01, 0xa4,
+0x01, 0x8e, 0x10, 0x00, 0x00, 0x06, 0xf6, 0x07, 0x05, 0x07, 0x07, 0x99,
+0x05, 0x00, 0x00, 0x07, 0x71, 0x9b, 0x07, 0x05, 0x07, 0xbd, 0x6b, 0x00,
+0x10, 0x00, 0x01, 0x7c, 0x01, 0x9b, 0x04, 0x07, 0x01, 0x97, 0x01, 0x75,
+0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09,
+0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0,
+0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3,
+0x07, 0x00, 0x00, 0x03, 0x03, 0x00, 0xe3, 0x00, 0x03, 0x09, 0x00, 0x04,
+0xb3, 0x11, 0x00, 0x03, 0x0d, 0x00, 0x00, 0x03, 0x03, 0x00, 0xa3, 0x00,
+0x03, 0xe6, 0x01, 0xd2, 0x01, 0x26, 0x07, 0x00, 0x00, 0x0c, 0x03, 0x00,
+0x00, 0xb0, 0xb3, 0xc9, 0xc9, 0xb3, 0xe8, 0x03, 0x00, 0x03, 0x08, 0x00,
+0x00, 0x08, 0xf5, 0x07, 0x05, 0x05, 0x97, 0x9a, 0x00, 0x71, 0x10, 0x00,
+0x01, 0xf5, 0x03, 0x07, 0x00, 0x03, 0x05, 0x95, 0x6b, 0x00, 0x06, 0x00,
+0x00, 0x06, 0x9a, 0x9b, 0x07, 0x07, 0x79, 0x94, 0x0f, 0x00, 0x01, 0xbd,
+0x04, 0x07, 0x01, 0x75, 0x04, 0x00, 0x00, 0x06, 0x9f, 0x05, 0x05, 0x07,
+0x95, 0x99, 0x11, 0x00, 0x01, 0x9a, 0x01, 0x92, 0x03, 0x07, 0x01, 0x05,
+0x01, 0xb6, 0x05, 0x00, 0x00, 0x05, 0x85, 0x05, 0x07, 0x07, 0xa9, 0x00,
+0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x07, 0x07, 0x05, 0x87, 0x00,
+0x0e, 0x00, 0x00, 0x06, 0x94, 0x05, 0x05, 0x07, 0xbf, 0x6b, 0x04, 0x00,
+0x00, 0x08, 0xc2, 0x05, 0x07, 0x07, 0x98, 0x75, 0x00, 0x26, 0x0f, 0x00,
+0x00, 0x06, 0xb2, 0x79, 0x05, 0x07, 0x07, 0x94, 0x05, 0x00, 0x00, 0x06,
+0x84, 0x07, 0x07, 0x05, 0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00,
+0x7c, 0x9b, 0x07, 0x07, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x01, 0x85,
+0x03, 0x05, 0x01, 0x87, 0x09, 0x00, 0x00, 0x06, 0x84, 0x79, 0x05, 0x07,
+0x07, 0x84, 0x11, 0x00, 0x00, 0x06, 0x6b, 0x9b, 0x07, 0x07, 0x05, 0xc4,
+0x05, 0x00, 0x00, 0x06, 0xd6, 0x07, 0x05, 0x07, 0x79, 0x99, 0x12, 0x00,
+0x01, 0xc5, 0x01, 0x05, 0x03, 0x07, 0x01, 0x97, 0x01, 0x75, 0x25, 0x00,
+0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2,
+0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d,
+0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x06, 0x00,
+0x00, 0x04, 0x03, 0x00, 0x03, 0xb3, 0x03, 0x09, 0x00, 0x03, 0xe8, 0x00,
+0x11, 0x00, 0x0f, 0x00, 0x01, 0x03, 0x0e, 0x00, 0x00, 0x0a, 0x03, 0x00,
+0x00, 0x11, 0xa3, 0xa3, 0x26, 0x00, 0x00, 0x03, 0x06, 0x00, 0x00, 0x0a,
+0x03, 0x00, 0x71, 0xa4, 0x05, 0x79, 0x05, 0x9f, 0x00, 0x26, 0x11, 0x00,
+0x00, 0x07, 0x8e, 0x97, 0x05, 0x07, 0x05, 0x95, 0x6b, 0x00, 0x06, 0x00,
+0x00, 0x06, 0x99, 0x92, 0x07, 0x07, 0xb5, 0xb2, 0x0f, 0x00, 0x01, 0xf6,
+0x04, 0x07, 0x01, 0x75, 0x03, 0x00, 0x00, 0x09, 0x4d, 0x9b, 0x05, 0x07,
+0x05, 0xc2, 0x00, 0x00, 0x03, 0x00, 0x0d, 0x00, 0x00, 0x09, 0x03, 0x00,
+0x00, 0x9f, 0x05, 0x05, 0x07, 0x05, 0xb6, 0x00, 0x05, 0x00, 0x01, 0x85,
+0x03, 0x07, 0x01, 0xa9, 0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x05,
+0x07, 0x07, 0x87, 0x00, 0x0e, 0x00, 0x00, 0x11, 0x94, 0x07, 0x05, 0x07,
+0xbf, 0x6b, 0x00, 0x03, 0x00, 0x8e, 0x9b, 0x05, 0x07, 0x07, 0xf6, 0x00,
+0x4d, 0x00, 0x11, 0x00, 0x00, 0x06, 0xd6, 0xd7, 0xf6, 0xf5, 0x96, 0x03,
+0x04, 0x00, 0x01, 0x84, 0x03, 0x07, 0x01, 0xa4, 0x01, 0x7c, 0x0d, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0x7c, 0x9b, 0x07, 0x05, 0x92, 0x96, 0x00, 0x4d,
+0x07, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x05, 0x87, 0x00, 0x09, 0x00,
+0x00, 0x08, 0x87, 0x05, 0x05, 0x07, 0x87, 0x00, 0x00, 0x03, 0x10, 0x00,
+0x00, 0x06, 0x96, 0xa9, 0xc2, 0xa9, 0xd7, 0x71, 0x04, 0x00, 0x01, 0xbf,
+0x03, 0x07, 0x00, 0x04, 0xa9, 0x00, 0x00, 0x03, 0x0e, 0x00, 0x00, 0x04,
+0x03, 0x00, 0x71, 0xbf, 0x03, 0x07, 0x01, 0x97, 0x01, 0x75, 0x25, 0x00,
+0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2,
+0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d,
+0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x06, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0xe6, 0xf9, 0x09, 0x09, 0xfe, 0xa2, 0x00, 0x11,
+0x16, 0x03, 0x09, 0x00, 0x01, 0x03, 0x0e, 0x00, 0x00, 0x0a, 0x26, 0x00,
+0x99, 0xb5, 0x07, 0x05, 0xb5, 0x99, 0x00, 0x26, 0x12, 0x00, 0x00, 0x06,
+0xc2, 0x05, 0x07, 0x05, 0x95, 0x6b, 0x06, 0x00, 0x00, 0x06, 0x84, 0x07,
+0x05, 0x07, 0x98, 0x6b, 0x0f, 0x00, 0x01, 0x84, 0x03, 0x07, 0x01, 0x05,
+0x01, 0x75, 0x03, 0x00, 0x01, 0xb1, 0x01, 0x92, 0x03, 0x07, 0x00, 0x03,
+0x96, 0x00, 0x71, 0x00, 0x11, 0x00, 0x00, 0x06, 0xb1, 0x79, 0x05, 0x07,
+0x07, 0xb6, 0x05, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x07, 0xa9, 0x00,
+0x0c, 0x00, 0x00, 0x03, 0x4d, 0x00, 0xd7, 0x00, 0x03, 0x07, 0x01, 0x87,
+0x0e, 0x00, 0x00, 0x11, 0x94, 0x07, 0x05, 0x05, 0xbf, 0x6b, 0x00, 0x26,
+0x00, 0x84, 0x92, 0x05, 0x05, 0x97, 0xb2, 0x00, 0x71, 0x00, 0x0f, 0x26,
+0x01, 0x4d, 0x06, 0x00, 0x01, 0x26, 0x04, 0x00, 0x00, 0x06, 0x84, 0x07,
+0x05, 0x07, 0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x7c, 0x9b,
+0x05, 0x05, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x00, 0x05, 0x85, 0x07,
+0x05, 0x05, 0x87, 0x00, 0x08, 0x00, 0x00, 0x08, 0x8e, 0x98, 0x07, 0x07,
+0x05, 0x94, 0x00, 0x71, 0x0f, 0x26, 0x01, 0x4d, 0x01, 0x03, 0x05, 0x00,
+0x01, 0x26, 0x03, 0x00, 0x01, 0x8e, 0x01, 0x97, 0x03, 0x07, 0x00, 0x03,
+0xc5, 0x00, 0x71, 0x00, 0x10, 0x00, 0x00, 0x03, 0x4d, 0x00, 0xdb, 0x00,
+0x03, 0x07, 0x01, 0x97, 0x01, 0x75, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00,
+0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00,
+0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6,
+0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x06, 0x00, 0x00, 0x07, 0x11, 0x00,
+0xb0, 0xe9, 0x09, 0x09, 0xda, 0x00, 0x1a, 0x00, 0x01, 0x03, 0x16, 0x00,
+0x00, 0x0a, 0x4d, 0x00, 0xdb, 0x07, 0x07, 0x05, 0xa4, 0x71, 0x00, 0x03,
+0x12, 0x00, 0x00, 0x06, 0x84, 0x05, 0x07, 0x05, 0x95, 0x6b, 0x06, 0x00,
+0x01, 0xc5, 0x03, 0x07, 0x01, 0x98, 0x10, 0x00, 0x01, 0xb1, 0x03, 0x07,
+0x01, 0x05, 0x01, 0x75, 0x03, 0x00, 0x00, 0x08, 0xdb, 0x79, 0x07, 0x07,
+0xa4, 0x7c, 0x00, 0x4d, 0x11, 0x00, 0x00, 0x06, 0x8e, 0xbd, 0x05, 0x07,
+0x07, 0xb6, 0x05, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x07, 0xa9, 0x00,
+0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x07, 0x07, 0x05, 0x87, 0x00,
+0x0e, 0x00, 0x00, 0x0e, 0x94, 0x07, 0x07, 0x05, 0xbf, 0x6b, 0x00, 0x26,
+0x00, 0xf6, 0x07, 0x07, 0x05, 0xbf, 0x1a, 0x00, 0x01, 0x03, 0x03, 0x00,
+0x00, 0x06, 0x84, 0x79, 0x07, 0x05, 0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a,
+0x03, 0x00, 0x7c, 0x9b, 0x07, 0x07, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00,
+0x01, 0x85, 0x03, 0x07, 0x01, 0x87, 0x06, 0x00, 0x00, 0x08, 0x03, 0x00,
+0x99, 0xb5, 0x07, 0x07, 0x98, 0xad, 0x19, 0x00, 0x00, 0x0b, 0x03, 0x00,
+0x00, 0x96, 0x92, 0x07, 0x07, 0x98, 0xb2, 0x00, 0x4d, 0x00, 0x10, 0x00,
+0x00, 0x08, 0x4d, 0x00, 0x99, 0x92, 0x07, 0x07, 0x97, 0x75, 0x25, 0x00,
+0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2,
+0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d,
+0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x06, 0x00,
+0x00, 0x03, 0x26, 0x00, 0xd8, 0x00, 0x03, 0x09, 0x01, 0xf9, 0x18, 0xa0,
+0x01, 0xe3, 0x01, 0xa2, 0x17, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xf5, 0x07,
+0x07, 0x05, 0x87, 0x00, 0x15, 0x00, 0x00, 0x06, 0xb2, 0x95, 0x05, 0x07,
+0x95, 0x6b, 0x06, 0x00, 0x01, 0xc5, 0x03, 0x07, 0x01, 0x98, 0x10, 0x00,
+0x01, 0xb2, 0x04, 0x07, 0x01, 0x75, 0x03, 0x00, 0x00, 0x08, 0xf5, 0x07,
+0x07, 0x05, 0x87, 0x26, 0x00, 0x03, 0x12, 0x00, 0x00, 0x05, 0xc2, 0x07,
+0x05, 0x07, 0xb6, 0x00, 0x05, 0x00, 0x00, 0x05, 0x85, 0x05, 0x07, 0x07,
+0xa9, 0x00, 0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x05, 0x07, 0x07,
+0x87, 0x00, 0x0e, 0x00, 0x01, 0x94, 0x03, 0x07, 0x00, 0x0b, 0xbf, 0x6b,
+0x00, 0x4d, 0x00, 0xc2, 0x07, 0x79, 0x07, 0x98, 0xd7, 0x00, 0x16, 0x9f,
+0x00, 0x03, 0x85, 0x85, 0x99, 0x00, 0x04, 0x00, 0x00, 0x06, 0x84, 0x79,
+0x07, 0x07, 0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x7c, 0x9b,
+0x07, 0x07, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x00, 0x05, 0x85, 0x07,
+0x05, 0x05, 0x87, 0x00, 0x06, 0x00, 0x00, 0x09, 0x03, 0x00, 0xd6, 0x95,
+0x05, 0x07, 0xb5, 0xc2, 0xf5, 0x00, 0x15, 0x9f, 0x00, 0x03, 0x85, 0xc2,
+0xd6, 0x00, 0x03, 0x00, 0x00, 0x08, 0x94, 0x79, 0x07, 0x07, 0xbd, 0x8e,
+0x00, 0x26, 0x10, 0x00, 0x00, 0x08, 0x4d, 0x00, 0x75, 0x9b, 0x05, 0x05,
+0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9,
+0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09,
+0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda,
+0x01, 0xa3, 0x06, 0x00, 0x00, 0x03, 0x26, 0x00, 0xd8, 0x00, 0x1c, 0x09,
+0x01, 0xe9, 0x01, 0xd2, 0x17, 0x00, 0x00, 0x07, 0x4d, 0x00, 0x85, 0x07,
+0x07, 0x05, 0xc4, 0x00, 0x15, 0x00, 0x00, 0x06, 0xb2, 0xb5, 0x07, 0x07,
+0x95, 0x6b, 0x06, 0x00, 0x00, 0x05, 0x84, 0x07, 0x07, 0x05, 0x98, 0x00,
+0x10, 0x00, 0x01, 0x9a, 0x01, 0x95, 0x03, 0x07, 0x01, 0x75, 0x03, 0x00,
+0x01, 0xc2, 0x03, 0x07, 0x00, 0x04, 0xc4, 0x00, 0x00, 0x03, 0x10, 0x00,
+0x00, 0x07, 0x26, 0x00, 0xf5, 0x05, 0x05, 0x07, 0xb6, 0x00, 0x05, 0x00,
+0x00, 0x05, 0x85, 0x07, 0x07, 0x05, 0xa9, 0x00, 0x0c, 0x00, 0x00, 0x03,
+0x4d, 0x00, 0xd7, 0x00, 0x03, 0x07, 0x01, 0x87, 0x0e, 0x00, 0x00, 0x0c,
+0x94, 0x05, 0x05, 0x07, 0xbf, 0x6b, 0x00, 0x4d, 0x00, 0xa9, 0x07, 0x79,
+0x07, 0x07, 0x01, 0x05, 0x08, 0x07, 0x00, 0x05, 0x05, 0x07, 0x05, 0x07,
+0x07, 0x00, 0x03, 0x05, 0x03, 0x07, 0x01, 0xd7, 0x04, 0x00, 0x01, 0x84,
+0x03, 0x07, 0x01, 0xa4, 0x01, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00,
+0x7c, 0x9b, 0x07, 0x05, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x00, 0x05,
+0x85, 0x05, 0x05, 0x07, 0x87, 0x00, 0x06, 0x00, 0x00, 0x03, 0x03, 0x00,
+0xdb, 0x00, 0x04, 0x07, 0x00, 0x04, 0x05, 0x05, 0x07, 0x05, 0x09, 0x07,
+0x00, 0x05, 0x05, 0x07, 0x05, 0x07, 0x07, 0x00, 0x04, 0x05, 0x00, 0x04,
+0x07, 0x05, 0x05, 0xbf, 0x03, 0x00, 0x00, 0x08, 0xb6, 0x79, 0x05, 0x07,
+0x87, 0x71, 0x00, 0x03, 0x10, 0x00, 0x00, 0x08, 0x26, 0x00, 0x7c, 0xa4,
+0x07, 0x07, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08,
+0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1,
+0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09,
+0x01, 0xda, 0x01, 0xa3, 0x06, 0x00, 0x00, 0x03, 0x26, 0x00, 0xd8, 0x00,
+0x1a, 0x09, 0x00, 0x04, 0xe9, 0x09, 0xf9, 0xd2, 0x17, 0x00, 0x00, 0x07,
+0x4d, 0x00, 0x85, 0x07, 0x07, 0x05, 0xa9, 0x00, 0x15, 0x00, 0x00, 0x06,
+0x9a, 0x97, 0x07, 0x07, 0x95, 0x6b, 0x06, 0x00, 0x01, 0x84, 0x03, 0x07,
+0x01, 0x98, 0x10, 0x00, 0x00, 0x06, 0x9a, 0x92, 0x05, 0x05, 0x07, 0x75,
+0x03, 0x00, 0x00, 0x08, 0xc2, 0x07, 0x05, 0x05, 0xc4, 0x00, 0x00, 0x03,
+0x10, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x05, 0x07, 0x07, 0xb6, 0x00,
+0x05, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x07, 0xa9, 0x00, 0x0c, 0x00,
+0x00, 0x07, 0x4d, 0x00, 0xd7, 0x05, 0x07, 0x07, 0x87, 0x00, 0x0e, 0x00,
+0x00, 0x0c, 0x94, 0x05, 0x07, 0x07, 0xbf, 0x6b, 0x00, 0x4d, 0x00, 0xa9,
+0x07, 0x79, 0x04, 0x07, 0x01, 0x05, 0x12, 0x07, 0x00, 0x05, 0x05, 0x79,
+0x07, 0x07, 0xf6, 0x00, 0x04, 0x00, 0x00, 0x06, 0x84, 0x07, 0x07, 0x05,
+0xa4, 0x7c, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x7c, 0x98, 0x07, 0x05,
+0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x05,
+0x87, 0x00, 0x06, 0x00, 0x00, 0x05, 0x03, 0x00, 0xb6, 0x07, 0x05, 0x00,
+0x04, 0x07, 0x01, 0x05, 0x03, 0x07, 0x01, 0x05, 0x08, 0x07, 0x00, 0x04,
+0x05, 0x07, 0x07, 0x05, 0x03, 0x07, 0x00, 0x04, 0x79, 0x07, 0x07, 0x87,
+0x03, 0x00, 0x00, 0x08, 0xb6, 0x07, 0x05, 0x07, 0x87, 0x71, 0x00, 0x03,
+0x10, 0x00, 0x00, 0x08, 0x26, 0x00, 0x8e, 0xbd, 0x05, 0x07, 0x97, 0x75,
+0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09,
+0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0,
+0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3,
+0x06, 0x00, 0x00, 0x03, 0x11, 0x00, 0xe8, 0x00, 0x03, 0x09, 0x01, 0xc9,
+0x01, 0xb3, 0x12, 0xe2, 0x00, 0x07, 0xb3, 0xe2, 0xe9, 0x09, 0x09, 0xe2,
+0xa2, 0x00, 0x17, 0x00, 0x00, 0x07, 0x4d, 0x00, 0x85, 0x05, 0x07, 0x05,
+0x87, 0x00, 0x15, 0x00, 0x00, 0x06, 0xb2, 0x92, 0x07, 0x05, 0x95, 0x6b,
+0x06, 0x00, 0x00, 0x05, 0x84, 0x05, 0x05, 0x07, 0x98, 0x00, 0x10, 0x00,
+0x00, 0x06, 0x9a, 0x92, 0x05, 0x07, 0x07, 0x75, 0x03, 0x00, 0x01, 0xf5,
+0x03, 0x05, 0x00, 0x04, 0x87, 0x00, 0x00, 0x03, 0x12, 0x00, 0x00, 0x05,
+0x85, 0x07, 0x07, 0x05, 0xb6, 0x00, 0x05, 0x00, 0x00, 0x05, 0x85, 0x07,
+0x05, 0x07, 0xa9, 0x00, 0x0c, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xd7, 0x05,
+0x07, 0x07, 0x87, 0x00, 0x0e, 0x00, 0x00, 0x0d, 0x94, 0x07, 0x07, 0x05,
+0xbf, 0x6b, 0x00, 0x4d, 0x00, 0xc2, 0x07, 0x79, 0x07, 0x00, 0x17, 0x79,
+0x03, 0x07, 0x01, 0xdb, 0x04, 0x00, 0x01, 0x84, 0x03, 0x07, 0x01, 0xa4,
+0x01, 0x7c, 0x0f, 0x00, 0x00, 0x08, 0x7c, 0x9b, 0x07, 0x05, 0x92, 0x96,
+0x00, 0x4d, 0x07, 0x00, 0x01, 0x85, 0x03, 0x07, 0x01, 0x87, 0x06, 0x00,
+0x00, 0x07, 0x03, 0x00, 0xd6, 0x95, 0x05, 0x05, 0x07, 0x00, 0x16, 0x79,
+0x03, 0x07, 0x01, 0xc4, 0x03, 0x00, 0x00, 0x08, 0xdb, 0x79, 0x07, 0x05,
+0xbd, 0x8e, 0x00, 0x26, 0x10, 0x00, 0x00, 0x08, 0x26, 0x00, 0x75, 0xa4,
+0x07, 0x07, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08,
+0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1,
+0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09,
+0x01, 0xda, 0x01, 0xa3, 0x06, 0x00, 0x00, 0x07, 0x11, 0x00, 0xa1, 0xc9,
+0x09, 0x09, 0xb3, 0x00, 0x14, 0x00, 0x00, 0x06, 0xa3, 0xe9, 0x09, 0x09,
+0xda, 0xa3, 0x17, 0x00, 0x00, 0x07, 0x4d, 0x00, 0xb6, 0x05, 0x07, 0x07,
+0xbd, 0x00, 0x15, 0x00, 0x01, 0x96, 0x03, 0x07, 0x01, 0x95, 0x01, 0x6b,
+0x06, 0x00, 0x00, 0x05, 0x84, 0x05, 0x07, 0x07, 0x98, 0x00, 0x10, 0x00,
+0x01, 0x9a, 0x01, 0x92, 0x03, 0x07, 0x01, 0x75, 0x03, 0x00, 0x00, 0x08,
+0xdb, 0x79, 0x05, 0x05, 0xa4, 0x7c, 0x00, 0x26, 0x11, 0x00, 0x01, 0x6b,
+0x01, 0x87, 0x03, 0x07, 0x01, 0xb6, 0x05, 0x00, 0x01, 0x85, 0x03, 0x07,
+0x01, 0xa9, 0x0c, 0x00, 0x00, 0x03, 0x4d, 0x00, 0xd7, 0x00, 0x03, 0x07,
+0x01, 0x87, 0x0e, 0x00, 0x00, 0x0a, 0x94, 0x05, 0x07, 0x07, 0xbf, 0x6b,
+0x00, 0x26, 0x00, 0xd7, 0x03, 0x07, 0x01, 0x9b, 0x13, 0x94, 0x00, 0x03,
+0xc5, 0xb6, 0xb5, 0x00, 0x03, 0x07, 0x01, 0x96, 0x04, 0x00, 0x00, 0x06,
+0x84, 0x79, 0x07, 0x07, 0x9b, 0x75, 0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00,
+0x7c, 0x98, 0x07, 0x05, 0x92, 0x96, 0x00, 0x4d, 0x07, 0x00, 0x00, 0x05,
+0x85, 0x05, 0x07, 0x07, 0x87, 0x00, 0x06, 0x00, 0x00, 0x09, 0x03, 0x00,
+0x96, 0xb5, 0x07, 0x07, 0xb5, 0xf5, 0xd6, 0x00, 0x11, 0x94, 0x00, 0x07,
+0xd6, 0xdb, 0xa4, 0x05, 0x07, 0x05, 0xf5, 0x00, 0x03, 0x00, 0x00, 0x08,
+0x84, 0x92, 0x05, 0x07, 0x9b, 0x9a, 0x00, 0x4d, 0x10, 0x00, 0x00, 0x08,
+0x4d, 0x00, 0x99, 0xb5, 0x05, 0x05, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00,
+0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03,
+0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00,
+0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x06, 0x00, 0x00, 0x08,
+0x03, 0x00, 0xa2, 0xe2, 0x09, 0x09, 0xf9, 0xe6, 0x13, 0x00, 0x00, 0x05,
+0xb0, 0x09, 0x09, 0xfd, 0xe3, 0x00, 0x18, 0x00, 0x00, 0x0a, 0x26, 0x00,
+0x84, 0x92, 0x07, 0x05, 0x98, 0x9a, 0x00, 0x26, 0x12, 0x00, 0x00, 0x06,
+0xf5, 0x07, 0x07, 0x05, 0x95, 0x6b, 0x06, 0x00, 0x01, 0x84, 0x03, 0x07,
+0x01, 0x98, 0x10, 0x00, 0x01, 0x9a, 0x01, 0x95, 0x03, 0x07, 0x01, 0x75,
+0x03, 0x00, 0x00, 0x08, 0x99, 0x92, 0x05, 0x05, 0x92, 0x99, 0x00, 0x71,
+0x0f, 0x00, 0x00, 0x04, 0x03, 0x00, 0x75, 0x97, 0x03, 0x07, 0x01, 0xb6,
+0x05, 0x00, 0x01, 0x85, 0x03, 0x05, 0x01, 0xc4, 0x0c, 0x00, 0x00, 0x07,
+0x4d, 0x00, 0x9f, 0x07, 0x79, 0x07, 0x87, 0x00, 0x0e, 0x00, 0x00, 0x0f,
+0xb6, 0x05, 0x07, 0x07, 0x87, 0x6b, 0x00, 0x26, 0x00, 0xc5, 0x95, 0x07,
+0x07, 0x9b, 0x6b, 0x00, 0x13, 0x00, 0x00, 0x06, 0xad, 0x95, 0x07, 0x05,
+0x79, 0x75, 0x04, 0x00, 0x00, 0x06, 0x84, 0x79, 0x07, 0x07, 0x97, 0x9a,
+0x0d, 0x00, 0x00, 0x0a, 0x03, 0x00, 0xb1, 0x97, 0x07, 0x05, 0xb5, 0x99,
+0x00, 0x4d, 0x07, 0x00, 0x01, 0x85, 0x03, 0x05, 0x01, 0x87, 0x08, 0x00,
+0x00, 0x06, 0x7c, 0x98, 0x07, 0x07, 0x95, 0x99, 0x13, 0x00, 0x00, 0x06,
+0x4d, 0xa4, 0x05, 0x07, 0x05, 0x84, 0x03, 0x00, 0x00, 0x08, 0x7c, 0x97,
+0x05, 0x07, 0x07, 0x84, 0x00, 0x71, 0x10, 0x00, 0x00, 0x08, 0x71, 0x00,
+0x94, 0x05, 0x05, 0x07, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00,
+0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00,
+0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6,
+0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x09, 0x00, 0x01, 0xa0, 0x03, 0x09,
+0x00, 0x04, 0xe3, 0x00, 0x00, 0x03, 0x10, 0x00, 0x00, 0x05, 0xb3, 0x09,
+0x09, 0xfd, 0xa1, 0x00, 0x18, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x8e, 0x9b,
+0x05, 0x05, 0x07, 0xdb, 0x00, 0x4d, 0x11, 0x00, 0x00, 0x07, 0x6b, 0x9b,
+0x07, 0x07, 0x05, 0x95, 0x6b, 0x00, 0x06, 0x00, 0x00, 0x05, 0x84, 0x05,
+0x07, 0x07, 0x98, 0x00, 0x10, 0x00, 0x01, 0x9a, 0x01, 0x92, 0x03, 0x07,
+0x01, 0x75, 0x03, 0x00, 0x01, 0x71, 0x01, 0x98, 0x03, 0x07, 0x00, 0x03,
+0xd7, 0x00, 0x26, 0x00, 0x11, 0x00, 0x01, 0xd6, 0x04, 0x07, 0x01, 0xb6,
+0x05, 0x00, 0x00, 0x06, 0x85, 0x05, 0x05, 0x07, 0xbf, 0x26, 0x0b, 0x00,
+0x00, 0x0a, 0x26, 0x00, 0xa9, 0x07, 0x79, 0x07, 0xbd, 0x00, 0x00, 0x03,
+0x0b, 0x00, 0x01, 0x9f, 0x03, 0x05, 0x00, 0x07, 0xc4, 0x71, 0x00, 0x03,
+0x00, 0x7c, 0x98, 0x00, 0x03, 0x07, 0x00, 0x04, 0x94, 0x00, 0x4d, 0x03,
+0x0d, 0x00, 0x00, 0x09, 0x03, 0x00, 0x00, 0xd7, 0x07, 0x07, 0x05, 0xbd,
+0x6b, 0x00, 0x04, 0x00, 0x00, 0x08, 0x84, 0x79, 0x07, 0x07, 0x05, 0x99,
+0x00, 0x03, 0x0b, 0x00, 0x00, 0x0a, 0x26, 0x00, 0xc5, 0x95, 0x05, 0x07,
+0x9b, 0x9a, 0x00, 0x26, 0x07, 0x00, 0x00, 0x05, 0x85, 0x07, 0x05, 0x05,
+0x87, 0x00, 0x09, 0x00, 0x01, 0xbf, 0x03, 0x07, 0x00, 0x04, 0x85, 0x00,
+0x03, 0x03, 0x0d, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x99, 0x03, 0x07,
+0x01, 0x79, 0x01, 0x7c, 0x04, 0x00, 0x00, 0x05, 0xbd, 0x05, 0x07, 0x05,
+0x85, 0x00, 0x11, 0x00, 0x00, 0x09, 0x03, 0x00, 0x26, 0x87, 0x05, 0x07,
+0x07, 0x97, 0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08,
+0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1,
+0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09,
+0x01, 0xda, 0x01, 0xa3, 0x07, 0x00, 0x00, 0x0a, 0x03, 0x00, 0xb0, 0xe9,
+0x09, 0x09, 0xf9, 0xe6, 0x00, 0x11, 0x0f, 0x00, 0x01, 0xb0, 0x03, 0x09,
+0x01, 0xb3, 0x01, 0xa2, 0x1b, 0x00, 0x00, 0x08, 0xa9, 0x07, 0x05, 0x07,
+0xbd, 0x71, 0x00, 0x4d, 0x10, 0x00, 0x01, 0xd6, 0x03, 0x07, 0x00, 0x03,
+0x05, 0x95, 0x6b, 0x00, 0x06, 0x00, 0x01, 0x84, 0x03, 0x07, 0x01, 0x98,
+0x10, 0x00, 0x01, 0x9a, 0x01, 0x92, 0x03, 0x07, 0x01, 0x75, 0x04, 0x00,
+0x00, 0x08, 0xa9, 0x05, 0x07, 0x07, 0x98, 0x7c, 0x00, 0x03, 0x0d, 0x00,
+0x00, 0x04, 0x03, 0x00, 0x71, 0xa4, 0x04, 0x07, 0x01, 0xb6, 0x05, 0x00,
+0x00, 0x06, 0x85, 0x07, 0x05, 0x07, 0x98, 0x71, 0x0a, 0x00, 0x00, 0x0b,
+0x03, 0x00, 0x03, 0x87, 0x07, 0x79, 0x07, 0x9b, 0x7c, 0x00, 0x03, 0x00,
+0x0b, 0x00, 0x00, 0x05, 0x87, 0x07, 0x05, 0x07, 0x85, 0x00, 0x05, 0x00,
+0x01, 0xc4, 0x03, 0x07, 0x00, 0x04, 0xbf, 0x26, 0x00, 0x03, 0x0f, 0x00,
+0x01, 0x6b, 0x01, 0x98, 0x03, 0x05, 0x01, 0xf6, 0x05, 0x00, 0x01, 0x84,
+0x04, 0x07, 0x01, 0xdb, 0x0d, 0x00, 0x00, 0x0a, 0x26, 0x00, 0x85, 0x07,
+0x07, 0x05, 0xbd, 0x71, 0x00, 0x03, 0x07, 0x00, 0x01, 0x85, 0x03, 0x07,
+0x01, 0x87, 0x09, 0x00, 0x01, 0xdb, 0x03, 0x07, 0x00, 0x04, 0x98, 0x75,
+0x00, 0x03, 0x0d, 0x00, 0x00, 0x08, 0x03, 0x00, 0x00, 0xc4, 0x05, 0x07,
+0x07, 0xbf, 0x05, 0x00, 0x00, 0x08, 0xf6, 0x07, 0x05, 0x07, 0x98, 0xad,
+0x00, 0x03, 0x10, 0x00, 0x01, 0x96, 0x03, 0x07, 0x00, 0x03, 0x05, 0x97,
+0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9,
+0x09, 0xfd, 0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09,
+0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda,
+0x01, 0xa3, 0x0a, 0x00, 0x01, 0xb3, 0x03, 0x09, 0x00, 0x04, 0xda, 0x71,
+0x00, 0x03, 0x0a, 0x00, 0x00, 0x05, 0x03, 0x11, 0x00, 0xd2, 0xf9, 0x00,
+0x03, 0x09, 0x00, 0x03, 0xe8, 0x00, 0x26, 0x00, 0x1a, 0x00, 0x01, 0x99,
+0x01, 0x92, 0x03, 0x07, 0x00, 0x04, 0xf6, 0x00, 0x26, 0x03, 0x0c, 0x00,
+0x00, 0x04, 0x26, 0x00, 0x7c, 0x97, 0x04, 0x07, 0x01, 0x95, 0x01, 0x6b,
+0x06, 0x00, 0x00, 0x05, 0x84, 0x07, 0x07, 0x05, 0x98, 0x00, 0x10, 0x00,
+0x00, 0x06, 0x9a, 0x92, 0x05, 0x07, 0x07, 0x75, 0x04, 0x00, 0x00, 0x09,
+0xb2, 0x95, 0x07, 0x05, 0x05, 0xc2, 0x00, 0x00, 0x03, 0x00, 0x0b, 0x00,
+0x00, 0x06, 0x03, 0x00, 0x00, 0xf6, 0x07, 0x07, 0x03, 0x05, 0x01, 0xb6,
+0x05, 0x00, 0x01, 0x85, 0x04, 0x07, 0x01, 0x99, 0x0a, 0x00, 0x00, 0x04,
+0x4d, 0x00, 0xb2, 0x97, 0x03, 0x07, 0x00, 0x04, 0x79, 0xc5, 0x00, 0x4d,
+0x0a, 0x00, 0x01, 0x6b, 0x01, 0x97, 0x03, 0x07, 0x01, 0xd6, 0x05, 0x00,
+0x01, 0x99, 0x01, 0x92, 0x03, 0x05, 0x00, 0x04, 0xdb, 0x00, 0x00, 0x03,
+0x0b, 0x00, 0x00, 0x0b, 0x03, 0x00, 0x00, 0x9f, 0x05, 0x07, 0x05, 0x97,
+0x75, 0x00, 0x03, 0x00, 0x03, 0x00, 0x01, 0x84, 0x03, 0x07, 0x00, 0x05,
+0x05, 0xbd, 0x6b, 0x00, 0x03, 0x00, 0x09, 0x00, 0x00, 0x04, 0x4d, 0x00,
+0x8e, 0xa4, 0x03, 0x07, 0x00, 0x03, 0xc2, 0x00, 0x03, 0x00, 0x08, 0x00,
+0x00, 0x05, 0x85, 0x05, 0x07, 0x05, 0x87, 0x00, 0x09, 0x00, 0x01, 0x6b,
+0x01, 0x98, 0x03, 0x07, 0x00, 0x04, 0xa9, 0x00, 0x00, 0x03, 0x0e, 0x00,
+0x00, 0x06, 0x96, 0x07, 0x05, 0x07, 0x07, 0x96, 0x05, 0x00, 0x01, 0x8e,
+0x01, 0xb5, 0x03, 0x07, 0x00, 0x04, 0xa9, 0x00, 0x00, 0x03, 0x0c, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0x6b, 0xa4, 0x05, 0x07, 0x05, 0x05, 0x97, 0x75,
+0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09,
+0xb3, 0xa2, 0x00, 0x03, 0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0,
+0x01, 0x4d, 0x0b, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3,
+0x0a, 0x00, 0x01, 0xa1, 0x04, 0x09, 0x00, 0x05, 0xa0, 0x26, 0x00, 0x03,
+0x03, 0x00, 0x07, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0xa2, 0xb3, 0x00,
+0x03, 0x09, 0x00, 0x04, 0xb3, 0x71, 0x00, 0x03, 0x1b, 0x00, 0x01, 0xc4,
+0x03, 0x07, 0x00, 0x05, 0x92, 0x96, 0x00, 0x00, 0x03, 0x00, 0x0a, 0x00,
+0x00, 0x04, 0x4d, 0x00, 0x00, 0x87, 0x04, 0x07, 0x00, 0x03, 0x05, 0x95,
+0x6b, 0x00, 0x06, 0x00, 0x00, 0x05, 0x84, 0x05, 0x07, 0x07, 0x98, 0x00,
+0x10, 0x00, 0x00, 0x06, 0x9a, 0x95, 0x07, 0x05, 0x07, 0x75, 0x05, 0x00,
+0x00, 0x09, 0xc4, 0x07, 0x05, 0x07, 0x07, 0xd6, 0x00, 0x00, 0x03, 0x00,
+0x09, 0x00, 0x00, 0x0b, 0x03, 0x00, 0x00, 0x99, 0x95, 0x07, 0x05, 0x05,
+0x07, 0x07, 0xb6, 0x00, 0x05, 0x00, 0x01, 0x85, 0x04, 0x07, 0x01, 0xa9,
+0x0a, 0x00, 0x00, 0x0c, 0x26, 0x00, 0xf6, 0x05, 0x05, 0x07, 0x79, 0x07,
+0xc4, 0x00, 0x00, 0x03, 0x09, 0x00, 0x00, 0x06, 0xdb, 0x05, 0x07, 0x07,
+0xb5, 0xb1, 0x06, 0x00, 0x01, 0xc4, 0x03, 0x05, 0x00, 0x05, 0xb5, 0x99,
+0x00, 0x00, 0x03, 0x00, 0x09, 0x00, 0x00, 0x0b, 0x03, 0x00, 0x00, 0x84,
+0x79, 0x05, 0x05, 0x07, 0xd7, 0x00, 0x03, 0x00, 0x04, 0x00, 0x01, 0x84,
+0x01, 0x79, 0x03, 0x07, 0x01, 0x05, 0x01, 0xc5, 0x0a, 0x00, 0x00, 0x0b,
+0x03, 0x26, 0x00, 0xb6, 0x07, 0x07, 0x05, 0x95, 0x84, 0x00, 0x03, 0x00,
+0x08, 0x00, 0x00, 0x05, 0x85, 0x05, 0x05, 0x07, 0x87, 0x00, 0x0a, 0x00,
+0x01, 0xdb, 0x04, 0x07, 0x00, 0x04, 0xdb, 0x00, 0x00, 0x03, 0x0a, 0x00,
+0x00, 0x04, 0x03, 0x00, 0x75, 0x98, 0x03, 0x07, 0x00, 0x04, 0x87, 0x4d,
+0x00, 0x03, 0x04, 0x00, 0x01, 0x9f, 0x03, 0x07, 0x00, 0x05, 0x05, 0x94,
+0x00, 0x00, 0x03, 0x00, 0x0a, 0x00, 0x00, 0x0b, 0x26, 0x00, 0x00, 0xa9,
+0x07, 0x07, 0x05, 0x07, 0x07, 0x97, 0x75, 0x00, 0x25, 0x00, 0x00, 0x00,
+0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03,
+0x0a, 0x00, 0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x0b, 0x00,
+0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x01, 0xa3, 0x0b, 0x00, 0x01, 0xa0,
+0x04, 0x09, 0x01, 0xda, 0x01, 0xa2, 0x0b, 0x00, 0x01, 0xa1, 0x01, 0xe2,
+0x03, 0x09, 0x00, 0x04, 0xe9, 0xa1, 0x00, 0x03, 0x1c, 0x00, 0x00, 0x07,
+0x9a, 0x92, 0x05, 0x05, 0x07, 0xb5, 0x96, 0x00, 0x0d, 0x00, 0x00, 0x0a,
+0x71, 0xa9, 0x07, 0x07, 0x05, 0x07, 0x07, 0x05, 0x95, 0x6b, 0x06, 0x00,
+0x00, 0x05, 0x84, 0x07, 0x05, 0x07, 0x98, 0x00, 0x10, 0x00, 0x00, 0x06,
+0x9a, 0x95, 0x07, 0x07, 0x05, 0x75, 0x05, 0x00, 0x01, 0x9a, 0x01, 0xb5,
+0x03, 0x07, 0x01, 0x79, 0x01, 0x84, 0x0d, 0x00, 0x00, 0x09, 0x99, 0x97,
+0x05, 0x07, 0x07, 0x05, 0x07, 0x07, 0xb6, 0x00, 0x05, 0x00, 0x00, 0x07,
+0x85, 0x07, 0x05, 0x07, 0x07, 0x95, 0x99, 0x00, 0x0a, 0x00, 0x00, 0x04,
+0x9a, 0x97, 0x05, 0x05, 0x03, 0x07, 0x01, 0x79, 0x01, 0x84, 0x08, 0x00,
+0x00, 0x09, 0x03, 0x00, 0x7c, 0x98, 0x05, 0x79, 0x07, 0x87, 0x03, 0x00,
+0x06, 0x00, 0x01, 0x75, 0x01, 0xb5, 0x03, 0x07, 0x01, 0x97, 0x01, 0xb1,
+0x0d, 0x00, 0x01, 0x84, 0x01, 0x92, 0x03, 0x07, 0x00, 0x04, 0xa4, 0x6b,
+0x00, 0x4d, 0x04, 0x00, 0x01, 0x84, 0x01, 0x79, 0x03, 0x07, 0x00, 0x03,
+0x05, 0x98, 0x75, 0x00, 0x0b, 0x00, 0x00, 0x07, 0x99, 0xb5, 0x07, 0x07,
+0x05, 0xa4, 0x4d, 0x00, 0x0a, 0x00, 0x01, 0x85, 0x03, 0x07, 0x01, 0x87,
+0x0a, 0x00, 0x01, 0x26, 0x01, 0xbd, 0x03, 0x05, 0x01, 0x79, 0x01, 0xd6,
+0x0d, 0x00, 0x00, 0x07, 0x75, 0xa4, 0x05, 0x07, 0x07, 0x92, 0xb1, 0x00,
+0x07, 0x00, 0x00, 0x07, 0x8e, 0x9b, 0x07, 0x05, 0x05, 0x79, 0xc5, 0x00,
+0x0e, 0x00, 0x01, 0xf5, 0x03, 0x07, 0x00, 0x05, 0x05, 0x05, 0x07, 0x97,
+0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9,
+0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x04, 0x00, 0x01, 0x03, 0x05, 0x00,
+0x01, 0xa1, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d, 0x05, 0x00, 0x01, 0x03,
+0x05, 0x00, 0x01, 0xd2, 0x03, 0x09, 0x01, 0xda, 0x01, 0x03, 0x04, 0x00,
+0x01, 0x03, 0x06, 0x00, 0x01, 0x4d, 0x01, 0xda, 0x04, 0x09, 0x00, 0x03,
+0xfe, 0xe8, 0x4d, 0x00, 0x07, 0x00, 0x00, 0x03, 0xd2, 0xe3, 0xe9, 0x00,
+0x04, 0x09, 0x01, 0xe8, 0x20, 0x00, 0x00, 0x07, 0x94, 0x07, 0x07, 0x05,
+0x07, 0x92, 0xb6, 0x00, 0x0b, 0x00, 0x00, 0x0b, 0xb2, 0xbd, 0x05, 0x07,
+0x07, 0x05, 0x05, 0x07, 0x05, 0x95, 0x6b, 0x00, 0x06, 0x00, 0x00, 0x05,
+0x84, 0x07, 0x05, 0x07, 0x98, 0x00, 0x10, 0x00, 0x00, 0x06, 0x9a, 0x92,
+0x07, 0x07, 0x05, 0x75, 0x06, 0x00, 0x00, 0x08, 0xd6, 0x05, 0x07, 0x07,
+0x05, 0x95, 0xf6, 0x4d, 0x0a, 0x00, 0x00, 0x04, 0xdb, 0xb5, 0x07, 0x07,
+0x03, 0x05, 0x00, 0x03, 0x07, 0x07, 0xb6, 0x00, 0x05, 0x00, 0x00, 0x08,
+0x85, 0x07, 0x05, 0x07, 0x07, 0x05, 0x98, 0xb2, 0x08, 0x00, 0x00, 0x04,
+0x7c, 0xbd, 0x07, 0x07, 0x03, 0x05, 0x00, 0x04, 0x07, 0x07, 0x97, 0x99,
+0x08, 0x00, 0x00, 0x09, 0x8e, 0xbd, 0x05, 0x07, 0x07, 0x79, 0x84, 0x00,
+0x4d, 0x00, 0x06, 0x00, 0x01, 0x94, 0x04, 0x07, 0x01, 0x97, 0x01, 0x94,
+0x0a, 0x00, 0x00, 0x0a, 0x71, 0xd7, 0x95, 0x05, 0x07, 0x07, 0x92, 0x99,
+0x00, 0x26, 0x05, 0x00, 0x00, 0x09, 0x84, 0x79, 0x07, 0x07, 0x05, 0x07,
+0x07, 0xa4, 0xb2, 0x00, 0x09, 0x00, 0x01, 0x96, 0x01, 0x97, 0x03, 0x07,
+0x01, 0x05, 0x01, 0xd6, 0x0b, 0x00, 0x00, 0x05, 0xf5, 0x05, 0x05, 0x07,
+0x87, 0x00, 0x07, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x08, 0xb2, 0xb5,
+0x07, 0x05, 0x07, 0x79, 0x9f, 0x6b, 0x0a, 0x00, 0x01, 0xc5, 0x01, 0x98,
+0x04, 0x07, 0x01, 0xb6, 0x09, 0x00, 0x00, 0x08, 0x96, 0x95, 0x07, 0x05,
+0x07, 0x79, 0x85, 0x8e, 0x0a, 0x00, 0x00, 0x0b, 0x75, 0x87, 0x07, 0x07,
+0x05, 0x07, 0x07, 0x05, 0x05, 0x97, 0x75, 0x00, 0x25, 0x00, 0x00, 0x00,
+0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03,
+0x05, 0x00, 0x01, 0x26, 0x01, 0xe6, 0x03, 0xa1, 0x01, 0xd8, 0x03, 0x09,
+0x01, 0xa0, 0x01, 0x4d, 0x06, 0x00, 0x00, 0x06, 0x4d, 0xa1, 0xe8, 0xe8,
+0xb0, 0xe3, 0x03, 0x09, 0x00, 0x08, 0xe2, 0xe8, 0xb0, 0xe8, 0xe8, 0xd2,
+0x00, 0x03, 0x06, 0x00, 0x01, 0xa2, 0x01, 0xb3, 0x05, 0x09, 0x00, 0x09,
+0xe2, 0xa0, 0xe8, 0xa1, 0xa1, 0xb0, 0xd8, 0xda, 0xf9, 0x00, 0x05, 0x09,
+0x01, 0xd8, 0x1f, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x85, 0x05, 0x07,
+0x05, 0x07, 0x07, 0xbd, 0xdb, 0x7c, 0x06, 0x00, 0x00, 0x03, 0xb2, 0xc2,
+0xb5, 0x00, 0x03, 0x07, 0x00, 0x07, 0x95, 0xbd, 0x07, 0x07, 0x05, 0x95,
+0x6b, 0x00, 0x06, 0x00, 0x00, 0x05, 0x84, 0x05, 0x07, 0x07, 0x98, 0x00,
+0x10, 0x00, 0x00, 0x06, 0x9a, 0x92, 0x07, 0x05, 0x05, 0x75, 0x04, 0x00,
+0x00, 0x05, 0x03, 0x00, 0x00, 0xd7, 0x05, 0x00, 0x04, 0x07, 0x00, 0x03,
+0xbd, 0x94, 0x8e, 0x00, 0x05, 0x00, 0x00, 0x0d, 0x71, 0xd6, 0xbf, 0x05,
+0x05, 0x07, 0x07, 0x9b, 0xbd, 0x07, 0x07, 0x05, 0xb6, 0x00, 0x05, 0x00,
+0x01, 0x85, 0x05, 0x07, 0x00, 0x04, 0x05, 0xb5, 0xb6, 0x6b, 0x04, 0x00,
+0x00, 0x0f, 0x71, 0xd6, 0x98, 0x05, 0x07, 0x07, 0x05, 0xa9, 0x92, 0x05,
+0x07, 0x07, 0x92, 0xf6, 0x6b, 0x00, 0x04, 0x00, 0x00, 0x0b, 0x71, 0xd6,
+0x9b, 0x05, 0x05, 0x07, 0x07, 0xa9, 0x00, 0x00, 0x03, 0x00, 0x04, 0x00,
+0x00, 0x04, 0x03, 0x00, 0x00, 0xf5, 0x05, 0x07, 0x00, 0x03, 0xbf, 0xd6,
+0x6b, 0x00, 0x05, 0x00, 0x00, 0x03, 0x8e, 0xdb, 0xa4, 0x00, 0x04, 0x07,
+0x01, 0x79, 0x01, 0xd6, 0x08, 0x00, 0x00, 0x03, 0x84, 0x79, 0x05, 0x00,
+0x05, 0x07, 0x00, 0x03, 0xb5, 0x85, 0x75, 0x00, 0x05, 0x00, 0x00, 0x03,
+0x9a, 0xc2, 0x92, 0x00, 0x03, 0x07, 0x01, 0x05, 0x01, 0x87, 0x06, 0x00,
+0x01, 0x9a, 0x01, 0x94, 0x04, 0xd6, 0x01, 0xbf, 0x03, 0x07, 0x00, 0x03,
+0xa4, 0xd6, 0xc5, 0x00, 0x04, 0xd6, 0x01, 0xb2, 0x05, 0x00, 0x00, 0x09,
+0x84, 0x92, 0x07, 0x05, 0x07, 0x07, 0xa4, 0xb6, 0x7c, 0x00, 0x05, 0x00,
+0x00, 0x05, 0x26, 0x84, 0x87, 0x79, 0x05, 0x00, 0x03, 0x07, 0x00, 0x04,
+0xc2, 0x00, 0x00, 0x03, 0x05, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x94,
+0x05, 0x07, 0x00, 0x03, 0x9b, 0xf5, 0x9a, 0x00, 0x06, 0x00, 0x00, 0x03,
+0xb2, 0x85, 0x97, 0x00, 0x03, 0x07, 0x00, 0x07, 0x05, 0x9b, 0x97, 0x07,
+0x05, 0x97, 0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08,
+0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x05, 0x00, 0x00, 0x03,
+0xa3, 0xda, 0x09, 0x00, 0x03, 0xe9, 0x03, 0x09, 0x01, 0xa0, 0x01, 0x4d,
+0x06, 0x00, 0x00, 0x03, 0xa2, 0xb3, 0x09, 0x00, 0x03, 0xe9, 0x00, 0x04,
+0x09, 0xfd, 0x09, 0x09, 0x03, 0xe9, 0x00, 0x04, 0x09, 0xd8, 0x00, 0x26,
+0x05, 0x00, 0x00, 0x04, 0x03, 0x00, 0xa3, 0xa0, 0x06, 0x09, 0x00, 0x04,
+0xe9, 0xc9, 0xc9, 0xe9, 0x06, 0x09, 0x00, 0x05, 0xc9, 0xe8, 0x00, 0x00,
+0x03, 0x00, 0x1e, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x9f, 0x07, 0x05,
+0x04, 0x07, 0x00, 0x08, 0xb5, 0xbd, 0xa9, 0x85, 0x85, 0xc4, 0xa4, 0xb5,
+0x04, 0x07, 0x00, 0x08, 0x05, 0xd7, 0x99, 0x07, 0x07, 0x05, 0x95, 0x6b,
+0x06, 0x00, 0x01, 0x84, 0x03, 0x07, 0x01, 0x98, 0x10, 0x00, 0x01, 0x9a,
+0x01, 0x92, 0x03, 0x07, 0x01, 0x75, 0x05, 0x00, 0x00, 0x05, 0x26, 0x00,
+0x00, 0xb6, 0x95, 0x00, 0x03, 0x07, 0x00, 0x0a, 0x05, 0x07, 0x97, 0xbf,
+0xc2, 0xf5, 0xc2, 0x87, 0x98, 0x79, 0x03, 0x07, 0x00, 0x08, 0x05, 0x9b,
+0xb1, 0xa9, 0x07, 0x07, 0x05, 0xb6, 0x05, 0x00, 0x01, 0x85, 0x05, 0x07,
+0x00, 0x09, 0x05, 0x07, 0x05, 0x97, 0xbf, 0xc2, 0xc2, 0x87, 0x98, 0x00,
+0x05, 0x07, 0x00, 0x03, 0xa9, 0x00, 0xb6, 0x00, 0x05, 0x07, 0x00, 0x0f,
+0x97, 0xbf, 0xc2, 0xc2, 0x87, 0x98, 0x79, 0x07, 0x05, 0x07, 0x07, 0xbd,
+0x8e, 0x00, 0x03, 0x00, 0x06, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0xf6,
+0x79, 0x00, 0x03, 0x07, 0x00, 0x09, 0x05, 0x79, 0x97, 0xbf, 0xc2, 0xc2,
+0xa9, 0xbd, 0x97, 0x00, 0x05, 0x07, 0x01, 0x95, 0x01, 0xd6, 0x09, 0x00,
+0x00, 0x06, 0x84, 0x79, 0x07, 0x07, 0x98, 0xb5, 0x04, 0x07, 0x00, 0x0e,
+0xb5, 0xa4, 0xa9, 0xc2, 0xc4, 0xa4, 0xb5, 0x07, 0x05, 0x79, 0x07, 0x05,
+0xbd, 0x8e, 0x06, 0x00, 0x00, 0x03, 0xf6, 0x07, 0x79, 0x00, 0x03, 0x95,
+0x01, 0x79, 0x04, 0x07, 0x04, 0x95, 0x00, 0x03, 0x79, 0x79, 0xf5, 0x00,
+0x03, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0x96, 0x97, 0x00, 0x03, 0x07,
+0x00, 0x13, 0x05, 0x05, 0xb5, 0xbd, 0xa9, 0x85, 0xc2, 0x87, 0x98, 0x95,
+0x07, 0x07, 0x05, 0x05, 0x07, 0x85, 0x00, 0x00, 0x26, 0x00, 0x07, 0x00,
+0x00, 0x05, 0x26, 0x00, 0x00, 0xd6, 0x92, 0x00, 0x05, 0x07, 0x00, 0x08,
+0xb5, 0xa4, 0xc4, 0xc2, 0xc2, 0xc4, 0xa4, 0x92, 0x03, 0x05, 0x00, 0x09,
+0x07, 0x07, 0xa9, 0x96, 0x98, 0x07, 0x07, 0x97, 0x75, 0x00, 0x25, 0x00,
+0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0xfd, 0xb3, 0xa2,
+0x00, 0x03, 0x05, 0x00, 0x01, 0xa3, 0x01, 0xe2, 0x05, 0x09, 0x00, 0x04,
+0xe9, 0x09, 0xa0, 0x4d, 0x06, 0x00, 0x01, 0xa2, 0x01, 0xe2, 0x04, 0x09,
+0x01, 0xfd, 0x07, 0x09, 0x00, 0x03, 0xd8, 0x00, 0x26, 0x00, 0x09, 0x00,
+0x01, 0xb0, 0x01, 0xe2, 0x0c, 0x09, 0x00, 0x06, 0xc9, 0xa0, 0xd2, 0x00,
+0x00, 0x03, 0x20, 0x00, 0x00, 0x0b, 0x03, 0x00, 0x00, 0xc5, 0x98, 0x07,
+0x07, 0x05, 0x05, 0x07, 0x07, 0x00, 0x03, 0x05, 0x06, 0x07, 0x00, 0x09,
+0x95, 0xd7, 0x00, 0xb2, 0x07, 0x07, 0x05, 0x92, 0x6b, 0x00, 0x06, 0x00,
+0x00, 0x05, 0x84, 0x07, 0x07, 0x05, 0x9b, 0x00, 0x10, 0x00, 0x00, 0x06,
+0x9a, 0x92, 0x05, 0x05, 0x79, 0x75, 0x06, 0x00, 0x00, 0x05, 0x03, 0x00,
+0x00, 0x96, 0xa4, 0x00, 0x03, 0x07, 0x01, 0x05, 0x03, 0x07, 0x00, 0x05,
+0x05, 0x07, 0x07, 0x05, 0x05, 0x00, 0x03, 0x07, 0x00, 0x08, 0xbf, 0x8e,
+0x00, 0xc4, 0x05, 0x07, 0x07, 0xb6, 0x05, 0x00, 0x01, 0x9f, 0x03, 0x07,
+0x01, 0xc4, 0x01, 0xbd, 0x03, 0x07, 0x01, 0x05, 0x01, 0x05, 0x05, 0x07,
+0x00, 0x0b, 0x05, 0x05, 0x07, 0xa9, 0x71, 0x00, 0x00, 0xf6, 0x79, 0x07,
+0x05, 0x00, 0x03, 0x07, 0x00, 0x04, 0x05, 0x07, 0x07, 0x05, 0x04, 0x07,
+0x01, 0xbf, 0x01, 0x8e, 0x0a, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x96,
+0x9b, 0x05, 0x08, 0x07, 0x01, 0x05, 0x04, 0x07, 0x00, 0x06, 0x05, 0xa4,
+0x99, 0x00, 0x00, 0x03, 0x07, 0x00, 0x00, 0x09, 0x84, 0x79, 0x07, 0x07,
+0xbf, 0x96, 0xa4, 0x07, 0x05, 0x00, 0x03, 0x07, 0x00, 0x04, 0x05, 0x07,
+0x07, 0x05, 0x03, 0x07, 0x00, 0x07, 0x05, 0x07, 0xc4, 0x6b, 0x00, 0x00,
+0x03, 0x00, 0x04, 0x00, 0x01, 0xf5, 0x03, 0x07, 0x01, 0x05, 0x05, 0x07,
+0x00, 0x04, 0x05, 0x07, 0x07, 0x05, 0x03, 0x07, 0x01, 0x9f, 0x04, 0x00,
+0x00, 0x05, 0x03, 0x00, 0x00, 0x75, 0x87, 0x00, 0x06, 0x07, 0x00, 0x0e,
+0x05, 0x07, 0x05, 0x05, 0x07, 0x07, 0x05, 0x05, 0x07, 0x97, 0x94, 0x00,
+0x00, 0x03, 0x09, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0xb1, 0xbd, 0x00,
+0x0a, 0x07, 0x01, 0x05, 0x04, 0x07, 0x00, 0x09, 0x79, 0x9f, 0x00, 0x9a,
+0xb5, 0x07, 0x07, 0x97, 0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00,
+0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x05, 0x00,
+0x01, 0xa3, 0x01, 0xfe, 0x07, 0x09, 0x01, 0xda, 0x01, 0x4d, 0x06, 0x00,
+0x01, 0xa2, 0x01, 0xf9, 0x0c, 0x09, 0x00, 0x03, 0xd8, 0x00, 0x26, 0x00,
+0x0a, 0x00, 0x00, 0x04, 0x4d, 0xd8, 0xb3, 0xf9, 0x06, 0x09, 0x00, 0x04,
+0xc9, 0xe2, 0xa0, 0xe6, 0x29, 0x00, 0x00, 0x03, 0x7c, 0x85, 0x97, 0x00,
+0x07, 0x07, 0x01, 0x05, 0x03, 0x07, 0x00, 0x07, 0x95, 0xbf, 0x99, 0x00,
+0x00, 0x96, 0x05, 0x00, 0x03, 0x07, 0x01, 0x6b, 0x06, 0x00, 0x00, 0x05,
+0xd6, 0x05, 0x05, 0x07, 0x92, 0x00, 0x10, 0x00, 0x01, 0xb2, 0x01, 0x05,
+0x03, 0x07, 0x01, 0x75, 0x07, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x6b,
+0x9f, 0x98, 0x05, 0x07, 0x00, 0x10, 0x05, 0x07, 0x05, 0x05, 0x07, 0x07,
+0x98, 0xd7, 0x71, 0x00, 0x71, 0xbf, 0x05, 0x07, 0x07, 0xd7, 0x05, 0x00,
+0x00, 0x08, 0xa9, 0x07, 0x07, 0x05, 0xa9, 0x6b, 0xc2, 0x95, 0x04, 0x07,
+0x01, 0x05, 0x03, 0x07, 0x00, 0x0f, 0x05, 0x9b, 0x94, 0x00, 0x00, 0x03,
+0x00, 0x00, 0x96, 0xbd, 0x05, 0x07, 0x07, 0x05, 0x05, 0x00, 0x04, 0x07,
+0x00, 0x04, 0x05, 0x97, 0xd7, 0x71, 0x0c, 0x00, 0x00, 0x06, 0x03, 0x00,
+0x00, 0x6b, 0x85, 0x97, 0x03, 0x07, 0x07, 0x05, 0x00, 0x07, 0x07, 0x9b,
+0xf6, 0x71, 0x00, 0x00, 0x03, 0x00, 0x08, 0x00, 0x01, 0xc5, 0x03, 0x07,
+0x00, 0x05, 0x98, 0x71, 0x6b, 0xc4, 0x79, 0x00, 0x03, 0x07, 0x03, 0x05,
+0x00, 0x06, 0x07, 0x07, 0x05, 0x07, 0x98, 0xb6, 0x03, 0x00, 0x01, 0x03,
+0x05, 0x00, 0x00, 0x03, 0x85, 0x07, 0x05, 0x00, 0x07, 0x07, 0x01, 0x05,
+0x05, 0x07, 0x01, 0x05, 0x01, 0xc2, 0x05, 0x00, 0x01, 0x03, 0x03, 0x00,
+0x01, 0xdb, 0x01, 0xa4, 0x05, 0x07, 0x00, 0x09, 0x05, 0x07, 0x05, 0x07,
+0x05, 0x07, 0x97, 0xa9, 0x75, 0x00, 0x0e, 0x00, 0x00, 0x0b, 0x03, 0x00,
+0x00, 0x71, 0xd7, 0x9b, 0x05, 0x07, 0x07, 0x05, 0x05, 0x00, 0x06, 0x07,
+0x00, 0x0b, 0x95, 0xbf, 0x96, 0x00, 0x00, 0x99, 0xb5, 0x07, 0x05, 0x97,
+0x75, 0x00, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9,
+0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x05, 0x00, 0x01, 0x71, 0x01, 0xe8,
+0x07, 0xe3, 0x01, 0xb0, 0x01, 0x26, 0x06, 0x00, 0x01, 0xa3, 0x01, 0xe8,
+0x03, 0xe3, 0x01, 0xda, 0x03, 0x09, 0x01, 0xfe, 0x03, 0xe3, 0x00, 0x04,
+0xa0, 0xe6, 0x00, 0x11, 0x0d, 0x00, 0x00, 0x03, 0xe6, 0xe8, 0xd8, 0x00,
+0x03, 0xe3, 0x00, 0x03, 0xe8, 0xa1, 0xa2, 0x00, 0x2d, 0x00, 0x00, 0x05,
+0x9a, 0xf6, 0x87, 0x9b, 0x92, 0x00, 0x04, 0x07, 0x00, 0x04, 0xb5, 0xa4,
+0xc2, 0x96, 0x04, 0x00, 0x00, 0x06, 0x75, 0x85, 0x9f, 0x85, 0xd7, 0x71,
+0x06, 0x00, 0x00, 0x05, 0x9a, 0x9f, 0x9f, 0xc2, 0xb6, 0x00, 0x10, 0x00,
+0x00, 0x06, 0x8e, 0xd7, 0x85, 0x85, 0x9f, 0x6b, 0x0c, 0x00, 0x00, 0x0d,
+0xad, 0xb6, 0xc4, 0x9b, 0x95, 0x07, 0x07, 0x05, 0x95, 0x98, 0x87, 0xb6,
+0x7c, 0x00, 0x03, 0x00, 0x00, 0x06, 0x71, 0xc5, 0x85, 0x85, 0x9f, 0x99,
+0x05, 0x00, 0x01, 0x96, 0x03, 0x85, 0x00, 0x0e, 0x84, 0x00, 0x00, 0x96,
+0xa9, 0xa4, 0x92, 0x07, 0x05, 0x95, 0x98, 0x87, 0xdb, 0x7c, 0x07, 0x00,
+0x00, 0x0c, 0x71, 0xd6, 0xc4, 0x9b, 0x92, 0x05, 0x07, 0x95, 0x98, 0x87,
+0xf6, 0x75, 0x13, 0x00, 0x00, 0x0d, 0x75, 0xb6, 0xc4, 0x9b, 0x92, 0x05,
+0x07, 0x07, 0x92, 0x9b, 0xc4, 0xdb, 0x8e, 0x00, 0x0d, 0x00, 0x00, 0x14,
+0x9a, 0x9f, 0x85, 0x85, 0x94, 0x6b, 0x00, 0x00, 0x96, 0xc2, 0xa4, 0xb5,
+0x07, 0x07, 0x05, 0x92, 0x98, 0xbf, 0xb6, 0x7c, 0x0a, 0x00, 0x00, 0x0d,
+0x99, 0x85, 0x9f, 0x9f, 0xf5, 0xf5, 0xa4, 0x05, 0x07, 0x05, 0x98, 0xf5,
+0xf5, 0x00, 0x03, 0x9f, 0x01, 0x85, 0x01, 0x96, 0x0a, 0x00, 0x00, 0x05,
+0x6b, 0x94, 0xa9, 0xa4, 0xb5, 0x00, 0x03, 0x07, 0x00, 0x05, 0x95, 0x98,
+0x87, 0xd7, 0xb2, 0x00, 0x15, 0x00, 0x00, 0x0d, 0x8e, 0x94, 0xa9, 0xa4,
+0xb5, 0x79, 0x07, 0x07, 0x79, 0x97, 0xbd, 0xc2, 0x84, 0x00, 0x04, 0x00,
+0x00, 0x06, 0x99, 0xb5, 0x07, 0x05, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00,
+0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03,
+0x04, 0x00, 0x01, 0x03, 0x0b, 0x00, 0x01, 0x03, 0x04, 0x00, 0x01, 0x03,
+0x05, 0x00, 0x01, 0xe6, 0x03, 0x09, 0x01, 0xda, 0x05, 0x00, 0x01, 0x11,
+0x0c, 0x00, 0x01, 0x03, 0x0b, 0x00, 0x01, 0x03, 0x29, 0x00, 0x01, 0x03,
+0x04, 0x00, 0x01, 0x75, 0x01, 0x99, 0x03, 0x84, 0x00, 0x03, 0x96, 0xb1,
+0x8e, 0x00, 0x03, 0x00, 0x00, 0x03, 0x03, 0x00, 0x26, 0x00, 0x06, 0x00,
+0x01, 0x26, 0x04, 0x00, 0x01, 0x26, 0x06, 0x00, 0x01, 0x03, 0x0d, 0x00,
+0x01, 0x26, 0x06, 0x00, 0x01, 0x26, 0x09, 0x00, 0x01, 0x03, 0x04, 0x00,
+0x01, 0x75, 0x01, 0x96, 0x03, 0x84, 0x00, 0x03, 0x96, 0x9a, 0x26, 0x00,
+0x0b, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 0x03, 0x03, 0x00, 0x05, 0x00,
+0x01, 0x03, 0x03, 0x00, 0x00, 0x0a, 0x7c, 0x99, 0x84, 0x84, 0x96, 0x9a,
+0x4d, 0x00, 0x00, 0x03, 0x05, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x07,
+0x75, 0x99, 0x84, 0x84, 0x96, 0x9a, 0x71, 0x00, 0x13, 0x00, 0x01, 0x03,
+0x04, 0x00, 0x01, 0x75, 0x01, 0x99, 0x03, 0x84, 0x01, 0x99, 0x01, 0x75,
+0x03, 0x00, 0x01, 0x03, 0x0b, 0x00, 0x01, 0x03, 0x06, 0x00, 0x01, 0x26,
+0x03, 0x00, 0x01, 0x7c, 0x01, 0x99, 0x03, 0x84, 0x00, 0x06, 0x99, 0x9a,
+0x71, 0x00, 0x00, 0x03, 0x07, 0x00, 0x01, 0x03, 0x01, 0x03, 0x06, 0x00,
+0x01, 0xd7, 0x03, 0x07, 0x01, 0xc4, 0x07, 0x00, 0x01, 0x26, 0x08, 0x00,
+0x01, 0x03, 0x03, 0x00, 0x01, 0x7c, 0x01, 0x99, 0x03, 0x84, 0x00, 0x03,
+0x96, 0xb2, 0x71, 0x00, 0x03, 0x00, 0x01, 0x03, 0x16, 0x00, 0x00, 0x08,
+0x7c, 0xb1, 0x96, 0x84, 0x84, 0x96, 0xb1, 0x8e, 0x03, 0x00, 0x00, 0x09,
+0x03, 0x4d, 0x00, 0x99, 0xb5, 0x07, 0x05, 0x97, 0x75, 0x00, 0x25, 0x00,
+0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2,
+0x00, 0x03, 0x06, 0x00, 0x01, 0x11, 0x07, 0x26, 0x01, 0x11, 0x08, 0x00,
+0x00, 0x05, 0x11, 0x26, 0x11, 0x00, 0xe6, 0x00, 0x03, 0x09, 0x00, 0x06,
+0xb3, 0xa2, 0x00, 0x26, 0x26, 0x03, 0x0e, 0x00, 0x00, 0x03, 0x03, 0x03,
+0x11, 0x00, 0x05, 0x26, 0x01, 0x11, 0x01, 0x03, 0x2d, 0x00, 0x01, 0x26,
+0x01, 0x4d, 0x09, 0x00, 0x00, 0x03, 0x26, 0x4d, 0x03, 0x00, 0x03, 0x00,
+0x00, 0x05, 0x03, 0x71, 0x4d, 0x71, 0x4d, 0x00, 0x07, 0x00, 0x00, 0x05,
+0x03, 0x71, 0x4d, 0x71, 0x4d, 0x00, 0x10, 0x00, 0x00, 0x06, 0x03, 0x4d,
+0x71, 0x71, 0x4d, 0x03, 0x0c, 0x00, 0x01, 0x26, 0x01, 0x4d, 0x09, 0x00,
+0x01, 0x4d, 0x01, 0x26, 0x04, 0x00, 0x01, 0x4d, 0x03, 0x71, 0x01, 0x26,
+0x05, 0x00, 0x01, 0x26, 0x03, 0x71, 0x00, 0x04, 0x4d, 0x00, 0x00, 0x4d,
+0x08, 0x00, 0x01, 0x4d, 0x01, 0x26, 0x07, 0x00, 0x01, 0x03, 0x01, 0x4d,
+0x08, 0x00, 0x01, 0x4d, 0x01, 0x26, 0x13, 0x00, 0x01, 0x26, 0x01, 0x4d,
+0x09, 0x00, 0x01, 0x4d, 0x01, 0x26, 0x0d, 0x00, 0x00, 0x05, 0x03, 0x4d,
+0x71, 0x71, 0x4d, 0x00, 0x03, 0x00, 0x01, 0x4d, 0x01, 0x03, 0x08, 0x00,
+0x01, 0x4d, 0x01, 0x26, 0x0a, 0x00, 0x00, 0x07, 0x26, 0x71, 0x4d, 0x4d,
+0x00, 0x00, 0x85, 0x00, 0x03, 0x07, 0x00, 0x08, 0x87, 0x00, 0x00, 0x4d,
+0x4d, 0x71, 0x71, 0x26, 0x0a, 0x00, 0x01, 0x03, 0x01, 0x4d, 0x09, 0x00,
+0x01, 0x4d, 0x01, 0x26, 0x15, 0x00, 0x01, 0x03, 0x01, 0x4d, 0x09, 0x00,
+0x00, 0x0c, 0x26, 0x4d, 0x03, 0x00, 0x4d, 0x00, 0x99, 0xb5, 0x07, 0x07,
+0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x08, 0xa1, 0xc9,
+0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03, 0x09, 0x00, 0x01, 0x03, 0x04, 0x26,
+0x0d, 0x00, 0x01, 0xa2, 0x03, 0x09, 0x00, 0x04, 0xf9, 0xa2, 0x00, 0x03,
+0xff, 0x00, 0x1d, 0x00, 0x01, 0x85, 0x03, 0x07, 0x01, 0x87, 0x42, 0x00,
+0x00, 0x08, 0x4d, 0x00, 0x99, 0xb5, 0x07, 0x07, 0x97, 0x75, 0x25, 0x00,
+0x00, 0x00, 0x21, 0x00, 0x03, 0x03, 0x00, 0x09, 0x00, 0xa1, 0xc9, 0x09,
+0x09, 0xb3, 0xa2, 0x00, 0x03, 0x00, 0x08, 0x00, 0x01, 0x03, 0x06, 0x00,
+0x01, 0x03, 0x0b, 0x00, 0x01, 0xa3, 0x01, 0xf9, 0x03, 0x09, 0x00, 0x04,
+0xb0, 0x00, 0x00, 0x03, 0xff, 0x00, 0x1c, 0x00, 0x00, 0x05, 0x85, 0x05,
+0x07, 0x05, 0x87, 0x00, 0x42, 0x00, 0x00, 0x08, 0x4d, 0x00, 0x99, 0xb5,
+0x07, 0x05, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x01, 0x03,
+0x05, 0x00, 0x00, 0x08, 0xe6, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x00, 0x03,
+0x09, 0x00, 0x00, 0x06, 0xa2, 0xe8, 0xd8, 0xd8, 0xb0, 0x4d, 0x0d, 0x00,
+0x01, 0xa0, 0x03, 0x09, 0x01, 0xe2, 0x01, 0xa2, 0xff, 0x00, 0x1e, 0x00,
+0x00, 0x05, 0x85, 0x07, 0x07, 0x05, 0x87, 0x00, 0x42, 0x00, 0x00, 0x08,
+0x4d, 0x00, 0x99, 0xb5, 0x07, 0x07, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00,
+0x21, 0x00, 0x00, 0x0c, 0xa1, 0xe8, 0xb0, 0xb0, 0xe3, 0xe9, 0x09, 0x09,
+0xb3, 0xa2, 0x00, 0x03, 0x09, 0x00, 0x01, 0xb0, 0x03, 0x09, 0x01, 0xfe,
+0x01, 0xa2, 0x0d, 0x00, 0x01, 0xb0, 0x04, 0x09, 0x01, 0xe2, 0x01, 0xb0,
+0x03, 0x00, 0x01, 0x03, 0xff, 0x00, 0x19, 0x00, 0x00, 0x05, 0x85, 0x07,
+0x07, 0x05, 0x87, 0x00, 0x42, 0x00, 0x00, 0x08, 0x4d, 0x00, 0x99, 0xb5,
+0x07, 0x05, 0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x21, 0x00, 0x01, 0xda,
+0x01, 0x09, 0x03, 0xe9, 0x03, 0x09, 0x00, 0x04, 0xb3, 0xa2, 0x00, 0x03,
+0x09, 0x00, 0x00, 0x06, 0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x0b, 0x00,
+0x00, 0x04, 0x03, 0x00, 0x00, 0xa0, 0x04, 0x09, 0x00, 0x04, 0xe9, 0xb3,
+0xda, 0xa1, 0xff, 0x00, 0x1a, 0x00, 0x00, 0x05, 0x85, 0x05, 0x07, 0x05,
+0x87, 0x00, 0x42, 0x00, 0x00, 0x08, 0x4d, 0x00, 0x99, 0xb5, 0x05, 0x07,
+0x97, 0x75, 0x25, 0x00, 0x00, 0x00, 0x21, 0x00, 0x01, 0xb3, 0x06, 0x09,
+0x00, 0x05, 0xfd, 0xe2, 0xa2, 0x00, 0x03, 0x00, 0x09, 0x00, 0x00, 0x06,
+0xa1, 0xc9, 0xfd, 0x09, 0xb3, 0xa2, 0x0c, 0x00, 0x00, 0x04, 0x03, 0x00,
+0xa3, 0xda, 0x06, 0x09, 0x01, 0xe3, 0xff, 0x00, 0x1a, 0x00, 0x01, 0x85,
+0x03, 0x07, 0x01, 0x87, 0x42, 0x00, 0x00, 0x08, 0x4d, 0x00, 0x99, 0xb5,
+0x07, 0x07, 0x97, 0x9a, 0x25, 0x00, 0x00, 0x00, 0x21, 0x00, 0x01, 0xb3,
+0x07, 0x09, 0x00, 0x04, 0xe2, 0xa2, 0x00, 0x03, 0x09, 0x00, 0x00, 0x06,
+0xa1, 0xc9, 0x09, 0x09, 0xb3, 0xa2, 0x0d, 0x00, 0x00, 0x05, 0x03, 0x00,
+0x00, 0xd8, 0xf9, 0x00, 0x04, 0x09, 0x01, 0xe3, 0xff, 0x00, 0x1a, 0x00,
+0x00, 0x05, 0xc2, 0x07, 0x05, 0x05, 0xbf, 0x00, 0x42, 0x00, 0x00, 0x08,
+0x4d, 0x00, 0x99, 0x92, 0x07, 0x07, 0x92, 0x9a, 0x25, 0x00, 0x00, 0x00,
+0x21, 0x00, 0x01, 0xd8, 0x07, 0xa0, 0x00, 0x04, 0xd8, 0xa3, 0x00, 0x03,
+0x09, 0x00, 0x01, 0xb0, 0x03, 0x09, 0x01, 0xfe, 0x01, 0xa2, 0x11, 0x00,
+0x00, 0x06, 0xd2, 0xe3, 0xda, 0xe2, 0xf9, 0xe8, 0xff, 0x00, 0x1a, 0x00,
+0x00, 0x05, 0x84, 0xc4, 0xa9, 0xa9, 0x94, 0x00, 0x42, 0x00, 0x00, 0x08,
+0x26, 0x00, 0x75, 0x9f, 0xa9, 0xc4, 0x9f, 0x8e, 0x25, 0x00, 0x00, 0x00,
+0x1f, 0x00, 0x01, 0x03, 0x0b, 0x00, 0x01, 0x03, 0x0a, 0x00, 0x00, 0x06,
+0xd2, 0xe3, 0xe3, 0xa0, 0xe8, 0x71, 0x14, 0x00, 0x00, 0x03, 0xa3, 0xe6,
+0xa2, 0x00, 0xff, 0x00, 0x20, 0x00, 0x01, 0x03, 0x41, 0x00, 0x01, 0x03,
+0x06, 0x00, 0x01, 0x03, 0x24, 0x00, 0x00, 0x00, 0x35, 0x00, 0x01, 0x03,
+0x06, 0x00, 0x01, 0x03, 0xff, 0x00, 0xa4, 0x00, 0x00, 0x00, 0x36, 0x00,
+0x01, 0x03, 0x03, 0x26, 0x01, 0x11, 0x15, 0x00, 0x03, 0x03, 0xff, 0x00,
+0x8e, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0x2d, 0x00, 0x01, 0x0d, 0xb3, 0x00,
+0x00, 0x00, 0xc9, 0x00, 0x00, 0x04, 0x03, 0x00, 0x75, 0x69, 0x34, 0x7e,
+0x01, 0xad, 0x03, 0x00, 0x01, 0x0d, 0x28, 0x00, 0x01, 0x8e, 0x15, 0x7e,
+0x00, 0x05, 0xb1, 0x9a, 0x7c, 0xa3, 0x4d, 0x00, 0x97, 0x00, 0x00, 0x00,
+0xc9, 0x00, 0x00, 0x07, 0x03, 0x00, 0xf1, 0xac, 0x45, 0x0a, 0xc3, 0x00,
+0x30, 0x0a, 0x00, 0x07, 0x17, 0xc3, 0xf4, 0x7e, 0x00, 0x00, 0x03, 0x00,
+0x26, 0x00, 0x00, 0x03, 0x99, 0x30, 0x86, 0x00, 0x14, 0x0a, 0x00, 0x0b,
+0xc3, 0xc3, 0x76, 0x76, 0xbb, 0xd4, 0xea, 0x96, 0x9a, 0x8e, 0x71, 0x00,
+0x03, 0x00, 0x01, 0x26, 0x01, 0x26, 0x8c, 0x00, 0x00, 0x00, 0xc9, 0x00,
+0x00, 0x07, 0x03, 0x00, 0x8e, 0xea, 0x82, 0xac, 0xac, 0x00, 0x31, 0x3a,
+0x00, 0x05, 0x45, 0xac, 0x86, 0xcf, 0x11, 0x00, 0x26, 0x00, 0x00, 0x04,
+0x71, 0xbb, 0xae, 0x5b, 0x15, 0x3a, 0x00, 0x0d, 0x1c, 0x1c, 0x35, 0x1c,
+0x1c, 0x3a, 0x3a, 0x17, 0x82, 0xf7, 0x69, 0x9a, 0x6b, 0x00, 0x03, 0x00,
+0x01, 0x03, 0x8a, 0x00, 0x00, 0x00, 0xcd, 0x00, 0x00, 0x05, 0x6b, 0xf1,
+0x3e, 0xac, 0x86, 0x00, 0x30, 0x0a, 0x00, 0x04, 0x17, 0x3a, 0xac, 0xcf,
+0x26, 0x00, 0x00, 0x03, 0x7c, 0xc3, 0xac, 0x00, 0x1a, 0x0a, 0x00, 0x0b,
+0x17, 0x86, 0x86, 0x3a, 0x3a, 0x35, 0xac, 0x76, 0xd4, 0xf1, 0xb2, 0x00,
+0x8c, 0x00, 0x00, 0x00, 0xcf, 0x00, 0x00, 0x05, 0x75, 0xf7, 0x17, 0x35,
+0x17, 0x00, 0x03, 0x0a, 0x01, 0x7f, 0x0b, 0x6f, 0x1d, 0x45, 0x00, 0x07,
+0x7f, 0x17, 0x0a, 0x0a, 0x1c, 0x0a, 0xb2, 0x00, 0x25, 0x00, 0x00, 0x05,
+0x71, 0xa6, 0xac, 0x0a, 0x0a, 0x00, 0x16, 0x86, 0x01, 0x17, 0x01, 0x17,
+0x06, 0x0a, 0x00, 0x08, 0x17, 0x86, 0xac, 0xac, 0x30, 0xf7, 0x7e, 0x71,
+0x89, 0x00, 0x00, 0x00, 0xcd, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x0a,
+0x7e, 0x82, 0xac, 0x3a, 0x0a, 0x0a, 0x17, 0x6f, 0x66, 0x70, 0x04, 0x66,
+0x0a, 0x15, 0x01, 0x19, 0x03, 0x15, 0x0d, 0x19, 0x07, 0x0e, 0x00, 0x06,
+0x45, 0x17, 0x0a, 0x17, 0xac, 0xf7, 0x26, 0x00, 0x00, 0x05, 0xcf, 0x35,
+0x86, 0x0a, 0x86, 0x00, 0x06, 0x35, 0x01, 0x45, 0x01, 0x45, 0x06, 0x35,
+0x00, 0x05, 0x45, 0x35, 0x45, 0x35, 0x35, 0x00, 0x05, 0x45, 0x00, 0x04,
+0x3a, 0x86, 0x17, 0x17, 0x03, 0x0a, 0x00, 0x08, 0xc3, 0x0a, 0x3a, 0xac,
+0xc3, 0xb8, 0x69, 0x6b, 0x87, 0x00, 0x00, 0x00, 0xcf, 0x00, 0x00, 0x07,
+0x4d, 0x00, 0x00, 0x8e, 0xf7, 0x35, 0x35, 0x00, 0x03, 0x0a, 0x01, 0x7f,
+0x03, 0x15, 0x01, 0x19, 0x01, 0x15, 0x0d, 0x19, 0x11, 0x0e, 0x01, 0x4f,
+0x03, 0x6f, 0x00, 0x07, 0x0e, 0x7f, 0x0a, 0x0a, 0x35, 0x3e, 0xad, 0x00,
+0x25, 0x00, 0x00, 0x09, 0x9a, 0xc3, 0x3a, 0x0a, 0x0a, 0x3a, 0x45, 0x45,
+0x1c, 0x00, 0x18, 0x45, 0x00, 0x0d, 0x3a, 0x86, 0x17, 0x0a, 0x0a, 0xc3,
+0xc3, 0x86, 0x35, 0x86, 0xbb, 0x69, 0x71, 0x00, 0x85, 0x00, 0x00, 0x00,
+0xd4, 0x00, 0x00, 0x03, 0xf1, 0xc3, 0x1c, 0x00, 0x03, 0x0a, 0x00, 0x04,
+0x7f, 0x19, 0x15, 0x15, 0x0d, 0x19, 0x00, 0x04, 0x0e, 0x0e, 0x19, 0x19,
+0x0b, 0x0e, 0x07, 0x6f, 0x00, 0x07, 0x4f, 0x45, 0x17, 0x0a, 0x86, 0x3a,
+0xcf, 0x00, 0x25, 0x00, 0x00, 0x06, 0x03, 0xf7, 0x35, 0x17, 0x0a, 0x86,
+0x04, 0x1c, 0x01, 0x45, 0x08, 0x1c, 0x01, 0x45, 0x01, 0x1c, 0x04, 0x45,
+0x04, 0x1c, 0x00, 0x04, 0x45, 0x45, 0x35, 0x35, 0x03, 0x45, 0x00, 0x03,
+0x3a, 0x86, 0x17, 0x00, 0x03, 0x0a, 0x00, 0x09, 0x3a, 0xac, 0x35, 0xb8,
+0x7e, 0x0d, 0x00, 0x03, 0x03, 0x00, 0x80, 0x00, 0x00, 0x00, 0xd5, 0x00,
+0x00, 0x03, 0x7e, 0x30, 0x35, 0x00, 0x03, 0x0a, 0x00, 0x03, 0x7f, 0x19,
+0x15, 0x00, 0x0b, 0x19, 0x0e, 0x0e, 0x01, 0x4f, 0x07, 0x6f, 0x00, 0x0a,
+0x4f, 0x35, 0x4f, 0x4f, 0x86, 0x0a, 0x0a, 0xac, 0xbb, 0x6b, 0x25, 0x00,
+0x00, 0x06, 0x7e, 0x3a, 0x86, 0x0a, 0x0a, 0x3a, 0x0c, 0x1c, 0x01, 0x5b,
+0x0c, 0x1c, 0x04, 0x45, 0x00, 0x05, 0x35, 0x45, 0x45, 0x86, 0x17, 0x00,
+0x03, 0x0a, 0x00, 0x08, 0x86, 0x35, 0x86, 0xd4, 0x9a, 0x00, 0x00, 0x03,
+0x7f, 0x00, 0x00, 0x00, 0xd6, 0x00, 0x00, 0x03, 0xb2, 0x82, 0xac, 0x00,
+0x03, 0x0a, 0x00, 0x03, 0x7f, 0x19, 0x15, 0x00, 0x08, 0x19, 0x0e, 0x0e,
+0x01, 0x4f, 0x04, 0x6f, 0x07, 0x4f, 0x00, 0x0a, 0x35, 0x4f, 0x45, 0x0a,
+0x0a, 0x17, 0x17, 0x69, 0x00, 0x11, 0x23, 0x00, 0x00, 0x08, 0x8e, 0xb8,
+0x1c, 0x0a, 0x0a, 0x86, 0x1c, 0x1c, 0x06, 0x5b, 0x01, 0x1c, 0x01, 0x1c,
+0x03, 0x5b, 0x03, 0x1c, 0x01, 0x5b, 0x0a, 0x1c, 0x00, 0x09, 0x45, 0x1c,
+0x45, 0x1c, 0x45, 0x45, 0x1c, 0x86, 0x17, 0x00, 0x03, 0x0a, 0x00, 0x05,
+0x86, 0xac, 0x30, 0xf1, 0x0d, 0x00, 0x80, 0x00, 0x00, 0x00, 0xd7, 0x00,
+0x00, 0x07, 0x75, 0xbb, 0xac, 0x86, 0x0a, 0x0a, 0x7f, 0x00, 0x06, 0x19,
+0x0d, 0x0e, 0x01, 0x4f, 0x06, 0x6f, 0x07, 0x4f, 0x05, 0x35, 0x00, 0x08,
+0x86, 0x0a, 0xc3, 0xac, 0xd4, 0x0d, 0x00, 0x03, 0x21, 0x00, 0x00, 0x07,
+0x11, 0x00, 0xf1, 0xac, 0x0a, 0x0a, 0x17, 0x00, 0x0c, 0x5b, 0x01, 0x1c,
+0x09, 0x5b, 0x00, 0x06, 0x1c, 0x1c, 0x5b, 0x1c, 0x1c, 0x5b, 0x08, 0x1c,
+0x01, 0x86, 0x01, 0x17, 0x03, 0x0a, 0x00, 0x04, 0x1c, 0x45, 0xd4, 0x8e,
+0x7f, 0x00, 0x00, 0x00, 0xd8, 0x00, 0x00, 0x07, 0x7c, 0xbb, 0xac, 0x17,
+0x0a, 0x0a, 0x45, 0x00, 0x03, 0x19, 0x01, 0x0e, 0x01, 0x19, 0x0a, 0x0e,
+0x01, 0x4f, 0x05, 0x6f, 0x05, 0x4f, 0x01, 0x6f, 0x01, 0x4f, 0x09, 0x35,
+0x00, 0x08, 0x86, 0x0a, 0x0a, 0x86, 0x76, 0xb1, 0x00, 0x4d, 0x21, 0x00,
+0x00, 0x0b, 0x26, 0x00, 0x9a, 0xa6, 0x3a, 0xc3, 0x0a, 0x86, 0x3a, 0x3a,
+0x5b, 0x00, 0x08, 0x3a, 0x01, 0x5b, 0x05, 0x3a, 0x01, 0x5b, 0x01, 0x3a,
+0x08, 0x5b, 0x00, 0x03, 0x1c, 0x1c, 0x5b, 0x00, 0x05, 0x1c, 0x00, 0x03,
+0x45, 0x3a, 0x86, 0x00, 0x03, 0x0a, 0x00, 0x07, 0x86, 0xd3, 0x82, 0xb1,
+0x00, 0x00, 0x0d, 0x00, 0x7b, 0x00, 0x00, 0x00, 0xd9, 0x00, 0x00, 0x03,
+0x7c, 0xbb, 0xac, 0x00, 0x03, 0x0a, 0x01, 0x45, 0x01, 0x19, 0x0b, 0x0e,
+0x01, 0x4f, 0x01, 0x4f, 0x04, 0x6f, 0x04, 0x4f, 0x01, 0x35, 0x01, 0x4f,
+0x09, 0x35, 0x04, 0x45, 0x00, 0x05, 0x17, 0x0a, 0xc3, 0xac, 0xcf, 0x00,
+0x26, 0x00, 0x00, 0x08, 0xcf, 0xac, 0xc3, 0x0a, 0x17, 0x3a, 0x3a, 0x28,
+0x17, 0x3a, 0x08, 0x5b, 0x04, 0x1c, 0x00, 0x0b, 0x3a, 0x17, 0x7f, 0x7f,
+0x45, 0xae, 0x7f, 0xf1, 0x00, 0x00, 0x03, 0x00, 0x7a, 0x00, 0x00, 0x00,
+0xda, 0x00, 0x00, 0x08, 0x9a, 0xa6, 0x35, 0x0a, 0x0a, 0x17, 0x6f, 0x19,
+0x03, 0x0e, 0x01, 0x6f, 0x04, 0x0e, 0x01, 0x4f, 0x01, 0x4f, 0x04, 0x6f,
+0x06, 0x4f, 0x05, 0x35, 0x00, 0x03, 0x45, 0x35, 0x35, 0x00, 0x07, 0x45,
+0x00, 0x06, 0x86, 0x0a, 0x0a, 0x3a, 0xa6, 0xad, 0x23, 0x00, 0x00, 0x08,
+0x11, 0x00, 0xb1, 0x76, 0x86, 0x0a, 0x0a, 0x51, 0x0b, 0x28, 0x03, 0x3a,
+0x01, 0x28, 0x01, 0x28, 0x0e, 0x3a, 0x07, 0x5b, 0x00, 0x0a, 0x1c, 0x1c,
+0x3a, 0x7f, 0x7f, 0x45, 0xd3, 0xd3, 0x8a, 0x4d, 0x7b, 0x00, 0x00, 0x00,
+0xdb, 0x00, 0x00, 0x06, 0xb1, 0x76, 0x1c, 0x0a, 0x0a, 0x86, 0x08, 0x0e,
+0x01, 0x4f, 0x04, 0x6f, 0x06, 0x4f, 0x06, 0x35, 0x03, 0x45, 0x01, 0x35,
+0x03, 0x45, 0x01, 0x1c, 0x03, 0x45, 0x00, 0x06, 0x3a, 0x0a, 0x0a, 0x17,
+0xac, 0x69, 0x26, 0x00, 0x00, 0x05, 0xf4, 0xac, 0x0a, 0x0a, 0x86, 0x00,
+0x17, 0x28, 0x00, 0x03, 0x3a, 0x28, 0x28, 0x00, 0x0a, 0x3a, 0x04, 0x5b,
+0x00, 0x08, 0x1c, 0x45, 0x6f, 0x6f, 0xd3, 0x89, 0xd4, 0x11, 0x7a, 0x00,
+0x00, 0x00, 0xdc, 0x00, 0x00, 0x06, 0x69, 0x17, 0x86, 0x0a, 0x0a, 0x7f,
+0x03, 0x0e, 0x01, 0x4f, 0x05, 0x6f, 0x05, 0x4f, 0x08, 0x35, 0x05, 0x45,
+0x00, 0x03, 0x35, 0x1c, 0x45, 0x00, 0x06, 0x1c, 0x00, 0x06, 0x17, 0x0a,
+0x0a, 0x1c, 0xb8, 0x6b, 0x25, 0x00, 0x00, 0x08, 0x69, 0x17, 0x3a, 0x0a,
+0x17, 0x2f, 0x2f, 0x28, 0x07, 0x2f, 0x00, 0x06, 0x28, 0x28, 0x2f, 0x2f,
+0x28, 0x2f, 0x04, 0x28, 0x01, 0x2f, 0x01, 0x2f, 0x08, 0x28, 0x01, 0x3a,
+0x01, 0x28, 0x09, 0x3a, 0x00, 0x08, 0x45, 0x6f, 0x0e, 0x19, 0x9c, 0xce,
+0xd4, 0x0d, 0x79, 0x00, 0x00, 0x00, 0xda, 0x00, 0x00, 0x0b, 0x03, 0x00,
+0x00, 0xcf, 0x35, 0x86, 0x0a, 0x0a, 0x45, 0x0e, 0x4f, 0x00, 0x04, 0x6f,
+0x06, 0x4f, 0x06, 0x35, 0x07, 0x45, 0x07, 0x1c, 0x00, 0x09, 0x5b, 0x5b,
+0x1c, 0x3a, 0x0a, 0x0a, 0x86, 0x86, 0xb1, 0x00, 0x25, 0x00, 0x00, 0x06,
+0x6b, 0x82, 0xac, 0x0a, 0x0a, 0x51, 0x19, 0x2f, 0x09, 0x28, 0x07, 0x3a,
+0x00, 0x0a, 0x45, 0x0e, 0xd3, 0xd3, 0x9c, 0x89, 0xd4, 0x03, 0x00, 0x03,
+0x76, 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x11, 0x03, 0x00, 0x71, 0xb8,
+0xac, 0x17, 0x0a, 0x17, 0x6f, 0x0e, 0x6f, 0x6f, 0x4f, 0x4f, 0x6f, 0x4f,
+0x4f, 0x00, 0x05, 0x35, 0x03, 0x45, 0x00, 0x03, 0x35, 0x45, 0x35, 0x00,
+0x04, 0x45, 0x06, 0x1c, 0x00, 0x0b, 0x5b, 0x5b, 0x1c, 0x5b, 0x5b, 0x3a,
+0x17, 0x0a, 0x17, 0x1c, 0xf7, 0x00, 0x26, 0x00, 0x00, 0x05, 0xcf, 0x35,
+0x86, 0x0a, 0x17, 0x00, 0x08, 0x51, 0x01, 0x2f, 0x05, 0x51, 0x0a, 0x2f,
+0x01, 0x28, 0x01, 0x28, 0x06, 0x2f, 0x05, 0x28, 0x01, 0x3a, 0x04, 0x28,
+0x01, 0x1c, 0x01, 0xd3, 0x03, 0x9c, 0x00, 0x05, 0xce, 0xd4, 0x00, 0x00,
+0x11, 0x00, 0x75, 0x00, 0x00, 0x00, 0xde, 0x00, 0x00, 0x07, 0x9a, 0x76,
+0x1c, 0x0a, 0x0a, 0x86, 0x6f, 0x00, 0x04, 0x4f, 0x07, 0x35, 0x08, 0x45,
+0x07, 0x1c, 0x08, 0x5b, 0x00, 0x06, 0x86, 0x0a, 0x0a, 0x1c, 0x76, 0xad,
+0x25, 0x00, 0x00, 0x05, 0x75, 0xc3, 0x1c, 0x0a, 0x0a, 0x00, 0x12, 0x51,
+0x01, 0x2f, 0x03, 0x51, 0x0b, 0x2f, 0x00, 0x03, 0x28, 0x28, 0x2f, 0x00,
+0x07, 0x28, 0x00, 0x0a, 0x1c, 0xd3, 0x9c, 0x9c, 0x89, 0xce, 0x8a, 0x00,
+0x00, 0x03, 0x74, 0x00, 0x00, 0x00, 0xdf, 0x00, 0x00, 0x06, 0xf1, 0x45,
+0x86, 0x0a, 0x0a, 0x45, 0x04, 0x4f, 0x04, 0x35, 0x09, 0x45, 0x04, 0x1c,
+0x06, 0x5b, 0x06, 0x3a, 0x00, 0x07, 0x5b, 0x51, 0x0a, 0x0a, 0x86, 0x45,
+0xea, 0x00, 0x26, 0x00, 0x00, 0x05, 0xd4, 0x1c, 0x17, 0x0a, 0xfc, 0x00,
+0x06, 0x39, 0x05, 0x51, 0x01, 0x39, 0x0f, 0x51, 0x0c, 0x2f, 0x03, 0x28,
+0x00, 0x08, 0x51, 0x1c, 0x9c, 0x89, 0x89, 0xce, 0xce, 0xf1, 0x76, 0x00,
+0x00, 0x00, 0xdf, 0x00, 0x00, 0x06, 0x71, 0xf4, 0xac, 0x0a, 0x0a, 0x17,
+0x08, 0x35, 0x06, 0x45, 0x06, 0x1c, 0x06, 0x5b, 0x03, 0x3a, 0x00, 0x03,
+0x28, 0x28, 0x3a, 0x00, 0x03, 0x28, 0x00, 0x06, 0x86, 0x0a, 0x0a, 0xac,
+0xbb, 0x71, 0x25, 0x00, 0x00, 0x05, 0x7e, 0x45, 0x86, 0x0a, 0x0a, 0x00,
+0x12, 0x39, 0x00, 0x06, 0x51, 0x51, 0x39, 0x39, 0x51, 0x39, 0x09, 0x51,
+0x00, 0x03, 0x2f, 0x2f, 0x51, 0x00, 0x05, 0x2f, 0x00, 0x04, 0x28, 0x2f,
+0x51, 0x35, 0x03, 0x89, 0x00, 0x03, 0xce, 0x66, 0x99, 0x00, 0x75, 0x00,
+0x00, 0x00, 0xe0, 0x00, 0x00, 0x06, 0xb1, 0xc3, 0x3a, 0x0a, 0x0a, 0x3a,
+0x04, 0x35, 0x05, 0x45, 0x06, 0x1c, 0x06, 0x5b, 0x05, 0x3a, 0x06, 0x28,
+0x00, 0x08, 0x2f, 0x28, 0x51, 0x0a, 0x0a, 0x3a, 0xc3, 0x96, 0x25, 0x00,
+0x00, 0x06, 0x8e, 0xbb, 0x1c, 0x0a, 0x0a, 0xfc, 0x0c, 0x1b, 0x03, 0x39,
+0x01, 0x1b, 0x06, 0x39, 0x01, 0x51, 0x03, 0x39, 0x01, 0x51, 0x01, 0x39,
+0x0a, 0x51, 0x04, 0x2f, 0x00, 0x03, 0x51, 0x39, 0xac, 0x00, 0x03, 0x89,
+0x00, 0x03, 0xce, 0xee, 0x6b, 0x00, 0x74, 0x00, 0x00, 0x00, 0xe1, 0x00,
+0x00, 0x05, 0xcf, 0xac, 0x0a, 0x0a, 0x17, 0x00, 0x07, 0x45, 0x01, 0x1c,
+0x01, 0x45, 0x04, 0x1c, 0x06, 0x5b, 0x03, 0x3a, 0x00, 0x03, 0x28, 0x3a,
+0x3a, 0x00, 0x05, 0x28, 0x05, 0x2f, 0x00, 0x05, 0x17, 0x0a, 0x0a, 0xac,
+0xd4, 0x00, 0x26, 0x00, 0x00, 0x05, 0xf1, 0xac, 0x0a, 0x0a, 0xfc, 0x00,
+0x13, 0x1b, 0x01, 0x39, 0x01, 0x39, 0x03, 0x1b, 0x06, 0x39, 0x00, 0x03,
+0x51, 0x39, 0x39, 0x00, 0x09, 0x51, 0x00, 0x04, 0x2f, 0x51, 0x51, 0xcb,
+0x03, 0x9c, 0x01, 0xce, 0x01, 0xf7, 0x74, 0x00, 0x00, 0x00, 0xdf, 0x00,
+0x00, 0x08, 0x4d, 0x00, 0xad, 0xa6, 0x3a, 0xc3, 0x0a, 0x86, 0x04, 0x45,
+0x05, 0x1c, 0x00, 0x03, 0x5b, 0x5b, 0x1c, 0x00, 0x03, 0x5b, 0x05, 0x3a,
+0x00, 0x07, 0x28, 0x3a, 0x3a, 0x28, 0x28, 0x2f, 0x28, 0x00, 0x07, 0x2f,
+0x00, 0x08, 0xfc, 0x0a, 0x0a, 0x3a, 0x76, 0xb1, 0x00, 0x11, 0x23, 0x00,
+0x00, 0x06, 0x75, 0x3e, 0x3a, 0x0a, 0x0a, 0x39, 0x04, 0x1b, 0x00, 0x05,
+0x1a, 0x1b, 0x1b, 0x1a, 0x1a, 0x00, 0x0f, 0x1b, 0x00, 0x04, 0x39, 0x39,
+0x1b, 0x1b, 0x07, 0x39, 0x08, 0x51, 0x00, 0x0a, 0x39, 0x39, 0xcb, 0x9c,
+0xae, 0x9c, 0xae, 0x69, 0x00, 0x03, 0x71, 0x00, 0x00, 0x00, 0xe2, 0x00,
+0x00, 0x07, 0xea, 0x1c, 0x0a, 0x0a, 0x17, 0x1c, 0x45, 0x00, 0x05, 0x1c,
+0x05, 0x5b, 0x05, 0x3a, 0x05, 0x28, 0x03, 0x2f, 0x01, 0x28, 0x04, 0x2f,
+0x05, 0x51, 0x00, 0x07, 0x17, 0x0a, 0xc3, 0xac, 0xcf, 0x00, 0x03, 0x00,
+0x24, 0x00, 0x00, 0x05, 0xf7, 0xac, 0xc3, 0x0a, 0xfc, 0x00, 0x0c, 0x1a,
+0x01, 0x1b, 0x03, 0x1a, 0x04, 0x1b, 0x01, 0x1a, 0x07, 0x1b, 0x00, 0x03,
+0x39, 0x1b, 0x1b, 0x00, 0x08, 0x39, 0x06, 0x51, 0x00, 0x09, 0x28, 0xcb,
+0xae, 0xcb, 0x9c, 0xb9, 0x7c, 0x00, 0x11, 0x00, 0x70, 0x00, 0x00, 0x00,
+0xe0, 0x00, 0x00, 0x08, 0x03, 0x00, 0x7c, 0x82, 0x1c, 0x0a, 0x0a, 0x86,
+0x05, 0x1c, 0x04, 0x5b, 0x05, 0x3a, 0x05, 0x28, 0x08, 0x2f, 0x04, 0x51,
+0x00, 0x09, 0x39, 0x51, 0x39, 0xfc, 0x0a, 0xc3, 0x1c, 0xbb, 0xad, 0x00,
+0x23, 0x00, 0x00, 0x07, 0x4d, 0x00, 0x7e, 0xc3, 0x86, 0x0a, 0x0a, 0x00,
+0x15, 0x1a, 0x04, 0x1b, 0x01, 0x1a, 0x07, 0x1b, 0x01, 0x39, 0x01, 0x1b,
+0x08, 0x39, 0x03, 0x51, 0x00, 0x06, 0x5b, 0xcb, 0xcb, 0xbe, 0xae, 0xf7,
+0x72, 0x00, 0x00, 0x00, 0xe3, 0x00, 0x00, 0x07, 0xcf, 0x45, 0x86, 0x0a,
+0x86, 0x1c, 0x1c, 0x00, 0x05, 0x5b, 0x03, 0x3a, 0x06, 0x28, 0x01, 0x2f,
+0x01, 0x28, 0x03, 0x2f, 0x09, 0x51, 0x04, 0x39, 0x01, 0x51, 0x03, 0x0a,
+0x01, 0x35, 0x01, 0x69, 0x23, 0x00, 0x00, 0x08, 0x03, 0x00, 0x71, 0xf4,
+0xac, 0xc3, 0x0a, 0xfc, 0x1a, 0x1a, 0x00, 0x03, 0x39, 0x1a, 0x1a, 0x00,
+0x0b, 0x1b, 0x04, 0x39, 0x01, 0x51, 0x01, 0x51, 0x03, 0xbe, 0x00, 0x03,
+0xcb, 0x31, 0xb1, 0x00, 0x71, 0x00, 0x00, 0x00, 0xe3, 0x00, 0x00, 0x07,
+0x9a, 0x76, 0x35, 0x0a, 0x0a, 0x3a, 0x1c, 0x00, 0x03, 0x5b, 0x03, 0x3a,
+0x05, 0x28, 0x00, 0x03, 0x2f, 0x28, 0x28, 0x00, 0x03, 0x2f, 0x07, 0x51,
+0x07, 0x39, 0x00, 0x08, 0x1b, 0x1b, 0xfc, 0x0a, 0x0a, 0x35, 0xf4, 0x71,
+0x23, 0x00, 0x00, 0x0c, 0x03, 0x00, 0xf1, 0x86, 0x0a, 0x0a, 0xfc, 0x1a,
+0x31, 0x1a, 0x1a, 0x31, 0x06, 0x1a, 0x01, 0x31, 0x15, 0x1a, 0x09, 0x1b,
+0x04, 0x39, 0x00, 0x07, 0x2f, 0xbe, 0xcd, 0xcd, 0xcb, 0x88, 0x11, 0x00,
+0x70, 0x00, 0x00, 0x00, 0xe4, 0x00, 0x00, 0x06, 0xd4, 0xac, 0x17, 0x0a,
+0x86, 0x5b, 0x06, 0x3a, 0x04, 0x28, 0x06, 0x2f, 0x06, 0x51, 0x06, 0x39,
+0x05, 0x1b, 0x00, 0x06, 0x39, 0x0a, 0x0a, 0x86, 0x7f, 0xb1, 0x25, 0x00,
+0x00, 0x06, 0x7c, 0x82, 0x1c, 0x0a, 0x0a, 0x1a, 0x07, 0x31, 0x01, 0x1a,
+0x01, 0x1a, 0x05, 0x31, 0x00, 0x03, 0x1a, 0x1a, 0x31, 0x00, 0x13, 0x1a,
+0x06, 0x1b, 0x04, 0x39, 0x01, 0x1b, 0x03, 0xcd, 0x01, 0xef, 0x01, 0xb1,
+0x70, 0x00, 0x00, 0x00, 0xe4, 0x00, 0x00, 0x0a, 0x99, 0x17, 0x3a, 0x0a,
+0x17, 0x3a, 0x3a, 0x28, 0x28, 0x3a, 0x03, 0x28, 0x06, 0x2f, 0x06, 0x51,
+0x04, 0x39, 0x01, 0x1b, 0x01, 0x39, 0x05, 0x1b, 0x00, 0x09, 0x1a, 0x1a,
+0x1b, 0x1a, 0x0a, 0x0a, 0x17, 0xac, 0xf7, 0x00, 0x26, 0x00, 0x00, 0x06,
+0xcf, 0x3a, 0x86, 0x0a, 0xfc, 0x2c, 0x10, 0x31, 0x00, 0x06, 0x1a, 0x1a,
+0x31, 0x1a, 0x31, 0x31, 0x11, 0x1a, 0x05, 0x1b, 0x00, 0x08, 0x39, 0x1b,
+0xcd, 0xef, 0xef, 0xcd, 0x74, 0x0d, 0x6f, 0x00, 0x00, 0x00, 0xe4, 0x00,
+0x00, 0x06, 0x71, 0x82, 0x1c, 0x0a, 0x0a, 0x86, 0x08, 0x28, 0x01, 0x2f,
+0x07, 0x51, 0x04, 0x39, 0x08, 0x1b, 0x01, 0x1a, 0x01, 0x1b, 0x04, 0x1a,
+0x00, 0x06, 0xfc, 0x0a, 0x0a, 0x3a, 0x76, 0x7c, 0x25, 0x00, 0x00, 0x06,
+0x9a, 0x76, 0x1c, 0x0a, 0x17, 0x1a, 0x07, 0x2c, 0x10, 0x31, 0x04, 0x1a,
+0x01, 0x31, 0x01, 0x31, 0x0d, 0x1a, 0x03, 0x1b, 0x00, 0x07, 0x39, 0x31,
+0xdc, 0xdc, 0xef, 0xdc, 0xe7, 0x00, 0x6f, 0x00, 0x00, 0x00, 0xe5, 0x00,
+0x00, 0x05, 0xcf, 0x1c, 0x17, 0x0a, 0x86, 0x00, 0x05, 0x28, 0x01, 0x2f,
+0x08, 0x51, 0x05, 0x39, 0x07, 0x1b, 0x09, 0x1a, 0x00, 0x05, 0x0a, 0x0a,
+0x86, 0x1c, 0xf1, 0x00, 0x26, 0x00, 0x00, 0x05, 0xf4, 0xac, 0x86, 0x7f,
+0xfc, 0x00, 0x0c, 0x2c, 0x00, 0x05, 0x31, 0x2c, 0x31, 0x2c, 0x2c, 0x00,
+0x0d, 0x31, 0x00, 0x03, 0x1a, 0x1a, 0x31, 0x00, 0x0c, 0x1a, 0x01, 0x39,
+0x01, 0x1a, 0x04, 0xdc, 0x01, 0x77, 0x6f, 0x00, 0x00, 0x00, 0xe5, 0x00,
+0x00, 0x05, 0xb1, 0x3a, 0x86, 0x0a, 0x17, 0x00, 0x05, 0x2f, 0x06, 0x51,
+0x03, 0x39, 0x01, 0x1b, 0x03, 0x39, 0x05, 0x1b, 0x0a, 0x1a, 0x00, 0x08,
+0x31, 0x1a, 0xfc, 0x0a, 0x17, 0xac, 0xbb, 0x4d, 0x25, 0x00, 0x00, 0x07,
+0x7e, 0x4f, 0x35, 0x7f, 0x3a, 0x2c, 0x25, 0x00, 0x15, 0x2c, 0x08, 0x31,
+0x00, 0x06, 0x1a, 0x31, 0x31, 0x1a, 0x31, 0x31, 0x0a, 0x1a, 0x00, 0x06,
+0x25, 0xe4, 0xe4, 0xdc, 0xc7, 0xe7, 0x6e, 0x00, 0x00, 0x00, 0xe5, 0x00,
+0x00, 0x06, 0x7c, 0xa6, 0x3a, 0x0a, 0x0a, 0x51, 0x03, 0x2f, 0x05, 0x51,
+0x05, 0x39, 0x06, 0x1b, 0x0c, 0x1a, 0x00, 0x09, 0x31, 0x1a, 0x31, 0x1a,
+0x0a, 0x0a, 0x3a, 0xc3, 0x7e, 0x00, 0x25, 0x00, 0x00, 0x0a, 0x6b, 0x63,
+0xd3, 0x45, 0x6f, 0x39, 0x25, 0x2c, 0x2c, 0x25, 0x18, 0x2c, 0x0a, 0x31,
+0x01, 0x1a, 0x01, 0x31, 0x06, 0x1a, 0x01, 0x2c, 0x01, 0xe4, 0x03, 0x4b,
+0x01, 0xeb, 0x6e, 0x00, 0x00, 0x00, 0xe5, 0x00, 0x00, 0x06, 0x4d, 0xf7,
+0x35, 0x0a, 0x0a, 0xfc, 0x06, 0x51, 0x04, 0x39, 0x07, 0x1b, 0x0a, 0x1a,
+0x00, 0x03, 0x31, 0x1a, 0x1a, 0x00, 0x05, 0x31, 0x00, 0x05, 0xfc, 0x0a,
+0x17, 0xac, 0xd4, 0x00, 0x26, 0x00, 0x00, 0x05, 0xea, 0xd3, 0x6f, 0x0e,
+0x35, 0x00, 0x09, 0x25, 0x01, 0x2c, 0x01, 0x25, 0x15, 0x2c, 0x08, 0x31,
+0x06, 0x1a, 0x00, 0x07, 0x1b, 0x2b, 0x33, 0x33, 0x4b, 0xc8, 0x8e, 0x00,
+0x6d, 0x00, 0x00, 0x00, 0x3a, 0x00, 0x01, 0x03, 0x7f, 0x11, 0x01, 0x03,
+0x01, 0x03, 0x2a, 0x00, 0x00, 0x05, 0x69, 0xac, 0x0a, 0x0a, 0x17, 0x00,
+0x04, 0x51, 0x00, 0x05, 0x39, 0x39, 0x1b, 0x39, 0x39, 0x00, 0x04, 0x1b,
+0x0b, 0x1a, 0x0a, 0x31, 0x00, 0x09, 0x2c, 0xfc, 0x7f, 0x7f, 0x35, 0x76,
+0xb2, 0x00, 0x0d, 0x00, 0x23, 0x00, 0x00, 0x06, 0x9a, 0x7f, 0xd3, 0x19,
+0x19, 0x31, 0x0e, 0x25, 0x08, 0x2c, 0x01, 0x25, 0x0a, 0x2c, 0x09, 0x31,
+0x00, 0x06, 0x1a, 0x31, 0x1a, 0x1a, 0x3b, 0x33, 0x03, 0xd5, 0x00, 0x03,
+0x68, 0x00, 0x03, 0x00, 0x6b, 0x00, 0x00, 0x00, 0xe6, 0x00, 0x00, 0x06,
+0xb1, 0xc3, 0x86, 0x17, 0x17, 0x51, 0x04, 0x39, 0x07, 0x1b, 0x09, 0x1a,
+0x00, 0x03, 0x31, 0x31, 0x1a, 0x00, 0x07, 0x31, 0x04, 0x2c, 0x00, 0x06,
+0x31, 0x3a, 0x45, 0x7f, 0xd3, 0xcf, 0x25, 0x00, 0x00, 0x07, 0x0d, 0xd4,
+0x89, 0x19, 0xd3, 0x1c, 0x43, 0x00, 0x04, 0x25, 0x01, 0x43, 0x10, 0x25,
+0x03, 0x2c, 0x01, 0x25, 0x0a, 0x2c, 0x01, 0x31, 0x01, 0x2c, 0x07, 0x31,
+0x00, 0x0a, 0x1a, 0x1a, 0x4b, 0xab, 0xab, 0xd5, 0xf2, 0x4d, 0x00, 0x0d,
+0x6a, 0x00, 0x00, 0x00, 0x37, 0x00, 0x00, 0x04, 0x0d, 0x00, 0x00, 0x75,
+0x7f, 0x69, 0x00, 0x03, 0x7e, 0x9a, 0x0d, 0x00, 0x29, 0x00, 0x00, 0x06,
+0xad, 0xbb, 0x4f, 0x7f, 0x86, 0x51, 0x03, 0x39, 0x05, 0x1b, 0x0a, 0x1a,
+0x08, 0x31, 0x08, 0x2c, 0x00, 0x09, 0x25, 0x28, 0x6f, 0x7f, 0xae, 0x82,
+0x8e, 0x00, 0x11, 0x00, 0x23, 0x00, 0x01, 0x96, 0x01, 0x9c, 0x03, 0xd3,
+0x01, 0x2c, 0x0a, 0x43, 0x00, 0x03, 0x25, 0x25, 0x43, 0x00, 0x0c, 0x25,
+0x01, 0x2c, 0x01, 0x25, 0x0d, 0x2c, 0x05, 0x31, 0x01, 0x1a, 0x01, 0x42,
+0x03, 0xab, 0x00, 0x04, 0xd1, 0xec, 0x00, 0x26, 0x6a, 0x00, 0x00, 0x00,
+0x39, 0x00, 0x01, 0x7e, 0x01, 0xa6, 0x7f, 0x17, 0x00, 0x08, 0xc3, 0xa6,
+0xb8, 0xf1, 0x6b, 0x00, 0x00, 0x03, 0x24, 0x00, 0x00, 0x06, 0x71, 0xd4,
+0xae, 0x7f, 0x45, 0x28, 0x06, 0x1b, 0x08, 0x1a, 0x01, 0x31, 0x03, 0x1a,
+0x06, 0x31, 0x0a, 0x2c, 0x00, 0x09, 0x25, 0x1a, 0x4f, 0x0e, 0x0e, 0xd3,
+0x69, 0x00, 0x4d, 0x00, 0x23, 0x00, 0x00, 0x07, 0x8e, 0x82, 0x89, 0xd3,
+0x9c, 0xbe, 0x24, 0x00, 0x0d, 0x43, 0x00, 0x04, 0x25, 0x43, 0x25, 0x43,
+0x0c, 0x25, 0x0e, 0x2c, 0x00, 0x08, 0x31, 0x1a, 0x2c, 0xd5, 0xab, 0xab,
+0xd5, 0xeb, 0x6c, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x07, 0x8e, 0xbb,
+0xac, 0x17, 0x0a, 0x17, 0x0a, 0x00, 0x7b, 0x17, 0x00, 0x09, 0x86, 0x3a,
+0xac, 0x45, 0xb8, 0xb1, 0x00, 0x00, 0x03, 0x00, 0x22, 0x00, 0x00, 0x07,
+0x03, 0x00, 0xcf, 0x9c, 0x45, 0x6f, 0x1c, 0x00, 0x04, 0x1b, 0x09, 0x1a,
+0x08, 0x31, 0x0c, 0x2c, 0x03, 0x25, 0x00, 0x06, 0x35, 0xd3, 0x19, 0x89,
+0xf4, 0x71, 0x23, 0x00, 0x00, 0x07, 0x26, 0x00, 0xdb, 0xce, 0x9c, 0x89,
+0xae, 0x00, 0x16, 0x43, 0x0c, 0x25, 0x00, 0x03, 0x2c, 0x2c, 0x25, 0x00,
+0x08, 0x2c, 0x00, 0x08, 0x31, 0x1a, 0x61, 0xd1, 0xd1, 0xab, 0xdd, 0xad,
+0x6b, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x03, 0x75, 0xc3, 0x3a, 0x00,
+0x82, 0x0a, 0x00, 0x06, 0x3a, 0xac, 0xc3, 0x96, 0x00, 0x03, 0x22, 0x00,
+0x00, 0x0a, 0x4d, 0x00, 0xf1, 0x9c, 0x0e, 0x19, 0x35, 0x1a, 0x1b, 0x1b,
+0x08, 0x1a, 0x07, 0x31, 0x0a, 0x2c, 0x07, 0x25, 0x01, 0x43, 0x01, 0x2f,
+0x04, 0x9c, 0x01, 0x7e, 0x23, 0x00, 0x00, 0x09, 0x11, 0x00, 0x75, 0x8c,
+0xce, 0x89, 0x89, 0xbe, 0x24, 0x00, 0x04, 0x43, 0x00, 0x06, 0x3b, 0x43,
+0x43, 0x3b, 0x43, 0x3b, 0x0f, 0x43, 0x0b, 0x25, 0x01, 0x2c, 0x01, 0x25,
+0x06, 0x2c, 0x01, 0x1a, 0x01, 0x43, 0x03, 0xd1, 0x01, 0xab, 0x01, 0x68,
+0x6b, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x06, 0x7c, 0x82, 0x3a, 0x0a,
+0x0a, 0x17, 0x45, 0x7f, 0x09, 0x17, 0x01, 0x7f, 0x2d, 0x17, 0x05, 0x0a,
+0x00, 0x03, 0xac, 0x30, 0x9a, 0x00, 0x23, 0x00, 0x00, 0x08, 0x4d, 0x00,
+0x96, 0x19, 0xd3, 0xd3, 0x0e, 0x1b, 0x06, 0x1a, 0x00, 0x03, 0x31, 0x31,
+0x1a, 0x00, 0x05, 0x31, 0x0a, 0x2c, 0x0a, 0x25, 0x00, 0x08, 0x43, 0x25,
+0xae, 0x9c, 0x9c, 0xce, 0xd4, 0x0d, 0x25, 0x00, 0x00, 0x0f, 0xd4, 0xce,
+0x89, 0x89, 0xae, 0x24, 0x3b, 0x3b, 0x43, 0x43, 0x3b, 0x3b, 0x43, 0x3b,
+0x3b, 0x00, 0x04, 0x43, 0x01, 0x3b, 0x0e, 0x43, 0x0a, 0x25, 0x07, 0x2c,
+0x00, 0x07, 0x31, 0xc7, 0xc8, 0xc8, 0xd1, 0xde, 0x6b, 0x00, 0x6a, 0x00,
+0x00, 0x00, 0x39, 0x00, 0x00, 0x07, 0xea, 0xac, 0x0a, 0x0a, 0x7f, 0x3c,
+0x2d, 0x00, 0x22, 0x3c, 0x08, 0x5d, 0x09, 0x66, 0x08, 0x15, 0x00, 0x03,
+0x19, 0x15, 0x15, 0x00, 0x05, 0x19, 0x01, 0x0e, 0x01, 0x19, 0x07, 0x0e,
+0x08, 0x6f, 0x00, 0x07, 0x4f, 0x6f, 0x45, 0x6f, 0x45, 0x45, 0x35, 0x00,
+0x09, 0x45, 0x01, 0x1c, 0x08, 0x3a, 0x00, 0x06, 0x28, 0x51, 0x28, 0x51,
+0x51, 0x2f, 0x06, 0x51, 0x00, 0x04, 0x39, 0x51, 0xfc, 0x17, 0x03, 0x0a,
+0x01, 0xac, 0x01, 0xcf, 0x23, 0x00, 0x00, 0x08, 0x26, 0x00, 0xb1, 0x7f,
+0x9c, 0x9c, 0xd3, 0x1b, 0x04, 0x1a, 0x08, 0x31, 0x06, 0x2c, 0x01, 0x25,
+0x03, 0x2c, 0x09, 0x25, 0x04, 0x43, 0x00, 0x07, 0x3b, 0xcb, 0x89, 0x89,
+0xce, 0x15, 0x75, 0x00, 0x25, 0x00, 0x00, 0x07, 0x99, 0x70, 0xce, 0x89,
+0x9c, 0x31, 0x2b, 0x00, 0x0c, 0x3b, 0x04, 0x43, 0x01, 0x3b, 0x0e, 0x43,
+0x08, 0x25, 0x01, 0x2c, 0x01, 0x25, 0x03, 0x2c, 0x01, 0x31, 0x01, 0x3f,
+0x04, 0xc8, 0x01, 0xec, 0x6a, 0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x06,
+0xb2, 0xc3, 0x86, 0xc3, 0x17, 0x5d, 0x20, 0x9e, 0x04, 0x0b, 0x00, 0x03,
+0xba, 0x0b, 0xba, 0x00, 0x07, 0x2d, 0x04, 0x3c, 0x04, 0x5d, 0x04, 0x70,
+0x05, 0x66, 0x09, 0x15, 0x05, 0x19, 0x00, 0x04, 0x0e, 0x0e, 0x19, 0x19,
+0x05, 0x0e, 0x03, 0x6f, 0x03, 0x4f, 0x04, 0x35, 0x04, 0x45, 0x03, 0x1c,
+0x00, 0x03, 0x5b, 0x1c, 0x5b, 0x00, 0x04, 0x3a, 0x03, 0x28, 0x04, 0x2f,
+0x03, 0x51, 0x05, 0x39, 0x00, 0x07, 0x1b, 0xfc, 0x0a, 0x0a, 0x3a, 0x3e,
+0xad, 0x00, 0x22, 0x00, 0x00, 0x08, 0x11, 0x00, 0xb2, 0x17, 0x89, 0x9c,
+0x9c, 0x2f, 0x03, 0x1a, 0x06, 0x31, 0x09, 0x2c, 0x0b, 0x25, 0x06, 0x43,
+0x01, 0x24, 0x01, 0x31, 0x03, 0x89, 0x01, 0xce, 0x01, 0xdb, 0x26, 0x00,
+0x00, 0x06, 0x82, 0xce, 0x89, 0x89, 0xbe, 0x24, 0x11, 0x3b, 0x01, 0x43,
+0x01, 0x3b, 0x10, 0x43, 0x09, 0x25, 0x00, 0x07, 0x31, 0x43, 0xe1, 0xdd,
+0xc8, 0xc8, 0x9d, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x07,
+0x4d, 0xd4, 0xac, 0xc3, 0x0a, 0xe5, 0x9e, 0x00, 0x0a, 0x0b, 0x01, 0xba,
+0x15, 0x0b, 0x07, 0x2d, 0x05, 0x3c, 0x06, 0x5d, 0x04, 0x70, 0x04, 0x66,
+0x0a, 0x15, 0x06, 0x19, 0x09, 0x0e, 0x03, 0x6f, 0x03, 0x4f, 0x05, 0x35,
+0x03, 0x45, 0x05, 0x1c, 0x01, 0x5b, 0x01, 0x5b, 0x03, 0x3a, 0x03, 0x28,
+0x04, 0x2f, 0x04, 0x51, 0x04, 0x39, 0x03, 0x1b, 0x00, 0x06, 0x1a, 0x0a,
+0x0a, 0x86, 0x3a, 0xb2, 0x22, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x75, 0xee,
+0xce, 0x89, 0x9c, 0x2f, 0x31, 0x1a, 0x05, 0x31, 0x08, 0x2c, 0x01, 0x25,
+0x01, 0x2c, 0x08, 0x25, 0x0a, 0x43, 0x00, 0x08, 0x3b, 0x25, 0xae, 0x89,
+0x89, 0xce, 0xee, 0x4d, 0x25, 0x00, 0x00, 0x06, 0xf1, 0x89, 0x89, 0x9c,
+0xae, 0x25, 0x07, 0x24, 0x00, 0x04, 0x3b, 0x3b, 0x24, 0x24, 0x0b, 0x3b,
+0x04, 0x43, 0x01, 0x3b, 0x09, 0x43, 0x01, 0x25, 0x01, 0x43, 0x07, 0x25,
+0x00, 0x07, 0x31, 0xdf, 0xdd, 0xdd, 0xc8, 0xbc, 0xd2, 0x00, 0x69, 0x00,
+0x00, 0x00, 0x38, 0x00, 0x00, 0x0b, 0x4d, 0x00, 0x7e, 0x17, 0x17, 0x0a,
+0x7f, 0x3c, 0x9e, 0x0b, 0xba, 0x00, 0x0a, 0x0b, 0x03, 0xba, 0x00, 0x05,
+0x0b, 0xba, 0x0b, 0x0b, 0xba, 0x00, 0x0b, 0x0b, 0x07, 0x2d, 0x06, 0x3c,
+0x05, 0x5d, 0x03, 0x70, 0x04, 0x66, 0x01, 0x15, 0x01, 0x66, 0x08, 0x15,
+0x07, 0x19, 0x04, 0x0e, 0x01, 0x6f, 0x03, 0x0e, 0x03, 0x6f, 0x04, 0x4f,
+0x03, 0x35, 0x04, 0x45, 0x05, 0x1c, 0x00, 0x06, 0x5b, 0x5b, 0x3a, 0x3a,
+0x28, 0x3a, 0x05, 0x28, 0x01, 0x2f, 0x04, 0x51, 0x00, 0x04, 0x39, 0x39,
+0x1b, 0x39, 0x03, 0x1b, 0x00, 0x07, 0x1a, 0x1a, 0xfc, 0x0a, 0x86, 0x1c,
+0x7e, 0x00, 0x22, 0x00, 0x00, 0x09, 0x03, 0x00, 0x7c, 0xee, 0xce, 0x89,
+0x89, 0x5b, 0x2c, 0x00, 0x05, 0x31, 0x06, 0x2c, 0x00, 0x03, 0x25, 0x2c,
+0x2c, 0x00, 0x08, 0x25, 0x0c, 0x43, 0x00, 0x08, 0x3b, 0x24, 0xcd, 0x9c,
+0x9c, 0x89, 0x89, 0x7e, 0x25, 0x00, 0x00, 0x07, 0x6b, 0x7f, 0x89, 0xae,
+0xae, 0x31, 0x34, 0x00, 0x0f, 0x24, 0x08, 0x3b, 0x00, 0x07, 0x43, 0x3b,
+0x3b, 0x43, 0x43, 0x3b, 0x3b, 0x00, 0x09, 0x43, 0x05, 0x25, 0x00, 0x07,
+0x2c, 0x24, 0xe1, 0xdd, 0xdd, 0xc8, 0x90, 0x00, 0x69, 0x00, 0x00, 0x00,
+0x38, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x6b, 0xb8, 0xac, 0x0a, 0x0a, 0x19,
+0x9e, 0x0b, 0xba, 0xba, 0x0a, 0x0b, 0x01, 0xba, 0x03, 0x0b, 0x00, 0x06,
+0xba, 0x0b, 0xba, 0x0b, 0x0b, 0xba, 0x07, 0x0b, 0x05, 0x2d, 0x00, 0x03,
+0x3c, 0x3c, 0x2d, 0x00, 0x05, 0x3c, 0x06, 0x5d, 0x03, 0x70, 0x03, 0x66,
+0x0a, 0x15, 0x07, 0x19, 0x07, 0x0e, 0x01, 0x4f, 0x03, 0x6f, 0x04, 0x4f,
+0x03, 0x35, 0x04, 0x45, 0x04, 0x1c, 0x05, 0x5b, 0x00, 0x04, 0x3a, 0x3a,
+0x28, 0x28, 0x04, 0x2f, 0x03, 0x51, 0x03, 0x39, 0x01, 0x1b, 0x01, 0x39,
+0x03, 0x1b, 0x03, 0x1a, 0x00, 0x05, 0x0a, 0x0a, 0x86, 0x45, 0xb1, 0x00,
+0x22, 0x00, 0x00, 0x09, 0x03, 0x00, 0x7c, 0xee, 0xce, 0x89, 0x9c, 0x2f,
+0x2c, 0x00, 0x03, 0x31, 0x06, 0x2c, 0x00, 0x03, 0x25, 0x2c, 0x2c, 0x00,
+0x07, 0x25, 0x08, 0x43, 0x03, 0x3b, 0x01, 0x43, 0x04, 0x3b, 0x00, 0x07,
+0x24, 0x3b, 0xcb, 0xae, 0xae, 0x89, 0xb8, 0x00, 0x26, 0x00, 0x00, 0x07,
+0x8a, 0x89, 0xae, 0xae, 0xbe, 0x3b, 0x2b, 0x00, 0x13, 0x24, 0x0a, 0x3b,
+0x00, 0x04, 0x43, 0x43, 0x3b, 0x3b, 0x09, 0x43, 0x03, 0x25, 0x00, 0x06,
+0xe0, 0xbc, 0x10, 0xc8, 0x5e, 0xa3, 0x68, 0x00, 0x00, 0x00, 0x39, 0x00,
+0x00, 0x07, 0x03, 0x00, 0xf1, 0x3a, 0x86, 0x0a, 0x7f, 0x00, 0x09, 0x0b,
+0x01, 0xba, 0x01, 0xba, 0x0b, 0x0b, 0x01, 0xba, 0x08, 0x0b, 0x05, 0x2d,
+0x07, 0x3c, 0x06, 0x5d, 0x03, 0x70, 0x05, 0x66, 0x08, 0x15, 0x07, 0x19,
+0x08, 0x0e, 0x03, 0x6f, 0x00, 0x07, 0x4f, 0x4f, 0x6f, 0x4f, 0x45, 0x35,
+0x35, 0x00, 0x05, 0x45, 0x03, 0x1c, 0x01, 0x5b, 0x01, 0x5b, 0x05, 0x3a,
+0x01, 0x28, 0x01, 0x28, 0x04, 0x2f, 0x04, 0x51, 0x03, 0x39, 0x04, 0x1b,
+0x04, 0x1a, 0x00, 0x05, 0x17, 0x17, 0x45, 0x8c, 0x75, 0x00, 0x22, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0x7c, 0xed, 0x89, 0x9c, 0xae, 0x2f, 0x2c, 0x31,
+0x09, 0x2c, 0x05, 0x25, 0x0a, 0x43, 0x01, 0x3b, 0x01, 0x43, 0x09, 0x3b,
+0x00, 0x07, 0x24, 0xcd, 0xae, 0xcb, 0x9c, 0x51, 0x75, 0x00, 0x25, 0x00,
+0x00, 0x07, 0xb2, 0xcb, 0xae, 0xcb, 0xcb, 0xef, 0x34, 0x00, 0x03, 0x2b,
+0x14, 0x24, 0x0a, 0x3b, 0x01, 0x43, 0x01, 0x3b, 0x09, 0x43, 0x00, 0x07,
+0x31, 0xdf, 0x10, 0xbc, 0x10, 0xbc, 0xd9, 0x00, 0x68, 0x00, 0x00, 0x00,
+0x3b, 0x00, 0x00, 0x07, 0xad, 0xa6, 0xac, 0x0a, 0x0a, 0x66, 0x9e, 0x00,
+0x0d, 0x0b, 0x01, 0xba, 0x06, 0x0b, 0x01, 0xba, 0x06, 0x0b, 0x01, 0x2d,
+0x01, 0x0b, 0x06, 0x2d, 0x05, 0x3c, 0x06, 0x5d, 0x03, 0x70, 0x04, 0x66,
+0x09, 0x15, 0x07, 0x19, 0x08, 0x0e, 0x03, 0x6f, 0x04, 0x4f, 0x03, 0x35,
+0x00, 0x04, 0x45, 0x35, 0x45, 0x45, 0x05, 0x1c, 0x01, 0x5b, 0x04, 0x3a,
+0x03, 0x28, 0x03, 0x2f, 0x04, 0x51, 0x03, 0x39, 0x04, 0x1b, 0x05, 0x1a,
+0x00, 0x06, 0x51, 0x7f, 0x7f, 0xd3, 0xf4, 0x6b, 0x22, 0x00, 0x00, 0x08,
+0x03, 0x00, 0x7c, 0x63, 0x89, 0xae, 0xae, 0x1b, 0x09, 0x2c, 0x05, 0x25,
+0x0a, 0x43, 0x00, 0x03, 0x3b, 0x43, 0x43, 0x00, 0x07, 0x3b, 0x04, 0x24,
+0x00, 0x06, 0x25, 0xbe, 0xcb, 0xcb, 0xae, 0xcf, 0x25, 0x00, 0x00, 0x07,
+0x71, 0xa8, 0xae, 0xcb, 0xbe, 0xcd, 0x34, 0x00, 0x0c, 0x2b, 0x0e, 0x24,
+0x01, 0x3b, 0x01, 0x24, 0x09, 0x3b, 0x07, 0x43, 0x00, 0x07, 0x25, 0x43,
+0xe1, 0xbc, 0xbc, 0xdd, 0xeb, 0x00, 0x68, 0x00, 0x00, 0x00, 0x3c, 0x00,
+0x00, 0x05, 0xf7, 0xac, 0x17, 0x0a, 0xe5, 0x00, 0x07, 0x0b, 0x01, 0xba,
+0x01, 0xba, 0x05, 0x0b, 0x01, 0xba, 0x07, 0x0b, 0x01, 0xba, 0x05, 0x0b,
+0x08, 0x2d, 0x04, 0x3c, 0x05, 0x5d, 0x03, 0x70, 0x01, 0x66, 0x01, 0x70,
+0x04, 0x66, 0x09, 0x15, 0x06, 0x19, 0x09, 0x0e, 0x01, 0x6f, 0x01, 0x6f,
+0x04, 0x4f, 0x04, 0x35, 0x03, 0x45, 0x04, 0x1c, 0x01, 0x5b, 0x01, 0x5b,
+0x04, 0x3a, 0x01, 0x28, 0x01, 0x28, 0x04, 0x2f, 0x04, 0x51, 0x03, 0x39,
+0x04, 0x1b, 0x05, 0x1a, 0x00, 0x06, 0x39, 0x7f, 0x7f, 0x45, 0xd3, 0x69,
+0x23, 0x00, 0x00, 0x08, 0x03, 0x00, 0xe7, 0xf0, 0xae, 0xcb, 0xcb, 0x1a,
+0x04, 0x2c, 0x00, 0x03, 0x25, 0x25, 0x2c, 0x00, 0x05, 0x25, 0x09, 0x43,
+0x00, 0x03, 0x3b, 0x3b, 0x43, 0x00, 0x07, 0x3b, 0x08, 0x24, 0x00, 0x08,
+0xcd, 0xbe, 0xbe, 0xcb, 0x52, 0x6b, 0x00, 0x03, 0x23, 0x00, 0x00, 0x07,
+0x69, 0xae, 0xbe, 0xbe, 0xcd, 0x2b, 0x42, 0x00, 0x10, 0x2b, 0x01, 0x24,
+0x01, 0x2b, 0x0b, 0x24, 0x07, 0x3b, 0x04, 0x43, 0x01, 0x3b, 0x03, 0x43,
+0x00, 0x09, 0x31, 0xe0, 0x4c, 0xbc, 0xbc, 0xde, 0xe7, 0x00, 0x03, 0x00,
+0x65, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x0e, 0xb1, 0x17, 0x45, 0x0a,
+0x7f, 0x5d, 0x9e, 0x0b, 0x0b, 0xba, 0xba, 0x0b, 0x0b, 0xba, 0x05, 0x0b,
+0x01, 0xba, 0x01, 0xba, 0x03, 0x0b, 0x01, 0xba, 0x08, 0x0b, 0x07, 0x2d,
+0x03, 0x3c, 0x06, 0x5d, 0x05, 0x70, 0x03, 0x66, 0x0a, 0x15, 0x07, 0x19,
+0x07, 0x0e, 0x04, 0x6f, 0x03, 0x4f, 0x03, 0x35, 0x05, 0x45, 0x03, 0x1c,
+0x01, 0x5b, 0x01, 0x5b, 0x04, 0x3a, 0x01, 0x28, 0x01, 0x28, 0x04, 0x2f,
+0x04, 0x51, 0x03, 0x39, 0x04, 0x1b, 0x04, 0x1a, 0x00, 0x08, 0x31, 0x39,
+0x45, 0x45, 0x7f, 0x9c, 0xb8, 0x6b, 0x23, 0x00, 0x00, 0x0c, 0x11, 0x00,
+0xb1, 0xfc, 0xcb, 0xcb, 0xbe, 0x31, 0x2c, 0x25, 0x25, 0x2c, 0x05, 0x25,
+0x0b, 0x43, 0x08, 0x3b, 0x0b, 0x24, 0x01, 0x3b, 0x04, 0xcd, 0x00, 0x03,
+0x69, 0x00, 0x11, 0x00, 0x23, 0x00, 0x00, 0x06, 0x8e, 0x52, 0xcb, 0xcd,
+0xcd, 0x3b, 0x04, 0x34, 0x01, 0x2b, 0x01, 0x34, 0x0e, 0x2b, 0x0d, 0x24,
+0x06, 0x3b, 0x06, 0x43, 0x00, 0x07, 0x25, 0x34, 0xf3, 0xf2, 0xf2, 0xbc,
+0x68, 0x00, 0x67, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x0a, 0xb8, 0xac,
+0x7f, 0x17, 0x19, 0x9e, 0x9e, 0x0b, 0x0b, 0xba, 0x0c, 0x0b, 0x01, 0xba,
+0x01, 0xba, 0x07, 0x0b, 0x07, 0x2d, 0x04, 0x3c, 0x06, 0x5d, 0x04, 0x70,
+0x05, 0x66, 0x07, 0x15, 0x08, 0x19, 0x07, 0x0e, 0x00, 0x03, 0x4f, 0x6f,
+0x6f, 0x00, 0x04, 0x4f, 0x03, 0x35, 0x03, 0x45, 0x04, 0x1c, 0x04, 0x5b,
+0x01, 0x3a, 0x01, 0x3a, 0x03, 0x28, 0x04, 0x2f, 0x03, 0x51, 0x03, 0x39,
+0x06, 0x1b, 0x03, 0x1a, 0x00, 0x0a, 0x31, 0x51, 0x45, 0x6f, 0x45, 0xd3,
+0x8c, 0xb2, 0x00, 0x26, 0x22, 0x00, 0x00, 0x07, 0x26, 0x00, 0x7e, 0x1b,
+0xbe, 0xbe, 0xcd, 0x00, 0x04, 0x2c, 0x05, 0x25, 0x09, 0x43, 0x07, 0x3b,
+0x0c, 0x24, 0x04, 0x2b, 0x00, 0x08, 0xef, 0xef, 0x3b, 0xbe, 0x72, 0x4d,
+0x00, 0x03, 0x21, 0x00, 0x00, 0x04, 0x26, 0x00, 0xd0, 0xcb, 0x03, 0xef,
+0x0a, 0x34, 0x00, 0x06, 0x2b, 0x34, 0x2b, 0x34, 0x2b, 0x34, 0x04, 0x2b,
+0x01, 0x24, 0x05, 0x2b, 0x0a, 0x24, 0x04, 0x3b, 0x00, 0x03, 0x43, 0x3b,
+0x3b, 0x00, 0x03, 0x43, 0x00, 0x09, 0x31, 0xc6, 0xf2, 0xf2, 0x4c, 0x56,
+0xd2, 0x00, 0x03, 0x00, 0x64, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x07,
+0x69, 0x4f, 0x45, 0x7f, 0x45, 0x2d, 0x9e, 0x00, 0x16, 0x0b, 0x08, 0x2d,
+0x06, 0x3c, 0x05, 0x5d, 0x01, 0x70, 0x01, 0x70, 0x04, 0x66, 0x01, 0x15,
+0x01, 0x66, 0x07, 0x15, 0x07, 0x19, 0x09, 0x0e, 0x03, 0x6f, 0x03, 0x4f,
+0x04, 0x35, 0x03, 0x45, 0x04, 0x1c, 0x01, 0x5b, 0x01, 0x5b, 0x03, 0x3a,
+0x03, 0x28, 0x04, 0x2f, 0x03, 0x51, 0x03, 0x39, 0x04, 0x1b, 0x05, 0x1a,
+0x00, 0x08, 0x31, 0x2f, 0x6f, 0x0e, 0x6f, 0x9c, 0x6f, 0x69, 0x25, 0x00,
+0x00, 0x04, 0x4d, 0x00, 0x8b, 0xbe, 0x03, 0xcd, 0x01, 0x2c, 0x01, 0x2c,
+0x04, 0x25, 0x09, 0x43, 0x00, 0x03, 0x3b, 0x43, 0x43, 0x00, 0x05, 0x3b,
+0x0a, 0x24, 0x08, 0x2b, 0x03, 0xdc, 0x00, 0x05, 0xef, 0x34, 0xec, 0x00,
+0x4d, 0x00, 0x21, 0x00, 0x00, 0x08, 0x26, 0x00, 0xe7, 0xdf, 0xcd, 0xdc,
+0xdc, 0x2b, 0x0f, 0x34, 0x0b, 0x2b, 0x0b, 0x24, 0x06, 0x3b, 0x00, 0x0b,
+0x43, 0x43, 0x25, 0xdf, 0x41, 0xde, 0xf2, 0x4c, 0xd9, 0x00, 0x03, 0x00,
+0x64, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x07, 0x8e, 0x40, 0x0e, 0x45,
+0x7f, 0x66, 0x9e, 0x00, 0x0e, 0x0b, 0x01, 0xba, 0x05, 0x0b, 0x01, 0x2d,
+0x01, 0x0b, 0x08, 0x2d, 0x03, 0x3c, 0x07, 0x5d, 0x04, 0x70, 0x03, 0x66,
+0x01, 0x15, 0x01, 0x66, 0x07, 0x15, 0x07, 0x19, 0x07, 0x0e, 0x03, 0x6f,
+0x04, 0x4f, 0x03, 0x35, 0x04, 0x45, 0x04, 0x1c, 0x03, 0x5b, 0x03, 0x3a,
+0x03, 0x28, 0x03, 0x2f, 0x03, 0x51, 0x03, 0x39, 0x05, 0x1b, 0x04, 0x1a,
+0x00, 0x08, 0x2c, 0x2f, 0x0e, 0x19, 0x0e, 0x9c, 0x6f, 0x69, 0x26, 0x00,
+0x00, 0x04, 0x26, 0x00, 0xea, 0xbe, 0x03, 0xef, 0x01, 0x25, 0x01, 0x43,
+0x04, 0x25, 0x0a, 0x43, 0x05, 0x3b, 0x0b, 0x24, 0x03, 0x2b, 0x01, 0x24,
+0x05, 0x2b, 0x01, 0x34, 0x03, 0xe4, 0x01, 0xef, 0x01, 0x9d, 0x26, 0x00,
+0x00, 0x05, 0x8f, 0xcd, 0xdc, 0xdc, 0x42, 0x00, 0x05, 0x34, 0x01, 0x42,
+0x01, 0x42, 0x0c, 0x34, 0x0b, 0x2b, 0x0a, 0x24, 0x05, 0x3b, 0x00, 0x08,
+0x43, 0x25, 0x54, 0x50, 0x50, 0xf2, 0xeb, 0xa3, 0x65, 0x00, 0x00, 0x00,
+0x3e, 0x00, 0x00, 0x07, 0xcf, 0x9c, 0x45, 0x45, 0x0e, 0x0b, 0x9e, 0x00,
+0x06, 0x0b, 0x01, 0xba, 0x0d, 0x0b, 0x08, 0x2d, 0x04, 0x3c, 0x07, 0x5d,
+0x01, 0x66, 0x01, 0x70, 0x06, 0x66, 0x06, 0x15, 0x08, 0x19, 0x08, 0x0e,
+0x03, 0x6f, 0x03, 0x4f, 0x00, 0x03, 0x45, 0x35, 0x35, 0x00, 0x04, 0x45,
+0x00, 0x06, 0x1c, 0x1c, 0x5b, 0x1c, 0x1c, 0x5b, 0x03, 0x3a, 0x03, 0x28,
+0x04, 0x2f, 0x03, 0x51, 0x00, 0x04, 0x39, 0x39, 0x1b, 0x39, 0x03, 0x1b,
+0x05, 0x1a, 0x01, 0x31, 0x01, 0x5b, 0x03, 0xd3, 0x00, 0x03, 0x89, 0x6f,
+0x69, 0x00, 0x28, 0x00, 0x00, 0x06, 0x03, 0x6c, 0xcd, 0xdc, 0xdc, 0x3b,
+0x03, 0x25, 0x06, 0x43, 0x01, 0x3b, 0x01, 0x43, 0x07, 0x3b, 0x09, 0x24,
+0x0b, 0x2b, 0x04, 0x34, 0x00, 0x06, 0xe4, 0x4b, 0x4b, 0xe4, 0xc6, 0xad,
+0x23, 0x00, 0x00, 0x13, 0x03, 0x00, 0xd9, 0x34, 0xdc, 0xe4, 0xe4, 0x42,
+0x42, 0x34, 0x34, 0x42, 0x42, 0x34, 0x42, 0x34, 0x34, 0x42, 0x42, 0x00,
+0x0a, 0x34, 0x0b, 0x2b, 0x0a, 0x24, 0x03, 0x3b, 0x00, 0x07, 0xef, 0xe0,
+0x50, 0x5e, 0x55, 0xf2, 0xe7, 0x00, 0x65, 0x00, 0x00, 0x00, 0x3e, 0x00,
+0x00, 0x07, 0xb1, 0x6f, 0x0e, 0x45, 0x6f, 0x3c, 0x9e, 0x00, 0x05, 0x0b,
+0x01, 0xba, 0x0e, 0x0b, 0x07, 0x2d, 0x04, 0x3c, 0x06, 0x5d, 0x01, 0x70,
+0x01, 0x70, 0x05, 0x66, 0x01, 0x15, 0x01, 0x66, 0x07, 0x15, 0x07, 0x19,
+0x08, 0x0e, 0x03, 0x6f, 0x04, 0x4f, 0x03, 0x35, 0x04, 0x45, 0x03, 0x1c,
+0x03, 0x5b, 0x00, 0x06, 0x3a, 0x3a, 0x28, 0x3a, 0x28, 0x28, 0x03, 0x2f,
+0x03, 0x51, 0x03, 0x39, 0x04, 0x1b, 0x04, 0x1a, 0x00, 0x03, 0x31, 0x31,
+0x1c, 0x00, 0x03, 0xd3, 0x00, 0x06, 0x89, 0xe5, 0x7e, 0x00, 0x00, 0x03,
+0x26, 0x00, 0x00, 0x08, 0x8e, 0x1f, 0xdc, 0xe4, 0xe4, 0x3b, 0x25, 0x25,
+0x06, 0x43, 0x00, 0x03, 0x3b, 0x43, 0x43, 0x00, 0x05, 0x3b, 0x0b, 0x24,
+0x04, 0x2b, 0x00, 0x03, 0x34, 0x2b, 0x2b, 0x00, 0x08, 0x34, 0x01, 0x3f,
+0x03, 0x33, 0x01, 0xe4, 0x01, 0x68, 0x25, 0x00, 0x00, 0x06, 0x0d, 0xf8,
+0xef, 0xe4, 0x4b, 0x36, 0x0a, 0x42, 0x03, 0x34, 0x01, 0x42, 0x0c, 0x34,
+0x07, 0x2b, 0x00, 0x03, 0x24, 0x2b, 0x2b, 0x00, 0x08, 0x24, 0x00, 0x08,
+0x3b, 0xef, 0x24, 0xfb, 0x5e, 0xde, 0x4c, 0xfa, 0x65, 0x00, 0x00, 0x00,
+0x3e, 0x00, 0x00, 0x07, 0x71, 0xf4, 0x9c, 0x6f, 0x4f, 0x66, 0x9e, 0x00,
+0x14, 0x0b, 0x06, 0x2d, 0x04, 0x3c, 0x06, 0x5d, 0x05, 0x70, 0x00, 0x05,
+0x66, 0x66, 0x15, 0x66, 0x66, 0x00, 0x07, 0x15, 0x07, 0x19, 0x07, 0x0e,
+0x00, 0x03, 0x4f, 0x6f, 0x6f, 0x00, 0x03, 0x4f, 0x03, 0x35, 0x00, 0x0a,
+0x45, 0x45, 0x35, 0x35, 0x45, 0x1c, 0x1c, 0x5b, 0x1c, 0x5b, 0x03, 0x3a,
+0x03, 0x28, 0x04, 0x2f, 0x03, 0x51, 0x01, 0x39, 0x01, 0x39, 0x04, 0x1b,
+0x06, 0x1a, 0x00, 0x0b, 0x31, 0xac, 0x9c, 0xd3, 0xd3, 0xce, 0x93, 0x99,
+0x00, 0x00, 0x03, 0x00, 0x27, 0x00, 0x00, 0x07, 0xec, 0x61, 0xe4, 0x4b,
+0xe4, 0x3b, 0x25, 0x00, 0x07, 0x43, 0x05, 0x3b, 0x01, 0x24, 0x01, 0x3b,
+0x07, 0x24, 0x04, 0x2b, 0x00, 0x05, 0x34, 0x2b, 0x2b, 0x34, 0x2b, 0x00,
+0x09, 0x34, 0x00, 0x09, 0x42, 0x34, 0x34, 0x33, 0xd5, 0xd5, 0x33, 0xbc,
+0x71, 0x00, 0x25, 0x00, 0x00, 0x06, 0x90, 0xe4, 0xe4, 0x33, 0x4b, 0x3f,
+0x0e, 0x42, 0x01, 0x34, 0x04, 0x42, 0x09, 0x34, 0x01, 0x2b, 0x01, 0x34,
+0x06, 0x2b, 0x08, 0x24, 0x00, 0x08, 0x3b, 0x3b, 0xc6, 0x50, 0xf2, 0x4c,
+0x55, 0xd2, 0x64, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x09, 0x4d, 0x00,
+0x69, 0x9c, 0xd3, 0x0e, 0xd3, 0x2d, 0x9e, 0x00, 0x12, 0x0b, 0x07, 0x2d,
+0x03, 0x3c, 0x07, 0x5d, 0x00, 0x03, 0x70, 0x70, 0x5d, 0x00, 0x06, 0x66,
+0x06, 0x15, 0x08, 0x19, 0x01, 0x0e, 0x01, 0x19, 0x05, 0x0e, 0x00, 0x06,
+0x4f, 0x6f, 0x6f, 0x4f, 0x4f, 0x6f, 0x04, 0x35, 0x00, 0x04, 0x45, 0x45,
+0x35, 0x45, 0x03, 0x1c, 0x01, 0x5b, 0x01, 0x5b, 0x03, 0x3a, 0x01, 0x28,
+0x01, 0x28, 0x04, 0x2f, 0x04, 0x51, 0x03, 0x39, 0x04, 0x1b, 0x04, 0x1a,
+0x00, 0x03, 0x2c, 0x1a, 0xac, 0x00, 0x03, 0x9c, 0x00, 0x06, 0x89, 0xee,
+0xb2, 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x05, 0x68, 0xe4, 0x33, 0x33,
+0x4b, 0x00, 0x06, 0x43, 0x07, 0x3b, 0x06, 0x24, 0x00, 0x06, 0x2b, 0x24,
+0x2b, 0x2b, 0x24, 0x34, 0x04, 0x2b, 0x08, 0x34, 0x01, 0x42, 0x01, 0x34,
+0x04, 0x42, 0x00, 0x07, 0x34, 0x4b, 0xab, 0xab, 0xd5, 0xd5, 0xec, 0x00,
+0x25, 0x00, 0x00, 0x0b, 0x6b, 0xe1, 0xe4, 0x33, 0xd5, 0x4b, 0x42, 0x3f,
+0x3f, 0x42, 0x3f, 0x00, 0x0e, 0x42, 0x03, 0x34, 0x01, 0x42, 0x01, 0x42,
+0x07, 0x34, 0x09, 0x2b, 0x05, 0x24, 0x00, 0x07, 0x25, 0xdf, 0x49, 0xf2,
+0x4c, 0xbc, 0x7d, 0x00, 0x64, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x0a,
+0x26, 0x00, 0x8e, 0x82, 0x89, 0x0e, 0xd3, 0x5d, 0x9e, 0xba, 0x09, 0x0b,
+0x01, 0xba, 0x05, 0x0b, 0x09, 0x2d, 0x03, 0x3c, 0x06, 0x5d, 0x04, 0x70,
+0x05, 0x66, 0x07, 0x15, 0x07, 0x19, 0x08, 0x0e, 0x01, 0x6f, 0x01, 0x6f,
+0x03, 0x4f, 0x03, 0x35, 0x05, 0x45, 0x04, 0x1c, 0x01, 0x5b, 0x03, 0x3a,
+0x03, 0x28, 0x04, 0x2f, 0x04, 0x51, 0x03, 0x39, 0x03, 0x1b, 0x04, 0x1a,
+0x00, 0x09, 0x31, 0x1a, 0xd3, 0x89, 0x9c, 0x89, 0xce, 0xed, 0x75, 0x00,
+0x2b, 0x00, 0x00, 0x06, 0x4d, 0x4e, 0x4b, 0xd5, 0xd5, 0x4b, 0x06, 0x43,
+0x06, 0x3b, 0x05, 0x24, 0x0a, 0x2b, 0x0a, 0x34, 0x01, 0x42, 0x01, 0x34,
+0x05, 0x42, 0x01, 0x3f, 0x04, 0xab, 0x01, 0x48, 0x26, 0x00, 0x01, 0xeb,
+0x01, 0x4b, 0x03, 0xd5, 0x0b, 0x3f, 0x0c, 0x42, 0x0a, 0x34, 0x08, 0x2b,
+0x04, 0x24, 0x00, 0x08, 0x3b, 0x24, 0x38, 0xf2, 0x41, 0x10, 0x64, 0x71,
+0x63, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x07, 0x03, 0x00, 0xcf, 0x89,
+0xd3, 0xd3, 0x70, 0x00, 0x07, 0x0b, 0x01, 0xba, 0x0a, 0x0b, 0x07, 0x2d,
+0x04, 0x3c, 0x06, 0x5d, 0x01, 0x70, 0x01, 0x70, 0x04, 0x66, 0x01, 0x15,
+0x01, 0x66, 0x08, 0x15, 0x06, 0x19, 0x08, 0x0e, 0x03, 0x6f, 0x03, 0x4f,
+0x03, 0x35, 0x04, 0x45, 0x05, 0x1c, 0x00, 0x03, 0x5b, 0x3a, 0x3a, 0x00,
+0x03, 0x28, 0x04, 0x2f, 0x01, 0x51, 0x01, 0x51, 0x03, 0x39, 0x04, 0x1b,
+0x05, 0x1a, 0x00, 0x03, 0x2c, 0x1a, 0xd3, 0x00, 0x03, 0x89, 0x00, 0x03,
+0xce, 0xa5, 0x7c, 0x00, 0x2c, 0x00, 0x00, 0x0a, 0xd2, 0xc8, 0xd5, 0xab,
+0xab, 0x36, 0x43, 0x43, 0x3b, 0x43, 0x06, 0x3b, 0x06, 0x24, 0x08, 0x2b,
+0x06, 0x34, 0x01, 0x42, 0x05, 0x34, 0x09, 0x42, 0x00, 0x06, 0xd5, 0xd1,
+0xd1, 0xab, 0xc8, 0xd2, 0x25, 0x00, 0x00, 0x06, 0xad, 0xd5, 0xd5, 0xab,
+0xab, 0x4b, 0x0c, 0x3f, 0x00, 0x03, 0x42, 0x3f, 0x3f, 0x00, 0x09, 0x42,
+0x0a, 0x34, 0x0a, 0x2b, 0x00, 0x08, 0x24, 0x3b, 0xdf, 0x4c, 0x4c, 0x10,
+0xbc, 0xec, 0x63, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x09, 0x03, 0x00,
+0x9a, 0x93, 0x89, 0x9c, 0x9c, 0xba, 0x9e, 0x00, 0x0d, 0x0b, 0x00, 0x03,
+0x2d, 0x0b, 0x0b, 0x00, 0x06, 0x2d, 0x04, 0x3c, 0x06, 0x5d, 0x04, 0x70,
+0x05, 0x66, 0x07, 0x15, 0x06, 0x19, 0x08, 0x0e, 0x03, 0x6f, 0x00, 0x03,
+0x4f, 0x6f, 0x4f, 0x00, 0x03, 0x35, 0x04, 0x45, 0x04, 0x1c, 0x00, 0x08,
+0x5b, 0x28, 0x3a, 0x3a, 0x28, 0x3a, 0x28, 0x28, 0x03, 0x2f, 0x03, 0x51,
+0x01, 0x39, 0x01, 0x39, 0x05, 0x1b, 0x04, 0x1a, 0x00, 0x03, 0x2c, 0x1b,
+0xae, 0x00, 0x03, 0x89, 0x00, 0x03, 0xce, 0x82, 0x7c, 0x00, 0x2d, 0x00,
+0x01, 0xd9, 0x04, 0xab, 0x00, 0x04, 0x2b, 0x25, 0x3b, 0x43, 0x04, 0x3b,
+0x07, 0x24, 0x07, 0x2b, 0x09, 0x34, 0x0b, 0x42, 0x03, 0x3f, 0x01, 0x42,
+0x01, 0x61, 0x04, 0xd1, 0x01, 0x90, 0x25, 0x00, 0x00, 0x09, 0x0d, 0xf2,
+0xd5, 0xab, 0xab, 0xd5, 0x3f, 0x3f, 0x36, 0x00, 0x0f, 0x3f, 0x08, 0x42,
+0x03, 0x34, 0x01, 0x42, 0x08, 0x34, 0x07, 0x2b, 0x00, 0x07, 0x3b, 0x34,
+0x1d, 0x41, 0xbc, 0xc8, 0xeb, 0x00, 0x63, 0x00, 0x00, 0x00, 0x41, 0x00,
+0x00, 0x05, 0xf4, 0xce, 0x9c, 0x9c, 0x3c, 0x00, 0x10, 0x0b, 0x06, 0x2d,
+0x04, 0x3c, 0x07, 0x5d, 0x03, 0x70, 0x03, 0x66, 0x09, 0x15, 0x06, 0x19,
+0x08, 0x0e, 0x03, 0x6f, 0x03, 0x4f, 0x00, 0x03, 0x45, 0x35, 0x35, 0x00,
+0x04, 0x45, 0x04, 0x1c, 0x03, 0x5b, 0x01, 0x3a, 0x04, 0x28, 0x03, 0x2f,
+0x03, 0x51, 0x03, 0x39, 0x03, 0x1b, 0x05, 0x1a, 0x00, 0x03, 0x2c, 0x1b,
+0x9c, 0x00, 0x03, 0x89, 0x00, 0x03, 0xce, 0xb8, 0x8e, 0x00, 0x2e, 0x00,
+0x00, 0x07, 0x5f, 0xab, 0xab, 0xd1, 0xab, 0x3b, 0x25, 0x00, 0x04, 0x3b,
+0x08, 0x24, 0x07, 0x2b, 0x06, 0x34, 0x01, 0x42, 0x01, 0x42, 0x03, 0x34,
+0x07, 0x42, 0x08, 0x3f, 0x00, 0x06, 0xc7, 0xc8, 0xc8, 0xab, 0xde, 0x4d,
+0x25, 0x00, 0x01, 0xd9, 0x04, 0xab, 0x01, 0x36, 0x01, 0x3f, 0x05, 0x36,
+0x01, 0x3f, 0x01, 0x36, 0x0c, 0x3f, 0x09, 0x42, 0x00, 0x03, 0x34, 0x42,
+0x42, 0x00, 0x06, 0x34, 0x06, 0x2b, 0x00, 0x0a, 0x34, 0x3b, 0xc7, 0xbc,
+0xbc, 0xc8, 0x41, 0xe7, 0x00, 0x0d, 0x60, 0x00, 0x00, 0x00, 0x41, 0x00,
+0x00, 0x06, 0x7e, 0xd3, 0xce, 0x9c, 0x89, 0xba, 0x0d, 0x0b, 0x08, 0x2d,
+0x03, 0x3c, 0x07, 0x5d, 0x03, 0x70, 0x03, 0x66, 0x01, 0x15, 0x01, 0x66,
+0x08, 0x15, 0x06, 0x19, 0x07, 0x0e, 0x00, 0x03, 0x4f, 0x6f, 0x6f, 0x00,
+0x03, 0x4f, 0x04, 0x35, 0x03, 0x45, 0x04, 0x1c, 0x01, 0x5b, 0x05, 0x3a,
+0x01, 0x28, 0x04, 0x2f, 0x03, 0x51, 0x01, 0x39, 0x05, 0x1b, 0x05, 0x1a,
+0x00, 0x03, 0x2c, 0x2f, 0x9c, 0x00, 0x03, 0x89, 0x00, 0x06, 0xce, 0xf4,
+0x71, 0x00, 0x00, 0x0d, 0x2b, 0x00, 0x00, 0x07, 0xd2, 0xc8, 0xab, 0xd1,
+0xd1, 0x61, 0x25, 0x00, 0x04, 0x3b, 0x07, 0x24, 0x00, 0x03, 0x2b, 0x2b,
+0x34, 0x00, 0x03, 0x2b, 0x09, 0x34, 0x08, 0x42, 0x0b, 0x3f, 0x01, 0x42,
+0x01, 0xc7, 0x04, 0xc8, 0x01, 0xd9, 0x25, 0x00, 0x00, 0x07, 0x6b, 0xbc,
+0xab, 0xd1, 0xd1, 0xd5, 0x3f, 0x00, 0x0a, 0x36, 0x01, 0x3f, 0x01, 0x36,
+0x0b, 0x3f, 0x0a, 0x42, 0x07, 0x34, 0x00, 0x0b, 0x2b, 0x34, 0x2b, 0x2b,
+0x3b, 0x3f, 0xdd, 0xbc, 0xdd, 0xc8, 0xfa, 0x00, 0x62, 0x00, 0x00, 0x00,
+0x42, 0x00, 0x00, 0x05, 0xa5, 0xce, 0x89, 0x89, 0xba, 0x00, 0x0d, 0x0b,
+0x07, 0x2d, 0x03, 0x3c, 0x00, 0x03, 0x5d, 0x5d, 0x3c, 0x00, 0x04, 0x5d,
+0x00, 0x03, 0x70, 0x66, 0x70, 0x00, 0x03, 0x66, 0x09, 0x15, 0x08, 0x19,
+0x06, 0x0e, 0x00, 0x03, 0x4f, 0x6f, 0x6f, 0x00, 0x03, 0x4f, 0x04, 0x35,
+0x04, 0x45, 0x03, 0x1c, 0x01, 0x5b, 0x03, 0x3a, 0x03, 0x28, 0x03, 0x2f,
+0x04, 0x51, 0x01, 0x39, 0x01, 0x39, 0x05, 0x1b, 0x04, 0x1a, 0x00, 0x03,
+0x2c, 0x2f, 0x9c, 0x00, 0x03, 0x89, 0x01, 0xce, 0x01, 0xd4, 0x30, 0x00,
+0x00, 0x08, 0x90, 0xd1, 0xd1, 0xc8, 0xd1, 0x34, 0x25, 0x3b, 0x08, 0x24,
+0x04, 0x2b, 0x08, 0x34, 0x00, 0x03, 0x42, 0x34, 0x34, 0x00, 0x08, 0x42,
+0x0b, 0x3f, 0x00, 0x09, 0x36, 0x3f, 0x3f, 0x36, 0xe1, 0xdd, 0xdd, 0xd1,
+0x9d, 0x00, 0x26, 0x00, 0x01, 0x68, 0x01, 0xab, 0x03, 0xd1, 0x10, 0x36,
+0x0b, 0x3f, 0x09, 0x42, 0x07, 0x34, 0x03, 0x2b, 0x00, 0x09, 0x3b, 0xc7,
+0xdd, 0xdd, 0xc8, 0xf2, 0xd2, 0x00, 0x03, 0x00, 0x5f, 0x00, 0x00, 0x00,
+0x42, 0x00, 0x00, 0x06, 0xf1, 0xce, 0xce, 0x89, 0x89, 0xba, 0x0c, 0x0b,
+0x04, 0x2d, 0x00, 0x03, 0x3c, 0x2d, 0x2d, 0x00, 0x03, 0x3c, 0x06, 0x5d,
+0x01, 0x70, 0x01, 0x70, 0x05, 0x66, 0x09, 0x15, 0x07, 0x19, 0x06, 0x0e,
+0x01, 0x4f, 0x03, 0x6f, 0x01, 0x4f, 0x01, 0x4f, 0x04, 0x35, 0x03, 0x45,
+0x05, 0x1c, 0x01, 0x5b, 0x03, 0x3a, 0x03, 0x28, 0x03, 0x2f, 0x03, 0x51,
+0x03, 0x39, 0x04, 0x1b, 0x04, 0x1a, 0x00, 0x08, 0x2c, 0x2f, 0x9c, 0x89,
+0x9c, 0x89, 0xce, 0xf7, 0x30, 0x00, 0x00, 0x08, 0x71, 0xf2, 0xd1, 0xc8,
+0xdd, 0xc7, 0x3b, 0x3b, 0x07, 0x24, 0x06, 0x2b, 0x07, 0x34, 0x09, 0x42,
+0x0a, 0x3f, 0x03, 0x36, 0x01, 0x3f, 0x03, 0x36, 0x01, 0xe4, 0x01, 0xc7,
+0x03, 0xdd, 0x00, 0x04, 0x4c, 0xe7, 0x00, 0x11, 0x23, 0x00, 0x00, 0x09,
+0xad, 0xdd, 0xd1, 0xc8, 0xc8, 0xc7, 0x3f, 0x61, 0x61, 0x00, 0x0b, 0x36,
+0x01, 0x3f, 0x04, 0x36, 0x09, 0x3f, 0x07, 0x42, 0x01, 0x34, 0x03, 0x42,
+0x05, 0x34, 0x00, 0x0a, 0x2b, 0x3b, 0x61, 0xc8, 0xdd, 0xc8, 0xd1, 0x7d,
+0x00, 0x11, 0x5f, 0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x06, 0x8e, 0x15,
+0xce, 0x89, 0x89, 0xba, 0x05, 0x0b, 0x01, 0xba, 0x01, 0xba, 0x03, 0x0b,
+0x08, 0x2d, 0x04, 0x3c, 0x06, 0x5d, 0x00, 0x03, 0x66, 0x70, 0x70, 0x00,
+0x03, 0x66, 0x0a, 0x15, 0x06, 0x19, 0x06, 0x0e, 0x01, 0x4f, 0x01, 0x4f,
+0x03, 0x6f, 0x01, 0x4f, 0x04, 0x35, 0x03, 0x45, 0x01, 0x1c, 0x01, 0x1c,
+0x04, 0x5b, 0x00, 0x03, 0x3a, 0x5b, 0x3a, 0x00, 0x03, 0x28, 0x03, 0x2f,
+0x03, 0x51, 0x00, 0x03, 0x39, 0x1b, 0x39, 0x00, 0x03, 0x1b, 0x05, 0x1a,
+0x00, 0x08, 0x2c, 0x2f, 0xae, 0x9c, 0x9c, 0x89, 0x89, 0x8a, 0x31, 0x00,
+0x00, 0x07, 0x7d, 0xdd, 0xc8, 0xdd, 0xdd, 0xdf, 0x25, 0x00, 0x06, 0x24,
+0x06, 0x2b, 0x06, 0x34, 0x00, 0x03, 0x42, 0x34, 0x34, 0x00, 0x06, 0x42,
+0x0a, 0x3f, 0x0b, 0x36, 0x00, 0x08, 0x61, 0xdd, 0xbc, 0xbc, 0xc8, 0x68,
+0x00, 0x0d, 0x24, 0x00, 0x00, 0x06, 0xeb, 0xab, 0xc8, 0xc8, 0xd1, 0x36,
+0x08, 0x61, 0x0c, 0x36, 0x0a, 0x3f, 0x09, 0x42, 0x05, 0x34, 0x00, 0x08,
+0x2b, 0x2b, 0xc6, 0xc8, 0xc8, 0xab, 0x64, 0xa3, 0x60, 0x00, 0x00, 0x00,
+0x43, 0x00, 0x01, 0xd4, 0x01, 0xce, 0x03, 0x89, 0x0a, 0x0b, 0x07, 0x2d,
+0x05, 0x3c, 0x05, 0x5d, 0x04, 0x70, 0x03, 0x66, 0x08, 0x15, 0x08, 0x19,
+0x06, 0x0e, 0x00, 0x03, 0x4f, 0x6f, 0x6f, 0x00, 0x03, 0x4f, 0x03, 0x35,
+0x04, 0x45, 0x01, 0x1c, 0x01, 0x1c, 0x03, 0x5b, 0x03, 0x3a, 0x01, 0x28,
+0x01, 0x28, 0x04, 0x2f, 0x03, 0x51, 0x03, 0x39, 0x01, 0x1b, 0x07, 0x1a,
+0x01, 0x31, 0x01, 0x2f, 0x03, 0xae, 0x00, 0x06, 0x89, 0x9c, 0xea, 0x00,
+0x00, 0x03, 0x2c, 0x00, 0x00, 0x0a, 0x0d, 0x00, 0x4d, 0x4e, 0xc8, 0xdd,
+0xdd, 0xe1, 0x24, 0x3b, 0x04, 0x24, 0x06, 0x2b, 0x05, 0x34, 0x00, 0x03,
+0x42, 0x34, 0x34, 0x00, 0x09, 0x42, 0x07, 0x3f, 0x0b, 0x36, 0x00, 0x0a,
+0x61, 0x61, 0x36, 0x36, 0xe1, 0xbc, 0xbc, 0xdd, 0x4e, 0xd2, 0x23, 0x00,
+0x00, 0x09, 0x11, 0x00, 0xd9, 0xc8, 0xc8, 0xdd, 0xc8, 0x33, 0x36, 0x00,
+0x0b, 0x61, 0x0c, 0x36, 0x09, 0x3f, 0x06, 0x42, 0x00, 0x03, 0x34, 0x42,
+0x42, 0x00, 0x03, 0x34, 0x00, 0x07, 0x24, 0x61, 0xc8, 0xc8, 0xd1, 0xd1,
+0xec, 0x00, 0x60, 0x00, 0x00, 0x00, 0x43, 0x00, 0x00, 0x06, 0xb1, 0x89,
+0x89, 0x9c, 0x9c, 0xba, 0x09, 0x0b, 0x06, 0x2d, 0x04, 0x3c, 0x01, 0x5d,
+0x01, 0x3c, 0x04, 0x5d, 0x03, 0x70, 0x05, 0x66, 0x07, 0x15, 0x07, 0x19,
+0x07, 0x0e, 0x01, 0x4f, 0x03, 0x6f, 0x01, 0x4f, 0x04, 0x35, 0x04, 0x45,
+0x04, 0x1c, 0x01, 0x5b, 0x03, 0x3a, 0x03, 0x28, 0x03, 0x2f, 0x03, 0x51,
+0x04, 0x39, 0x01, 0x1b, 0x01, 0x1b, 0x05, 0x1a, 0x01, 0x31, 0x01, 0xbe,
+0x03, 0xae, 0x00, 0x06, 0x9c, 0xd3, 0xf1, 0x00, 0x00, 0x26, 0x2d, 0x00,
+0x00, 0x09, 0x03, 0x00, 0xd9, 0x47, 0xdd, 0x10, 0xbc, 0xc7, 0x43, 0x00,
+0x04, 0x24, 0x00, 0x05, 0x2b, 0x2b, 0x34, 0x2b, 0x2b, 0x00, 0x06, 0x34,
+0x09, 0x42, 0x08, 0x3f, 0x0c, 0x36, 0x04, 0x61, 0x00, 0x08, 0x36, 0x36,
+0xc7, 0xbc, 0x41, 0xbc, 0x10, 0xd9, 0x25, 0x00, 0x00, 0x0a, 0x71, 0x4e,
+0xd1, 0xdd, 0xdd, 0xc7, 0x36, 0x61, 0x4b, 0x4b, 0x05, 0x61, 0x01, 0x36,
+0x03, 0x61, 0x00, 0x03, 0x36, 0x61, 0x61, 0x00, 0x0b, 0x36, 0x08, 0x3f,
+0x08, 0x42, 0x00, 0x04, 0x34, 0x34, 0x2b, 0x34, 0x03, 0xd1, 0x01, 0xab,
+0x01, 0xeb, 0x60, 0x00, 0x00, 0x00, 0x43, 0x00, 0x00, 0x03, 0x71, 0xb8,
+0xce, 0x00, 0x03, 0x9c, 0x08, 0x0b, 0x07, 0x2d, 0x03, 0x3c, 0x07, 0x5d,
+0x03, 0x70, 0x03, 0x66, 0x01, 0x15, 0x01, 0x66, 0x06, 0x15, 0x07, 0x19,
+0x07, 0x0e, 0x01, 0x4f, 0x03, 0x6f, 0x01, 0x4f, 0x01, 0x4f, 0x04, 0x35,
+0x03, 0x45, 0x04, 0x1c, 0x01, 0x5b, 0x03, 0x3a, 0x03, 0x28, 0x00, 0x03,
+0x2f, 0x28, 0x2f, 0x00, 0x03, 0x51, 0x03, 0x39, 0x03, 0x1b, 0x05, 0x1a,
+0x00, 0x0b, 0x31, 0xbe, 0xcb, 0xae, 0xcb, 0x9c, 0x3a, 0x69, 0x00, 0x00,
+0x03, 0x00, 0x2d, 0x00, 0x00, 0x0b, 0x11, 0x00, 0x6b, 0x64, 0xdd, 0xbc,
+0xbc, 0x1d, 0x24, 0x3b, 0x24, 0x00, 0x07, 0x2b, 0x06, 0x34, 0x08, 0x42,
+0x07, 0x3f, 0x00, 0x03, 0x36, 0x36, 0x3f, 0x00, 0x08, 0x36, 0x06, 0x61,
+0x00, 0x0b, 0x4b, 0x61, 0x61, 0x36, 0x36, 0x58, 0xf2, 0x49, 0xbc, 0xeb,
+0xa3, 0x00, 0x23, 0x00, 0x00, 0x08, 0x0d, 0x00, 0x7d, 0xdd, 0xdd, 0x10,
+0xdd, 0x33, 0x03, 0x4b, 0x01, 0x61, 0x03, 0x4b, 0x00, 0x05, 0x61, 0x4b,
+0x61, 0x61, 0x4b, 0x00, 0x03, 0x61, 0x01, 0x36, 0x01, 0x61, 0x0b, 0x36,
+0x08, 0x3f, 0x06, 0x42, 0x04, 0x34, 0x00, 0x06, 0x33, 0xd1, 0xab, 0xab,
+0xd1, 0xad, 0x5f, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0x69, 0x89,
+0x9c, 0xae, 0xae, 0xba, 0x9e, 0xba, 0x04, 0x0b, 0x07, 0x2d, 0x04, 0x3c,
+0x05, 0x5d, 0x00, 0x07, 0x70, 0x5d, 0x70, 0x66, 0x70, 0x66, 0x66, 0x00,
+0x09, 0x15, 0x07, 0x19, 0x07, 0x0e, 0x03, 0x6f, 0x03, 0x4f, 0x03, 0x35,
+0x03, 0x45, 0x04, 0x1c, 0x03, 0x5b, 0x01, 0x3a, 0x03, 0x28, 0x03, 0x2f,
+0x04, 0x51, 0x01, 0x39, 0x01, 0x39, 0x04, 0x1b, 0x05, 0x1a, 0x01, 0xbe,
+0x03, 0xcb, 0x00, 0x03, 0x9c, 0x51, 0x7e, 0x00, 0x33, 0x00, 0x00, 0x09,
+0x7d, 0xdd, 0xbc, 0x41, 0x4c, 0xe0, 0x43, 0x24, 0x24, 0x00, 0x0d, 0x34,
+0x0b, 0x42, 0x00, 0x03, 0x3f, 0x3f, 0xe4, 0x00, 0x09, 0x36, 0x0c, 0x61,
+0x00, 0x08, 0x4b, 0x36, 0xc7, 0xf2, 0xf2, 0x49, 0x49, 0xe7, 0x25, 0x00,
+0x00, 0x07, 0x6b, 0xde, 0xc8, 0x10, 0xbc, 0xc7, 0x36, 0x00, 0x06, 0x4b,
+0x00, 0x05, 0x61, 0x4b, 0x61, 0x61, 0x4b, 0x00, 0x08, 0x61, 0x09, 0x36,
+0x09, 0x3f, 0x06, 0x42, 0x00, 0x03, 0x34, 0x2b, 0x3f, 0x00, 0x03, 0xab,
+0x01, 0xd5, 0x01, 0xfa, 0x5f, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x07,
+0x7c, 0x63, 0x9c, 0xcb, 0xae, 0x9c, 0x9e, 0x00, 0x04, 0x0b, 0x07, 0x2d,
+0x04, 0x3c, 0x07, 0x5d, 0x01, 0x70, 0x01, 0x70, 0x04, 0x66, 0x0a, 0x15,
+0x06, 0x19, 0x06, 0x0e, 0x00, 0x03, 0x4f, 0x6f, 0x6f, 0x00, 0x03, 0x4f,
+0x03, 0x35, 0x03, 0x45, 0x03, 0x1c, 0x03, 0x5b, 0x01, 0x3a, 0x01, 0x3a,
+0x03, 0x28, 0x03, 0x2f, 0x03, 0x51, 0x03, 0x39, 0x04, 0x1b, 0x05, 0x1a,
+0x00, 0x07, 0xbe, 0xcb, 0xcb, 0xbe, 0xae, 0xf0, 0x7e, 0x00, 0x33, 0x00,
+0x00, 0x08, 0xad, 0x4e, 0xf2, 0x50, 0x64, 0xfb, 0xca, 0xc0, 0x0e, 0xca,
+0x0e, 0xdf, 0x07, 0x61, 0x01, 0x36, 0x01, 0x61, 0x06, 0x36, 0x09, 0x4b,
+0x00, 0x06, 0x33, 0x41, 0x50, 0xf2, 0x41, 0x68, 0x26, 0x00, 0x00, 0x06,
+0xfa, 0xdd, 0x10, 0xbc, 0xe1, 0x33, 0x0c, 0x4b, 0x0a, 0x61, 0x07, 0x36,
+0x00, 0x03, 0x3f, 0x36, 0x36, 0x00, 0x06, 0x3f, 0x06, 0x42, 0x00, 0x08,
+0x34, 0x34, 0xd5, 0xab, 0xab, 0xd5, 0xdd, 0x71, 0x5e, 0x00, 0x00, 0x00,
+0x43, 0x00, 0x00, 0x07, 0x11, 0x00, 0xcf, 0x89, 0xcb, 0xcb, 0xae, 0x00,
+0x05, 0x0b, 0x08, 0x2d, 0x03, 0x3c, 0x06, 0x5d, 0x03, 0x70, 0x04, 0x66,
+0x08, 0x15, 0x06, 0x19, 0x07, 0x0e, 0x03, 0x6f, 0x03, 0x4f, 0x04, 0x35,
+0x03, 0x45, 0x04, 0x1c, 0x01, 0x5b, 0x04, 0x3a, 0x01, 0x28, 0x04, 0x2f,
+0x03, 0x51, 0x03, 0x39, 0x01, 0x1b, 0x01, 0x1b, 0x05, 0x1a, 0x01, 0x31,
+0x01, 0xcd, 0x03, 0xbe, 0x00, 0x06, 0xae, 0xf0, 0xb2, 0x00, 0x00, 0x03,
+0x30, 0x00, 0x00, 0x0c, 0x0d, 0x90, 0x50, 0x56, 0x5f, 0x56, 0xaa, 0x52,
+0x29, 0x29, 0x27, 0x27, 0x08, 0x7b, 0x09, 0x12, 0x01, 0x14, 0x05, 0x12,
+0x03, 0x02, 0x06, 0x5a, 0x06, 0xe0, 0x01, 0xc7, 0x01, 0xc7, 0x04, 0x61,
+0x06, 0x4b, 0x00, 0x06, 0xe1, 0x46, 0x50, 0xf2, 0x4e, 0x6b, 0x25, 0x00,
+0x00, 0x07, 0xad, 0xbc, 0xdd, 0xbc, 0xbc, 0xc7, 0x4b, 0x00, 0x04, 0x33,
+0x0b, 0x4b, 0x03, 0x61, 0x01, 0x4b, 0x03, 0x61, 0x01, 0x36, 0x01, 0x61,
+0x07, 0x36, 0x00, 0x03, 0x3f, 0x3f, 0x36, 0x00, 0x06, 0x3f, 0x04, 0x42,
+0x00, 0x07, 0x2b, 0x4b, 0xab, 0xab, 0xd5, 0xd5, 0xd9, 0x00, 0x5e, 0x00,
+0x00, 0x00, 0x43, 0x00, 0x00, 0x0b, 0x26, 0x00, 0xb2, 0xfc, 0xae, 0xbe,
+0xcb, 0x5d, 0x9e, 0x0b, 0x0b, 0x00, 0x08, 0x2d, 0x04, 0x3c, 0x05, 0x5d,
+0x04, 0x70, 0x04, 0x66, 0x07, 0x15, 0x07, 0x19, 0x07, 0x0e, 0x01, 0x6f,
+0x01, 0x6f, 0x04, 0x4f, 0x01, 0x35, 0x01, 0x35, 0x04, 0x45, 0x03, 0x1c,
+0x01, 0x5b, 0x01, 0x5b, 0x03, 0x3a, 0x00, 0x05, 0x28, 0x3a, 0x28, 0x2f,
+0x2f, 0x00, 0x04, 0x51, 0x01, 0x39, 0x01, 0x39, 0x03, 0x1b, 0x05, 0x1a,
+0x01, 0x31, 0x03, 0xcd, 0x00, 0x07, 0xbe, 0xae, 0x52, 0x9a, 0x00, 0x03,
+0x03, 0x00, 0x31, 0x00, 0x00, 0x08, 0xec, 0x60, 0x4e, 0x56, 0x5f, 0x80,
+0x52, 0x52, 0x04, 0x29, 0x01, 0x27, 0x01, 0x7b, 0x04, 0x27, 0x01, 0x7b,
+0x06, 0x5a, 0x05, 0x12, 0x08, 0x02, 0x07, 0x14, 0x03, 0xaa, 0x01, 0x14,
+0x01, 0x14, 0x03, 0x0c, 0x03, 0x02, 0x01, 0xc6, 0x01, 0xc6, 0x03, 0xe0,
+0x00, 0x07, 0xc7, 0xc6, 0x50, 0x5e, 0xf2, 0xf2, 0xd9, 0x00, 0x26, 0x00,
+0x00, 0x07, 0x9d, 0xdd, 0xbc, 0xf2, 0xe1, 0x4b, 0x4b, 0x00, 0x06, 0x33,
+0x09, 0x4b, 0x01, 0x61, 0x01, 0x4b, 0x03, 0x61, 0x01, 0x36, 0x04, 0x61,
+0x05, 0x36, 0x00, 0x03, 0x3f, 0x36, 0x36, 0x00, 0x07, 0x3f, 0x04, 0x42,
+0x01, 0x3f, 0x03, 0xd5, 0x01, 0x4b, 0x01, 0x55, 0x5e, 0x00, 0x00, 0x00,
+0x46, 0x00, 0x00, 0x08, 0x88, 0xae, 0xbe, 0xbe, 0xd3, 0x9e, 0x0b, 0x0b,
+0x07, 0x2d, 0x03, 0x3c, 0x01, 0x5d, 0x01, 0x3c, 0x05, 0x5d, 0x03, 0x70,
+0x04, 0x66, 0x07, 0x15, 0x07, 0x19, 0x07, 0x0e, 0x03, 0x6f, 0x00, 0x03,
+0x4f, 0x35, 0x4f, 0x00, 0x03, 0x35, 0x04, 0x45, 0x00, 0x07, 0x1c, 0x5b,
+0x1c, 0x1c, 0x5b, 0x3a, 0x3a, 0x00, 0x03, 0x28, 0x03, 0x2f, 0x03, 0x51,
+0x00, 0x07, 0x39, 0x39, 0x1b, 0x39, 0x1b, 0x1b, 0x39, 0x00, 0x03, 0x1a,
+0x01, 0x31, 0x04, 0xcd, 0x00, 0x06, 0xbe, 0xaf, 0x7c, 0x00, 0x00, 0x0d,
+0x31, 0x00, 0x00, 0x0a, 0xd2, 0x9d, 0x60, 0x48, 0x9d, 0x60, 0x12, 0xca,
+0x29, 0x29, 0x05, 0x27, 0x01, 0x7b, 0x01, 0x27, 0x03, 0x7b, 0x00, 0x03,
+0x5a, 0x5a, 0x7b, 0x00, 0x06, 0x12, 0x09, 0x02, 0x0a, 0x14, 0x01, 0x0c,
+0x01, 0x0c, 0x06, 0x20, 0x06, 0xaa, 0x00, 0x08, 0x20, 0x04, 0x78, 0x48,
+0x4e, 0x50, 0xeb, 0x11, 0x25, 0x00, 0x00, 0x07, 0xec, 0xbc, 0xbc, 0xf2,
+0x4c, 0xc7, 0x4b, 0x00, 0x03, 0x33, 0x01, 0x61, 0x06, 0x33, 0x08, 0x4b,
+0x00, 0x03, 0x61, 0x4b, 0x4b, 0x00, 0x07, 0x61, 0x05, 0x36, 0x01, 0x3f,
+0x01, 0x36, 0x08, 0x3f, 0x00, 0x08, 0x42, 0x42, 0x4b, 0xd5, 0x33, 0xe4,
+0xc7, 0xe7, 0x5d, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x04, 0x03, 0x00,
+0x7e, 0x1b, 0x03, 0xbe, 0x01, 0x5d, 0x01, 0x9e, 0x08, 0x2d, 0x03, 0x3c,
+0x01, 0x5d, 0x01, 0x3c, 0x04, 0x5d, 0x03, 0x70, 0x04, 0x66, 0x08, 0x15,
+0x06, 0x19, 0x07, 0x0e, 0x01, 0x4f, 0x03, 0x6f, 0x01, 0x4f, 0x04, 0x35,
+0x04, 0x45, 0x01, 0x1c, 0x01, 0x1c, 0x03, 0x5b, 0x03, 0x3a, 0x01, 0x28,
+0x01, 0x28, 0x03, 0x2f, 0x04, 0x51, 0x01, 0x39, 0x05, 0x1b, 0x00, 0x0b,
+0x1a, 0x1a, 0xfc, 0xfc, 0x25, 0x25, 0x43, 0x43, 0x1a, 0x88, 0x6b, 0x00,
+0x34, 0x00, 0x00, 0x0a, 0x71, 0xfa, 0x64, 0x48, 0x5f, 0x9d, 0xc1, 0x52,
+0x52, 0x29, 0x04, 0x27, 0x01, 0x7b, 0x01, 0x27, 0x04, 0x7b, 0x01, 0x5a,
+0x01, 0x5a, 0x06, 0x12, 0x09, 0x02, 0x0a, 0x14, 0x05, 0x0c, 0x0a, 0x20,
+0x00, 0x09, 0x04, 0x20, 0x0c, 0xf8, 0x4e, 0x4e, 0x5e, 0x4e, 0xe7, 0x00,
+0x25, 0x00, 0x00, 0x07, 0xa3, 0x4e, 0xbc, 0xf2, 0xde, 0xe1, 0x4b, 0x00,
+0x0c, 0x33, 0x09, 0x4b, 0x09, 0x61, 0x07, 0x36, 0x07, 0x3f, 0x00, 0x07,
+0x42, 0x3f, 0x33, 0x33, 0x4b, 0xe4, 0xa7, 0x00, 0x5d, 0x00, 0x00, 0x00,
+0x46, 0x00, 0x00, 0x07, 0x03, 0xb4, 0xcb, 0xcd, 0xcd, 0xd3, 0x9e, 0x00,
+0x07, 0x2d, 0x04, 0x3c, 0x06, 0x5d, 0x01, 0x70, 0x01, 0x70, 0x04, 0x66,
+0x08, 0x15, 0x07, 0x19, 0x06, 0x0e, 0x01, 0x4f, 0x03, 0x6f, 0x03, 0x4f,
+0x01, 0x35, 0x01, 0x35, 0x04, 0x45, 0x01, 0x1c, 0x01, 0x1c, 0x03, 0x5b,
+0x01, 0x3a, 0x01, 0x3a, 0x04, 0x28, 0x03, 0x2f, 0x01, 0x51, 0x03, 0x2f,
+0x01, 0x39, 0x03, 0xfc, 0x00, 0x0c, 0xc3, 0xf0, 0xf0, 0x76, 0xb9, 0xc0,
+0xc0, 0x37, 0xc0, 0xf0, 0xf7, 0x71, 0x35, 0x00, 0x00, 0x09, 0x7d, 0x60,
+0x4e, 0x48, 0x5f, 0x80, 0x29, 0x52, 0x29, 0x00, 0x04, 0x27, 0x00, 0x03,
+0x7b, 0x7b, 0x27, 0x00, 0x03, 0x7b, 0x01, 0x5a, 0x06, 0x12, 0x0a, 0x02,
+0x09, 0x14, 0x07, 0x0c, 0x06, 0x20, 0x07, 0x04, 0x00, 0x06, 0x62, 0x78,
+0x64, 0x5e, 0x78, 0xfa, 0x26, 0x00, 0x00, 0x05, 0x7d, 0xbc, 0xf2, 0x50,
+0xbc, 0x00, 0x11, 0x33, 0x08, 0x4b, 0x04, 0x61, 0x01, 0x4b, 0x03, 0x61,
+0x06, 0x36, 0x01, 0x3f, 0x01, 0x36, 0x06, 0x3f, 0x00, 0x08, 0x36, 0x4b,
+0x4b, 0xdc, 0xc6, 0x8e, 0x00, 0x0d, 0x5a, 0x00, 0x00, 0x00, 0x47, 0x00,
+0x00, 0x07, 0xd0, 0xcd, 0xbe, 0xef, 0xbe, 0x3c, 0x0b, 0x00, 0x06, 0x2d,
+0x03, 0x3c, 0x06, 0x5d, 0x03, 0x70, 0x04, 0x66, 0x08, 0x15, 0x06, 0x19,
+0x07, 0x0e, 0x00, 0x03, 0x4f, 0x6f, 0x6f, 0x00, 0x03, 0x4f, 0x03, 0x35,
+0x04, 0x45, 0x00, 0x12, 0x1c, 0x1c, 0x5b, 0x5b, 0x3a, 0x3a, 0x28, 0x28,
+0x5b, 0x28, 0x28, 0x2f, 0x2f, 0x51, 0x17, 0x0a, 0xc3, 0xc3, 0x03, 0x76,
+0x01, 0x30, 0x03, 0x3e, 0x00, 0x08, 0x59, 0x37, 0x52, 0x52, 0xc0, 0xf0,
+0xcf, 0x71, 0x35, 0x00, 0x00, 0x08, 0xec, 0x60, 0x64, 0x4e, 0x5f, 0x77,
+0x12, 0x52, 0x04, 0x27, 0x04, 0x7b, 0x04, 0x5a, 0x05, 0x12, 0x09, 0x02,
+0x00, 0x04, 0x14, 0x14, 0x02, 0x02, 0x06, 0x14, 0x05, 0x0c, 0x07, 0x20,
+0x0a, 0x04, 0x00, 0x09, 0x0c, 0xf3, 0x5e, 0x50, 0x78, 0x56, 0xad, 0x00,
+0x0d, 0x00, 0x23, 0x00, 0x00, 0x06, 0xad, 0x50, 0xf2, 0x50, 0x50, 0xc7,
+0x13, 0x33, 0x09, 0x4b, 0x05, 0x61, 0x09, 0x36, 0x05, 0x3f, 0x00, 0x07,
+0x36, 0xe4, 0xe4, 0xdc, 0x90, 0x00, 0x11, 0x00, 0x5a, 0x00, 0x00, 0x00,
+0x47, 0x00, 0x00, 0x07, 0x8e, 0xdf, 0xbe, 0xef, 0xef, 0xd3, 0x9e, 0x00,
+0x05, 0x2d, 0x03, 0x3c, 0x07, 0x5d, 0x01, 0x70, 0x01, 0x70, 0x04, 0x66,
+0x09, 0x15, 0x06, 0x19, 0x06, 0x0e, 0x03, 0x6f, 0x03, 0x4f, 0x03, 0x35,
+0x04, 0x45, 0x04, 0x1c, 0x00, 0x0f, 0x5b, 0x3a, 0x5b, 0x28, 0x28, 0x86,
+0x17, 0xc3, 0xc3, 0x76, 0x76, 0x1e, 0x63, 0x63, 0x30, 0x00, 0x05, 0x3e,
+0x00, 0x0b, 0x30, 0x59, 0x52, 0x29, 0x29, 0xca, 0xdf, 0xcf, 0x11, 0x00,
+0x03, 0x00, 0x33, 0x00, 0x00, 0x08, 0xe7, 0x4e, 0x5e, 0x60, 0x4e, 0x46,
+0xaa, 0x52, 0x04, 0x27, 0x00, 0x08, 0x7b, 0x7b, 0x27, 0x7b, 0x7b, 0x5a,
+0x7b, 0x7b, 0x05, 0x12, 0x08, 0x02, 0x08, 0x14, 0x06, 0x0c, 0x06, 0x20,
+0x09, 0x04, 0x00, 0x0e, 0x62, 0x62, 0x04, 0x62, 0x62, 0x04, 0x1f, 0x78,
+0x55, 0x55, 0x41, 0x7d, 0x00, 0x0d, 0x23, 0x00, 0x00, 0x06, 0x11, 0xfa,
+0x4c, 0x5e, 0x46, 0x58, 0x15, 0x33, 0x08, 0x4b, 0x03, 0x61, 0x01, 0x36,
+0x03, 0x61, 0x06, 0x36, 0x05, 0x3f, 0x03, 0xe4, 0x00, 0x05, 0xef, 0x74,
+0x4d, 0x00, 0x03, 0x00, 0x59, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x0c,
+0xcc, 0xcd, 0xef, 0xdc, 0xbe, 0x2d, 0x0b, 0x2d, 0x2d, 0x3c, 0x3c, 0x2d,
+0x03, 0x3c, 0x05, 0x5d, 0x01, 0x70, 0x05, 0x66, 0x0a, 0x15, 0x06, 0x19,
+0x06, 0x0e, 0x01, 0x6f, 0x01, 0x6f, 0x03, 0x4f, 0x07, 0x35, 0x03, 0x1c,
+0x00, 0x0a, 0x5b, 0x3a, 0x86, 0x17, 0xc3, 0x8c, 0x40, 0x40, 0x1e, 0x1e,
+0x05, 0x63, 0x04, 0x30, 0x00, 0x0d, 0x3e, 0x3e, 0x30, 0x5c, 0x27, 0x5a,
+0x5a, 0xdf, 0xca, 0xd0, 0x00, 0x00, 0x11, 0x00, 0x33, 0x00, 0x00, 0x10,
+0xad, 0x56, 0x55, 0x46, 0x64, 0x46, 0xf8, 0x52, 0x27, 0x27, 0x7b, 0x27,
+0x7b, 0x27, 0x7b, 0x7b, 0x03, 0x5a, 0x06, 0x12, 0x07, 0x02, 0x08, 0x14,
+0x01, 0x0c, 0x01, 0x14, 0x04, 0x0c, 0x07, 0x20, 0x07, 0x04, 0x01, 0x62,
+0x03, 0x04, 0x04, 0x62, 0x00, 0x0a, 0x01, 0x04, 0xfb, 0x3d, 0x3d, 0x0f,
+0x9d, 0x6b, 0x00, 0x03, 0x21, 0x00, 0x00, 0x08, 0x11, 0x00, 0xec, 0xf2,
+0xf2, 0x50, 0x4c, 0xd5, 0x17, 0x33, 0x08, 0x4b, 0x06, 0x61, 0x07, 0x36,
+0x00, 0x03, 0x3f, 0x3f, 0x42, 0x00, 0x03, 0xdc, 0x00, 0x04, 0x2b, 0xd9,
+0x00, 0x4d, 0x59, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x07, 0xe7, 0xdc,
+0xef, 0xdc, 0xdc, 0xd3, 0x9e, 0x00, 0x03, 0x2d, 0x04, 0x3c, 0x06, 0x5d,
+0x01, 0x70, 0x01, 0x70, 0x04, 0x66, 0x01, 0x15, 0x01, 0x66, 0x06, 0x15,
+0x06, 0x19, 0x07, 0x0e, 0x03, 0x6f, 0x03, 0x4f, 0x04, 0x35, 0x00, 0x08,
+0x45, 0x45, 0x3a, 0x7f, 0x17, 0xc3, 0x8c, 0x40, 0x03, 0x2e, 0x01, 0x1e,
+0x06, 0x63, 0x01, 0x30, 0x01, 0x63, 0x04, 0x30, 0x00, 0x0a, 0x3e, 0x3e,
+0x30, 0x5c, 0x5a, 0x02, 0x02, 0xe0, 0x5a, 0x8b, 0x36, 0x00, 0x00, 0x0b,
+0xad, 0x4e, 0x49, 0x50, 0x50, 0x5e, 0xf8, 0x52, 0x29, 0x27, 0x27, 0x00,
+0x03, 0x7b, 0x00, 0x04, 0x27, 0x5a, 0x7b, 0x5a, 0x06, 0x12, 0x07, 0x02,
+0x09, 0x14, 0x05, 0x0c, 0x06, 0x20, 0x06, 0x04, 0x01, 0x62, 0x03, 0x04,
+0x04, 0x62, 0x05, 0x01, 0x00, 0x09, 0x62, 0x1f, 0x41, 0x67, 0x41, 0x13,
+0xd9, 0x00, 0x11, 0x00, 0x21, 0x00, 0x00, 0x08, 0x03, 0x00, 0xa3, 0xfa,
+0xf2, 0x5e, 0xde, 0xe1, 0x19, 0x33, 0x06, 0x4b, 0x07, 0x61, 0x07, 0x36,
+0x01, 0x3f, 0x01, 0x3f, 0x03, 0xdc, 0x01, 0xbe, 0x01, 0x8f, 0x5b, 0x00,
+0x00, 0x00, 0x48, 0x00, 0x00, 0x09, 0x0d, 0x74, 0xef, 0xdc, 0xe4, 0xbe,
+0x0b, 0x2d, 0x2d, 0x00, 0x05, 0x3c, 0x05, 0x5d, 0x03, 0x70, 0x05, 0x66,
+0x07, 0x15, 0x06, 0x19, 0x06, 0x0e, 0x04, 0x6f, 0x00, 0x0a, 0x4f, 0x4f,
+0x35, 0x45, 0x45, 0x7f, 0x7f, 0x8c, 0x8c, 0x4a, 0x08, 0x2e, 0x04, 0x1e,
+0x03, 0x63, 0x01, 0x30, 0x01, 0x63, 0x06, 0x30, 0x00, 0x07, 0x37, 0x02,
+0x0c, 0x02, 0xe0, 0x02, 0x68, 0x00, 0x36, 0x00, 0x00, 0x09, 0xe7, 0x64,
+0x4c, 0x3d, 0x55, 0x50, 0xfb, 0x29, 0x52, 0x00, 0x04, 0x27, 0x03, 0x7b,
+0x00, 0x03, 0x5a, 0x12, 0x5a, 0x00, 0x05, 0x12, 0x06, 0x02, 0x09, 0x14,
+0x05, 0x0c, 0x08, 0x20, 0x04, 0x04, 0x07, 0x62, 0x08, 0x01, 0x00, 0x08,
+0x62, 0x01, 0xf3, 0x4c, 0x4c, 0x58, 0xeb, 0x71, 0x23, 0x00, 0x00, 0x0b,
+0x03, 0x00, 0xd9, 0x60, 0x56, 0x4e, 0x78, 0xc6, 0xc7, 0xc7, 0xd5, 0x00,
+0x17, 0x33, 0x06, 0x4b, 0x08, 0x61, 0x06, 0x36, 0x00, 0x06, 0xdc, 0xef,
+0xef, 0xcd, 0x43, 0xe7, 0x5a, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x08,
+0x7d, 0xdc, 0xe4, 0xe4, 0xdc, 0x5d, 0x0b, 0x2d, 0x05, 0x3c, 0x04, 0x5d,
+0x04, 0x70, 0x03, 0x66, 0x08, 0x15, 0x07, 0x19, 0x06, 0x0e, 0x00, 0x0a,
+0x4f, 0x0e, 0x0e, 0x6f, 0x45, 0x7f, 0x17, 0x8c, 0x8c, 0x4a, 0x07, 0x40,
+0x05, 0x2e, 0x03, 0x1e, 0x04, 0x63, 0x04, 0x30, 0x00, 0x0a, 0x3e, 0x30,
+0x30, 0x37, 0x0c, 0x04, 0x04, 0xe0, 0x04, 0x7d, 0x36, 0x00, 0x00, 0x09,
+0xec, 0x5e, 0x4c, 0x78, 0x78, 0x3d, 0xfb, 0x12, 0x52, 0x00, 0x03, 0x27,
+0x03, 0x7b, 0x01, 0x5a, 0x01, 0x5a, 0x06, 0x12, 0x07, 0x02, 0x07, 0x14,
+0x05, 0x0c, 0x05, 0x20, 0x0b, 0x04, 0x00, 0x04, 0x62, 0x62, 0x01, 0x62,
+0x0c, 0x01, 0x00, 0x06, 0x54, 0x2a, 0x2a, 0x16, 0x2a, 0xe7, 0x23, 0x00,
+0x00, 0x0c, 0x0d, 0x00, 0x8e, 0xeb, 0x5e, 0x60, 0x64, 0xf8, 0x01, 0x01,
+0xc6, 0xc6, 0x03, 0xc7, 0x13, 0x33, 0x01, 0x61, 0x01, 0x33, 0x07, 0x4b,
+0x05, 0x61, 0x06, 0x36, 0x00, 0x06, 0x42, 0xef, 0xcd, 0xcd, 0xcb, 0xd0,
+0x5a, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x0c, 0xd2, 0xc6, 0xdc, 0x4b,
+0x4b, 0x35, 0x0b, 0x2d, 0x3c, 0x3c, 0x5d, 0x3c, 0x05, 0x5d, 0x03, 0x70,
+0x05, 0x66, 0x07, 0x15, 0x06, 0x19, 0x00, 0x03, 0x0e, 0x0e, 0x19, 0x00,
+0x03, 0x0e, 0x00, 0x07, 0x6f, 0x7f, 0x93, 0x93, 0x8c, 0x8c, 0x22, 0x00,
+0x05, 0x4a, 0x06, 0x40, 0x03, 0x2e, 0x05, 0x1e, 0x04, 0x63, 0x06, 0x30,
+0x00, 0x0a, 0x52, 0x04, 0x32, 0x62, 0xe0, 0x1f, 0xd9, 0x00, 0x00, 0x03,
+0x33, 0x00, 0x00, 0x09, 0xec, 0x78, 0x2a, 0x67, 0x49, 0x67, 0xf3, 0x12,
+0x29, 0x00, 0x03, 0x27, 0x03, 0x7b, 0x01, 0x5a, 0x01, 0x5a, 0x05, 0x12,
+0x08, 0x02, 0x06, 0x14, 0x03, 0x0c, 0x00, 0x03, 0x20, 0x0c, 0x0c, 0x00,
+0x05, 0x20, 0x09, 0x04, 0x03, 0x62, 0x0b, 0x01, 0x00, 0x0b, 0x38, 0x32,
+0x32, 0x01, 0x32, 0x38, 0x10, 0x16, 0x10, 0xe1, 0x90, 0x00, 0x26, 0x00,
+0x00, 0x11, 0x68, 0x55, 0x5e, 0x64, 0x49, 0x32, 0x32, 0x01, 0x1f, 0x1f,
+0x01, 0x04, 0xc6, 0xc6, 0xc7, 0xc7, 0xd5, 0x00, 0x13, 0x33, 0x04, 0x4b,
+0x00, 0x05, 0x61, 0x4b, 0x61, 0x61, 0x36, 0x00, 0x03, 0x61, 0x04, 0x36,
+0x00, 0x06, 0xef, 0xcd, 0xcd, 0xcb, 0x37, 0x6b, 0x59, 0x00, 0x00, 0x00,
+0x4a, 0x00, 0x00, 0x09, 0xeb, 0xdc, 0x4b, 0x33, 0xdc, 0x2d, 0x2d, 0x3c,
+0x3c, 0x00, 0x06, 0x5d, 0x01, 0x70, 0x01, 0x70, 0x04, 0x66, 0x00, 0x03,
+0x15, 0x15, 0x66, 0x00, 0x06, 0x15, 0x07, 0x19, 0x00, 0x09, 0x0e, 0x0e,
+0x6f, 0xe5, 0x93, 0x93, 0x44, 0x44, 0x22, 0x00, 0x03, 0x4a, 0x01, 0x22,
+0x01, 0x22, 0x05, 0x4a, 0x03, 0x40, 0x04, 0x2e, 0x06, 0x1e, 0x03, 0x63,
+0x04, 0x30, 0x00, 0x0c, 0x63, 0x30, 0x27, 0x38, 0x08, 0x38, 0xc6, 0xf8,
+0xec, 0x00, 0x00, 0x03, 0x33, 0x00, 0x00, 0x03, 0xd9, 0x4c, 0x13, 0x00,
+0x03, 0x41, 0x00, 0x05, 0xf3, 0x7b, 0x29, 0x27, 0x27, 0x00, 0x06, 0x7b,
+0x05, 0x12, 0x07, 0x02, 0x07, 0x14, 0x05, 0x0c, 0x05, 0x20, 0x08, 0x04,
+0x03, 0x62, 0x0a, 0x01, 0x03, 0x32, 0x07, 0x38, 0x00, 0x06, 0x06, 0x21,
+0x47, 0x06, 0x49, 0xd2, 0x25, 0x00, 0x00, 0x07, 0xad, 0x4e, 0x78, 0x5e,
+0x55, 0x54, 0x01, 0x00, 0x04, 0x32, 0x00, 0x09, 0x01, 0x1f, 0x1f, 0x01,
+0x04, 0x04, 0xc6, 0xc7, 0xc7, 0x00, 0x11, 0x33, 0x06, 0x4b, 0x06, 0x61,
+0x00, 0x09, 0x36, 0x36, 0x61, 0x2b, 0xcd, 0xbe, 0xcb, 0xcb, 0x7e, 0x00,
+0x59, 0x00, 0x00, 0x00, 0x4a, 0x00, 0x00, 0x09, 0xe7, 0xc7, 0x4b, 0xd5,
+0x33, 0x35, 0x2d, 0x3c, 0x3c, 0x00, 0x06, 0x5d, 0x03, 0x70, 0x03, 0x66,
+0x09, 0x15, 0x05, 0x19, 0x00, 0x06, 0x6f, 0xe5, 0xe5, 0x93, 0x53, 0x44,
+0x09, 0x22, 0x04, 0x4a, 0x04, 0x40, 0x05, 0x2e, 0x04, 0x1e, 0x04, 0x63,
+0x05, 0x30, 0x00, 0x0b, 0x3e, 0x12, 0x06, 0x06, 0x1d, 0xc6, 0x78, 0xe7,
+0x00, 0x00, 0x0d, 0x00, 0x30, 0x00, 0x00, 0x0e, 0x03, 0x00, 0x00, 0x68,
+0xb7, 0x23, 0x2a, 0x2a, 0x0f, 0x54, 0x7b, 0x52, 0x27, 0x27, 0x03, 0x7b,
+0x01, 0x5a, 0x01, 0x5a, 0x05, 0x12, 0x08, 0x02, 0x06, 0x14, 0x04, 0x0c,
+0x06, 0x20, 0x06, 0x04, 0x05, 0x62, 0x08, 0x01, 0x05, 0x32, 0x05, 0x38,
+0x04, 0x1f, 0x00, 0x06, 0x08, 0x23, 0x23, 0x1d, 0xe1, 0x7d, 0x26, 0x00,
+0x00, 0x05, 0xeb, 0x49, 0x55, 0x50, 0xf3, 0x00, 0x03, 0x38, 0x03, 0x32,
+0x00, 0x0c, 0x38, 0x32, 0x01, 0x01, 0x1f, 0x1f, 0x01, 0x01, 0x04, 0xc6,
+0xc7, 0xc7, 0x0f, 0x33, 0x06, 0x4b, 0x00, 0x03, 0x61, 0x61, 0x4b, 0x00,
+0x04, 0x61, 0x00, 0x06, 0xe4, 0xcd, 0xbe, 0xcb, 0xae, 0xb8, 0x59, 0x00,
+0x00, 0x00, 0x4b, 0x00, 0x00, 0x07, 0x48, 0xe4, 0xd5, 0xd5, 0x3b, 0x0b,
+0x3c, 0x00, 0x06, 0x5d, 0x00, 0x04, 0x70, 0x66, 0x5d, 0x70, 0x03, 0x66,
+0x09, 0x15, 0x00, 0x06, 0x19, 0x19, 0xe5, 0xe5, 0x93, 0x53, 0x03, 0x44,
+0x0a, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x05, 0x2e, 0x04, 0x1e, 0x04, 0x63,
+0x03, 0x30, 0x00, 0x09, 0x63, 0x3e, 0x14, 0x58, 0x58, 0x23, 0xe1, 0x78,
+0xad, 0x00, 0x33, 0x00, 0x00, 0x06, 0x03, 0x00, 0x0d, 0x68, 0x58, 0x58,
+0x03, 0x13, 0x00, 0x05, 0x1f, 0x27, 0x52, 0x27, 0x27, 0x00, 0x03, 0x7b,
+0x01, 0x5a, 0x01, 0x5a, 0x05, 0x12, 0x07, 0x02, 0x07, 0x14, 0x04, 0x0c,
+0x05, 0x20, 0x09, 0x04, 0x01, 0x62, 0x01, 0x62, 0x09, 0x01, 0x04, 0x32,
+0x00, 0x05, 0x38, 0x38, 0x1f, 0x38, 0x38, 0x00, 0x06, 0x1f, 0x00, 0x07,
+0x08, 0x1d, 0x06, 0x06, 0xe1, 0x50, 0x4d, 0x00, 0x25, 0x00, 0x00, 0x0a,
+0xec, 0x78, 0x49, 0x3d, 0x49, 0x54, 0x38, 0x1f, 0x38, 0x38, 0x07, 0x32,
+0x00, 0x03, 0x01, 0x1f, 0x1f, 0x00, 0x03, 0x01, 0x00, 0x04, 0x04, 0xc6,
+0xc7, 0xc7, 0x0d, 0x33, 0x04, 0x4b, 0x00, 0x03, 0x61, 0x61, 0x4b, 0x00,
+0x05, 0x61, 0x00, 0x06, 0xdc, 0xcb, 0xcb, 0xae, 0x1c, 0x9a, 0x58, 0x00,
+0x00, 0x00, 0x49, 0x00, 0x00, 0x09, 0x11, 0x00, 0xd9, 0xd5, 0xd5, 0xab,
+0x33, 0x19, 0x2d, 0x00, 0x06, 0x5d, 0x03, 0x70, 0x03, 0x66, 0x01, 0x15,
+0x01, 0x66, 0x05, 0x15, 0x00, 0x06, 0x19, 0xe5, 0xe5, 0x93, 0x93, 0x53,
+0x09, 0x44, 0x05, 0x22, 0x01, 0x4a, 0x01, 0x22, 0x04, 0x4a, 0x05, 0x40,
+0x04, 0x2e, 0x04, 0x1e, 0x04, 0x63, 0x03, 0x30, 0x00, 0x09, 0x63, 0x3e,
+0x20, 0x21, 0x10, 0x47, 0xe1, 0x5e, 0xad, 0x00, 0x33, 0x00, 0x00, 0x0c,
+0x0d, 0x00, 0x4d, 0xfa, 0x06, 0x58, 0x47, 0x21, 0x10, 0x1f, 0x27, 0x29,
+0x04, 0x27, 0x00, 0x04, 0x7b, 0x7b, 0x5a, 0x5a, 0x04, 0x12, 0x07, 0x02,
+0x06, 0x14, 0x01, 0x0c, 0x01, 0x20, 0x03, 0x0c, 0x04, 0x20, 0x08, 0x04,
+0x04, 0x62, 0x03, 0x01, 0x00, 0x03, 0x62, 0x01, 0x01, 0x00, 0x03, 0x32,
+0x05, 0x38, 0x08, 0x1f, 0x07, 0x08, 0x00, 0x03, 0xc6, 0x38, 0xec, 0x00,
+0x25, 0x00, 0x00, 0x07, 0xa3, 0x56, 0x4c, 0x78, 0x78, 0xb7, 0x38, 0x00,
+0x04, 0x1f, 0x05, 0x38, 0x01, 0x32, 0x01, 0x32, 0x09, 0x01, 0x00, 0x04,
+0xc6, 0xe0, 0xc7, 0xd5, 0x0a, 0x33, 0x05, 0x4b, 0x06, 0x61, 0x00, 0x06,
+0x42, 0xbe, 0xcb, 0xae, 0x9c, 0xf7, 0x58, 0x00, 0x00, 0x00, 0x4b, 0x00,
+0x00, 0x07, 0x4d, 0xbc, 0xd5, 0xab, 0xab, 0x31, 0x9e, 0x00, 0x05, 0x5d,
+0x04, 0x70, 0x03, 0x66, 0x01, 0x15, 0x03, 0x66, 0x00, 0x09, 0x15, 0xe5,
+0x6e, 0x93, 0x53, 0x53, 0x44, 0x44, 0x53, 0x00, 0x07, 0x44, 0x07, 0x22,
+0x05, 0x4a, 0x05, 0x40, 0x04, 0x2e, 0x05, 0x1e, 0x03, 0x63, 0x03, 0x30,
+0x00, 0x09, 0x63, 0x3e, 0x62, 0x10, 0x10, 0x47, 0xe1, 0x56, 0xd2, 0x00,
+0x35, 0x00, 0x00, 0x12, 0x71, 0xeb, 0x1d, 0x58, 0x18, 0x47, 0x18, 0x62,
+0x27, 0x29, 0x27, 0x7b, 0x7b, 0x27, 0x7b, 0x7b, 0x5a, 0x5a, 0x04, 0x12,
+0x06, 0x02, 0x07, 0x14, 0x04, 0x0c, 0x05, 0x20, 0x04, 0x04, 0x00, 0x05,
+0x62, 0x04, 0x04, 0x62, 0x62, 0x00, 0x07, 0x01, 0x04, 0x32, 0x04, 0x38,
+0x01, 0x1f, 0x01, 0x38, 0x03, 0x1f, 0x0b, 0x08, 0x03, 0x38, 0x01, 0xc6,
+0x01, 0xeb, 0x26, 0x00, 0x00, 0x06, 0x7d, 0x2a, 0x41, 0x49, 0x2a, 0x08,
+0x08, 0x1f, 0x00, 0x03, 0x38, 0x38, 0x01, 0x00, 0x04, 0x32, 0x08, 0x01,
+0x00, 0x04, 0x04, 0xc6, 0xc7, 0xc7, 0x07, 0x33, 0x01, 0x61, 0x01, 0x33,
+0x06, 0x4b, 0x00, 0x0a, 0x61, 0x4b, 0x61, 0x61, 0xcd, 0xae, 0xae, 0x89,
+0x76, 0x6b, 0x57, 0x00, 0x00, 0x00, 0x4c, 0x00, 0x01, 0xfa, 0x03, 0xab,
+0x00, 0x03, 0x33, 0x66, 0x2d, 0x00, 0x04, 0x5d, 0x00, 0x05, 0x66, 0x70,
+0x70, 0x66, 0x70, 0x00, 0x03, 0x66, 0x00, 0x07, 0x15, 0xe5, 0x6e, 0x73,
+0x65, 0x53, 0x44, 0x00, 0x05, 0x53, 0x07, 0x44, 0x08, 0x22, 0x04, 0x4a,
+0x04, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x04, 0x63, 0x03, 0x30, 0x00, 0x0b,
+0x1e, 0x59, 0x1f, 0x13, 0x13, 0x58, 0xe1, 0x5f, 0x6b, 0x00, 0x03, 0x00,
+0x33, 0x00, 0x00, 0x09, 0x6b, 0x9d, 0xe1, 0x1d, 0x06, 0x23, 0x06, 0x20,
+0x29, 0x00, 0x04, 0x27, 0x01, 0x7b, 0x03, 0x5a, 0x04, 0x12, 0x07, 0x02,
+0x06, 0x14, 0x00, 0x04, 0x0c, 0x14, 0x0c, 0x0c, 0x05, 0x20, 0x07, 0x04,
+0x01, 0x62, 0x01, 0x62, 0x06, 0x01, 0x03, 0x32, 0x01, 0x01, 0x01, 0x32,
+0x03, 0x38, 0x05, 0x1f, 0x0e, 0x08, 0x00, 0x06, 0x38, 0x62, 0x62, 0xe0,
+0xf8, 0xad, 0x25, 0x00, 0x00, 0x06, 0xad, 0x49, 0x2a, 0x41, 0x0f, 0x54,
+0x06, 0x08, 0x04, 0x1f, 0x03, 0x38, 0x04, 0x32, 0x08, 0x01, 0x00, 0x05,
+0x62, 0x04, 0xc6, 0xc6, 0xc7, 0x00, 0x03, 0x33, 0x00, 0x04, 0x4b, 0x4b,
+0x33, 0x33, 0x06, 0x4b, 0x00, 0x0b, 0x61, 0x61, 0x33, 0xdc, 0xae, 0xae,
+0x9c, 0x9c, 0xf1, 0x00, 0x03, 0x00, 0x55, 0x00, 0x00, 0x00, 0x4c, 0x00,
+0x00, 0x07, 0xd2, 0xc8, 0xd5, 0xab, 0xab, 0x2f, 0x0b, 0x00, 0x04, 0x5d,
+0x04, 0x70, 0x00, 0x06, 0x66, 0x83, 0xe5, 0x6e, 0x65, 0x65, 0x09, 0x53,
+0x07, 0x44, 0x08, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x04, 0x2e, 0x05, 0x1e,
+0x01, 0x63, 0x01, 0x63, 0x03, 0x30, 0x00, 0x0b, 0x1e, 0x59, 0x1f, 0x2a,
+0x13, 0x47, 0xe1, 0xeb, 0xa3, 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x09,
+0x6b, 0x56, 0xe1, 0x1d, 0x54, 0x06, 0x1d, 0x0c, 0x29, 0x00, 0x03, 0x27,
+0x01, 0x7b, 0x01, 0x7b, 0x03, 0x5a, 0x04, 0x12, 0x07, 0x02, 0x05, 0x14,
+0x05, 0x0c, 0x04, 0x20, 0x08, 0x04, 0x01, 0x62, 0x01, 0x62, 0x03, 0x01,
+0x00, 0x06, 0x62, 0x01, 0x32, 0x01, 0x32, 0x01, 0x03, 0x38, 0x06, 0x1f,
+0x0d, 0x08, 0x03, 0x1d, 0x00, 0x06, 0x1f, 0x04, 0x04, 0xc6, 0xc6, 0x90,
+0x25, 0x00, 0x00, 0x06, 0x71, 0xeb, 0x58, 0x0f, 0x0f, 0xb7, 0x08, 0x08,
+0x03, 0x1f, 0x01, 0x38, 0x01, 0x1f, 0x03, 0x38, 0x01, 0x32, 0x01, 0x32,
+0x07, 0x01, 0x04, 0x62, 0x00, 0x04, 0x04, 0x0c, 0xc6, 0xc7, 0x03, 0x33,
+0x00, 0x03, 0x4b, 0x4b, 0x33, 0x00, 0x06, 0x4b, 0x00, 0x0a, 0x61, 0x36,
+0xbe, 0x9c, 0xae, 0xce, 0xbb, 0x0d, 0x00, 0x0d, 0x54, 0x00, 0x00, 0x00,
+0x4d, 0x00, 0x00, 0x05, 0xeb, 0xab, 0xab, 0xd1, 0x3f, 0x00, 0x04, 0x5d,
+0x00, 0x06, 0x70, 0x70, 0x66, 0x83, 0x57, 0x73, 0x03, 0x65, 0x0b, 0x53,
+0x07, 0x44, 0x07, 0x22, 0x04, 0x4a, 0x05, 0x40, 0x05, 0x2e, 0x04, 0x1e,
+0x03, 0x63, 0x00, 0x0b, 0x30, 0x30, 0x1e, 0x5c, 0xb7, 0x4c, 0x0f, 0x16,
+0x23, 0xeb, 0x4d, 0x00, 0x35, 0x00, 0x00, 0x09, 0xd2, 0x7a, 0xe0, 0x38,
+0x08, 0x1d, 0x38, 0x02, 0x29, 0x00, 0x03, 0x27, 0x00, 0x04, 0x7b, 0x7b,
+0x5a, 0x5a, 0x05, 0x12, 0x06, 0x02, 0x03, 0x14, 0x00, 0x03, 0x02, 0x14,
+0x14, 0x00, 0x04, 0x0c, 0x05, 0x20, 0x06, 0x04, 0x03, 0x62, 0x06, 0x01,
+0x01, 0x32, 0x01, 0x32, 0x05, 0x38, 0x03, 0x1f, 0x0d, 0x08, 0x07, 0x1d,
+0x00, 0x09, 0x54, 0x01, 0x0c, 0x0c, 0xe0, 0x91, 0x6b, 0x00, 0x0d, 0x00,
+0x23, 0x00, 0x00, 0x06, 0xec, 0x16, 0x13, 0x13, 0x16, 0x1d, 0x09, 0x08,
+0x04, 0x1f, 0x04, 0x38, 0x03, 0x32, 0x06, 0x01, 0x06, 0x62, 0x00, 0x06,
+0x04, 0xc6, 0xc7, 0xc7, 0x33, 0x33, 0x07, 0x4b, 0x00, 0x09, 0x33, 0xef,
+0x9c, 0x9c, 0x89, 0x9c, 0x7e, 0x00, 0x26, 0x00, 0x54, 0x00, 0x00, 0x00,
+0x4d, 0x00, 0x00, 0x0c, 0xe7, 0xd1, 0xab, 0xd1, 0xd1, 0x45, 0xba, 0x5d,
+0x66, 0x83, 0x57, 0x73, 0x08, 0x65, 0x08, 0x53, 0x07, 0x44, 0x06, 0x22,
+0x06, 0x4a, 0x04, 0x40, 0x05, 0x2e, 0x04, 0x1e, 0x03, 0x63, 0x00, 0x0b,
+0x30, 0x30, 0x1e, 0x37, 0xf3, 0x41, 0x4c, 0x13, 0x16, 0xfa, 0x11, 0x00,
+0x35, 0x00, 0x00, 0x10, 0xad, 0x91, 0xc6, 0x04, 0x32, 0x38, 0x01, 0x02,
+0x29, 0x27, 0x7b, 0x7b, 0x27, 0x27, 0x5a, 0x5a, 0x04, 0x12, 0x07, 0x02,
+0x00, 0x03, 0x14, 0x14, 0x02, 0x00, 0x03, 0x14, 0x04, 0x0c, 0x05, 0x20,
+0x07, 0x04, 0x01, 0x62, 0x05, 0x01, 0x00, 0x05, 0x32, 0x01, 0x01, 0x32,
+0x32, 0x00, 0x04, 0x38, 0x03, 0x1f, 0x00, 0x03, 0x08, 0x08, 0x1f, 0x00,
+0x07, 0x08, 0x04, 0x1d, 0x07, 0x54, 0x01, 0x06, 0x01, 0x38, 0x03, 0x02,
+0x00, 0x04, 0x5a, 0x7d, 0x00, 0x11, 0x23, 0x00, 0x00, 0x06, 0x6b, 0x5f,
+0x06, 0x13, 0x21, 0x23, 0x09, 0x08, 0x00, 0x03, 0x1f, 0x08, 0x08, 0x00,
+0x04, 0x1f, 0x03, 0x38, 0x01, 0x01, 0x01, 0x32, 0x07, 0x01, 0x08, 0x62,
+0x00, 0x04, 0xc6, 0xe0, 0xc7, 0x33, 0x03, 0x4b, 0x00, 0x09, 0x61, 0x4b,
+0x4b, 0x36, 0xae, 0x89, 0x9c, 0xce, 0xd4, 0x00, 0x56, 0x00, 0x00, 0x00,
+0x4e, 0x00, 0x00, 0x08, 0xde, 0xab, 0xd1, 0xd1, 0xf0, 0x83, 0x57, 0x73,
+0x0a, 0x65, 0x09, 0x53, 0x06, 0x44, 0x08, 0x22, 0x05, 0x4a, 0x03, 0x40,
+0x05, 0x2e, 0x05, 0x1e, 0x03, 0x63, 0x00, 0x09, 0x30, 0x1e, 0x37, 0xf3,
+0x41, 0x4c, 0x13, 0x13, 0x90, 0x00, 0x36, 0x00, 0x00, 0x08, 0xe7, 0x74,
+0xe0, 0x62, 0x62, 0x32, 0x04, 0x12, 0x03, 0x27, 0x00, 0x06, 0x7b, 0x27,
+0x27, 0x7b, 0x5a, 0x5a, 0x03, 0x12, 0x07, 0x02, 0x06, 0x14, 0x04, 0x0c,
+0x03, 0x20, 0x07, 0x04, 0x03, 0x62, 0x05, 0x01, 0x04, 0x32, 0x01, 0x38,
+0x01, 0x38, 0x04, 0x1f, 0x09, 0x08, 0x01, 0x1d, 0x01, 0x08, 0x04, 0x1d,
+0x09, 0x54, 0x00, 0x08, 0x06, 0x54, 0x0c, 0x5a, 0x14, 0xdf, 0xcc, 0x0d,
+0x23, 0x00, 0x00, 0x07, 0x03, 0x00, 0x7d, 0xe1, 0x10, 0x18, 0x23, 0x00,
+0x05, 0x1d, 0x09, 0x08, 0x03, 0x1f, 0x03, 0x38, 0x04, 0x32, 0x06, 0x01,
+0x01, 0x62, 0x01, 0x62, 0x03, 0x04, 0x00, 0x08, 0x62, 0x62, 0xaa, 0x20,
+0xc6, 0xe0, 0xc7, 0x33, 0x03, 0x4b, 0x00, 0x09, 0x33, 0xbe, 0x89, 0x89,
+0xce, 0xe5, 0x9a, 0x00, 0x0d, 0x00, 0x53, 0x00, 0x00, 0x00, 0x4e, 0x00,
+0x00, 0x07, 0xd9, 0xd1, 0xc8, 0xdd, 0x1d, 0x53, 0x73, 0x00, 0x0b, 0x65,
+0x08, 0x53, 0x07, 0x44, 0x08, 0x22, 0x03, 0x4a, 0x04, 0x40, 0x05, 0x2e,
+0x04, 0x1e, 0x05, 0x63, 0x00, 0x0b, 0x1e, 0x52, 0xfb, 0x49, 0x41, 0x13,
+0x0f, 0x7d, 0x00, 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x03, 0xe7, 0xf8,
+0xe0, 0x00, 0x03, 0x04, 0x01, 0x0c, 0x01, 0x5a, 0x04, 0x27, 0x03, 0x7b,
+0x01, 0x5a, 0x01, 0x5a, 0x03, 0x12, 0x07, 0x02, 0x05, 0x14, 0x04, 0x0c,
+0x04, 0x20, 0x04, 0x04, 0x00, 0x05, 0x62, 0x62, 0x04, 0x04, 0x62, 0x00,
+0x05, 0x01, 0x03, 0x32, 0x03, 0x38, 0x05, 0x1f, 0x08, 0x08, 0x03, 0x1d,
+0x0a, 0x54, 0x05, 0x06, 0x00, 0x07, 0x23, 0x01, 0x5a, 0x5a, 0xca, 0x14,
+0xe7, 0x00, 0x23, 0x00, 0x00, 0x06, 0x11, 0x00, 0xad, 0x67, 0xe1, 0x23,
+0x05, 0x54, 0x03, 0x1d, 0x0a, 0x08, 0x04, 0x1f, 0x01, 0x38, 0x04, 0x32,
+0x05, 0x01, 0x03, 0x62, 0x05, 0x04, 0x00, 0x0e, 0x20, 0xaa, 0x20, 0xc6,
+0xe0, 0xc7, 0x4b, 0x33, 0xdc, 0x89, 0xce, 0x89, 0xce, 0xf1, 0x55, 0x00,
+0x00, 0x00, 0x4e, 0x00, 0x00, 0x08, 0x6b, 0x50, 0x10, 0x49, 0x49, 0xa6,
+0x73, 0x73, 0x0a, 0x65, 0x07, 0x53, 0x07, 0x44, 0x06, 0x22, 0x01, 0x4a,
+0x01, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x04, 0x2e, 0x05, 0x1e, 0x00, 0x0e,
+0x63, 0x30, 0x63, 0x40, 0x52, 0xfb, 0x78, 0x49, 0x13, 0x49, 0x7d, 0x00,
+0x00, 0x03, 0x33, 0x00, 0x00, 0x03, 0xd9, 0x1f, 0xe0, 0x00, 0x03, 0x0c,
+0x01, 0x14, 0x01, 0x5a, 0x05, 0x27, 0x00, 0x04, 0x7b, 0x7b, 0x5a, 0x5a,
+0x03, 0x12, 0x07, 0x02, 0x06, 0x14, 0x03, 0x0c, 0x04, 0x20, 0x07, 0x04,
+0x01, 0x62, 0x06, 0x01, 0x00, 0x06, 0x32, 0x32, 0x38, 0x32, 0x38, 0x38,
+0x03, 0x1f, 0x07, 0x08, 0x06, 0x1d, 0x07, 0x54, 0x01, 0x06, 0x01, 0x54,
+0x07, 0x06, 0x00, 0x07, 0x23, 0x06, 0x5a, 0x29, 0x27, 0xdf, 0xd0, 0x00,
+0x26, 0x00, 0x00, 0x05, 0xeb, 0xe1, 0x1d, 0x08, 0x08, 0x00, 0x05, 0x54,
+0x04, 0x1d, 0x09, 0x08, 0x03, 0x1f, 0x00, 0x03, 0x38, 0x38, 0x32, 0x00,
+0x08, 0x01, 0x04, 0x62, 0x04, 0x04, 0x00, 0x0d, 0x20, 0xaa, 0xaa, 0x0c,
+0xc6, 0xc7, 0x61, 0xcb, 0x89, 0x89, 0xce, 0xa5, 0x6b, 0x00, 0x54, 0x00,
+0x00, 0x00, 0x4f, 0x00, 0x00, 0x07, 0x7d, 0x13, 0x49, 0x67, 0xf8, 0x65,
+0x73, 0x00, 0x09, 0x65, 0x08, 0x53, 0x06, 0x44, 0x09, 0x22, 0x05, 0x4a,
+0x03, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x00, 0x0c, 0x63, 0x1e, 0x63, 0x30,
+0x1e, 0x37, 0xfb, 0xde, 0x78, 0x0f, 0x78, 0xec, 0x33, 0x00, 0x00, 0x06,
+0x03, 0x00, 0x00, 0x7e, 0x02, 0xdf, 0x04, 0x02, 0x01, 0x27, 0x01, 0x29,
+0x05, 0x27, 0x00, 0x03, 0x7b, 0x5a, 0x5a, 0x00, 0x03, 0x12, 0x07, 0x02,
+0x07, 0x14, 0x01, 0x0c, 0x01, 0x0c, 0x04, 0x20, 0x03, 0x04, 0x00, 0x05,
+0x62, 0x04, 0x04, 0x62, 0x62, 0x00, 0x05, 0x01, 0x03, 0x32, 0x03, 0x38,
+0x03, 0x1f, 0x08, 0x08, 0x04, 0x1d, 0x07, 0x54, 0x0c, 0x06, 0x00, 0x08,
+0x23, 0x18, 0x0c, 0x52, 0x52, 0xc0, 0xaf, 0xad, 0x23, 0x00, 0x00, 0x08,
+0x0d, 0x00, 0xec, 0xb7, 0xc6, 0x38, 0x32, 0x1d, 0x06, 0x54, 0x04, 0x1d,
+0x08, 0x08, 0x04, 0x1f, 0x00, 0x04, 0x38, 0x38, 0x32, 0x32, 0x06, 0x01,
+0x01, 0x62, 0x01, 0x62, 0x06, 0x04, 0x00, 0x0c, 0x20, 0x20, 0xaa, 0xaa,
+0x20, 0x04, 0xc0, 0x70, 0x9c, 0x89, 0xce, 0x96, 0x54, 0x00, 0x00, 0x00,
+0x4f, 0x00, 0x00, 0x07, 0xad, 0x50, 0x4c, 0x3d, 0x49, 0x2e, 0x73, 0x00,
+0x08, 0x65, 0x08, 0x53, 0x07, 0x44, 0x08, 0x22, 0x03, 0x4a, 0x05, 0x40,
+0x05, 0x2e, 0x03, 0x1e, 0x04, 0x63, 0x00, 0x08, 0x1e, 0x59, 0xfb, 0xde,
+0x3d, 0x41, 0x55, 0xec, 0x33, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x7d,
+0x5a, 0xdf, 0x5a, 0x5a, 0x02, 0x5a, 0x27, 0x29, 0x05, 0x27, 0x00, 0x03,
+0x5a, 0x12, 0x5a, 0x00, 0x04, 0x12, 0x05, 0x02, 0x06, 0x14, 0x04, 0x0c,
+0x04, 0x20, 0x03, 0x04, 0x00, 0x04, 0x62, 0x04, 0x62, 0x62, 0x05, 0x01,
+0x03, 0x32, 0x04, 0x38, 0x01, 0x1f, 0x01, 0x1f, 0x08, 0x08, 0x05, 0x1d,
+0x06, 0x54, 0x08, 0x06, 0x07, 0x23, 0x00, 0x07, 0x47, 0x08, 0x52, 0xc0,
+0xc0, 0xf0, 0x69, 0x00, 0x26, 0x00, 0x00, 0x06, 0xcc, 0xe0, 0x04, 0x0c,
+0x38, 0x06, 0x08, 0x54, 0x03, 0x1d, 0x08, 0x08, 0x03, 0x1f, 0x04, 0x38,
+0x01, 0x32, 0x06, 0x01, 0x00, 0x03, 0x62, 0x04, 0x62, 0x00, 0x04, 0x04,
+0x04, 0x20, 0x00, 0x07, 0x62, 0x14, 0x53, 0x6e, 0x57, 0x89, 0xf4, 0x00,
+0x54, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x06, 0xfa, 0x13, 0x3d, 0xde,
+0xaf, 0x73, 0x08, 0x65, 0x08, 0x53, 0x07, 0x44, 0x08, 0x22, 0x03, 0x4a,
+0x05, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x04, 0x63, 0x00, 0x07, 0x30, 0xf8,
+0xde, 0x55, 0x49, 0x78, 0xd9, 0x00, 0x33, 0x00, 0x00, 0x06, 0x03, 0x00,
+0x00, 0x8b, 0x29, 0xca, 0x04, 0x5a, 0x01, 0x27, 0x01, 0x29, 0x04, 0x27,
+0x00, 0x04, 0x7b, 0x7b, 0x5a, 0x7b, 0x03, 0x12, 0x06, 0x02, 0x06, 0x14,
+0x00, 0x03, 0x0c, 0x20, 0x0c, 0x00, 0x04, 0x20, 0x07, 0x04, 0x01, 0x62,
+0x06, 0x01, 0x00, 0x04, 0x32, 0x32, 0x38, 0x38, 0x04, 0x1f, 0x08, 0x08,
+0x00, 0x03, 0x1d, 0x54, 0x1d, 0x00, 0x05, 0x54, 0x01, 0x06, 0x01, 0x54,
+0x07, 0x06, 0x0a, 0x23, 0x00, 0x08, 0x47, 0x18, 0x5a, 0xc0, 0xc0, 0xf0,
+0x88, 0x4d, 0x25, 0x00, 0x00, 0x06, 0x7d, 0xc6, 0xc6, 0x0c, 0x0c, 0x54,
+0x04, 0x06, 0x04, 0x54, 0x04, 0x1d, 0x08, 0x08, 0x05, 0x1f, 0x01, 0x38,
+0x01, 0x32, 0x08, 0x01, 0x01, 0x62, 0x06, 0x04, 0x00, 0x0a, 0x20, 0x20,
+0x04, 0x04, 0x59, 0x73, 0x65, 0x57, 0x65, 0x75, 0x53, 0x00, 0x00, 0x00,
+0x4e, 0x00, 0x00, 0x09, 0x11, 0x00, 0xec, 0x78, 0x78, 0xde, 0xfb, 0x44,
+0x73, 0x00, 0x06, 0x65, 0x08, 0x53, 0x07, 0x44, 0x08, 0x22, 0x04, 0x4a,
+0x05, 0x40, 0x04, 0x2e, 0x03, 0x1e, 0x00, 0x0b, 0x63, 0x1e, 0x63, 0x63,
+0x1e, 0xaf, 0x50, 0x50, 0x3d, 0x67, 0x7d, 0x00, 0x36, 0x00, 0x00, 0x08,
+0xea, 0xca, 0xca, 0x5a, 0x27, 0x27, 0x29, 0x29, 0x05, 0x27, 0x00, 0x03,
+0x7b, 0x7b, 0x5a, 0x00, 0x05, 0x12, 0x05, 0x02, 0x07, 0x14, 0x03, 0x0c,
+0x03, 0x20, 0x04, 0x04, 0x04, 0x62, 0x04, 0x01, 0x03, 0x32, 0x00, 0x05,
+0x38, 0x38, 0x1f, 0x38, 0x1f, 0x00, 0x08, 0x08, 0x03, 0x1d, 0x06, 0x54,
+0x07, 0x06, 0x00, 0x03, 0x23, 0x23, 0x06, 0x00, 0x03, 0x23, 0x09, 0x18,
+0x00, 0x07, 0x21, 0x01, 0xb9, 0xc0, 0xf0, 0xb9, 0xb2, 0x00, 0x25, 0x00,
+0x00, 0x07, 0x6b, 0xf8, 0xe0, 0x02, 0x5a, 0x38, 0x23, 0x00, 0x05, 0x06,
+0x05, 0x54, 0x05, 0x1d, 0x07, 0x08, 0x03, 0x1f, 0x01, 0x38, 0x04, 0x32,
+0x04, 0x01, 0x01, 0x62, 0x01, 0x62, 0x06, 0x04, 0x00, 0x09, 0x20, 0x20,
+0x01, 0x7b, 0x65, 0x73, 0x73, 0x6e, 0xdb, 0x00, 0x53, 0x00, 0x00, 0x00,
+0x4e, 0x00, 0x00, 0x09, 0x0d, 0x00, 0xa3, 0xeb, 0x4c, 0x50, 0xde, 0xb4,
+0x6e, 0x00, 0x06, 0x65, 0x08, 0x53, 0x07, 0x44, 0x06, 0x22, 0x06, 0x4a,
+0x04, 0x40, 0x04, 0x2e, 0x03, 0x1e, 0x03, 0x63, 0x00, 0x0b, 0x30, 0x40,
+0x52, 0x55, 0x5e, 0x55, 0x49, 0xfa, 0x0d, 0x00, 0x03, 0x00, 0x32, 0x00,
+0x00, 0x04, 0x4d, 0xea, 0xc0, 0xca, 0x05, 0x29, 0x04, 0x27, 0x04, 0x7b,
+0x01, 0x5a, 0x04, 0x12, 0x06, 0x02, 0x05, 0x14, 0x04, 0x0c, 0x03, 0x20,
+0x04, 0x04, 0x04, 0x62, 0x01, 0x01, 0x01, 0x62, 0x03, 0x01, 0x00, 0x04,
+0x32, 0x32, 0x38, 0x38, 0x03, 0x1f, 0x07, 0x08, 0x04, 0x1d, 0x06, 0x54,
+0x06, 0x06, 0x08, 0x23, 0x09, 0x18, 0x00, 0x07, 0x21, 0x06, 0xca, 0xb9,
+0xb9, 0xf0, 0xcf, 0x00, 0x26, 0x00, 0x00, 0x07, 0xea, 0xdf, 0x5a, 0x5a,
+0x0c, 0x06, 0x23, 0x00, 0x06, 0x06, 0x06, 0x54, 0x03, 0x1d, 0x07, 0x08,
+0x03, 0x1f, 0x01, 0x38, 0x01, 0x38, 0x04, 0x32, 0x04, 0x01, 0x03, 0x62,
+0x04, 0x04, 0x00, 0x09, 0x20, 0x62, 0x20, 0x63, 0x73, 0x65, 0xe5, 0xbb,
+0x71, 0x00, 0x52, 0x00, 0x00, 0x00, 0x4f, 0x00, 0x00, 0x09, 0x0d, 0x00,
+0xd9, 0x67, 0x50, 0x5e, 0x72, 0x65, 0x73, 0x00, 0x04, 0x65, 0x09, 0x53,
+0x06, 0x44, 0x06, 0x22, 0x01, 0x4a, 0x01, 0x22, 0x04, 0x4a, 0x04, 0x40,
+0x05, 0x2e, 0x04, 0x1e, 0x00, 0x0c, 0x63, 0x63, 0x1e, 0x3e, 0x80, 0x64,
+0x5e, 0x49, 0xeb, 0x6b, 0x00, 0x03, 0x32, 0x00, 0x00, 0x09, 0x11, 0xcf,
+0xb9, 0xc0, 0x52, 0xca, 0xca, 0x52, 0x29, 0x00, 0x03, 0x27, 0x00, 0x06,
+0x7b, 0x27, 0x7b, 0x7b, 0x5a, 0x5a, 0x04, 0x12, 0x05, 0x02, 0x06, 0x14,
+0x04, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x06, 0x04, 0x01, 0x62, 0x01, 0x62,
+0x06, 0x01, 0x00, 0x03, 0x38, 0x32, 0x38, 0x00, 0x04, 0x1f, 0x06, 0x08,
+0x03, 0x1d, 0x06, 0x54, 0x05, 0x06, 0x08, 0x23, 0x0c, 0x18, 0x00, 0x09,
+0x47, 0x47, 0x21, 0x02, 0x76, 0xb9, 0x0a, 0xb4, 0x7c, 0x00, 0x25, 0x00,
+0x00, 0x09, 0xe7, 0x5a, 0xca, 0x29, 0x29, 0x08, 0x18, 0x23, 0x23, 0x00,
+0x06, 0x06, 0x06, 0x54, 0x04, 0x1d, 0x06, 0x08, 0x03, 0x1f, 0x01, 0x38,
+0x03, 0x32, 0x05, 0x01, 0x03, 0x62, 0x00, 0x0c, 0x04, 0x04, 0x20, 0x04,
+0x04, 0x01, 0x29, 0x53, 0x53, 0x93, 0x44, 0x96, 0x52, 0x00, 0x00, 0x00,
+0x4f, 0x00, 0x00, 0x09, 0x0d, 0x00, 0x8e, 0x9d, 0x78, 0x5e, 0x50, 0x82,
+0x73, 0x00, 0x04, 0x65, 0x07, 0x53, 0x08, 0x44, 0x08, 0x22, 0x04, 0x4a,
+0x04, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x00, 0x0a, 0x63, 0x63, 0x1e, 0x1e,
+0xc1, 0x4e, 0x46, 0x55, 0x64, 0xad, 0x32, 0x00, 0x00, 0x06, 0x03, 0x00,
+0x6b, 0xf7, 0xf0, 0xb9, 0x03, 0xc0, 0x01, 0x52, 0x01, 0x29, 0x04, 0x27,
+0x03, 0x7b, 0x00, 0x03, 0x5a, 0x5a, 0x7b, 0x00, 0x03, 0x12, 0x06, 0x02,
+0x04, 0x14, 0x04, 0x0c, 0x03, 0x20, 0x04, 0x04, 0x00, 0x04, 0x62, 0x04,
+0x62, 0x62, 0x04, 0x01, 0x03, 0x32, 0x00, 0x05, 0x38, 0x1f, 0x1f, 0x38,
+0x1f, 0x00, 0x07, 0x08, 0x03, 0x1d, 0x06, 0x54, 0x05, 0x06, 0x05, 0x23,
+0x00, 0x04, 0x18, 0x18, 0x23, 0x23, 0x08, 0x18, 0x06, 0x47, 0x00, 0x07,
+0x10, 0x1d, 0xb9, 0x76, 0x76, 0xc3, 0xf1, 0x00, 0x25, 0x00, 0x00, 0x08,
+0x4d, 0x8f, 0xdf, 0x52, 0xc0, 0x14, 0x18, 0x18, 0x03, 0x23, 0x06, 0x06,
+0x06, 0x54, 0x03, 0x1d, 0x06, 0x08, 0x03, 0x1f, 0x00, 0x06, 0x38, 0x38,
+0x32, 0x01, 0x01, 0x32, 0x03, 0x01, 0x01, 0x62, 0x01, 0x62, 0x06, 0x04,
+0x00, 0x06, 0x20, 0x1e, 0x53, 0x44, 0x6e, 0xd4, 0x52, 0x00, 0x00, 0x00,
+0x52, 0x00, 0x00, 0x05, 0x68, 0x3d, 0x50, 0x64, 0xc1, 0x00, 0x04, 0x65,
+0x09, 0x53, 0x07, 0x44, 0x07, 0x22, 0x05, 0x4a, 0x03, 0x40, 0x05, 0x2e,
+0x04, 0x1e, 0x00, 0x09, 0x63, 0x63, 0x40, 0x37, 0x46, 0x64, 0x5e, 0x3d,
+0x7d, 0x00, 0x32, 0x00, 0x00, 0x06, 0x0d, 0x00, 0x8e, 0x88, 0xf0, 0xb9,
+0x03, 0xc0, 0x01, 0x52, 0x01, 0x29, 0x04, 0x27, 0x03, 0x7b, 0x01, 0x5a,
+0x01, 0x5a, 0x04, 0x12, 0x06, 0x02, 0x04, 0x14, 0x04, 0x0c, 0x03, 0x20,
+0x04, 0x04, 0x00, 0x04, 0x62, 0x04, 0x62, 0x62, 0x03, 0x01, 0x03, 0x32,
+0x01, 0x38, 0x01, 0x38, 0x04, 0x1f, 0x07, 0x08, 0x01, 0x1d, 0x01, 0x1d,
+0x06, 0x54, 0x06, 0x06, 0x04, 0x23, 0x00, 0x03, 0x18, 0x18, 0x58, 0x00,
+0x07, 0x18, 0x05, 0x47, 0x06, 0x21, 0x00, 0x07, 0x10, 0x29, 0x8c, 0x76,
+0x17, 0xb8, 0x71, 0x00, 0x25, 0x00, 0x00, 0x07, 0x7e, 0xb9, 0xc0, 0xc0,
+0xca, 0x06, 0x47, 0x00, 0x05, 0x23, 0x06, 0x06, 0x05, 0x54, 0x03, 0x1d,
+0x06, 0x08, 0x04, 0x1f, 0x01, 0x38, 0x03, 0x32, 0x04, 0x01, 0x00, 0x04,
+0x62, 0x62, 0x04, 0x62, 0x03, 0x04, 0x00, 0x09, 0x01, 0x37, 0x44, 0xee,
+0x53, 0xa5, 0xb2, 0x00, 0x03, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x52, 0x00,
+0x00, 0x09, 0xad, 0x4e, 0x3d, 0x64, 0x7a, 0xed, 0x73, 0x65, 0x65, 0x00,
+0x08, 0x53, 0x07, 0x44, 0x07, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x04, 0x2e,
+0x04, 0x1e, 0x00, 0x0a, 0x63, 0x63, 0x1e, 0x63, 0x74, 0x56, 0x64, 0x50,
+0xeb, 0xa3, 0x33, 0x00, 0x00, 0x0a, 0x7c, 0xa8, 0xc3, 0xc0, 0xc0, 0xb9,
+0xb9, 0x52, 0x29, 0x29, 0x03, 0x27, 0x03, 0x7b, 0x01, 0x5a, 0x01, 0x5a,
+0x04, 0x12, 0x05, 0x02, 0x05, 0x14, 0x04, 0x0c, 0x03, 0x20, 0x05, 0x04,
+0x03, 0x62, 0x04, 0x01, 0x03, 0x32, 0x00, 0x04, 0x38, 0x38, 0x1f, 0x1f,
+0x08, 0x08, 0x01, 0x1d, 0x05, 0x54, 0x06, 0x06, 0x04, 0x23, 0x00, 0x05,
+0x18, 0x18, 0x23, 0x18, 0x23, 0x00, 0x06, 0x18, 0x01, 0x47, 0x01, 0x47,
+0x0a, 0x21, 0x00, 0x0a, 0x47, 0x13, 0x04, 0x76, 0x76, 0x8c, 0x76, 0x7e,
+0x00, 0x03, 0x23, 0x00, 0x00, 0x07, 0x8e, 0xa8, 0xf0, 0xc0, 0xb9, 0x0c,
+0x21, 0x00, 0x03, 0x18, 0x04, 0x23, 0x06, 0x06, 0x04, 0x54, 0x04, 0x1d,
+0x06, 0x08, 0x03, 0x1f, 0x00, 0x04, 0x38, 0x38, 0x32, 0x32, 0x05, 0x01,
+0x01, 0x62, 0x04, 0x04, 0x00, 0x07, 0x01, 0x14, 0x2e, 0xee, 0xed, 0x93,
+0xdb, 0x00, 0x51, 0x00, 0x00, 0x00, 0x53, 0x00, 0x00, 0x08, 0xfa, 0x55,
+0x46, 0x4e, 0xb4, 0x73, 0x65, 0x65, 0x06, 0x53, 0x01, 0x44, 0x01, 0x53,
+0x06, 0x44, 0x07, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x05, 0x2e, 0x03, 0x1e,
+0x03, 0x63, 0x00, 0x07, 0x40, 0xb4, 0x60, 0x56, 0x64, 0x64, 0xe7, 0x00,
+0x33, 0x00, 0x00, 0x03, 0x75, 0xb8, 0xc3, 0x00, 0x04, 0xb9, 0x01, 0x52,
+0x03, 0x29, 0x03, 0x27, 0x03, 0x7b, 0x01, 0x5a, 0x04, 0x12, 0x06, 0x02,
+0x05, 0x14, 0x03, 0x0c, 0x04, 0x20, 0x05, 0x04, 0x01, 0x62, 0x06, 0x01,
+0x01, 0x32, 0x03, 0x38, 0x01, 0x1f, 0x01, 0x1f, 0x06, 0x08, 0x01, 0x1d,
+0x01, 0x1d, 0x05, 0x54, 0x07, 0x06, 0x03, 0x23, 0x05, 0x18, 0x01, 0x23,
+0x03, 0x18, 0x04, 0x47, 0x07, 0x21, 0x01, 0x47, 0x05, 0x21, 0x00, 0x0a,
+0x10, 0x18, 0xb9, 0x8c, 0x76, 0x7f, 0xf7, 0x00, 0x00, 0x0d, 0x21, 0x00,
+0x00, 0x0c, 0x03, 0x00, 0xf1, 0x0a, 0xc0, 0xb9, 0xca, 0x47, 0x47, 0x18,
+0x58, 0x18, 0x04, 0x23, 0x06, 0x06, 0x05, 0x54, 0x03, 0x1d, 0x06, 0x08,
+0x04, 0x1f, 0x01, 0x38, 0x03, 0x32, 0x00, 0x06, 0x01, 0x62, 0x01, 0x01,
+0x62, 0x62, 0x03, 0x04, 0x00, 0x09, 0x01, 0x5c, 0xee, 0xed, 0x8c, 0xb8,
+0x7c, 0x00, 0x11, 0x00, 0x4e, 0x00, 0x00, 0x00, 0x53, 0x00, 0x00, 0x07,
+0xec, 0x5e, 0x46, 0x56, 0x91, 0x22, 0x73, 0x00, 0x09, 0x53, 0x07, 0x44,
+0x06, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x05, 0x2e, 0x03, 0x1e, 0x00, 0x0a,
+0x63, 0x63, 0x1e, 0x1e, 0x74, 0x5f, 0x48, 0x5e, 0xfa, 0x4d, 0x2f, 0x00,
+0x00, 0x0b, 0x0d, 0x00, 0x00, 0xe7, 0xb4, 0x0a, 0xb9, 0xb9, 0x76, 0xb9,
+0x52, 0x00, 0x06, 0x27, 0x01, 0x7b, 0x01, 0x7b, 0x03, 0x5a, 0x03, 0x12,
+0x06, 0x02, 0x06, 0x14, 0x01, 0x0c, 0x01, 0x0c, 0x03, 0x20, 0x06, 0x04,
+0x01, 0x62, 0x04, 0x01, 0x00, 0x05, 0x32, 0x32, 0x01, 0x32, 0x38, 0x00,
+0x03, 0x1f, 0x06, 0x08, 0x01, 0x1d, 0x01, 0x1d, 0x05, 0x54, 0x05, 0x06,
+0x04, 0x23, 0x09, 0x18, 0x03, 0x47, 0x10, 0x21, 0x00, 0x03, 0x10, 0x13,
+0x5a, 0x00, 0x03, 0x8c, 0x00, 0x04, 0xa5, 0xb2, 0x00, 0x4d, 0x21, 0x00,
+0x00, 0x09, 0x4d, 0x00, 0xe7, 0x37, 0xf0, 0x76, 0xb9, 0x01, 0x21, 0x00,
+0x04, 0x18, 0x01, 0x23, 0x01, 0x18, 0x04, 0x23, 0x05, 0x06, 0x05, 0x54,
+0x03, 0x1d, 0x06, 0x08, 0x03, 0x1f, 0x00, 0x04, 0x38, 0x32, 0x01, 0x32,
+0x03, 0x01, 0x03, 0x62, 0x00, 0x0b, 0x04, 0x62, 0x01, 0x12, 0xed, 0xee,
+0xed, 0x8c, 0x69, 0x00, 0x26, 0x00, 0x4e, 0x00, 0x00, 0x00, 0x53, 0x00,
+0x00, 0x08, 0x71, 0xeb, 0x46, 0x56, 0x5f, 0xbb, 0x73, 0x65, 0x07, 0x53,
+0x07, 0x44, 0x05, 0x22, 0x00, 0x03, 0x4a, 0x22, 0x22, 0x00, 0x03, 0x4a,
+0x04, 0x40, 0x05, 0x2e, 0x04, 0x1e, 0x00, 0x0b, 0x63, 0x63, 0x40, 0xb4,
+0x4e, 0x5f, 0x56, 0x5f, 0xad, 0x00, 0x11, 0x00, 0x2d, 0x00, 0x00, 0x06,
+0x03, 0x00, 0x00, 0xb1, 0x82, 0x86, 0x04, 0x76, 0x00, 0x04, 0x37, 0x27,
+0x29, 0x29, 0x04, 0x27, 0x00, 0x04, 0x7b, 0x7b, 0x5a, 0x5a, 0x03, 0x12,
+0x06, 0x02, 0x05, 0x14, 0x03, 0x0c, 0x03, 0x20, 0x05, 0x04, 0x01, 0x62,
+0x01, 0x62, 0x04, 0x01, 0x03, 0x32, 0x01, 0x38, 0x01, 0x38, 0x03, 0x1f,
+0x05, 0x08, 0x01, 0x1d, 0x01, 0x1d, 0x05, 0x54, 0x05, 0x06, 0x05, 0x23,
+0x08, 0x18, 0x03, 0x47, 0x05, 0x21, 0x01, 0x47, 0x06, 0x21, 0x00, 0x03,
+0x10, 0x10, 0x21, 0x00, 0x05, 0x10, 0x00, 0x08, 0x06, 0x76, 0x93, 0x8c,
+0x0e, 0xcf, 0x00, 0x03, 0x21, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x00, 0xcf,
+0x17, 0x1e, 0x8c, 0x52, 0x10, 0x47, 0x06, 0x18, 0x05, 0x23, 0x05, 0x06,
+0x05, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x06, 0x08, 0x03, 0x1f, 0x00, 0x04,
+0x38, 0x38, 0x01, 0x32, 0x04, 0x01, 0x00, 0x0b, 0x62, 0x62, 0x04, 0x62,
+0x04, 0xa6, 0xed, 0xa5, 0x8c, 0xd4, 0x6b, 0x00, 0x4f, 0x00, 0x00, 0x00,
+0x54, 0x00, 0x00, 0x07, 0xd9, 0x46, 0x56, 0x5f, 0x80, 0x53, 0x73, 0x00,
+0x07, 0x53, 0x06, 0x44, 0x08, 0x22, 0x04, 0x4a, 0x04, 0x40, 0x04, 0x2e,
+0x04, 0x1e, 0x03, 0x63, 0x00, 0x09, 0x40, 0x74, 0x9d, 0x9d, 0x64, 0x68,
+0x00, 0x00, 0x0d, 0x00, 0x2c, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x7e,
+0x3e, 0x17, 0x04, 0x76, 0x00, 0x04, 0x37, 0x27, 0x29, 0x29, 0x04, 0x27,
+0x03, 0x7b, 0x01, 0x5a, 0x04, 0x12, 0x05, 0x02, 0x06, 0x14, 0x03, 0x0c,
+0x01, 0x20, 0x01, 0x20, 0x06, 0x04, 0x01, 0x62, 0x04, 0x01, 0x03, 0x32,
+0x01, 0x38, 0x03, 0x1f, 0x06, 0x08, 0x03, 0x1d, 0x04, 0x54, 0x05, 0x06,
+0x00, 0x04, 0x23, 0x06, 0x23, 0x23, 0x06, 0x18, 0x01, 0x47, 0x01, 0x18,
+0x03, 0x47, 0x0e, 0x21, 0x06, 0x10, 0x00, 0x09, 0x16, 0x16, 0xbc, 0x52,
+0x93, 0x53, 0xe5, 0x82, 0xad, 0x00, 0x23, 0x00, 0x00, 0x0a, 0x26, 0x00,
+0x7e, 0x1e, 0x76, 0x8c, 0x76, 0x08, 0x10, 0x47, 0x03, 0x18, 0x01, 0x23,
+0x03, 0x18, 0x05, 0x23, 0x04, 0x06, 0x04, 0x54, 0x03, 0x1d, 0x07, 0x08,
+0x00, 0x06, 0x1f, 0x38, 0x38, 0x32, 0x32, 0x38, 0x04, 0x01, 0x03, 0x62,
+0x01, 0x01, 0x01, 0x7b, 0x03, 0xa5, 0x01, 0xed, 0x01, 0xb1, 0x4f, 0x00,
+0x00, 0x00, 0x54, 0x00, 0x00, 0x07, 0xd2, 0x5f, 0x4e, 0x5f, 0x48, 0xa5,
+0x73, 0x00, 0x06, 0x53, 0x07, 0x44, 0x06, 0x22, 0x06, 0x4a, 0x04, 0x40,
+0x04, 0x2e, 0x04, 0x1e, 0x00, 0x0b, 0x63, 0x63, 0x1e, 0x37, 0x8f, 0x9d,
+0x5f, 0x5f, 0xe7, 0x00, 0x03, 0x00, 0x2c, 0x00, 0x00, 0x0e, 0x03, 0x00,
+0x00, 0x69, 0x63, 0x7f, 0x76, 0x76, 0x8c, 0x76, 0x37, 0x27, 0x29, 0x29,
+0x05, 0x27, 0x00, 0x03, 0x7b, 0x5a, 0x5a, 0x00, 0x04, 0x12, 0x05, 0x02,
+0x05, 0x14, 0x04, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x03, 0x62,
+0x04, 0x01, 0x03, 0x32, 0x00, 0x04, 0x38, 0x38, 0x1f, 0x1f, 0x06, 0x08,
+0x01, 0x1d, 0x01, 0x1d, 0x05, 0x54, 0x03, 0x06, 0x05, 0x23, 0x08, 0x18,
+0x01, 0x47, 0x01, 0x47, 0x0b, 0x21, 0x06, 0x10, 0x08, 0x16, 0x00, 0x07,
+0xbc, 0x1f, 0x8c, 0x93, 0x93, 0x19, 0x69, 0x00, 0x23, 0x00, 0x00, 0x0d,
+0x0d, 0x00, 0x71, 0xf4, 0x7f, 0x8c, 0x8c, 0x5a, 0x10, 0x47, 0x47, 0x18,
+0x47, 0x00, 0x06, 0x18, 0x04, 0x23, 0x05, 0x06, 0x04, 0x54, 0x03, 0x1d,
+0x05, 0x08, 0x03, 0x1f, 0x00, 0x04, 0x38, 0x38, 0x32, 0x32, 0x04, 0x01,
+0x00, 0x0a, 0x62, 0x62, 0x01, 0x04, 0xa6, 0xa5, 0x82, 0x40, 0xcf, 0x4d,
+0x4e, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x08, 0x11, 0x68, 0x60, 0x9d,
+0x9d, 0xa8, 0x73, 0x65, 0x05, 0x53, 0x06, 0x44, 0x06, 0x22, 0x06, 0x4a,
+0x04, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x00, 0x0a, 0x63, 0x63, 0x30, 0x76,
+0xc1, 0x9d, 0xa7, 0x60, 0xfa, 0x4d, 0x30, 0x00, 0x00, 0x08, 0xc5, 0x8c,
+0x7f, 0x76, 0x8c, 0x8c, 0x76, 0x37, 0x04, 0x29, 0x03, 0x27, 0x00, 0x04,
+0x7b, 0x7b, 0x5a, 0x5a, 0x04, 0x12, 0x05, 0x02, 0x05, 0x14, 0x04, 0x0c,
+0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x03, 0x62, 0x05, 0x01, 0x00, 0x03,
+0x32, 0x32, 0x38, 0x00, 0x03, 0x1f, 0x06, 0x08, 0x01, 0x1d, 0x06, 0x54,
+0x04, 0x06, 0x04, 0x23, 0x06, 0x18, 0x03, 0x47, 0x04, 0x21, 0x01, 0x47,
+0x01, 0x47, 0x06, 0x21, 0x03, 0x10, 0x04, 0x16, 0x01, 0x13, 0x06, 0x16,
+0x03, 0x13, 0x00, 0x06, 0x76, 0x6e, 0x93, 0xe5, 0xf4, 0x6b, 0x25, 0x00,
+0x00, 0x07, 0xf1, 0x93, 0x8c, 0x93, 0xb9, 0x06, 0x10, 0x00, 0x05, 0x47,
+0x00, 0x06, 0x18, 0x18, 0x58, 0x18, 0x23, 0x18, 0x04, 0x23, 0x04, 0x06,
+0x05, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x05, 0x08, 0x03, 0x1f, 0x00, 0x04,
+0x38, 0x38, 0x32, 0x38, 0x04, 0x01, 0x03, 0x62, 0x00, 0x06, 0x7b, 0x82,
+0x82, 0xa5, 0xbb, 0xad, 0x4e, 0x00, 0x00, 0x00, 0x55, 0x00, 0x00, 0x07,
+0xe7, 0x48, 0x5f, 0x9d, 0x8f, 0xee, 0x65, 0x00, 0x05, 0x53, 0x06, 0x44,
+0x07, 0x22, 0x05, 0x4a, 0x03, 0x40, 0x05, 0x2e, 0x04, 0x1e, 0x03, 0x63,
+0x00, 0x06, 0x30, 0x80, 0x9d, 0x4e, 0x4e, 0xd9, 0x30, 0x00, 0x00, 0x03,
+0xf1, 0x8c, 0x7f, 0x00, 0x03, 0x8c, 0x01, 0x76, 0x01, 0x37, 0x03, 0x29,
+0x06, 0x27, 0x00, 0x03, 0x7b, 0x5a, 0x5a, 0x00, 0x04, 0x12, 0x06, 0x02,
+0x03, 0x14, 0x00, 0x06, 0x0c, 0x0c, 0x20, 0x0c, 0x20, 0x20, 0x05, 0x04,
+0x01, 0x62, 0x01, 0x62, 0x04, 0x01, 0x00, 0x04, 0x32, 0x32, 0x01, 0x38,
+0x03, 0x1f, 0x05, 0x08, 0x03, 0x1d, 0x05, 0x54, 0x03, 0x06, 0x00, 0x0d,
+0x23, 0x06, 0x23, 0x23, 0x18, 0x18, 0x58, 0x23, 0x18, 0x18, 0x47, 0x47,
+0x21, 0x00, 0x05, 0x47, 0x07, 0x21, 0x04, 0x10, 0x0b, 0x16, 0x03, 0x13,
+0x00, 0x07, 0xbc, 0x02, 0x6e, 0x6e, 0xe5, 0x6e, 0xb1, 0x00, 0x25, 0x00,
+0x00, 0x0a, 0x7c, 0x82, 0xe5, 0x93, 0x93, 0x14, 0xbc, 0x18, 0x21, 0x21,
+0x03, 0x47, 0x07, 0x18, 0x04, 0x23, 0x03, 0x06, 0x05, 0x54, 0x03, 0x1d,
+0x05, 0x08, 0x03, 0x1f, 0x00, 0x04, 0x38, 0x38, 0x32, 0x32, 0x03, 0x01,
+0x00, 0x08, 0x62, 0x32, 0x20, 0x82, 0x82, 0xa6, 0xa5, 0x69, 0x4e, 0x00,
+0x00, 0x00, 0x55, 0x00, 0x00, 0x07, 0xa3, 0xfa, 0x60, 0x9d, 0x5f, 0xb8,
+0x73, 0x00, 0x04, 0x53, 0x07, 0x44, 0x07, 0x22, 0x04, 0x4a, 0x04, 0x40,
+0x05, 0x2e, 0x03, 0x1e, 0x00, 0x0a, 0x63, 0x63, 0x30, 0x40, 0xb4, 0x60,
+0x48, 0x46, 0x9d, 0xd2, 0x2f, 0x00, 0x00, 0x03, 0xdb, 0x93, 0x7f, 0x00,
+0x03, 0x8c, 0x00, 0x03, 0x76, 0x52, 0x27, 0x00, 0x03, 0x29, 0x04, 0x27,
+0x03, 0x7b, 0x05, 0x12, 0x05, 0x02, 0x04, 0x14, 0x04, 0x0c, 0x03, 0x20,
+0x03, 0x04, 0x04, 0x62, 0x03, 0x01, 0x00, 0x07, 0x32, 0x01, 0x01, 0x38,
+0x38, 0x1f, 0x1f, 0x00, 0x05, 0x08, 0x03, 0x1d, 0x00, 0x04, 0x54, 0x54,
+0x06, 0x54, 0x03, 0x06, 0x04, 0x23, 0x08, 0x18, 0x01, 0x47, 0x0a, 0x21,
+0x01, 0x10, 0x01, 0x16, 0x03, 0x10, 0x06, 0x16, 0x01, 0x13, 0x01, 0x16,
+0x03, 0x13, 0x01, 0x16, 0x01, 0x16, 0x04, 0x13, 0x00, 0x07, 0x2a, 0xb7,
+0x93, 0x6e, 0x6e, 0x83, 0x6a, 0x00, 0x26, 0x00, 0x00, 0x08, 0x6a, 0xe5,
+0x93, 0x6e, 0xb9, 0x21, 0x10, 0x47, 0x04, 0x21, 0x01, 0x47, 0x01, 0x47,
+0x05, 0x18, 0x05, 0x23, 0x04, 0x06, 0x04, 0x54, 0x03, 0x1d, 0x05, 0x08,
+0x00, 0x04, 0x1f, 0x1f, 0x38, 0x38, 0x03, 0x32, 0x00, 0x0b, 0x01, 0x01,
+0x62, 0x01, 0x62, 0xb4, 0x82, 0x82, 0xa5, 0xf4, 0x4d, 0x00, 0x4d, 0x00,
+0x00, 0x00, 0x54, 0x00, 0x00, 0x07, 0x03, 0x00, 0xec, 0x64, 0x48, 0x9d,
+0x81, 0x00, 0x04, 0x53, 0x07, 0x44, 0x08, 0x22, 0x04, 0x4a, 0x04, 0x40,
+0x04, 0x2e, 0x04, 0x1e, 0x00, 0x09, 0x63, 0x63, 0x30, 0x40, 0xc1, 0x5f,
+0x4e, 0x50, 0xfa, 0x00, 0x2c, 0x00, 0x00, 0x0c, 0x11, 0x00, 0x4d, 0x8a,
+0xe5, 0xe5, 0x8c, 0x93, 0x93, 0x76, 0x52, 0x27, 0x04, 0x29, 0x04, 0x27,
+0x00, 0x04, 0x7b, 0x7b, 0x5a, 0x5a, 0x03, 0x12, 0x05, 0x02, 0x01, 0x14,
+0x01, 0x02, 0x03, 0x14, 0x03, 0x0c, 0x04, 0x20, 0x03, 0x04, 0x03, 0x62,
+0x04, 0x01, 0x01, 0x32, 0x01, 0x38, 0x03, 0x1f, 0x06, 0x08, 0x03, 0x1d,
+0x04, 0x54, 0x03, 0x06, 0x04, 0x23, 0x06, 0x18, 0x03, 0x47, 0x00, 0x03,
+0x21, 0x21, 0x47, 0x00, 0x06, 0x21, 0x03, 0x10, 0x0a, 0x16, 0x01, 0x13,
+0x01, 0x16, 0x09, 0x13, 0x00, 0x08, 0x2a, 0x2a, 0x52, 0x57, 0x6e, 0x83,
+0x65, 0x7c, 0x25, 0x00, 0x00, 0x07, 0xb2, 0x93, 0xe5, 0x6e, 0x93, 0x04,
+0x10, 0x00, 0x06, 0x21, 0x01, 0x47, 0x01, 0x47, 0x07, 0x18, 0x00, 0x03,
+0x23, 0x06, 0x23, 0x00, 0x04, 0x06, 0x04, 0x54, 0x01, 0x1d, 0x01, 0x1d,
+0x06, 0x08, 0x03, 0x1f, 0x00, 0x03, 0x38, 0x32, 0x32, 0x00, 0x05, 0x01,
+0x00, 0x06, 0xaa, 0xbb, 0xbb, 0x82, 0xbb, 0xb1, 0x4d, 0x00, 0x00, 0x00,
+0x54, 0x00, 0x00, 0x0a, 0x03, 0x00, 0xd2, 0xeb, 0x46, 0x56, 0x4e, 0xbb,
+0x73, 0x53, 0x08, 0x44, 0x07, 0x22, 0x05, 0x4a, 0x03, 0x40, 0x05, 0x2e,
+0x04, 0x1e, 0x00, 0x09, 0x63, 0x63, 0x30, 0x3e, 0x74, 0x56, 0x46, 0x46,
+0xd9, 0x00, 0x2d, 0x00, 0x00, 0x03, 0x71, 0xd4, 0xe5, 0x00, 0x04, 0x93,
+0x00, 0x04, 0x76, 0x52, 0x29, 0x52, 0x03, 0x29, 0x04, 0x27, 0x03, 0x7b,
+0x01, 0x5a, 0x03, 0x12, 0x06, 0x02, 0x04, 0x14, 0x03, 0x0c, 0x03, 0x20,
+0x05, 0x04, 0x01, 0x62, 0x01, 0x62, 0x03, 0x01, 0x00, 0x06, 0x32, 0x32,
+0x38, 0x38, 0x1f, 0x1f, 0x06, 0x08, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x54,
+0x04, 0x06, 0x04, 0x23, 0x07, 0x18, 0x00, 0x05, 0x47, 0x21, 0x21, 0x47,
+0x47, 0x00, 0x06, 0x21, 0x00, 0x03, 0x10, 0x16, 0x10, 0x00, 0x09, 0x16,
+0x0c, 0x13, 0x00, 0x09, 0x2a, 0x2a, 0x4c, 0x1f, 0x6e, 0x57, 0x83, 0x6d,
+0x94, 0x00, 0x26, 0x00, 0x00, 0x07, 0xb8, 0x83, 0x6e, 0x57, 0xc0, 0x10,
+0x10, 0x00, 0x07, 0x21, 0x01, 0x47, 0x07, 0x18, 0x03, 0x23, 0x04, 0x06,
+0x05, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x05, 0x08, 0x03, 0x1f, 0x00, 0x04,
+0x38, 0x32, 0x01, 0x32, 0x03, 0x01, 0x00, 0x06, 0x62, 0xb4, 0xbb, 0xb4,
+0xa6, 0xcf, 0x4d, 0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x07, 0x68, 0x50,
+0x64, 0x5f, 0x72, 0x65, 0x53, 0x00, 0x07, 0x44, 0x06, 0x22, 0x01, 0x4a,
+0x01, 0x22, 0x05, 0x4a, 0x03, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x03, 0x63,
+0x00, 0x07, 0x1e, 0x37, 0x7a, 0x64, 0x55, 0x64, 0xd2, 0x00, 0x2c, 0x00,
+0x00, 0x03, 0x6b, 0xf4, 0x83, 0x00, 0x04, 0x93, 0x01, 0x76, 0x01, 0x52,
+0x05, 0x29, 0x05, 0x27, 0x01, 0x7b, 0x01, 0x5a, 0x05, 0x12, 0x06, 0x02,
+0x04, 0x14, 0x03, 0x0c, 0x03, 0x20, 0x04, 0x04, 0x01, 0x62, 0x01, 0x62,
+0x03, 0x01, 0x03, 0x32, 0x01, 0x38, 0x03, 0x1f, 0x05, 0x08, 0x01, 0x1d,
+0x01, 0x1d, 0x04, 0x54, 0x06, 0x06, 0x01, 0x23, 0x01, 0x23, 0x06, 0x18,
+0x01, 0x47, 0x03, 0x21, 0x01, 0x47, 0x01, 0x47, 0x04, 0x21, 0x04, 0x10,
+0x08, 0x16, 0x0a, 0x13, 0x03, 0x2a, 0x01, 0x13, 0x01, 0x13, 0x04, 0x2a,
+0x00, 0x06, 0x30, 0x8d, 0x57, 0x9e, 0x87, 0x71, 0x25, 0x00, 0x00, 0x07,
+0x69, 0x83, 0x57, 0x57, 0x93, 0x54, 0xbc, 0x00, 0x09, 0x21, 0x01, 0x47,
+0x06, 0x18, 0x04, 0x23, 0x04, 0x06, 0x03, 0x54, 0x03, 0x1d, 0x05, 0x08,
+0x03, 0x1f, 0x00, 0x03, 0x38, 0x32, 0x32, 0x00, 0x04, 0x01, 0x00, 0x06,
+0xaa, 0xbb, 0xb8, 0x82, 0xa8, 0x75, 0x4c, 0x00, 0x00, 0x00, 0x57, 0x00,
+0x00, 0x07, 0xe7, 0x56, 0x55, 0x4e, 0x7a, 0xa5, 0x65, 0x00, 0x07, 0x44,
+0x07, 0x22, 0x05, 0x4a, 0x03, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x03, 0x63,
+0x00, 0x08, 0x30, 0x2e, 0xb4, 0x64, 0x46, 0x3d, 0xeb, 0x11, 0x2b, 0x00,
+0x00, 0x0b, 0x8e, 0xf4, 0x66, 0x6e, 0x93, 0x6e, 0x93, 0x76, 0x52, 0x29,
+0x52, 0x00, 0x04, 0x29, 0x04, 0x27, 0x00, 0x03, 0x7b, 0x7b, 0x5a, 0x00,
+0x04, 0x12, 0x05, 0x02, 0x05, 0x14, 0x03, 0x0c, 0x01, 0x20, 0x01, 0x20,
+0x05, 0x04, 0x01, 0x62, 0x01, 0x62, 0x04, 0x01, 0x00, 0x06, 0x32, 0x32,
+0x38, 0x38, 0x1f, 0x1f, 0x04, 0x08, 0x03, 0x1d, 0x04, 0x54, 0x04, 0x06,
+0x03, 0x23, 0x06, 0x18, 0x01, 0x47, 0x09, 0x21, 0x04, 0x10, 0x06, 0x16,
+0x0a, 0x13, 0x03, 0x2a, 0x01, 0x13, 0x01, 0x13, 0x07, 0x2a, 0x00, 0x07,
+0x41, 0x14, 0x57, 0x57, 0x83, 0x73, 0x96, 0x00, 0x25, 0x00, 0x00, 0x09,
+0x7c, 0xed, 0x83, 0x8d, 0x8d, 0x5a, 0xbc, 0x10, 0x10, 0x00, 0x08, 0x21,
+0x01, 0x47, 0x01, 0x47, 0x03, 0x18, 0x00, 0x03, 0x23, 0x23, 0x18, 0x00,
+0x03, 0x23, 0x04, 0x06, 0x04, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x05, 0x08,
+0x03, 0x1f, 0x00, 0x0c, 0x38, 0x32, 0x32, 0x01, 0x01, 0x32, 0x62, 0xb4,
+0xb8, 0xb4, 0xb4, 0xf1, 0x4c, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x06,
+0xeb, 0x78, 0x46, 0x4e, 0xaf, 0x65, 0x07, 0x44, 0x07, 0x22, 0x04, 0x4a,
+0x04, 0x40, 0x04, 0x2e, 0x03, 0x1e, 0x06, 0x63, 0x00, 0x05, 0xaf, 0x64,
+0x50, 0x78, 0x90, 0x00, 0x28, 0x00, 0x00, 0x0f, 0x0d, 0x00, 0x00, 0x8e,
+0xf4, 0x5d, 0x6e, 0x93, 0x6e, 0x6e, 0x63, 0x29, 0x29, 0x52, 0x52, 0x00,
+0x03, 0x29, 0x05, 0x27, 0x00, 0x03, 0x7b, 0x5a, 0x5a, 0x00, 0x04, 0x12,
+0x05, 0x02, 0x03, 0x14, 0x00, 0x04, 0x0c, 0x14, 0x0c, 0x0c, 0x03, 0x20,
+0x03, 0x04, 0x03, 0x62, 0x04, 0x01, 0x00, 0x03, 0x32, 0x32, 0x38, 0x00,
+0x03, 0x1f, 0x04, 0x08, 0x03, 0x1d, 0x04, 0x54, 0x05, 0x06, 0x01, 0x23,
+0x01, 0x23, 0x05, 0x18, 0x03, 0x47, 0x07, 0x21, 0x04, 0x10, 0x08, 0x16,
+0x09, 0x13, 0x0d, 0x2a, 0x00, 0x07, 0x0f, 0xf3, 0x40, 0x6e, 0x73, 0x83,
+0xd4, 0x00, 0x26, 0x00, 0x00, 0x09, 0xb6, 0x9e, 0x57, 0x8d, 0x8c, 0x13,
+0x13, 0x10, 0x10, 0x00, 0x08, 0x21, 0x01, 0x47, 0x01, 0x47, 0x06, 0x18,
+0x01, 0x23, 0x01, 0x23, 0x05, 0x06, 0x03, 0x54, 0x03, 0x1d, 0x05, 0x08,
+0x03, 0x1f, 0x00, 0x0e, 0x38, 0x32, 0x32, 0x01, 0x01, 0x32, 0xaf, 0xb8,
+0xb8, 0xb4, 0xf7, 0x6b, 0x00, 0x03, 0x49, 0x00, 0x00, 0x00, 0x58, 0x00,
+0x00, 0x07, 0xec, 0x55, 0x55, 0x64, 0x80, 0xee, 0x65, 0x00, 0x05, 0x44,
+0x07, 0x22, 0x04, 0x4a, 0x05, 0x40, 0x04, 0x2e, 0x03, 0x1e, 0x03, 0x63,
+0x00, 0x08, 0x30, 0x1e, 0x3e, 0xf8, 0x5e, 0x55, 0x78, 0xd9, 0x27, 0x00,
+0x00, 0x0e, 0x03, 0x00, 0x00, 0x75, 0xbb, 0x83, 0x6e, 0x6e, 0x57, 0x6e,
+0x63, 0x29, 0x29, 0x52, 0x04, 0x29, 0x06, 0x27, 0x01, 0x5a, 0x01, 0x5a,
+0x04, 0x12, 0x05, 0x02, 0x04, 0x14, 0x00, 0x03, 0x0c, 0x14, 0x0c, 0x00,
+0x03, 0x20, 0x04, 0x04, 0x01, 0x62, 0x01, 0x62, 0x04, 0x01, 0x01, 0x32,
+0x03, 0x38, 0x01, 0x1f, 0x01, 0x1f, 0x05, 0x08, 0x03, 0x1d, 0x03, 0x54,
+0x03, 0x06, 0x04, 0x23, 0x05, 0x18, 0x01, 0x47, 0x01, 0x47, 0x08, 0x21,
+0x03, 0x10, 0x07, 0x16, 0x08, 0x13, 0x0b, 0x2a, 0x00, 0x03, 0x0f, 0x2a,
+0x2a, 0x00, 0x03, 0x0f, 0x00, 0x0a, 0x2a, 0x41, 0x7b, 0x73, 0x65, 0x6e,
+0xed, 0x9a, 0x00, 0x11, 0x23, 0x00, 0x00, 0x07, 0xb1, 0x6e, 0x57, 0x57,
+0x6e, 0x62, 0xbc, 0x00, 0x05, 0x10, 0x07, 0x21, 0x07, 0x18, 0x00, 0x03,
+0x23, 0x06, 0x23, 0x00, 0x04, 0x06, 0x04, 0x54, 0x01, 0x1d, 0x01, 0x1d,
+0x05, 0x08, 0x00, 0x09, 0x1f, 0x1f, 0x38, 0x38, 0x32, 0x32, 0x01, 0x32,
+0xaa, 0x00, 0x04, 0xaf, 0x00, 0x03, 0x7e, 0x00, 0x11, 0x00, 0x49, 0x00,
+0x00, 0x00, 0x58, 0x00, 0x00, 0x07, 0x71, 0x5f, 0x67, 0x50, 0x5e, 0x82,
+0x65, 0x00, 0x05, 0x44, 0x08, 0x22, 0x03, 0x4a, 0x04, 0x40, 0x04, 0x2e,
+0x05, 0x1e, 0x00, 0x0a, 0x63, 0x63, 0x30, 0x1e, 0x59, 0xfb, 0x50, 0x78,
+0x78, 0xad, 0x26, 0x00, 0x00, 0x0e, 0x03, 0x00, 0x00, 0xb2, 0xed, 0x2d,
+0x6e, 0x6e, 0x57, 0x6e, 0x30, 0x29, 0x29, 0x52, 0x05, 0x29, 0x03, 0x27,
+0x03, 0x7b, 0x01, 0x5a, 0x01, 0x5a, 0x03, 0x12, 0x05, 0x02, 0x05, 0x14,
+0x01, 0x0c, 0x01, 0x0c, 0x03, 0x20, 0x05, 0x04, 0x01, 0x62, 0x05, 0x01,
+0x01, 0x32, 0x01, 0x38, 0x04, 0x1f, 0x04, 0x08, 0x01, 0x1d, 0x01, 0x1d,
+0x04, 0x54, 0x03, 0x06, 0x04, 0x23, 0x05, 0x18, 0x01, 0x47, 0x01, 0x47,
+0x08, 0x21, 0x07, 0x16, 0x0b, 0x13, 0x09, 0x2a, 0x0a, 0x0f, 0x00, 0x09,
+0x4c, 0xf3, 0x40, 0x65, 0x22, 0xe5, 0xdb, 0x00, 0x03, 0x00, 0x23, 0x00,
+0x00, 0x07, 0x4d, 0xd4, 0x6d, 0x73, 0x6e, 0x3e, 0xbc, 0x00, 0x03, 0x16,
+0x01, 0x10, 0x01, 0x16, 0x04, 0x21, 0x00, 0x06, 0x47, 0x47, 0x21, 0x21,
+0x47, 0x47, 0x05, 0x18, 0x03, 0x23, 0x04, 0x06, 0x03, 0x54, 0x03, 0x1d,
+0x05, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x38, 0x32, 0x00, 0x03, 0x01,
+0x00, 0x06, 0xaf, 0xa8, 0xa8, 0xb4, 0xcf, 0x71, 0x4a, 0x00, 0x00, 0x00,
+0x59, 0x00, 0x00, 0x07, 0x7d, 0x49, 0x3d, 0x5e, 0xf8, 0x22, 0x53, 0x00,
+0x04, 0x44, 0x06, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x04, 0x2e, 0x04, 0x1e,
+0x00, 0x0b, 0x63, 0x63, 0x30, 0x30, 0x1e, 0x37, 0x78, 0x3d, 0x49, 0x46,
+0xd2, 0x00, 0x25, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x99, 0x44, 0x2d,
+0x57, 0x57, 0x8d, 0x6e, 0x30, 0x29, 0x03, 0x52, 0x05, 0x29, 0x01, 0x27,
+0x01, 0x27, 0x04, 0x7b, 0x01, 0x5a, 0x04, 0x12, 0x04, 0x02, 0x05, 0x14,
+0x01, 0x0c, 0x01, 0x0c, 0x03, 0x20, 0x04, 0x04, 0x03, 0x62, 0x03, 0x01,
+0x01, 0x32, 0x01, 0x32, 0x03, 0x38, 0x01, 0x1f, 0x05, 0x08, 0x01, 0x1d,
+0x01, 0x1d, 0x04, 0x54, 0x03, 0x06, 0x03, 0x23, 0x07, 0x18, 0x01, 0x47,
+0x07, 0x21, 0x01, 0x10, 0x06, 0x16, 0x00, 0x03, 0x13, 0x13, 0x16, 0x00,
+0x07, 0x13, 0x09, 0x2a, 0x0e, 0x0f, 0x00, 0x09, 0x41, 0xb4, 0x44, 0xee,
+0x93, 0xf4, 0x7c, 0x00, 0x26, 0x00, 0x21, 0x00, 0x00, 0x09, 0x4d, 0x00,
+0x96, 0x57, 0x6e, 0x6e, 0x44, 0x54, 0x13, 0x00, 0x03, 0x16, 0x03, 0x10,
+0x03, 0x21, 0x00, 0x06, 0x47, 0x47, 0x21, 0x21, 0x47, 0x47, 0x05, 0x18,
+0x04, 0x23, 0x03, 0x06, 0x03, 0x54, 0x03, 0x1d, 0x05, 0x08, 0x03, 0x1f,
+0x04, 0x32, 0x01, 0xaa, 0x04, 0xa8, 0x01, 0xe7, 0x4a, 0x00, 0x00, 0x00,
+0x59, 0x00, 0x00, 0x07, 0xad, 0x55, 0x49, 0xde, 0x3d, 0x3e, 0x65, 0x00,
+0x03, 0x44, 0x08, 0x22, 0x03, 0x4a, 0x04, 0x40, 0x05, 0x2e, 0x04, 0x1e,
+0x00, 0x0b, 0x63, 0x63, 0x30, 0x30, 0x1e, 0x7b, 0x3d, 0x3d, 0x0f, 0x9d,
+0x6b, 0x00, 0x27, 0x00, 0x00, 0x09, 0x96, 0x73, 0x2d, 0x57, 0x57, 0x8d,
+0x6e, 0x30, 0x29, 0x00, 0x03, 0x52, 0x05, 0x29, 0x03, 0x27, 0x03, 0x7b,
+0x00, 0x04, 0x5a, 0x7b, 0x12, 0x12, 0x06, 0x02, 0x04, 0x14, 0x03, 0x0c,
+0x03, 0x20, 0x04, 0x04, 0x01, 0x62, 0x01, 0x62, 0x04, 0x01, 0x00, 0x05,
+0x32, 0x38, 0x38, 0x1f, 0x1f, 0x00, 0x05, 0x08, 0x01, 0x1d, 0x04, 0x54,
+0x04, 0x06, 0x03, 0x23, 0x05, 0x18, 0x03, 0x47, 0x06, 0x21, 0x03, 0x10,
+0x06, 0x16, 0x09, 0x13, 0x07, 0x2a, 0x0e, 0x0f, 0x00, 0x0c, 0x4c, 0x0f,
+0x0f, 0x4c, 0xf8, 0xed, 0xee, 0xed, 0x8c, 0x96, 0x00, 0x26, 0x21, 0x00,
+0x00, 0x09, 0x03, 0x00, 0x8e, 0xb8, 0x83, 0x65, 0x73, 0x27, 0xbc, 0x00,
+0x04, 0x16, 0x03, 0x10, 0x07, 0x21, 0x01, 0x47, 0x01, 0x47, 0x06, 0x18,
+0x03, 0x23, 0x03, 0x06, 0x03, 0x54, 0x03, 0x1d, 0x05, 0x08, 0x03, 0x1f,
+0x03, 0x32, 0x00, 0x06, 0x62, 0xa8, 0xa8, 0x72, 0xaf, 0x8b, 0x4a, 0x00,
+0x00, 0x00, 0x59, 0x00, 0x00, 0x0a, 0x4d, 0xfa, 0x2a, 0x78, 0xde, 0xaf,
+0x53, 0x53, 0x44, 0x44, 0x06, 0x22, 0x06, 0x4a, 0x03, 0x40, 0x04, 0x2e,
+0x04, 0x1e, 0x03, 0x63, 0x00, 0x09, 0x30, 0x63, 0x63, 0x12, 0x67, 0x67,
+0x2a, 0xeb, 0xa3, 0x00, 0x26, 0x00, 0x00, 0x03, 0x99, 0x65, 0x6d, 0x00,
+0x03, 0x6e, 0x00, 0x03, 0x93, 0x3e, 0x29, 0x00, 0x04, 0x52, 0x04, 0x29,
+0x05, 0x27, 0x00, 0x03, 0x7b, 0x5a, 0x5a, 0x00, 0x03, 0x12, 0x05, 0x02,
+0x04, 0x14, 0x03, 0x0c, 0x03, 0x20, 0x03, 0x04, 0x03, 0x62, 0x00, 0x07,
+0x01, 0x62, 0x01, 0x32, 0x01, 0x38, 0x38, 0x00, 0x03, 0x1f, 0x04, 0x08,
+0x01, 0x1d, 0x01, 0x1d, 0x04, 0x54, 0x03, 0x06, 0x03, 0x23, 0x05, 0x18,
+0x01, 0x47, 0x01, 0x47, 0x08, 0x21, 0x01, 0x10, 0x01, 0x10, 0x05, 0x16,
+0x07, 0x13, 0x08, 0x2a, 0x11, 0x0f, 0x00, 0x0b, 0x4c, 0x0f, 0x0f, 0x4c,
+0x0f, 0x82, 0xed, 0xa5, 0x8c, 0xf7, 0x71, 0x00, 0x23, 0x00, 0x00, 0x09,
+0x03, 0x00, 0xdb, 0x57, 0x65, 0x73, 0x63, 0x16, 0x13, 0x00, 0x05, 0x16,
+0x01, 0x10, 0x01, 0x10, 0x08, 0x21, 0x01, 0x47, 0x01, 0x47, 0x03, 0x18,
+0x01, 0x58, 0x01, 0x18, 0x03, 0x23, 0x04, 0x06, 0x03, 0x54, 0x01, 0x1d,
+0x01, 0x1d, 0x05, 0x08, 0x00, 0x03, 0x1f, 0x38, 0x38, 0x00, 0x03, 0x32,
+0x00, 0x06, 0xc1, 0xa8, 0x72, 0xa8, 0x81, 0x8e, 0x49, 0x00, 0x00, 0x00,
+0x5a, 0x00, 0x00, 0x09, 0xec, 0x2a, 0x49, 0x3d, 0xfb, 0x4a, 0x53, 0x44,
+0x44, 0x00, 0x07, 0x22, 0x03, 0x4a, 0x05, 0x40, 0x04, 0x2e, 0x03, 0x1e,
+0x04, 0x63, 0x03, 0x30, 0x00, 0x06, 0xaa, 0x49, 0x41, 0x16, 0x90, 0x11,
+0x25, 0x00, 0x00, 0x03, 0x75, 0xed, 0x83, 0x00, 0x03, 0x73, 0x00, 0x04,
+0x53, 0x59, 0x29, 0x37, 0x04, 0x52, 0x04, 0x29, 0x04, 0x27, 0x00, 0x03,
+0x7b, 0x5a, 0x5a, 0x00, 0x04, 0x12, 0x05, 0x02, 0x03, 0x14, 0x04, 0x0c,
+0x03, 0x20, 0x03, 0x04, 0x01, 0x62, 0x01, 0x62, 0x04, 0x01, 0x00, 0x05,
+0x32, 0x32, 0x38, 0x38, 0x1f, 0x00, 0x05, 0x08, 0x01, 0x1d, 0x01, 0x1d,
+0x04, 0x54, 0x03, 0x06, 0x03, 0x23, 0x05, 0x18, 0x00, 0x06, 0x47, 0x47,
+0x21, 0x21, 0x47, 0x47, 0x03, 0x21, 0x03, 0x10, 0x05, 0x16, 0x07, 0x13,
+0x07, 0x2a, 0x0e, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x04, 0x0f, 0x03, 0x4c,
+0x00, 0x07, 0x41, 0xc1, 0x82, 0x82, 0xa5, 0x82, 0x9a, 0x00, 0x23, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0x75, 0xed, 0x6e, 0x65, 0x53, 0xaa, 0xbc, 0x13,
+0x06, 0x16, 0x03, 0x10, 0x05, 0x21, 0x03, 0x47, 0x04, 0x18, 0x04, 0x23,
+0x03, 0x06, 0x04, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08, 0x03, 0x1f,
+0x00, 0x09, 0x38, 0x32, 0x32, 0x01, 0x72, 0x74, 0x72, 0xc1, 0x7e, 0x00,
+0x49, 0x00, 0x00, 0x00, 0x5a, 0x00, 0x00, 0x0a, 0xa3, 0x9d, 0x13, 0x67,
+0x49, 0xb4, 0x53, 0x44, 0x22, 0x44, 0x04, 0x22, 0x01, 0x4a, 0x01, 0x22,
+0x03, 0x4a, 0x05, 0x40, 0x03, 0x2e, 0x04, 0x1e, 0x03, 0x63, 0x00, 0x09,
+0x30, 0x30, 0x63, 0x30, 0xaa, 0x41, 0x0f, 0x47, 0x7d, 0x00, 0x25, 0x00,
+0x00, 0x0b, 0x11, 0xd4, 0x83, 0x65, 0x53, 0x65, 0x22, 0x5c, 0x52, 0x37,
+0x37, 0x00, 0x03, 0x52, 0x05, 0x29, 0x00, 0x06, 0x27, 0x27, 0x7b, 0x27,
+0x7b, 0x5a, 0x04, 0x12, 0x05, 0x02, 0x04, 0x14, 0x03, 0x0c, 0x03, 0x20,
+0x03, 0x04, 0x03, 0x62, 0x01, 0x01, 0x01, 0x62, 0x03, 0x01, 0x01, 0x38,
+0x03, 0x1f, 0x04, 0x08, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x54, 0x04, 0x06,
+0x01, 0x23, 0x01, 0x23, 0x05, 0x18, 0x01, 0x47, 0x01, 0x47, 0x06, 0x21,
+0x03, 0x10, 0x05, 0x16, 0x06, 0x13, 0x00, 0x03, 0x2a, 0x2a, 0x13, 0x00,
+0x06, 0x2a, 0x0d, 0x0f, 0x00, 0x06, 0x4c, 0x4c, 0x0f, 0x4c, 0x4c, 0x0f,
+0x05, 0x4c, 0x00, 0x08, 0x41, 0x4c, 0xb4, 0x82, 0x82, 0x63, 0xea, 0x0d,
+0x25, 0x00, 0x00, 0x05, 0x6a, 0x6e, 0x53, 0x65, 0x5c, 0x00, 0x03, 0x13,
+0x01, 0x16, 0x01, 0x13, 0x04, 0x16, 0x03, 0x10, 0x06, 0x21, 0x00, 0x0a,
+0x47, 0x47, 0x18, 0x18, 0x23, 0x18, 0x18, 0x23, 0x06, 0x23, 0x03, 0x06,
+0x04, 0x54, 0x01, 0x1d, 0x05, 0x08, 0x03, 0x1f, 0x00, 0x09, 0x38, 0x32,
+0x32, 0xc1, 0x88, 0x88, 0x72, 0xcc, 0x71, 0x00, 0x48, 0x00, 0x00, 0x00,
+0x59, 0x00, 0x00, 0x09, 0x03, 0x00, 0x7d, 0x18, 0x4c, 0x41, 0xf8, 0x44,
+0x44, 0x00, 0x06, 0x22, 0x05, 0x4a, 0x04, 0x40, 0x04, 0x2e, 0x03, 0x1e,
+0x03, 0x63, 0x05, 0x30, 0x00, 0x05, 0xaa, 0x4c, 0x2a, 0x23, 0xd9, 0x00,
+0x23, 0x00, 0x00, 0x0c, 0x11, 0x00, 0x7e, 0x53, 0x53, 0x44, 0x44, 0x4a,
+0x5c, 0x52, 0x37, 0x37, 0x03, 0x52, 0x05, 0x29, 0x00, 0x05, 0x27, 0x27,
+0x7b, 0x7b, 0x27, 0x00, 0x03, 0x5a, 0x03, 0x12, 0x04, 0x02, 0x05, 0x14,
+0x03, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x05, 0x04, 0x01, 0x62, 0x03, 0x01,
+0x03, 0x32, 0x00, 0x03, 0x38, 0x1f, 0x1f, 0x00, 0x05, 0x08, 0x01, 0x1d,
+0x04, 0x54, 0x03, 0x06, 0x03, 0x23, 0x05, 0x18, 0x01, 0x47, 0x01, 0x47,
+0x06, 0x21, 0x01, 0x10, 0x01, 0x10, 0x07, 0x16, 0x05, 0x13, 0x08, 0x2a,
+0x0d, 0x0f, 0x01, 0x4c, 0x01, 0x0f, 0x0b, 0x4c, 0x00, 0x08, 0x41, 0x41,
+0xc1, 0xbb, 0xbb, 0x82, 0xb8, 0x8e, 0x25, 0x00, 0x00, 0x07, 0xb1, 0xee,
+0x93, 0x44, 0xee, 0x1f, 0xbc, 0x00, 0x03, 0x13, 0x06, 0x16, 0x01, 0x10,
+0x07, 0x21, 0x01, 0x18, 0x01, 0x47, 0x05, 0x18, 0x01, 0x23, 0x01, 0x23,
+0x04, 0x06, 0x04, 0x54, 0x01, 0x1d, 0x05, 0x08, 0x00, 0x0b, 0x1f, 0x1f,
+0x38, 0x32, 0x32, 0xf8, 0x88, 0x88, 0x74, 0x74, 0xe7, 0x00, 0x48, 0x00,
+0x00, 0x00, 0x59, 0x00, 0x00, 0x09, 0x11, 0x00, 0xad, 0x5e, 0x16, 0x41,
+0x2a, 0x59, 0x53, 0x00, 0x05, 0x22, 0x01, 0x4a, 0x01, 0x22, 0x04, 0x4a,
+0x04, 0x40, 0x04, 0x2e, 0x03, 0x1e, 0x04, 0x63, 0x00, 0x09, 0x30, 0x30,
+0x63, 0x30, 0x1f, 0x2a, 0x13, 0x06, 0xd9, 0x00, 0x25, 0x00, 0x00, 0x09,
+0x8a, 0xe5, 0xed, 0xee, 0xee, 0x5c, 0x52, 0x37, 0x37, 0x00, 0x05, 0x52,
+0x03, 0x29, 0x04, 0x27, 0x01, 0x7b, 0x03, 0x5a, 0x03, 0x12, 0x05, 0x02,
+0x04, 0x14, 0x03, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x05, 0x04, 0x01, 0x62,
+0x04, 0x01, 0x00, 0x05, 0x32, 0x38, 0x38, 0x1f, 0x1f, 0x00, 0x05, 0x08,
+0x01, 0x1d, 0x01, 0x1d, 0x03, 0x54, 0x03, 0x06, 0x03, 0x23, 0x05, 0x18,
+0x01, 0x47, 0x01, 0x47, 0x06, 0x21, 0x01, 0x10, 0x01, 0x10, 0x06, 0x16,
+0x08, 0x13, 0x03, 0x2a, 0x01, 0x0f, 0x01, 0x2a, 0x05, 0x0f, 0x01, 0x4c,
+0x05, 0x0f, 0x0c, 0x4c, 0x07, 0x41, 0x00, 0x06, 0xfb, 0xb8, 0xb8, 0xb4,
+0xb4, 0x7e, 0x26, 0x00, 0x00, 0x06, 0xf4, 0x93, 0x22, 0x44, 0x12, 0x2a,
+0x05, 0x13, 0x00, 0x04, 0x16, 0x16, 0x13, 0x16, 0x03, 0x10, 0x06, 0x21,
+0x03, 0x47, 0x04, 0x18, 0x03, 0x23, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d,
+0x01, 0x1d, 0x05, 0x08, 0x00, 0x0a, 0x1f, 0x1f, 0x38, 0x32, 0x1f, 0x74,
+0x81, 0x81, 0x74, 0xd0, 0x48, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x06,
+0xfa, 0x06, 0x4c, 0x0f, 0xaa, 0x44, 0x07, 0x22, 0x04, 0x4a, 0x03, 0x40,
+0x05, 0x2e, 0x03, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x05, 0x30, 0x00, 0x06,
+0x3e, 0x1f, 0x13, 0x16, 0xe1, 0xd9, 0x22, 0x00, 0x00, 0x09, 0x03, 0x00,
+0x8e, 0xd4, 0x8c, 0xed, 0xed, 0x3e, 0x52, 0x00, 0x03, 0x37, 0x04, 0x52,
+0x03, 0x29, 0x00, 0x08, 0x27, 0x27, 0x7b, 0x27, 0x27, 0x7b, 0x5a, 0x5a,
+0x03, 0x12, 0x05, 0x02, 0x04, 0x14, 0x03, 0x0c, 0x03, 0x20, 0x00, 0x05,
+0x04, 0x04, 0x62, 0x04, 0x62, 0x00, 0x04, 0x01, 0x00, 0x05, 0x32, 0x32,
+0x38, 0x38, 0x1f, 0x00, 0x05, 0x08, 0x01, 0x1d, 0x01, 0x1d, 0x03, 0x54,
+0x04, 0x06, 0x00, 0x03, 0x23, 0x06, 0x23, 0x00, 0x04, 0x18, 0x01, 0x47,
+0x01, 0x47, 0x07, 0x21, 0x01, 0x10, 0x06, 0x16, 0x05, 0x13, 0x01, 0x2a,
+0x01, 0x13, 0x05, 0x2a, 0x09, 0x0f, 0x00, 0x03, 0x4c, 0x0f, 0x0f, 0x00,
+0x09, 0x4c, 0x0c, 0x41, 0x00, 0x06, 0xc1, 0xb8, 0xaf, 0xb4, 0xf7, 0x03,
+0x25, 0x00, 0x00, 0x07, 0x69, 0x65, 0x44, 0xee, 0xa5, 0xf3, 0xbc, 0x00,
+0x03, 0x13, 0x07, 0x16, 0x01, 0x10, 0x01, 0x10, 0x03, 0x21, 0x00, 0x05,
+0x47, 0x21, 0x21, 0x47, 0x47, 0x00, 0x05, 0x18, 0x01, 0x23, 0x01, 0x23,
+0x04, 0x06, 0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x05, 0x08, 0x00, 0x0a,
+0x1f, 0x1f, 0x38, 0x32, 0xf8, 0x81, 0x91, 0x74, 0x8f, 0x8e, 0x47, 0x00,
+0x00, 0x00, 0x5a, 0x00, 0x00, 0x09, 0x03, 0x00, 0xec, 0x0f, 0x47, 0x2a,
+0x54, 0x63, 0x44, 0x00, 0x05, 0x22, 0x05, 0x4a, 0x01, 0x40, 0x01, 0x40,
+0x05, 0x2e, 0x04, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x05, 0x30, 0x00, 0x06,
+0x3e, 0x01, 0x10, 0x21, 0xe1, 0xd9, 0x22, 0x00, 0x00, 0x08, 0x11, 0x00,
+0xad, 0xf4, 0x4a, 0xa5, 0xa5, 0x5c, 0x03, 0x37, 0x04, 0x52, 0x04, 0x29,
+0x00, 0x08, 0x27, 0x7b, 0x27, 0x27, 0x7b, 0x7b, 0x5a, 0x5a, 0x03, 0x12,
+0x04, 0x02, 0x04, 0x14, 0x00, 0x06, 0x0c, 0x14, 0x0c, 0x0c, 0x20, 0x20,
+0x03, 0x04, 0x00, 0x03, 0x62, 0x04, 0x62, 0x00, 0x04, 0x01, 0x00, 0x05,
+0x32, 0x38, 0x38, 0x1f, 0x1f, 0x00, 0x05, 0x08, 0x01, 0x1d, 0x04, 0x54,
+0x03, 0x06, 0x00, 0x04, 0x23, 0x06, 0x23, 0x58, 0x03, 0x18, 0x00, 0x04,
+0x47, 0x47, 0x21, 0x47, 0x04, 0x21, 0x03, 0x10, 0x05, 0x16, 0x04, 0x13,
+0x00, 0x03, 0x2a, 0x13, 0x13, 0x00, 0x04, 0x2a, 0x07, 0x0f, 0x01, 0x4c,
+0x03, 0x0f, 0x08, 0x4c, 0x10, 0x41, 0x00, 0x06, 0xfb, 0xa8, 0xa8, 0xaf,
+0xa8, 0xe7, 0x25, 0x00, 0x00, 0x08, 0x8e, 0x82, 0x8c, 0xee, 0xee, 0xaa,
+0xbc, 0x2a, 0x04, 0x13, 0x05, 0x16, 0x04, 0x10, 0x05, 0x21, 0x01, 0x47,
+0x01, 0x47, 0x04, 0x18, 0x04, 0x23, 0x01, 0x06, 0x01, 0x06, 0x04, 0x54,
+0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08, 0x03, 0x1f, 0x00, 0x07, 0x32, 0x1f,
+0x91, 0x6c, 0x91, 0x91, 0x7d, 0x00, 0x47, 0x00, 0x00, 0x00, 0x5c, 0x00,
+0x00, 0x07, 0x0d, 0x9d, 0xe1, 0x21, 0x10, 0x27, 0x53, 0x00, 0x05, 0x22,
+0x03, 0x4a, 0x04, 0x40, 0x05, 0x2e, 0x04, 0x1e, 0x00, 0x03, 0x63, 0x30,
+0x63, 0x00, 0x03, 0x30, 0x00, 0x07, 0x63, 0x3e, 0x38, 0x10, 0x47, 0xe1,
+0xd9, 0x00, 0x22, 0x00, 0x00, 0x08, 0x11, 0x00, 0x7c, 0xd4, 0x63, 0x82,
+0x82, 0x5c, 0x03, 0x37, 0x03, 0x52, 0x05, 0x29, 0x04, 0x27, 0x00, 0x03,
+0x7b, 0x7b, 0x5a, 0x00, 0x04, 0x12, 0x04, 0x02, 0x04, 0x14, 0x03, 0x0c,
+0x01, 0x20, 0x01, 0x20, 0x05, 0x04, 0x01, 0x62, 0x01, 0x62, 0x03, 0x01,
+0x00, 0x06, 0x32, 0x32, 0x38, 0x38, 0x1f, 0x1f, 0x04, 0x08, 0x01, 0x1d,
+0x01, 0x1d, 0x03, 0x54, 0x03, 0x06, 0x03, 0x23, 0x00, 0x06, 0x18, 0x58,
+0x18, 0x18, 0x47, 0x47, 0x07, 0x21, 0x01, 0x10, 0x06, 0x16, 0x07, 0x13,
+0x04, 0x2a, 0x09, 0x0f, 0x01, 0x4c, 0x01, 0x0f, 0x06, 0x4c, 0x0e, 0x41,
+0x00, 0x03, 0x49, 0x41, 0x41, 0x00, 0x03, 0x49, 0x00, 0x05, 0x74, 0x72,
+0x72, 0xaf, 0xd0, 0x00, 0x26, 0x00, 0x00, 0x07, 0xdb, 0x93, 0xee, 0xed,
+0x37, 0x2a, 0x2a, 0x00, 0x05, 0x13, 0x05, 0x16, 0x01, 0x10, 0x01, 0x10,
+0x04, 0x21, 0x00, 0x05, 0x47, 0x21, 0x21, 0x47, 0x47, 0x00, 0x05, 0x18,
+0x01, 0x23, 0x04, 0x06, 0x03, 0x54, 0x03, 0x1d, 0x04, 0x08, 0x00, 0x0a,
+0x1f, 0x1f, 0x38, 0x32, 0x74, 0x8f, 0x6c, 0x91, 0xeb, 0x71, 0x46, 0x00,
+0x00, 0x00, 0x5d, 0x00, 0x00, 0x07, 0xd9, 0x18, 0x06, 0x10, 0x38, 0x40,
+0x44, 0x00, 0x03, 0x22, 0x05, 0x4a, 0x03, 0x40, 0x05, 0x2e, 0x03, 0x1e,
+0x00, 0x04, 0x63, 0x63, 0x30, 0x63, 0x04, 0x30, 0x00, 0x06, 0x3e, 0x01,
+0x47, 0x23, 0xe1, 0xd9, 0x22, 0x00, 0x00, 0x07, 0x03, 0x00, 0x71, 0x8a,
+0x63, 0xbb, 0xbb, 0x00, 0x03, 0x37, 0x05, 0x52, 0x04, 0x29, 0x01, 0x27,
+0x01, 0x27, 0x03, 0x7b, 0x01, 0x5a, 0x01, 0x5a, 0x03, 0x12, 0x04, 0x02,
+0x05, 0x14, 0x01, 0x0c, 0x01, 0x14, 0x03, 0x20, 0x05, 0x04, 0x03, 0x01,
+0x03, 0x32, 0x01, 0x38, 0x03, 0x1f, 0x04, 0x08, 0x01, 0x1d, 0x01, 0x1d,
+0x03, 0x54, 0x03, 0x06, 0x03, 0x23, 0x05, 0x18, 0x01, 0x47, 0x06, 0x21,
+0x01, 0x10, 0x01, 0x10, 0x05, 0x16, 0x05, 0x13, 0x06, 0x2a, 0x0a, 0x0f,
+0x07, 0x4c, 0x0b, 0x41, 0x0a, 0x49, 0x00, 0x07, 0x41, 0x80, 0x88, 0x88,
+0x72, 0x8f, 0xad, 0x00, 0x25, 0x00, 0x00, 0x09, 0x9a, 0xed, 0xee, 0xed,
+0xa5, 0xf8, 0x2a, 0x13, 0x2a, 0x00, 0x04, 0x13, 0x00, 0x07, 0x16, 0x16,
+0x13, 0x16, 0x16, 0x10, 0x10, 0x00, 0x07, 0x21, 0x01, 0x47, 0x01, 0x47,
+0x04, 0x18, 0x01, 0x23, 0x01, 0x23, 0x04, 0x06, 0x03, 0x54, 0x01, 0x1d,
+0x01, 0x1d, 0x04, 0x08, 0x03, 0x1f, 0x00, 0x09, 0x32, 0xf8, 0x7a, 0x8f,
+0x77, 0x8f, 0xec, 0x00, 0x0d, 0x00, 0x44, 0x00, 0x00, 0x00, 0x5d, 0x00,
+0x00, 0x07, 0x6b, 0x55, 0xe1, 0x18, 0x47, 0x5c, 0x44, 0x00, 0x04, 0x22,
+0x04, 0x4a, 0x04, 0x40, 0x03, 0x2e, 0x04, 0x1e, 0x01, 0x63, 0x01, 0x63,
+0x06, 0x30, 0x00, 0x06, 0x3e, 0x04, 0x18, 0x06, 0xe1, 0x7d, 0x23, 0x00,
+0x00, 0x09, 0x03, 0x00, 0x8b, 0xa6, 0xb8, 0xbb, 0xb4, 0x37, 0x37, 0x00,
+0x05, 0x52, 0x01, 0x29, 0x01, 0x29, 0x03, 0x27, 0x03, 0x7b, 0x01, 0x5a,
+0x01, 0x5a, 0x04, 0x12, 0x04, 0x02, 0x04, 0x14, 0x03, 0x0c, 0x03, 0x20,
+0x03, 0x04, 0x01, 0x62, 0x01, 0x62, 0x03, 0x01, 0x00, 0x06, 0x32, 0x32,
+0x38, 0x38, 0x1f, 0x1f, 0x04, 0x08, 0x01, 0x1d, 0x01, 0x1d, 0x03, 0x54,
+0x03, 0x06, 0x03, 0x23, 0x04, 0x18, 0x01, 0x47, 0x01, 0x47, 0x06, 0x21,
+0x03, 0x10, 0x04, 0x16, 0x04, 0x13, 0x00, 0x03, 0x2a, 0x2a, 0x13, 0x00,
+0x04, 0x2a, 0x0a, 0x0f, 0x06, 0x4c, 0x0a, 0x41, 0x0e, 0x49, 0x00, 0x06,
+0x67, 0x91, 0x81, 0x80, 0x74, 0x7d, 0x25, 0x00, 0x00, 0x07, 0x71, 0x8a,
+0x8c, 0xa5, 0xa5, 0xb4, 0x0f, 0x00, 0x03, 0x2a, 0x05, 0x13, 0x05, 0x16,
+0x01, 0x10, 0x01, 0x10, 0x03, 0x21, 0x00, 0x09, 0x47, 0x21, 0x21, 0x47,
+0x18, 0x18, 0x58, 0x18, 0x18, 0x00, 0x03, 0x23, 0x03, 0x06, 0x04, 0x54,
+0x01, 0x1d, 0x05, 0x08, 0x00, 0x09, 0x1f, 0x38, 0x38, 0x91, 0xcc, 0xcc,
+0x7a, 0x90, 0x0d, 0x00, 0x45, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x09,
+0xfa, 0xe1, 0x06, 0x21, 0x14, 0x4a, 0x44, 0x22, 0x22, 0x00, 0x04, 0x4a,
+0x04, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x04, 0x30,
+0x03, 0x3e, 0x00, 0x05, 0x0c, 0x23, 0x06, 0xe1, 0x68, 0x00, 0x23, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0xad, 0xa8, 0xb4, 0xb8, 0xb8, 0xb4, 0x52, 0x37,
+0x05, 0x52, 0x01, 0x29, 0x01, 0x29, 0x05, 0x27, 0x03, 0x5a, 0x03, 0x12,
+0x05, 0x02, 0x00, 0x03, 0x14, 0x14, 0x02, 0x00, 0x03, 0x0c, 0x01, 0x20,
+0x01, 0x20, 0x05, 0x04, 0x04, 0x01, 0x00, 0x05, 0x32, 0x32, 0x38, 0x38,
+0x1f, 0x00, 0x05, 0x08, 0x04, 0x1d, 0x05, 0x06, 0x04, 0x23, 0x01, 0x18,
+0x03, 0x47, 0x01, 0x21, 0x04, 0x47, 0x00, 0x03, 0x21, 0x10, 0x10, 0x00,
+0x05, 0x16, 0x07, 0x13, 0x05, 0x2a, 0x09, 0x0f, 0x01, 0x4c, 0x01, 0x0f,
+0x05, 0x4c, 0x0b, 0x41, 0x00, 0x03, 0x49, 0x49, 0x41, 0x00, 0x0a, 0x49,
+0x00, 0x08, 0x91, 0x6c, 0x6c, 0x80, 0xeb, 0xa3, 0x00, 0x0d, 0x23, 0x00,
+0x00, 0x07, 0x7e, 0x4a, 0xa5, 0x82, 0x82, 0xf8, 0x4c, 0x00, 0x04, 0x2a,
+0x06, 0x13, 0x03, 0x16, 0x03, 0x10, 0x00, 0x04, 0x21, 0x21, 0x47, 0x21,
+0x04, 0x47, 0x01, 0x18, 0x04, 0x23, 0x04, 0x06, 0x01, 0x54, 0x03, 0x1d,
+0x04, 0x08, 0x03, 0x38, 0x00, 0x09, 0x04, 0xf8, 0xcc, 0xcc, 0x60, 0x9d,
+0xad, 0x00, 0x03, 0x00, 0x43, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x08,
+0xad, 0x06, 0xe1, 0x06, 0x06, 0x30, 0x44, 0x22, 0x04, 0x4a, 0x05, 0x40,
+0x03, 0x2e, 0x04, 0x1e, 0x04, 0x63, 0x03, 0x30, 0x03, 0x3e, 0x00, 0x06,
+0x02, 0x06, 0x1d, 0xe1, 0xfa, 0x0d, 0x25, 0x00, 0x00, 0x08, 0x69, 0xb4,
+0xb4, 0xaf, 0xa8, 0xaf, 0xb4, 0x7b, 0x03, 0x27, 0x05, 0x7b, 0x05, 0x12,
+0x00, 0x03, 0x14, 0x12, 0x12, 0x00, 0x05, 0x14, 0x0b, 0xaa, 0x00, 0x06,
+0x62, 0x62, 0x01, 0x1f, 0x01, 0x01, 0x05, 0x1f, 0x01, 0x54, 0x01, 0x1f,
+0x08, 0x54, 0x0b, 0xb7, 0x03, 0x16, 0x00, 0x03, 0xf3, 0x16, 0x16, 0x00,
+0x03, 0x13, 0x04, 0xf3, 0x04, 0x2a, 0x06, 0x0f, 0x08, 0xfb, 0x01, 0x4c,
+0x01, 0x4c, 0x04, 0x41, 0x09, 0x49, 0x06, 0x67, 0x0f, 0x78, 0x01, 0x55,
+0x04, 0x8f, 0x00, 0x03, 0xec, 0x00, 0x03, 0x00, 0x23, 0x00, 0x00, 0x07,
+0x6b, 0xd4, 0x4a, 0x82, 0x82, 0xbb, 0xc1, 0x00, 0x0c, 0xf3, 0x08, 0xb7,
+0x01, 0x16, 0x10, 0xb7, 0x00, 0x0e, 0x54, 0x54, 0xb7, 0x54, 0x54, 0xb7,
+0x54, 0x54, 0xf8, 0x77, 0xa7, 0xa7, 0x77, 0x7d, 0x45, 0x00, 0x00, 0x00,
+0x5e, 0x00, 0x00, 0x08, 0x0d, 0xa7, 0xc6, 0x1d, 0x06, 0x29, 0x22, 0x22,
+0x04, 0x4a, 0x05, 0x40, 0x03, 0x2e, 0x04, 0x1e, 0x04, 0x63, 0x01, 0x30,
+0x01, 0x30, 0x04, 0x3e, 0x00, 0x06, 0x7b, 0x1d, 0x1d, 0xc6, 0xeb, 0x71,
+0x25, 0x00, 0x00, 0x04, 0x26, 0xea, 0xb4, 0xaf, 0x11, 0xa8, 0x11, 0x72,
+0x10, 0x74, 0x13, 0x80, 0x12, 0x91, 0x0f, 0x7a, 0x0f, 0x77, 0x0b, 0x60,
+0x05, 0x4e, 0x03, 0x56, 0x00, 0x05, 0x48, 0xa7, 0xa7, 0x77, 0x7d, 0x00,
+0x24, 0x00, 0x00, 0x08, 0x11, 0x00, 0x7e, 0xa5, 0x63, 0x82, 0x82, 0xbb,
+0x05, 0xb4, 0x08, 0xaf, 0x03, 0xc1, 0x00, 0x03, 0xa8, 0xa8, 0xc1, 0x00,
+0x05, 0x72, 0x04, 0x74, 0x05, 0x80, 0x05, 0x91, 0x03, 0x7a, 0x04, 0x77,
+0x00, 0x07, 0x60, 0x56, 0xa7, 0x9d, 0x4e, 0xfa, 0x6b, 0x00, 0x44, 0x00,
+0x00, 0x00, 0x5f, 0x00, 0x00, 0x07, 0xec, 0xe1, 0x38, 0x1d, 0x32, 0x40,
+0x22, 0x00, 0x03, 0x4a, 0x05, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x01, 0x63,
+0x01, 0x63, 0x04, 0x30, 0x04, 0x3e, 0x00, 0x06, 0x29, 0x08, 0x08, 0xc6,
+0x8f, 0x6b, 0x26, 0x00, 0x00, 0x05, 0x4d, 0xd0, 0x72, 0xc1, 0x72, 0x00,
+0x10, 0x88, 0x10, 0x81, 0x01, 0x6c, 0x03, 0x81, 0x15, 0x6c, 0x17, 0x8f,
+0x13, 0xcc, 0x0f, 0xa7, 0x17, 0x9d, 0x01, 0x77, 0x01, 0x7d, 0x24, 0x00,
+0x00, 0x06, 0x0d, 0x00, 0x00, 0x69, 0xbb, 0x1e, 0x05, 0xbb, 0x08, 0xb8,
+0x07, 0xa8, 0x01, 0x72, 0x01, 0x72, 0x05, 0x88, 0x04, 0x81, 0x04, 0x6c,
+0x04, 0x8f, 0x04, 0xcc, 0x03, 0xa7, 0x05, 0x9d, 0x00, 0x03, 0x60, 0xfa,
+0xa3, 0x00, 0x44, 0x00, 0x00, 0x00, 0x5f, 0x00, 0x00, 0x0a, 0x6b, 0x7a,
+0xc6, 0x08, 0x08, 0x5c, 0x22, 0x22, 0x4a, 0x4a, 0x05, 0x40, 0x04, 0x2e,
+0x03, 0x1e, 0x04, 0x63, 0x01, 0x30, 0x01, 0x30, 0x05, 0x3e, 0x00, 0x06,
+0x37, 0x38, 0x38, 0xc6, 0xf8, 0xd2, 0x28, 0x00, 0x00, 0x04, 0xd9, 0xcf,
+0x81, 0xc1, 0x08, 0x72, 0x11, 0x74, 0x03, 0x80, 0x01, 0x74, 0x0f, 0x80,
+0x01, 0x91, 0x01, 0x80, 0x11, 0x91, 0x0d, 0x7a, 0x0d, 0x77, 0x00, 0x03,
+0x64, 0x77, 0x64, 0x00, 0x2b, 0x60, 0x00, 0x05, 0x64, 0xeb, 0xad, 0x00,
+0x03, 0x00, 0x23, 0x00, 0x00, 0x07, 0x03, 0x00, 0x00, 0xb1, 0xd4, 0xbb,
+0x3e, 0x00, 0x03, 0xa6, 0x01, 0x82, 0x01, 0x37, 0x08, 0xb4, 0x06, 0xaf,
+0x05, 0xc1, 0x03, 0x72, 0x04, 0x74, 0x03, 0x80, 0x04, 0x91, 0x03, 0x7a,
+0x01, 0x77, 0x01, 0x77, 0x05, 0x60, 0x00, 0x05, 0x64, 0x48, 0xec, 0x00,
+0x0d, 0x00, 0x43, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x07, 0x68, 0xe0,
+0x32, 0x08, 0x02, 0x22, 0x22, 0x00, 0x03, 0x4a, 0x03, 0x40, 0x04, 0x2e,
+0x04, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x04, 0x30, 0x05, 0x3e, 0x00, 0x06,
+0x5c, 0x04, 0x38, 0xc6, 0x04, 0xad, 0x29, 0x00, 0x00, 0x03, 0x71, 0xec,
+0x7d, 0x00, 0x19, 0xd0, 0x0f, 0x8b, 0x20, 0x90, 0x3e, 0x68, 0x00, 0x03,
+0x90, 0x7d, 0xad, 0x00, 0x2a, 0x00, 0x00, 0x03, 0x6b, 0x7e, 0xf1, 0x00,
+0x09, 0xcf, 0x0d, 0xea, 0x0a, 0xd0, 0x04, 0x8b, 0x05, 0x90, 0x08, 0x68,
+0x01, 0xe7, 0x46, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x09, 0xad, 0xf8,
+0xc6, 0x38, 0x04, 0x30, 0x22, 0x4a, 0x4a, 0x00, 0x04, 0x40, 0x04, 0x2e,
+0x03, 0x1e, 0x03, 0x63, 0x04, 0x30, 0x05, 0x3e, 0x00, 0x06, 0x5c, 0x0c,
+0x32, 0xc6, 0xc6, 0xd9, 0x2d, 0x00, 0x14, 0x4d, 0x08, 0x11, 0x05, 0x4d,
+0x12, 0x11, 0x01, 0x4d, 0x12, 0x11, 0x01, 0x26, 0x03, 0x11, 0x01, 0x4d,
+0x01, 0x11, 0x11, 0x4d, 0x01, 0x11, 0x0a, 0x4d, 0x00, 0x04, 0x11, 0x4d,
+0x4d, 0x11, 0x0f, 0x4d, 0x01, 0x11, 0x06, 0x4d, 0x00, 0x04, 0x11, 0x11,
+0x4d, 0x4d, 0x30, 0x00, 0x08, 0x71, 0x1a, 0x4d, 0x01, 0x11, 0x01, 0x11,
+0x03, 0x4d, 0x01, 0x11, 0x01, 0x11, 0x06, 0x4d, 0x48, 0x00, 0x00, 0x00,
+0x61, 0x00, 0x00, 0x07, 0xeb, 0xe0, 0x01, 0x32, 0x29, 0x22, 0x4a, 0x00,
+0x05, 0x40, 0x04, 0x2e, 0x03, 0x1e, 0x03, 0x63, 0x04, 0x30, 0x05, 0x3e,
+0x00, 0x06, 0x59, 0x5a, 0x04, 0xc6, 0xe0, 0xd0, 0x2a, 0x00, 0x01, 0x03,
+0x01, 0x03, 0x88, 0x00, 0x01, 0x0d, 0x2b, 0x00, 0x01, 0x03, 0x01, 0x03,
+0x31, 0x00, 0x01, 0x0d, 0x46, 0x00, 0x00, 0x00, 0x5f, 0x00, 0x00, 0x09,
+0x11, 0x00, 0xec, 0x04, 0xc6, 0x04, 0x02, 0x1e, 0x22, 0x00, 0x04, 0x40,
+0x04, 0x2e, 0x04, 0x1e, 0x03, 0x63, 0x04, 0x30, 0x05, 0x3e, 0x00, 0x06,
+0x59, 0x29, 0x04, 0x0c, 0xe0, 0x6c, 0x2d, 0x00, 0x3d, 0x0d, 0x00, 0x05,
+0x00, 0x00, 0x0d, 0x00, 0x0d, 0x00, 0x42, 0x00, 0x01, 0x0d, 0x01, 0x0d,
+0x2f, 0x00, 0x01, 0x0d, 0x0b, 0x03, 0x1e, 0x0d, 0x05, 0x00, 0x01, 0x0d,
+0x48, 0x00, 0x00, 0x00, 0x5f, 0x00, 0x00, 0x09, 0x0d, 0x00, 0x4d, 0xcc,
+0xe0, 0x0c, 0x04, 0x37, 0x22, 0x00, 0x04, 0x40, 0x04, 0x2e, 0x03, 0x1e,
+0x04, 0x63, 0x03, 0x30, 0x05, 0x3e, 0x00, 0x08, 0x59, 0x3e, 0x37, 0x0c,
+0x0c, 0xe0, 0xaa, 0x8e, 0xff, 0x00, 0x5a, 0x00, 0x00, 0x00, 0x60, 0x00,
+0x00, 0x09, 0x03, 0x00, 0x7d, 0xe0, 0x02, 0x0c, 0x5a, 0x2e, 0x4a, 0x00,
+0x03, 0x40, 0x04, 0x2e, 0x04, 0x1e, 0x03, 0x63, 0x01, 0x30, 0x01, 0x30,
+0x05, 0x3e, 0x00, 0x09, 0x59, 0x59, 0x3e, 0x5c, 0x02, 0x02, 0xe0, 0x02,
+0xd9, 0x00, 0xff, 0x00, 0x5a, 0x00, 0x00, 0x00, 0x62, 0x00, 0x00, 0x07,
+0x8e, 0x74, 0xdf, 0x02, 0x02, 0x3e, 0x4a, 0x00, 0x03, 0x40, 0x03, 0x2e,
+0x04, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x05, 0x30, 0x04, 0x3e, 0x03, 0x59,
+0x00, 0x06, 0x5c, 0x29, 0x02, 0x5a, 0xdf, 0xeb, 0xff, 0x00, 0x5a, 0x00,
+0x00, 0x00, 0x63, 0x00, 0x00, 0x05, 0xea, 0xdf, 0x5a, 0x02, 0x52, 0x00,
+0x03, 0x40, 0x04, 0x2e, 0x05, 0x1e, 0x01, 0x63, 0x05, 0x30, 0x04, 0x3e,
+0x04, 0x59, 0x00, 0x06, 0x52, 0x02, 0x5a, 0xdf, 0x74, 0xa3, 0xff, 0x00,
+0x59, 0x00, 0x00, 0x00, 0x63, 0x00, 0x00, 0x08, 0xe7, 0x02, 0xdf, 0x02,
+0x5a, 0x30, 0x4a, 0x40, 0x04, 0x2e, 0x05, 0x1e, 0x01, 0x63, 0x01, 0x63,
+0x04, 0x30, 0x04, 0x3e, 0x04, 0x59, 0x00, 0x06, 0x37, 0x5a, 0x5a, 0xca,
+0x14, 0xd9, 0xff, 0x00, 0x59, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x07,
+0x8f, 0xdf, 0x5a, 0x02, 0x5c, 0x40, 0x40, 0x00, 0x04, 0x2e, 0x04, 0x1e,
+0x03, 0x63, 0x03, 0x30, 0x04, 0x3e, 0x05, 0x59, 0x00, 0x06, 0x5c, 0x29,
+0x5a, 0x27, 0xdf, 0xcc, 0xff, 0x00, 0x59, 0x00, 0x00, 0x00, 0x64, 0x00,
+0x00, 0x07, 0xd9, 0xca, 0xca, 0x5a, 0x29, 0x1e, 0x4a, 0x00, 0x04, 0x2e,
+0x03, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x05, 0x30, 0x05, 0x3e, 0x03, 0x59,
+0x00, 0x0a, 0x5c, 0x59, 0x37, 0x27, 0x29, 0xca, 0xaf, 0x75, 0x00, 0x03,
+0xff, 0x00, 0x56, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x0a, 0x6b, 0xc1,
+0xca, 0x29, 0x27, 0x3e, 0x40, 0x40, 0x2e, 0x2e, 0x04, 0x1e, 0x03, 0x63,
+0x01, 0x30, 0x01, 0x30, 0x07, 0x3e, 0x01, 0x59, 0x01, 0x59, 0x04, 0x5c,
+0x00, 0x07, 0x52, 0x29, 0x27, 0xb9, 0xd0, 0x00, 0x03, 0x00, 0xff, 0x00,
+0x56, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x09, 0x8b, 0xf0, 0xca, 0x29,
+0x37, 0x2e, 0x40, 0x2e, 0x2e, 0x00, 0x04, 0x1e, 0x01, 0x63, 0x01, 0x63,
+0x04, 0x30, 0x05, 0x3e, 0x04, 0x59, 0x03, 0x5c, 0x00, 0x08, 0x52, 0x52,
+0x29, 0xdf, 0x72, 0x8e, 0x00, 0x26, 0xff, 0x00, 0x55, 0x00, 0x00, 0x00,
+0x65, 0x00, 0x00, 0x09, 0x75, 0x7b, 0xc0, 0x29, 0x52, 0x63, 0x40, 0x2e,
+0x2e, 0x00, 0x04, 0x1e, 0x03, 0x63, 0x03, 0x30, 0x05, 0x3e, 0x03, 0x59,
+0x04, 0x5c, 0x00, 0x08, 0x37, 0xca, 0xca, 0x52, 0xf0, 0x69, 0x00, 0x03,
+0xff, 0x00, 0x55, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x08, 0x4d, 0xcf,
+0xf0, 0x52, 0x52, 0x59, 0x40, 0x2e, 0x05, 0x1e, 0x01, 0x63, 0x01, 0x63,
+0x04, 0x30, 0x05, 0x3e, 0x03, 0x59, 0x05, 0x5c, 0x00, 0x06, 0x37, 0xc0,
+0x52, 0xf0, 0xa8, 0x8e, 0xff, 0x00, 0x56, 0x00, 0x00, 0x00, 0x64, 0x00,
+0x00, 0x0a, 0x4d, 0x00, 0xb1, 0xc0, 0xc0, 0xca, 0xc0, 0x1e, 0x2e, 0x2e,
+0x03, 0x1e, 0x03, 0x63, 0x04, 0x30, 0x04, 0x3e, 0x04, 0x59, 0x06, 0x5c,
+0x03, 0xc0, 0x01, 0xf0, 0x01, 0xf1, 0xff, 0x00, 0x56, 0x00, 0x00, 0x00,
+0x64, 0x00, 0x00, 0x0a, 0x03, 0x00, 0xa3, 0x81, 0xf0, 0x37, 0xc0, 0x30,
+0x2e, 0x2e, 0x04, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x03, 0x30, 0x05, 0x3e,
+0x04, 0x59, 0x04, 0x5c, 0x01, 0x37, 0x01, 0x5c, 0x03, 0xc0, 0x00, 0x03,
+0xf0, 0x37, 0x75, 0x00, 0xff, 0x00, 0x55, 0x00, 0x00, 0x00, 0x65, 0x00,
+0x00, 0x09, 0x11, 0x00, 0x69, 0xf0, 0xc0, 0xc0, 0xb9, 0x1e, 0x2e, 0x00,
+0x04, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x03, 0x30, 0x04, 0x3e, 0x04, 0x59,
+0x05, 0x5c, 0x00, 0x08, 0x37, 0x37, 0x5c, 0xc0, 0xc0, 0xb9, 0xc3, 0xf7,
+0xff, 0x00, 0x55, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x09, 0x03, 0x00,
+0x7c, 0xaf, 0xf0, 0xc0, 0xc0, 0x30, 0x2e, 0x00, 0x03, 0x1e, 0x01, 0x63,
+0x01, 0x63, 0x04, 0x30, 0x05, 0x3e, 0x04, 0x59, 0x05, 0x5c, 0x00, 0x08,
+0x37, 0x37, 0x59, 0xb9, 0xb9, 0xf0, 0xf0, 0x7e, 0xff, 0x00, 0x54, 0x00,
+0x00, 0x00, 0x68, 0x00, 0x00, 0x05, 0xcf, 0xc3, 0xb9, 0xb9, 0x30, 0x00,
+0x03, 0x1e, 0x03, 0x63, 0x03, 0x30, 0x06, 0x3e, 0x03, 0x59, 0x05, 0x5c,
+0x03, 0x37, 0x01, 0x5c, 0x03, 0xb9, 0x00, 0x05, 0xc3, 0xb4, 0xad, 0x00,
+0x03, 0x00, 0xff, 0x00, 0x51, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x05,
+0xb2, 0x37, 0xc3, 0xb9, 0xb9, 0x00, 0x04, 0x1e, 0x01, 0x63, 0x01, 0x63,
+0x04, 0x30, 0x05, 0x3e, 0x03, 0x59, 0x04, 0x5c, 0x00, 0x06, 0x37, 0x5c,
+0x37, 0x5c, 0x37, 0x59, 0x03, 0xb9, 0x00, 0x05, 0x0a, 0xd4, 0x71, 0x00,
+0x26, 0x00, 0xff, 0x00, 0x50, 0x00, 0x00, 0x00, 0x69, 0x00, 0x00, 0x04,
+0xd4, 0x0a, 0xb9, 0xb9, 0x04, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x04, 0x30,
+0x04, 0x3e, 0x03, 0x59, 0x06, 0x5c, 0x05, 0x37, 0x00, 0x09, 0xb9, 0x76,
+0xb9, 0x76, 0x17, 0xcf, 0x00, 0x00, 0x03, 0x00, 0xff, 0x00, 0x4f, 0x00,
+0x00, 0x00, 0x69, 0x00, 0x00, 0x05, 0x7e, 0xc3, 0xc3, 0x76, 0x76, 0x00,
+0x03, 0x1e, 0x01, 0x63, 0x01, 0x63, 0x04, 0x30, 0x05, 0x3e, 0x01, 0x59,
+0x01, 0x59, 0x05, 0x5c, 0x07, 0x37, 0x03, 0x76, 0x00, 0x06, 0xc3, 0xc3,
+0x69, 0x00, 0x00, 0x0d, 0xff, 0x00, 0x4e, 0x00, 0x00, 0x00, 0x69, 0x00,
+0x00, 0x06, 0x6b, 0xbb, 0x0a, 0x76, 0x76, 0x1e, 0x03, 0x63, 0x03, 0x30,
+0x06, 0x3e, 0x03, 0x59, 0x04, 0x5c, 0x01, 0x37, 0x01, 0x5c, 0x05, 0x37,
+0x01, 0x52, 0x01, 0x59, 0x03, 0x76, 0x00, 0x03, 0xc3, 0x76, 0x96, 0x00,
+0xff, 0x00, 0x50, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x01, 0xea, 0x01, 0x17,
+0x03, 0x76, 0x03, 0x63, 0x04, 0x30, 0x04, 0x3e, 0x03, 0x59, 0x07, 0x5c,
+0x06, 0x37, 0x01, 0x52, 0x01, 0x3e, 0x03, 0x76, 0x00, 0x06, 0x17, 0x63,
+0xb1, 0x00, 0x00, 0x0d, 0xff, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x6a, 0x00,
+0x00, 0x08, 0x75, 0x76, 0xc3, 0x76, 0x76, 0x1e, 0x63, 0x63, 0x04, 0x30,
+0x03, 0x3e, 0x01, 0x59, 0x01, 0x3e, 0x03, 0x59, 0x04, 0x5c, 0x01, 0x37,
+0x01, 0x5c, 0x06, 0x37, 0x00, 0x0c, 0x52, 0x52, 0x30, 0x8c, 0x76, 0x76,
+0x7f, 0x82, 0xb1, 0x00, 0x00, 0x03, 0xff, 0x00, 0x4b, 0x00, 0x00, 0x00,
+0x6a, 0x00, 0x00, 0x03, 0x26, 0xf7, 0x7f, 0x00, 0x03, 0x76, 0x03, 0x63,
+0x03, 0x30, 0x05, 0x3e, 0x03, 0x59, 0x04, 0x5c, 0x07, 0x37, 0x00, 0x0e,
+0x52, 0x52, 0x29, 0x52, 0x76, 0x8c, 0x76, 0x8c, 0x7f, 0x1e, 0x69, 0x00,
+0x00, 0x26, 0xff, 0x00, 0x4a, 0x00, 0x00, 0x00, 0x6b, 0x00, 0x01, 0x99,
+0x03, 0x8c, 0x00, 0x04, 0x76, 0x1e, 0x63, 0x63, 0x03, 0x30, 0x04, 0x3e,
+0x03, 0x59, 0x05, 0x5c, 0x07, 0x37, 0x03, 0x52, 0x00, 0x03, 0x29, 0x37,
+0x76, 0x00, 0x03, 0x8c, 0x00, 0x03, 0x7f, 0x8c, 0xf1, 0x00, 0xff, 0x00,
+0x4c, 0x00, 0x00, 0x00, 0x6b, 0x00, 0x00, 0x06, 0x6b, 0xf4, 0x7f, 0x8c,
+0x8c, 0x40, 0x05, 0x30, 0x04, 0x3e, 0x04, 0x59, 0x05, 0x5c, 0x07, 0x37,
+0x03, 0x52, 0x00, 0x03, 0x27, 0x52, 0x76, 0x00, 0x03, 0x8c, 0x00, 0x04,
+0x7f, 0x7f, 0x8a, 0x6b, 0xff, 0x00, 0x4a, 0x00, 0x00, 0x00, 0x6a, 0x00,
+0x00, 0x07, 0x11, 0x00, 0xf1, 0xe5, 0x8c, 0x8c, 0x4a, 0x00, 0x05, 0x30,
+0x03, 0x3e, 0x05, 0x59, 0x05, 0x5c, 0x07, 0x37, 0x03, 0x52, 0x00, 0x04,
+0x29, 0x27, 0x52, 0x76, 0x03, 0x8c, 0x00, 0x04, 0x93, 0xe5, 0xb8, 0xb2,
+0xff, 0x00, 0x49, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x08, 0x26, 0x00,
+0x75, 0x82, 0x7f, 0x8c, 0x8c, 0x40, 0x03, 0x30, 0x05, 0x3e, 0x03, 0x59,
+0x06, 0x5c, 0x00, 0x03, 0x37, 0x37, 0x5c, 0x00, 0x03, 0x37, 0x05, 0x52,
+0x00, 0x0c, 0x29, 0x27, 0x29, 0x76, 0x93, 0x93, 0x8c, 0x8c, 0xe5, 0xed,
+0xf1, 0x71, 0xff, 0x00, 0x47, 0x00, 0x00, 0x00, 0x6d, 0x00, 0x01, 0xcf,
+0x01, 0xe5, 0x03, 0x8c, 0x03, 0x30, 0x05, 0x3e, 0x03, 0x59, 0x04, 0x5c,
+0x01, 0x37, 0x01, 0x5c, 0x05, 0x37, 0x05, 0x52, 0x03, 0x29, 0x00, 0x10,
+0x7b, 0x27, 0x30, 0x93, 0x93, 0x8c, 0x93, 0xe5, 0xe5, 0xb8, 0x99, 0x26,
+0x00, 0x00, 0x4d, 0x03, 0xff, 0x00, 0x41, 0x00, 0x00, 0x00, 0x6b, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0xb1, 0xee, 0x93, 0x93, 0x8c, 0x1e, 0x3e, 0x30,
+0x04, 0x3e, 0x04, 0x59, 0x04, 0x5c, 0x00, 0x03, 0x37, 0x5c, 0x5c, 0x00,
+0x05, 0x37, 0x04, 0x52, 0x04, 0x29, 0x00, 0x04, 0x7b, 0x7b, 0x59, 0x8c,
+0x04, 0x93, 0x00, 0x04, 0xe5, 0x93, 0xd4, 0xb2, 0x03, 0x00, 0x01, 0x26,
+0x01, 0x03, 0xff, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x6e, 0x00, 0x00, 0x07,
+0xf4, 0xe5, 0x93, 0x93, 0x4a, 0x3e, 0x30, 0x00, 0x05, 0x3e, 0x03, 0x59,
+0x04, 0x5c, 0x01, 0x37, 0x01, 0x5c, 0x06, 0x37, 0x04, 0x52, 0x04, 0x29,
+0x00, 0x05, 0x27, 0x7b, 0x12, 0x52, 0x76, 0x00, 0x04, 0x93, 0x00, 0x06,
+0xe5, 0x15, 0x53, 0x8a, 0xb1, 0x0d, 0xff, 0x00, 0x41, 0x00, 0x00, 0x00,
+0x6e, 0x00, 0x00, 0x06, 0x69, 0x93, 0xe5, 0x93, 0x8c, 0x63, 0x06, 0x3e,
+0x03, 0x59, 0x06, 0x5c, 0x05, 0x37, 0x04, 0x52, 0x01, 0x29, 0x01, 0x52,
+0x03, 0x29, 0x00, 0x08, 0x27, 0x27, 0x7b, 0x12, 0x12, 0x59, 0x8c, 0x6e,
+0x03, 0x93, 0x00, 0x06, 0xe5, 0x15, 0x53, 0xd4, 0x69, 0x8e, 0xff, 0x00,
+0x3f, 0x00, 0x00, 0x00, 0x6e, 0x00, 0x00, 0x06, 0x6b, 0x82, 0x15, 0x93,
+0x93, 0x76, 0x04, 0x3e, 0x00, 0x04, 0x59, 0x3e, 0x59, 0x59, 0x05, 0x5c,
+0x00, 0x03, 0x37, 0x5c, 0x5c, 0x00, 0x04, 0x37, 0x04, 0x52, 0x04, 0x29,
+0x04, 0x27, 0x00, 0x11, 0x7b, 0x12, 0x02, 0x52, 0x76, 0x93, 0x6e, 0x6e,
+0x93, 0x93, 0xe5, 0x66, 0x6e, 0xbb, 0x8a, 0x99, 0x71, 0x00, 0xff, 0x00,
+0x3c, 0x00, 0x00, 0x00, 0x6f, 0x00, 0x00, 0x06, 0xcf, 0x83, 0xe5, 0x93,
+0x8c, 0x30, 0x04, 0x3e, 0x03, 0x59, 0x05, 0x5c, 0x01, 0x37, 0x01, 0x5c,
+0x05, 0x37, 0x05, 0x52, 0x03, 0x29, 0x04, 0x27, 0x00, 0x15, 0x7b, 0x7b,
+0x5a, 0x12, 0x02, 0x52, 0x76, 0x93, 0x6e, 0x6e, 0x73, 0x93, 0x6e, 0x83,
+0x83, 0x53, 0x82, 0xd4, 0xc5, 0x75, 0x71, 0x00, 0xff, 0x00, 0x38, 0x00,
+0x00, 0x00, 0x6f, 0x00, 0x00, 0x06, 0xad, 0x53, 0xe5, 0x6e, 0x6e, 0x40,
+0x04, 0x3e, 0x04, 0x59, 0x06, 0x5c, 0x05, 0x37, 0x05, 0x52, 0x04, 0x29,
+0x03, 0x27, 0x00, 0x0a, 0x7b, 0x7b, 0x12, 0x5a, 0x12, 0x14, 0x02, 0x52,
+0x76, 0x93, 0x05, 0x6e, 0x00, 0x10, 0x83, 0x5d, 0x83, 0x57, 0x73, 0xed,
+0xd4, 0xdb, 0x84, 0xb1, 0x75, 0x7c, 0x8e, 0x6b, 0xa3, 0x71, 0xf7, 0x4d,
+0x03, 0x00, 0x01, 0x0d, 0x32, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x05,
+0x6a, 0x66, 0x6e, 0x6e, 0x93, 0x00, 0x04, 0x3e, 0x04, 0x59, 0x06, 0x5c,
+0x05, 0x37, 0x04, 0x52, 0x04, 0x29, 0x03, 0x27, 0x03, 0x7b, 0x01, 0x5a,
+0x03, 0x12, 0x00, 0x08, 0x02, 0x14, 0x14, 0x29, 0x76, 0x8c, 0x6e, 0x57,
+0x04, 0x6e, 0x01, 0x57, 0x06, 0x83, 0x00, 0x06, 0x73, 0xed, 0xbb, 0xf4,
+0xd4, 0x6a, 0x11, 0x8a, 0x01, 0x6a, 0x01, 0x8a, 0x99, 0x6a, 0x00, 0x04,
+0x8a, 0x8a, 0x6a, 0x6a, 0x04, 0x8a, 0x01, 0x6a, 0x42, 0x8a, 0x01, 0xdb,
+0x01, 0x9a, 0x34, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x09, 0xb2, 0x6e,
+0x57, 0x6e, 0x6e, 0x40, 0x59, 0x3e, 0x3e, 0x00, 0x03, 0x59, 0x07, 0x5c,
+0x05, 0x37, 0x04, 0x52, 0x03, 0x29, 0x05, 0x27, 0x00, 0x03, 0x7b, 0x7b,
+0x5a, 0x00, 0x04, 0x12, 0x00, 0x09, 0x02, 0x02, 0x14, 0x20, 0x12, 0xc0,
+0x76, 0x93, 0x6e, 0x00, 0x03, 0x57, 0x01, 0x6e, 0x01, 0x6e, 0x04, 0x57,
+0x06, 0x83, 0x9a, 0x6d, 0x30, 0x83, 0x01, 0x8d, 0x0c, 0x83, 0x20, 0x57,
+0x00, 0x03, 0x83, 0xed, 0x9a, 0x00, 0x33, 0x00, 0x00, 0x00, 0x70, 0x00,
+0x00, 0x09, 0x0d, 0x6a, 0x3c, 0x6e, 0x6e, 0x93, 0x30, 0x59, 0x3e, 0x00,
+0x03, 0x59, 0x04, 0x5c, 0x00, 0x03, 0x37, 0x37, 0x5c, 0x00, 0x06, 0x37,
+0x03, 0x52, 0x04, 0x29, 0x04, 0x27, 0x00, 0x03, 0x7b, 0x5a, 0x5a, 0x00,
+0x03, 0x12, 0x05, 0x02, 0x00, 0x08, 0x0c, 0x04, 0x20, 0x27, 0xc0, 0x76,
+0x8c, 0x6e, 0x36, 0x57, 0x00, 0x03, 0x8d, 0x57, 0x57, 0x00, 0x03, 0x8d,
+0x00, 0x06, 0x57, 0x57, 0x8d, 0x57, 0x8d, 0x57, 0x04, 0x8d, 0x08, 0x57,
+0x01, 0x8d, 0x01, 0x8d, 0x2b, 0x57, 0x2f, 0x6e, 0x2a, 0x73, 0x04, 0x65,
+0x00, 0x05, 0x73, 0x73, 0x65, 0x65, 0x73, 0x00, 0x03, 0x65, 0x01, 0x73,
+0x1e, 0x65, 0x05, 0x53, 0x00, 0x03, 0x83, 0x6a, 0x26, 0x00, 0x32, 0x00,
+0x00, 0x00, 0x71, 0x00, 0x00, 0x08, 0xb2, 0x65, 0x83, 0x6e, 0x57, 0x8c,
+0x59, 0x3e, 0x05, 0x59, 0x00, 0x05, 0x5c, 0x5c, 0x37, 0x37, 0x5c, 0x00,
+0x06, 0x37, 0x03, 0x52, 0x04, 0x29, 0x03, 0x27, 0x00, 0x06, 0x7b, 0x7b,
+0x5a, 0x7b, 0x12, 0x12, 0x07, 0x02, 0x00, 0x0c, 0x14, 0x14, 0x0c, 0x01,
+0x62, 0x02, 0x27, 0x37, 0xb9, 0x8c, 0x93, 0x6e, 0x04, 0x57, 0x4b, 0x8d,
+0x00, 0x04, 0x57, 0x57, 0x8d, 0x8d, 0x26, 0x57, 0x00, 0x04, 0x6e, 0x6e,
+0x57, 0x57, 0x24, 0x6e, 0x01, 0x73, 0x01, 0x6e, 0x2c, 0x73, 0x1d, 0x65,
+0x11, 0x53, 0x00, 0x05, 0x44, 0x44, 0x93, 0xee, 0x75, 0x00, 0x32, 0x00,
+0x00, 0x00, 0x72, 0x00, 0x00, 0x08, 0xdb, 0x6d, 0x6e, 0x57, 0x6e, 0x1e,
+0x59, 0x3e, 0x03, 0x59, 0x03, 0x5c, 0x08, 0x37, 0x03, 0x52, 0x05, 0x29,
+0x03, 0x27, 0x03, 0x7b, 0x01, 0x5a, 0x03, 0x12, 0x05, 0x02, 0x04, 0x14,
+0x00, 0x10, 0x0c, 0x20, 0x62, 0x01, 0x1f, 0x01, 0x04, 0x0c, 0x14, 0x12,
+0x52, 0xc0, 0xb9, 0xb9, 0x76, 0x76, 0x0c, 0x8c, 0x1a, 0x76, 0x01, 0x2e,
+0x03, 0x76, 0x01, 0x2e, 0x01, 0x2e, 0x06, 0x1e, 0x01, 0x63, 0x04, 0x1e,
+0x0e, 0x63, 0x01, 0x30, 0x01, 0x3e, 0x1c, 0xa5, 0x01, 0xa6, 0x25, 0x82,
+0x00, 0x03, 0xa6, 0x82, 0x82, 0x00, 0x29, 0xa6, 0x00, 0x06, 0x59, 0xa6,
+0x59, 0x59, 0xa6, 0xa6, 0x19, 0x59, 0x00, 0x05, 0x3e, 0x59, 0x3e, 0x3e,
+0x59, 0x00, 0x17, 0x3e, 0x00, 0x0b, 0x30, 0x30, 0x3e, 0x30, 0x3e, 0x63,
+0xee, 0xee, 0x44, 0x93, 0xdb, 0x00, 0x32, 0x00, 0x00, 0x00, 0x70, 0x00,
+0x00, 0x09, 0x11, 0x00, 0x8e, 0x87, 0x6d, 0x57, 0x8d, 0x73, 0x3e, 0x00,
+0x03, 0x59, 0x04, 0x5c, 0x01, 0x37, 0x01, 0x5c, 0x07, 0x37, 0x03, 0x52,
+0x04, 0x29, 0x05, 0x27, 0x01, 0x5a, 0x01, 0x5a, 0x03, 0x12, 0x04, 0x02,
+0x04, 0x14, 0x03, 0x0c, 0x00, 0x06, 0x20, 0x20, 0x04, 0x62, 0x01, 0x38,
+0x07, 0x1f, 0x04, 0x08, 0x03, 0x1d, 0x00, 0x09, 0x54, 0x54, 0x06, 0x06,
+0x23, 0x06, 0x23, 0x23, 0x18, 0x00, 0x03, 0x47, 0x01, 0x21, 0x01, 0x21,
+0x06, 0x10, 0x01, 0x16, 0x01, 0x16, 0x03, 0x13, 0x04, 0x2a, 0x04, 0x0f,
+0x05, 0x4c, 0x04, 0x41, 0x03, 0x49, 0x03, 0x67, 0x03, 0x78, 0x08, 0x3d,
+0x01, 0xde, 0x03, 0x55, 0x01, 0x50, 0x01, 0x55, 0x06, 0x50, 0x03, 0x5e,
+0x06, 0x46, 0x07, 0x64, 0x07, 0x4e, 0x04, 0x56, 0x04, 0x48, 0x00, 0x03,
+0x5f, 0x48, 0x5f, 0x00, 0x05, 0x48, 0x01, 0x5f, 0x04, 0x48, 0x01, 0x5f,
+0x04, 0x48, 0x05, 0x56, 0x07, 0x4e, 0x05, 0x64, 0x07, 0x46, 0x03, 0x5e,
+0x05, 0x50, 0x07, 0x55, 0x06, 0x3d, 0x04, 0x78, 0x03, 0x67, 0x04, 0x49,
+0x04, 0x41, 0x04, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x05, 0x13, 0x01, 0x16,
+0x04, 0x10, 0x04, 0x21, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23, 0x01, 0x23,
+0x03, 0x06, 0x01, 0x54, 0x03, 0x1d, 0x03, 0x08, 0x01, 0x1f, 0x04, 0x38,
+0x00, 0x04, 0x32, 0x32, 0x01, 0x01, 0x03, 0x62, 0x03, 0x04, 0x00, 0x08,
+0x20, 0x0c, 0x59, 0xee, 0xee, 0x93, 0xbb, 0x6b, 0x31, 0x00, 0x00, 0x00,
+0x73, 0x00, 0x00, 0x06, 0x96, 0x8d, 0x6d, 0x57, 0x8d, 0x8c, 0x03, 0x59,
+0x04, 0x5c, 0x01, 0x37, 0x01, 0x5c, 0x07, 0x37, 0x03, 0x52, 0x04, 0x29,
+0x00, 0x07, 0x27, 0x7b, 0x7b, 0x27, 0x7b, 0x5a, 0x5a, 0x00, 0x03, 0x12,
+0x04, 0x02, 0x00, 0x04, 0x14, 0x02, 0x14, 0x14, 0x03, 0x0c, 0x01, 0x20,
+0x01, 0x20, 0x04, 0x04, 0x00, 0x04, 0x62, 0x01, 0x32, 0x01, 0x03, 0x1f,
+0x00, 0x06, 0x08, 0x54, 0x1d, 0x1d, 0x54, 0x1d, 0x03, 0x06, 0x03, 0x23,
+0x00, 0x05, 0x18, 0x47, 0x18, 0x10, 0x10, 0x00, 0x03, 0x21, 0x06, 0x10,
+0x04, 0x13, 0x01, 0xbc, 0x05, 0x2a, 0x07, 0x4c, 0x05, 0x41, 0x01, 0x49,
+0x05, 0x67, 0x01, 0x78, 0x01, 0x78, 0x05, 0x3d, 0x09, 0xde, 0x04, 0x50,
+0x05, 0x5e, 0x04, 0x46, 0x08, 0x64, 0x05, 0x4e, 0x03, 0x56, 0x01, 0x48,
+0x01, 0x56, 0x03, 0x48, 0x18, 0x5f, 0x04, 0x48, 0x03, 0x56, 0x06, 0x4e,
+0x09, 0x64, 0x03, 0x46, 0x04, 0x5e, 0x05, 0x50, 0x07, 0xde, 0x01, 0x3d,
+0x01, 0xde, 0x05, 0x3d, 0x01, 0x78, 0x06, 0x67, 0x01, 0x49, 0x04, 0x41,
+0x07, 0x4c, 0x01, 0x0f, 0x03, 0x2a, 0x01, 0x13, 0x01, 0x2a, 0x04, 0x13,
+0x06, 0x10, 0x05, 0x21, 0x00, 0x03, 0x47, 0x18, 0x18, 0x00, 0x03, 0x23,
+0x00, 0x07, 0x06, 0x06, 0x54, 0x1d, 0x54, 0x1d, 0x1d, 0x00, 0x03, 0x08,
+0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32, 0x38, 0x00, 0x04, 0x01, 0x01, 0x62,
+0x03, 0x04, 0x00, 0x08, 0x20, 0x04, 0x7b, 0xed, 0xed, 0x22, 0x4a, 0x96,
+0x31, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x06, 0x6a, 0x2d, 0x57, 0x6e,
+0x6e, 0x40, 0x07, 0x5c, 0x07, 0x37, 0x03, 0x52, 0x04, 0x29, 0x01, 0x27,
+0x01, 0x27, 0x04, 0x7b, 0x01, 0x5a, 0x01, 0x5a, 0x03, 0x12, 0x04, 0x02,
+0x04, 0x14, 0x03, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x01, 0x62,
+0x04, 0x01, 0x03, 0x38, 0x01, 0x1f, 0x04, 0x08, 0x01, 0x1d, 0x04, 0x54,
+0x00, 0x04, 0x06, 0x06, 0x23, 0x23, 0x05, 0x18, 0x00, 0x06, 0x21, 0x21,
+0x47, 0x21, 0x21, 0x10, 0x05, 0x16, 0x03, 0x13, 0x03, 0x2a, 0x05, 0x0f,
+0x01, 0x4c, 0x01, 0x0f, 0x03, 0x4c, 0x04, 0x41, 0x05, 0x49, 0x01, 0x67,
+0x05, 0x78, 0x06, 0x3d, 0x06, 0x55, 0x00, 0x04, 0x50, 0x50, 0x5e, 0x50,
+0x05, 0x5e, 0x05, 0x46, 0x06, 0x64, 0x01, 0x60, 0x06, 0x4e, 0x06, 0x56,
+0x09, 0x48, 0x01, 0x5f, 0x08, 0x48, 0x06, 0x56, 0x05, 0x4e, 0x01, 0x64,
+0x01, 0x60, 0x06, 0x64, 0x06, 0x46, 0x04, 0x5e, 0x05, 0x50, 0x05, 0x55,
+0x07, 0x3d, 0x03, 0x78, 0x03, 0x67, 0x04, 0x49, 0x04, 0x41, 0x04, 0x4c,
+0x05, 0x0f, 0x05, 0x2a, 0x01, 0x13, 0x01, 0x13, 0x05, 0x16, 0x01, 0x10,
+0x04, 0x21, 0x01, 0x47, 0x01, 0x47, 0x03, 0x18, 0x01, 0x23, 0x01, 0x23,
+0x03, 0x06, 0x03, 0x54, 0x00, 0x04, 0x1d, 0x1d, 0x08, 0x08, 0x03, 0x1f,
+0x00, 0x03, 0x38, 0x32, 0x32, 0x00, 0x04, 0x01, 0x01, 0x62, 0x04, 0x04,
+0x00, 0x0a, 0x20, 0x20, 0x0c, 0x0c, 0x14, 0xa6, 0xed, 0xed, 0x8c, 0xd4,
+0x31, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x08, 0x8e, 0x82, 0x5d, 0x6e,
+0x6e, 0x73, 0x30, 0x37, 0x05, 0x5c, 0x01, 0x37, 0x01, 0x5c, 0x05, 0x37,
+0x04, 0x52, 0x03, 0x29, 0x03, 0x27, 0x00, 0x07, 0x7b, 0x7b, 0x5a, 0x7b,
+0x7b, 0x12, 0x12, 0x00, 0x05, 0x02, 0x03, 0x14, 0x03, 0x0c, 0x03, 0x20,
+0x03, 0x04, 0x01, 0x62, 0x01, 0x62, 0x04, 0x01, 0x03, 0x38, 0x01, 0x1f,
+0x04, 0x08, 0x00, 0x04, 0x1d, 0x1d, 0x54, 0x54, 0x03, 0x06, 0x01, 0x23,
+0x01, 0x23, 0x05, 0x18, 0x05, 0x21, 0x01, 0x10, 0x01, 0x10, 0x03, 0x16,
+0x03, 0x13, 0x04, 0x2a, 0x05, 0x0f, 0x00, 0x04, 0x4c, 0x0f, 0x4c, 0x4c,
+0x03, 0x41, 0x06, 0x49, 0x03, 0x67, 0x04, 0x78, 0x04, 0x3d, 0x07, 0x55,
+0x04, 0x50, 0x05, 0x5e, 0x07, 0x46, 0x05, 0x64, 0x01, 0x60, 0x06, 0x4e,
+0x04, 0x56, 0x15, 0x48, 0x05, 0x56, 0x05, 0x4e, 0x01, 0x64, 0x01, 0x60,
+0x05, 0x64, 0x06, 0x46, 0x05, 0x5e, 0x05, 0x50, 0x06, 0x55, 0x05, 0x3d,
+0x04, 0x78, 0x03, 0x67, 0x04, 0x49, 0x04, 0x41, 0x01, 0x4c, 0x01, 0x4c,
+0x07, 0x0f, 0x05, 0x2a, 0x03, 0x13, 0x03, 0x16, 0x01, 0x10, 0x01, 0x10,
+0x04, 0x21, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23, 0x01, 0x23, 0x03, 0x06,
+0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x03, 0x08, 0x00, 0x06, 0x1f, 0x1f,
+0x38, 0x38, 0x32, 0x32, 0x03, 0x01, 0x01, 0x62, 0x04, 0x04, 0x00, 0x0b,
+0x20, 0x20, 0x0c, 0x0c, 0x20, 0x29, 0xa5, 0xa5, 0x40, 0xbb, 0x9a, 0x00,
+0x30, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x07, 0xb1, 0x73, 0x83, 0x65,
+0x73, 0x53, 0x59, 0x00, 0x04, 0x5c, 0x00, 0x03, 0x37, 0x37, 0x5c, 0x00,
+0x04, 0x37, 0x04, 0x52, 0x05, 0x29, 0x04, 0x27, 0x01, 0x5a, 0x01, 0x5a,
+0x04, 0x12, 0x04, 0x02, 0x05, 0x14, 0x01, 0x0c, 0x03, 0x20, 0x04, 0x04,
+0x01, 0x62, 0x04, 0x01, 0x00, 0x04, 0x32, 0x38, 0x38, 0x1f, 0x04, 0x08,
+0x00, 0x04, 0x1d, 0x1d, 0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23,
+0x05, 0x18, 0x05, 0x21, 0x05, 0x16, 0x04, 0x13, 0x04, 0x2a, 0x06, 0x0f,
+0x01, 0x4c, 0x01, 0x4c, 0x04, 0x41, 0x04, 0x49, 0x04, 0x67, 0x04, 0x78,
+0x06, 0x3d, 0x05, 0x55, 0x04, 0x50, 0x05, 0x5e, 0x07, 0x46, 0x06, 0x64,
+0x05, 0x4e, 0x05, 0x56, 0x08, 0x48, 0x06, 0x5f, 0x08, 0x48, 0x05, 0x56,
+0x05, 0x4e, 0x06, 0x64, 0x06, 0x46, 0x05, 0x5e, 0x05, 0x50, 0x06, 0x55,
+0x05, 0x3d, 0x04, 0x78, 0x04, 0x67, 0x04, 0x49, 0x04, 0x41, 0x01, 0x4c,
+0x01, 0x4c, 0x06, 0x0f, 0x04, 0x2a, 0x05, 0x13, 0x00, 0x04, 0x16, 0x16,
+0x10, 0x10, 0x04, 0x21, 0x03, 0x18, 0x01, 0x23, 0x01, 0x18, 0x03, 0x23,
+0x01, 0x06, 0x01, 0x06, 0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x03, 0x08,
+0x03, 0x1f, 0x00, 0x0d, 0x38, 0x32, 0x32, 0x01, 0x01, 0x62, 0x62, 0x04,
+0x04, 0x20, 0x04, 0x20, 0x20, 0x00, 0x03, 0x0c, 0x00, 0x06, 0x02, 0x82,
+0x82, 0xa6, 0x1e, 0xea, 0x30, 0x00, 0x00, 0x00, 0x76, 0x00, 0x00, 0x07,
+0xc5, 0x6e, 0x73, 0x65, 0x73, 0x22, 0x59, 0x00, 0x03, 0x5c, 0x01, 0x37,
+0x01, 0x5c, 0x06, 0x37, 0x03, 0x52, 0x04, 0x29, 0x05, 0x27, 0x00, 0x03,
+0x7b, 0x7b, 0x5a, 0x00, 0x03, 0x12, 0x04, 0x02, 0x04, 0x14, 0x01, 0x0c,
+0x01, 0x0c, 0x03, 0x20, 0x04, 0x04, 0x00, 0x09, 0x62, 0x01, 0x62, 0x01,
+0x32, 0x32, 0x38, 0x1f, 0x1f, 0x00, 0x04, 0x08, 0x00, 0x04, 0x1d, 0x1d,
+0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23, 0x04, 0x18, 0x00, 0x08,
+0x47, 0x21, 0x21, 0x47, 0x21, 0x21, 0x10, 0x10, 0x03, 0x16, 0x04, 0x13,
+0x03, 0x2a, 0x06, 0x0f, 0x03, 0x4c, 0x05, 0x41, 0x03, 0x49, 0x04, 0x67,
+0x05, 0x78, 0x04, 0x3d, 0x05, 0x55, 0x06, 0x50, 0x04, 0x5e, 0x07, 0x46,
+0x04, 0x64, 0x01, 0x60, 0x01, 0x64, 0x05, 0x4e, 0x04, 0x56, 0x07, 0x48,
+0x01, 0x5f, 0x01, 0x48, 0x08, 0x5f, 0x06, 0x48, 0x04, 0x56, 0x06, 0x4e,
+0x07, 0x64, 0x05, 0x46, 0x05, 0x5e, 0x04, 0x50, 0x01, 0x55, 0x01, 0x50,
+0x05, 0x55, 0x05, 0x3d, 0x05, 0x78, 0x01, 0x67, 0x01, 0x67, 0x05, 0x49,
+0x03, 0x41, 0x04, 0x4c, 0x05, 0x0f, 0x04, 0x2a, 0x05, 0x13, 0x03, 0x16,
+0x01, 0x10, 0x04, 0x21, 0x01, 0x47, 0x04, 0x18, 0x03, 0x23, 0x03, 0x06,
+0x00, 0x04, 0x54, 0x54, 0x1d, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f,
+0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x04, 0x04, 0x00, 0x0e,
+0x20, 0x20, 0x0c, 0x0c, 0x14, 0x0c, 0xb4, 0x82, 0x82, 0x63, 0xf4, 0x7c,
+0x00, 0x03, 0x2d, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x09, 0x0d, 0x00,
+0x00, 0xdb, 0x6e, 0x65, 0x53, 0x65, 0x4a, 0x00, 0x05, 0x5c, 0x06, 0x37,
+0x04, 0x52, 0x03, 0x29, 0x04, 0x27, 0x00, 0x06, 0x7b, 0x7b, 0x5a, 0x5a,
+0x12, 0x12, 0x05, 0x02, 0x04, 0x14, 0x01, 0x0c, 0x01, 0x0c, 0x03, 0x20,
+0x04, 0x04, 0x01, 0x62, 0x04, 0x01, 0x00, 0x04, 0x38, 0x38, 0x1f, 0x1f,
+0x04, 0x08, 0x01, 0x1d, 0x03, 0x54, 0x03, 0x06, 0x00, 0x0e, 0x23, 0x23,
+0x18, 0x18, 0x23, 0x18, 0x47, 0x21, 0x47, 0x47, 0x21, 0x21, 0x10, 0x10,
+0x04, 0x16, 0x04, 0x13, 0x01, 0x2a, 0x01, 0x2a, 0x06, 0x0f, 0x03, 0x4c,
+0x04, 0x41, 0x04, 0x49, 0x04, 0x67, 0x05, 0x78, 0x04, 0x3d, 0x06, 0x55,
+0x05, 0x50, 0x04, 0x5e, 0x06, 0x46, 0x05, 0x64, 0x01, 0x60, 0x01, 0x64,
+0x04, 0x4e, 0x05, 0x56, 0x07, 0x48, 0x0a, 0x5f, 0x07, 0x48, 0x04, 0x56,
+0x05, 0x4e, 0x01, 0x60, 0x01, 0x60, 0x05, 0x64, 0x06, 0x46, 0x05, 0x5e,
+0x03, 0x50, 0x01, 0x55, 0x01, 0x50, 0x05, 0x55, 0x06, 0x3d, 0x04, 0x78,
+0x01, 0x67, 0x01, 0x67, 0x05, 0x49, 0x03, 0x41, 0x04, 0x4c, 0x06, 0x0f,
+0x03, 0x2a, 0x04, 0x13, 0x03, 0x16, 0x01, 0x10, 0x01, 0x10, 0x04, 0x21,
+0x01, 0x47, 0x01, 0x47, 0x04, 0x18, 0x00, 0x04, 0x23, 0x23, 0x06, 0x06,
+0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08, 0x00, 0x04, 0x1f, 0x38,
+0x38, 0x32, 0x04, 0x01, 0x03, 0x62, 0x00, 0x09, 0x04, 0x04, 0x20, 0x20,
+0x0c, 0x0c, 0x14, 0x0c, 0x12, 0x00, 0x03, 0xbb, 0x00, 0x04, 0xa5, 0x69,
+0x00, 0x11, 0x2d, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x05, 0x03, 0x00,
+0x4d, 0x6a, 0x6e, 0x00, 0x03, 0x44, 0x00, 0x03, 0x40, 0x5c, 0x5c, 0x00,
+0x08, 0x37, 0x05, 0x52, 0x01, 0x29, 0x01, 0x29, 0x03, 0x27, 0x04, 0x7b,
+0x00, 0x03, 0x5a, 0x12, 0x12, 0x00, 0x05, 0x02, 0x04, 0x14, 0x01, 0x0c,
+0x01, 0x0c, 0x03, 0x20, 0x04, 0x04, 0x01, 0x62, 0x04, 0x01, 0x00, 0x04,
+0x32, 0x38, 0x1f, 0x1f, 0x04, 0x08, 0x01, 0x1d, 0x03, 0x54, 0x03, 0x06,
+0x00, 0x03, 0x23, 0x23, 0x58, 0x00, 0x04, 0x18, 0x05, 0x21, 0x05, 0x16,
+0x05, 0x13, 0x01, 0x2a, 0x01, 0x2a, 0x06, 0x0f, 0x03, 0x4c, 0x04, 0x41,
+0x04, 0x49, 0x04, 0x67, 0x05, 0x78, 0x04, 0x3d, 0x06, 0x55, 0x03, 0x50,
+0x05, 0x5e, 0x06, 0x46, 0x08, 0x64, 0x05, 0x4e, 0x04, 0x56, 0x05, 0x48,
+0x0d, 0x5f, 0x06, 0x48, 0x04, 0x56, 0x05, 0x4e, 0x01, 0x60, 0x01, 0x60,
+0x06, 0x64, 0x04, 0x46, 0x06, 0x5e, 0x05, 0x50, 0x05, 0x55, 0x04, 0x3d,
+0x01, 0x78, 0x01, 0x3d, 0x04, 0x78, 0x01, 0x67, 0x01, 0x67, 0x04, 0x49,
+0x04, 0x41, 0x04, 0x4c, 0x05, 0x0f, 0x04, 0x2a, 0x04, 0x13, 0x04, 0x16,
+0x05, 0x21, 0x01, 0x47, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23, 0x01, 0x23,
+0x03, 0x06, 0x00, 0x04, 0x54, 0x54, 0x1d, 0x1d, 0x04, 0x08, 0x00, 0x04,
+0x1f, 0x38, 0x38, 0x32, 0x03, 0x01, 0x03, 0x62, 0x03, 0x04, 0x00, 0x04,
+0x20, 0x20, 0x0c, 0x0c, 0x03, 0x14, 0x00, 0x06, 0xb4, 0xbb, 0xbb, 0xa6,
+0xf7, 0x6b, 0x2e, 0x00, 0x00, 0x00, 0x76, 0x00, 0x00, 0x0a, 0x03, 0x00,
+0x6b, 0xd4, 0x93, 0x44, 0xee, 0x22, 0x2e, 0x5c, 0x08, 0x37, 0x04, 0x52,
+0x03, 0x29, 0x04, 0x27, 0x00, 0x03, 0x7b, 0x7b, 0x5a, 0x00, 0x04, 0x12,
+0x04, 0x02, 0x04, 0x14, 0x03, 0x0c, 0x03, 0x20, 0x03, 0x04, 0x00, 0x09,
+0x62, 0x62, 0x01, 0x01, 0x32, 0x32, 0x38, 0x38, 0x1f, 0x00, 0x04, 0x08,
+0x01, 0x1d, 0x01, 0x1d, 0x03, 0x54, 0x00, 0x0f, 0x06, 0x06, 0x23, 0x23,
+0x18, 0x23, 0x18, 0x47, 0x47, 0x21, 0x21, 0x47, 0x21, 0x21, 0x10, 0x00,
+0x05, 0x16, 0x04, 0x13, 0x01, 0x2a, 0x01, 0x2a, 0x07, 0x0f, 0x01, 0x4c,
+0x01, 0x4c, 0x03, 0x41, 0x05, 0x49, 0x03, 0x67, 0x04, 0x78, 0x06, 0x3d,
+0x06, 0x55, 0x05, 0x50, 0x03, 0x5e, 0x06, 0x46, 0x08, 0x64, 0x05, 0x4e,
+0x04, 0x56, 0x05, 0x48, 0x06, 0x5f, 0x01, 0xa7, 0x07, 0x5f, 0x05, 0x48,
+0x04, 0x56, 0x05, 0x4e, 0x01, 0x60, 0x01, 0x60, 0x05, 0x64, 0x05, 0x46,
+0x05, 0x5e, 0x06, 0x50, 0x05, 0x55, 0x06, 0x3d, 0x04, 0x78, 0x01, 0x67,
+0x01, 0x67, 0x05, 0x49, 0x03, 0x41, 0x05, 0x4c, 0x04, 0x0f, 0x04, 0x2a,
+0x04, 0x13, 0x04, 0x16, 0x01, 0x10, 0x04, 0x21, 0x01, 0x47, 0x01, 0x47,
+0x04, 0x18, 0x01, 0x23, 0x01, 0x23, 0x03, 0x06, 0x01, 0x54, 0x01, 0x54,
+0x03, 0x1d, 0x03, 0x08, 0x00, 0x07, 0x1f, 0x1f, 0x38, 0x32, 0x32, 0x01,
+0x01, 0x00, 0x04, 0x62, 0x00, 0x04, 0x04, 0x04, 0x20, 0x20, 0x03, 0x0c,
+0x03, 0x14, 0x00, 0x05, 0xb4, 0xb8, 0xb4, 0xb4, 0xb1, 0x00, 0x2e, 0x00,
+0x00, 0x00, 0x77, 0x00, 0x00, 0x0a, 0x03, 0x00, 0x6b, 0xd4, 0x93, 0x22,
+0xee, 0xee, 0x1e, 0x59, 0x07, 0x37, 0x03, 0x52, 0x00, 0x04, 0x29, 0x52,
+0x29, 0x29, 0x03, 0x27, 0x03, 0x7b, 0x01, 0x5a, 0x01, 0x5a, 0x03, 0x12,
+0x04, 0x02, 0x04, 0x14, 0x01, 0x0c, 0x01, 0x0c, 0x03, 0x20, 0x03, 0x04,
+0x01, 0x62, 0x01, 0x62, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32, 0x38, 0x1f,
+0x1f, 0x00, 0x03, 0x08, 0x01, 0x1d, 0x01, 0x1d, 0x03, 0x54, 0x00, 0x05,
+0x06, 0x06, 0x23, 0x06, 0x23, 0x00, 0x03, 0x18, 0x00, 0x09, 0x47, 0x47,
+0x21, 0x21, 0x47, 0x21, 0x21, 0x10, 0x10, 0x00, 0x04, 0x16, 0x01, 0x13,
+0x01, 0x13, 0x03, 0x2a, 0x07, 0x0f, 0x03, 0x4c, 0x04, 0x41, 0x04, 0x49,
+0x03, 0x67, 0x04, 0x78, 0x06, 0x3d, 0x05, 0x55, 0x06, 0x50, 0x04, 0x5e,
+0x06, 0x46, 0x05, 0x64, 0x01, 0x60, 0x01, 0x64, 0x04, 0x4e, 0x05, 0x56,
+0x06, 0x48, 0x05, 0x5f, 0x01, 0xa7, 0x01, 0xa7, 0x05, 0x5f, 0x06, 0x48,
+0x04, 0x56, 0x05, 0x4e, 0x00, 0x04, 0x60, 0x60, 0x64, 0x60, 0x03, 0x64,
+0x06, 0x46, 0x04, 0x5e, 0x04, 0x50, 0x07, 0x55, 0x05, 0x3d, 0x05, 0x78,
+0x03, 0x67, 0x04, 0x49, 0x04, 0x41, 0x03, 0x4c, 0x05, 0x0f, 0x04, 0x2a,
+0x03, 0x13, 0x01, 0x16, 0x01, 0x13, 0x03, 0x16, 0x01, 0x10, 0x03, 0x21,
+0x00, 0x03, 0x47, 0x21, 0x47, 0x00, 0x03, 0x18, 0x03, 0x23, 0x01, 0x06,
+0x01, 0x06, 0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08, 0x00, 0x05,
+0x1f, 0x1f, 0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x00, 0x03, 0x62, 0x04,
+0x62, 0x00, 0x03, 0x04, 0x01, 0x20, 0x03, 0x0c, 0x03, 0x14, 0x00, 0x05,
+0xaf, 0xb8, 0xb8, 0x82, 0xea, 0x00, 0x2e, 0x00, 0x00, 0x00, 0x78, 0x00,
+0x00, 0x0a, 0x03, 0x00, 0x6b, 0xd4, 0x93, 0x4a, 0xed, 0xee, 0xed, 0x5c,
+0x06, 0x37, 0x03, 0x52, 0x04, 0x29, 0x03, 0x27, 0x01, 0x7b, 0x01, 0x7b,
+0x03, 0x5a, 0x03, 0x12, 0x04, 0x02, 0x05, 0x14, 0x01, 0x0c, 0x04, 0x20,
+0x00, 0x04, 0x04, 0x04, 0x62, 0x62, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
+0x38, 0x1f, 0x1f, 0x00, 0x04, 0x08, 0x01, 0x1d, 0x03, 0x54, 0x03, 0x06,
+0x03, 0x23, 0x00, 0x0a, 0x18, 0x58, 0x18, 0x47, 0x47, 0x21, 0x47, 0x21,
+0x21, 0x10, 0x05, 0x16, 0x01, 0x13, 0x01, 0x13, 0x04, 0x2a, 0x03, 0x0f,
+0x01, 0x4c, 0x03, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x04, 0x41, 0x04, 0x49,
+0x03, 0x67, 0x04, 0x78, 0x06, 0x3d, 0x05, 0x55, 0x04, 0x50, 0x06, 0x5e,
+0x06, 0x46, 0x05, 0x64, 0x01, 0x60, 0x05, 0x4e, 0x05, 0x56, 0x05, 0x48,
+0x05, 0x5f, 0x03, 0xa7, 0x05, 0x5f, 0x06, 0x48, 0x04, 0x56, 0x05, 0x4e,
+0x00, 0x03, 0x64, 0x4e, 0x60, 0x00, 0x05, 0x64, 0x05, 0x46, 0x04, 0x5e,
+0x06, 0x50, 0x05, 0x55, 0x00, 0x05, 0x3d, 0x3d, 0x78, 0x3d, 0x3d, 0x00,
+0x05, 0x78, 0x03, 0x67, 0x04, 0x49, 0x00, 0x04, 0x41, 0x49, 0x41, 0x41,
+0x03, 0x4c, 0x01, 0x0f, 0x01, 0x4c, 0x03, 0x0f, 0x04, 0x2a, 0x05, 0x13,
+0x00, 0x0d, 0x16, 0x16, 0x10, 0x10, 0x21, 0x21, 0x47, 0x47, 0x21, 0x47,
+0x47, 0x18, 0x18, 0x00, 0x03, 0x23, 0x03, 0x06, 0x00, 0x0d, 0x54, 0x54,
+0x1d, 0x1d, 0x08, 0x08, 0x1f, 0x08, 0x1f, 0x1f, 0x38, 0x32, 0x32, 0x00,
+0x03, 0x01, 0x03, 0x62, 0x00, 0x04, 0x04, 0x04, 0x20, 0x20, 0x03, 0x0c,
+0x03, 0x14, 0x00, 0x06, 0xaa, 0xb8, 0xaf, 0xb4, 0xa8, 0xad, 0x2d, 0x00,
+0x00, 0x00, 0x7b, 0x00, 0x00, 0x08, 0x6b, 0x8a, 0x4a, 0xee, 0xa5, 0xed,
+0xa5, 0xa6, 0x06, 0x37, 0x03, 0x52, 0x03, 0x29, 0x04, 0x27, 0x00, 0x04,
+0x7b, 0x7b, 0x5a, 0x5a, 0x03, 0x12, 0x04, 0x02, 0x05, 0x14, 0x00, 0x04,
+0x0c, 0x0c, 0x20, 0x20, 0x04, 0x04, 0x01, 0x62, 0x03, 0x01, 0x00, 0x05,
+0x32, 0x32, 0x38, 0x38, 0x1f, 0x00, 0x04, 0x08, 0x01, 0x1d, 0x03, 0x54,
+0x03, 0x06, 0x00, 0x10, 0x23, 0x23, 0x18, 0x23, 0x18, 0x18, 0x47, 0x21,
+0x21, 0x47, 0x21, 0x21, 0x10, 0x10, 0x16, 0x16, 0x05, 0x13, 0x03, 0x2a,
+0x05, 0x0f, 0x04, 0x4c, 0x04, 0x41, 0x03, 0x49, 0x04, 0x67, 0x05, 0x78,
+0x05, 0x3d, 0x06, 0x55, 0x04, 0x50, 0x04, 0x5e, 0x07, 0x46, 0x03, 0x64,
+0x01, 0x60, 0x01, 0x64, 0x06, 0x4e, 0x05, 0x56, 0x05, 0x48, 0x06, 0x5f,
+0x01, 0xa7, 0x01, 0xa7, 0x05, 0x5f, 0x06, 0x48, 0x04, 0x56, 0x06, 0x4e,
+0x01, 0x64, 0x01, 0x60, 0x03, 0x64, 0x07, 0x46, 0x04, 0x5e, 0x06, 0x50,
+0x05, 0x55, 0x05, 0x3d, 0x05, 0x78, 0x03, 0x67, 0x04, 0x49, 0x04, 0x41,
+0x01, 0x4c, 0x01, 0x4c, 0x06, 0x0f, 0x05, 0x2a, 0x04, 0x13, 0x03, 0x16,
+0x01, 0x10, 0x05, 0x21, 0x01, 0x47, 0x03, 0x18, 0x01, 0x23, 0x01, 0x23,
+0x04, 0x06, 0x01, 0x54, 0x01, 0x54, 0x03, 0x1d, 0x03, 0x08, 0x00, 0x05,
+0x1f, 0x1f, 0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x01, 0x62,
+0x03, 0x04, 0x01, 0x20, 0x01, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x05,
+0xaf, 0xa8, 0xaf, 0xb4, 0x69, 0x00, 0x2d, 0x00, 0x00, 0x00, 0x7c, 0x00,
+0x00, 0x04, 0x4d, 0xf1, 0xed, 0x1e, 0x03, 0xa5, 0x01, 0xa6, 0x04, 0x37,
+0x03, 0x52, 0x05, 0x29, 0x00, 0x06, 0x7b, 0x27, 0x27, 0x7b, 0x7b, 0x5a,
+0x04, 0x12, 0x04, 0x02, 0x04, 0x14, 0x01, 0x0c, 0x01, 0x0c, 0x03, 0x20,
+0x04, 0x04, 0x00, 0x09, 0x62, 0x62, 0x01, 0x01, 0x32, 0x32, 0x38, 0x1f,
+0x1f, 0x00, 0x03, 0x08, 0x03, 0x1d, 0x01, 0x54, 0x01, 0x54, 0x03, 0x06,
+0x01, 0x23, 0x01, 0x23, 0x04, 0x18, 0x00, 0x0a, 0x47, 0x21, 0x21, 0x47,
+0x21, 0x21, 0x10, 0x10, 0x16, 0x16, 0x05, 0x13, 0x04, 0x2a, 0x05, 0x0f,
+0x03, 0x4c, 0x04, 0x41, 0x05, 0x49, 0x01, 0x67, 0x01, 0x67, 0x04, 0x78,
+0x06, 0x3d, 0x05, 0x55, 0x06, 0x50, 0x04, 0x5e, 0x06, 0x46, 0x04, 0x64,
+0x01, 0x60, 0x01, 0x64, 0x06, 0x4e, 0x04, 0x56, 0x06, 0x48, 0x0b, 0x5f,
+0x06, 0x48, 0x05, 0x56, 0x06, 0x4e, 0x01, 0x60, 0x01, 0x60, 0x04, 0x64,
+0x05, 0x46, 0x05, 0x5e, 0x05, 0x50, 0x06, 0x55, 0x05, 0x3d, 0x04, 0x78,
+0x03, 0x67, 0x04, 0x49, 0x05, 0x41, 0x03, 0x4c, 0x06, 0x0f, 0x03, 0x2a,
+0x04, 0x13, 0x00, 0x05, 0x16, 0x13, 0x16, 0x10, 0x10, 0x00, 0x05, 0x21,
+0x01, 0x47, 0x03, 0x18, 0x00, 0x05, 0x23, 0x06, 0x23, 0x06, 0x06, 0x00,
+0x04, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x03, 0x08, 0x00, 0x05, 0x1f, 0x38,
+0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x04, 0x04, 0x01, 0x20,
+0x01, 0x20, 0x03, 0x0c, 0x00, 0x0a, 0x14, 0x14, 0x02, 0x14, 0xaf, 0xa8,
+0xa8, 0xaf, 0xf7, 0x71, 0x2c, 0x00, 0x00, 0x00, 0x7b, 0x00, 0x00, 0x07,
+0x03, 0x00, 0x00, 0x96, 0xbb, 0x76, 0xa6, 0x00, 0x03, 0x82, 0x01, 0xa6,
+0x01, 0x37, 0x05, 0x52, 0x04, 0x29, 0x03, 0x27, 0x00, 0x06, 0x7b, 0x7b,
+0x5a, 0x5a, 0x12, 0x12, 0x05, 0x02, 0x04, 0x14, 0x01, 0x0c, 0x01, 0x0c,
+0x03, 0x20, 0x04, 0x04, 0x01, 0x62, 0x04, 0x01, 0x00, 0x04, 0x32, 0x38,
+0x1f, 0x1f, 0x04, 0x08, 0x01, 0x1d, 0x03, 0x54, 0x03, 0x06, 0x01, 0x23,
+0x01, 0x23, 0x04, 0x18, 0x00, 0x0a, 0x47, 0x21, 0x21, 0x47, 0x21, 0x21,
+0x10, 0x10, 0x16, 0x16, 0x05, 0x13, 0x04, 0x2a, 0x04, 0x0f, 0x04, 0x4c,
+0x04, 0x41, 0x04, 0x49, 0x03, 0x67, 0x04, 0x78, 0x06, 0x3d, 0x05, 0x55,
+0x06, 0x50, 0x04, 0x5e, 0x06, 0x46, 0x05, 0x64, 0x01, 0x60, 0x01, 0x64,
+0x05, 0x4e, 0x05, 0x56, 0x05, 0x48, 0x0b, 0x5f, 0x07, 0x48, 0x04, 0x56,
+0x05, 0x4e, 0x07, 0x64, 0x06, 0x46, 0x05, 0x5e, 0x05, 0x50, 0x05, 0x55,
+0x06, 0x3d, 0x03, 0x78, 0x04, 0x67, 0x04, 0x49, 0x04, 0x41, 0x03, 0x4c,
+0x06, 0x0f, 0x03, 0x2a, 0x04, 0x13, 0x00, 0x05, 0x16, 0x16, 0x13, 0x16,
+0x10, 0x00, 0x05, 0x21, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23, 0x04, 0x06,
+0x00, 0x04, 0x54, 0x54, 0x1d, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f,
+0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x04, 0x04, 0x00, 0x04,
+0x20, 0x20, 0x0c, 0x0c, 0x04, 0x14, 0x00, 0x07, 0x02, 0xaa, 0x72, 0x72,
+0xc1, 0xa8, 0xb2, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x07,
+0x03, 0x00, 0x00, 0xb2, 0xf4, 0x76, 0xa5, 0x00, 0x04, 0x82, 0x01, 0x37,
+0x04, 0x52, 0x04, 0x29, 0x03, 0x27, 0x00, 0x03, 0x7b, 0x7b, 0x5a, 0x00,
+0x03, 0x12, 0x05, 0x02, 0x04, 0x14, 0x03, 0x0c, 0x03, 0x20, 0x03, 0x04,
+0x01, 0x62, 0x03, 0x01, 0x00, 0x05, 0x32, 0x38, 0x38, 0x1f, 0x1f, 0x00,
+0x04, 0x08, 0x01, 0x1d, 0x04, 0x54, 0x00, 0x04, 0x06, 0x06, 0x23, 0x23,
+0x04, 0x18, 0x01, 0x47, 0x05, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16,
+0x06, 0x13, 0x03, 0x2a, 0x05, 0x0f, 0x03, 0x4c, 0x04, 0x41, 0x04, 0x49,
+0x05, 0x67, 0x01, 0x78, 0x01, 0x78, 0x06, 0x3d, 0x05, 0x55, 0x06, 0x50,
+0x04, 0x5e, 0x05, 0x46, 0x06, 0x64, 0x01, 0x60, 0x06, 0x4e, 0x04, 0x56,
+0x06, 0x48, 0x0b, 0x5f, 0x06, 0x48, 0x06, 0x56, 0x05, 0x4e, 0x07, 0x64,
+0x05, 0x46, 0x06, 0x5e, 0x04, 0x50, 0x06, 0x55, 0x01, 0x3d, 0x01, 0x78,
+0x03, 0x3d, 0x03, 0x78, 0x04, 0x67, 0x04, 0x49, 0x04, 0x41, 0x03, 0x4c,
+0x05, 0x0f, 0x04, 0x2a, 0x04, 0x13, 0x04, 0x16, 0x01, 0x10, 0x04, 0x21,
+0x01, 0x47, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23, 0x04, 0x06, 0x03, 0x54,
+0x01, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32, 0x32, 0x00,
+0x03, 0x01, 0x01, 0x62, 0x04, 0x04, 0x00, 0x04, 0x20, 0x20, 0x0c, 0x0c,
+0x04, 0x14, 0x00, 0x07, 0x02, 0x14, 0xc1, 0x88, 0x72, 0xc1, 0xea, 0x00,
+0x2c, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x08, 0x03, 0x00, 0x00, 0x8e,
+0xcf, 0x82, 0xa5, 0x82, 0x03, 0xbb, 0x01, 0x82, 0x01, 0x37, 0x03, 0x52,
+0x03, 0x29, 0x04, 0x27, 0x00, 0x05, 0x7b, 0x5a, 0x5a, 0x12, 0x12, 0x00,
+0x05, 0x02, 0x04, 0x14, 0x03, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x04, 0x04,
+0x01, 0x62, 0x04, 0x01, 0x03, 0x38, 0x01, 0x1f, 0x04, 0x08, 0x01, 0x1d,
+0x01, 0x1d, 0x03, 0x54, 0x03, 0x06, 0x01, 0x23, 0x03, 0x18, 0x01, 0x47,
+0x01, 0x18, 0x05, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16, 0x06, 0x13,
+0x01, 0x2a, 0x01, 0x2a, 0x07, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x05, 0x41,
+0x04, 0x49, 0x03, 0x67, 0x04, 0x78, 0x05, 0x3d, 0x05, 0x55, 0x05, 0x50,
+0x05, 0x5e, 0x05, 0x46, 0x06, 0x64, 0x01, 0x60, 0x01, 0x60, 0x05, 0x4e,
+0x05, 0x56, 0x07, 0x48, 0x05, 0x5f, 0x00, 0x03, 0x48, 0x5f, 0x5f, 0x00,
+0x07, 0x48, 0x04, 0x56, 0x06, 0x4e, 0x01, 0x64, 0x01, 0x60, 0x04, 0x64,
+0x07, 0x46, 0x04, 0x5e, 0x01, 0x50, 0x01, 0x5e, 0x04, 0x50, 0x05, 0x55,
+0x05, 0x3d, 0x03, 0x78, 0x04, 0x67, 0x05, 0x49, 0x03, 0x41, 0x04, 0x4c,
+0x01, 0x0f, 0x01, 0x4c, 0x03, 0x0f, 0x04, 0x2a, 0x05, 0x13, 0x00, 0x04,
+0x16, 0x16, 0x10, 0x10, 0x04, 0x21, 0x01, 0x47, 0x05, 0x18, 0x00, 0x04,
+0x23, 0x23, 0x06, 0x06, 0x04, 0x54, 0x01, 0x1d, 0x04, 0x08, 0x00, 0x05,
+0x1f, 0x1f, 0x38, 0x38, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x01, 0x62,
+0x03, 0x04, 0x01, 0x20, 0x01, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x07,
+0x02, 0xaf, 0x88, 0x88, 0x72, 0x6c, 0xad, 0x00, 0x2b, 0x00, 0x00, 0x00,
+0x82, 0x00, 0x00, 0x05, 0xb1, 0xd4, 0x82, 0x82, 0xb8, 0x00, 0x03, 0xbb,
+0x01, 0xb4, 0x01, 0x52, 0x04, 0x29, 0x04, 0x27, 0x00, 0x05, 0x7b, 0x5a,
+0x5a, 0x12, 0x12, 0x00, 0x05, 0x02, 0x05, 0x14, 0x00, 0x04, 0x0c, 0x0c,
+0x20, 0x20, 0x04, 0x04, 0x01, 0x62, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
+0x38, 0x1f, 0x1f, 0x00, 0x04, 0x08, 0x00, 0x04, 0x1d, 0x1d, 0x54, 0x54,
+0x04, 0x06, 0x01, 0x23, 0x04, 0x18, 0x00, 0x06, 0x47, 0x21, 0x21, 0x47,
+0x21, 0x21, 0x04, 0x16, 0x04, 0x13, 0x05, 0x2a, 0x06, 0x0f, 0x03, 0x4c,
+0x04, 0x41, 0x04, 0x49, 0x01, 0x67, 0x01, 0x67, 0x05, 0x78, 0x05, 0x3d,
+0x06, 0x55, 0x05, 0x50, 0x04, 0x5e, 0x05, 0x46, 0x01, 0x64, 0x01, 0x46,
+0x04, 0x64, 0x03, 0x60, 0x04, 0x4e, 0x05, 0x56, 0x07, 0x48, 0x01, 0x5f,
+0x01, 0x48, 0x04, 0x5f, 0x09, 0x48, 0x04, 0x56, 0x06, 0x4e, 0x06, 0x64,
+0x07, 0x46, 0x04, 0x5e, 0x06, 0x50, 0x05, 0x55, 0x05, 0x3d, 0x05, 0x78,
+0x03, 0x67, 0x05, 0x49, 0x01, 0x41, 0x01, 0x41, 0x04, 0x4c, 0x05, 0x0f,
+0x04, 0x2a, 0x04, 0x13, 0x03, 0x16, 0x01, 0x10, 0x01, 0x10, 0x04, 0x21,
+0x01, 0x47, 0x05, 0x18, 0x00, 0x04, 0x23, 0x23, 0x06, 0x06, 0x03, 0x54,
+0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32,
+0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x01, 0x62, 0x03, 0x04, 0x01, 0x20,
+0x01, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x07, 0x02, 0xaa, 0x74, 0x81,
+0x88, 0x74, 0x90, 0x00, 0x2b, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x05,
+0x6b, 0x8b, 0xf4, 0xa6, 0xb4, 0x00, 0x04, 0xb8, 0x00, 0x0b, 0xb4, 0x7b,
+0x27, 0x29, 0x29, 0x27, 0x7b, 0x27, 0x7b, 0x12, 0x5a, 0x00, 0x03, 0x12,
+0x05, 0x02, 0x03, 0x14, 0x03, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x03, 0x04,
+0x04, 0x62, 0x00, 0x04, 0x01, 0x01, 0x32, 0x38, 0x03, 0x1f, 0x03, 0x08,
+0x00, 0x04, 0x1d, 0x1d, 0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23,
+0x04, 0x18, 0x03, 0x47, 0x01, 0x21, 0x01, 0x21, 0x03, 0x10, 0x03, 0x16,
+0x04, 0x13, 0x04, 0x2a, 0x05, 0x0f, 0x04, 0x4c, 0x04, 0x41, 0x04, 0x49,
+0x01, 0x67, 0x01, 0x67, 0x04, 0x78, 0x07, 0x3d, 0x05, 0x55, 0x06, 0x50,
+0x04, 0x5e, 0x05, 0x46, 0x06, 0x64, 0x01, 0x60, 0x01, 0x60, 0x05, 0x4e,
+0x05, 0x56, 0x14, 0x48, 0x05, 0x56, 0x06, 0x4e, 0x06, 0x64, 0x06, 0x46,
+0x05, 0x5e, 0x06, 0x50, 0x05, 0x55, 0x06, 0x3d, 0x03, 0x78, 0x03, 0x67,
+0x05, 0x49, 0x03, 0x41, 0x04, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x05, 0x13,
+0x03, 0x16, 0x01, 0x10, 0x01, 0x10, 0x04, 0x21, 0x00, 0x07, 0x47, 0x47,
+0x18, 0x18, 0x58, 0x23, 0x23, 0x00, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d,
+0x01, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32, 0x32, 0x00,
+0x03, 0x01, 0x01, 0x62, 0x01, 0x62, 0x03, 0x04, 0x01, 0x20, 0x01, 0x20,
+0x03, 0x0c, 0x04, 0x14, 0x00, 0x08, 0x02, 0x02, 0xc1, 0x6c, 0x6c, 0x74,
+0xa7, 0x6b, 0x2a, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x05, 0xad, 0xea,
+0xb8, 0x37, 0xb4, 0x00, 0x04, 0xb8, 0x00, 0x04, 0xaf, 0xb4, 0xb4, 0x7b,
+0x04, 0x27, 0x01, 0x5a, 0x03, 0x12, 0x06, 0x02, 0x03, 0x14, 0x00, 0x04,
+0x0c, 0x0c, 0x20, 0x20, 0x03, 0x04, 0x03, 0x62, 0x00, 0x05, 0x01, 0x01,
+0x32, 0x32, 0x38, 0x00, 0x04, 0x1f, 0x00, 0x06, 0x08, 0x08, 0x1d, 0x1d,
+0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23, 0x04, 0x18, 0x00, 0x04,
+0x47, 0x47, 0x21, 0x47, 0x03, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16,
+0x04, 0x13, 0x04, 0x2a, 0x06, 0x0f, 0x03, 0x4c, 0x03, 0x41, 0x03, 0x49,
+0x01, 0x67, 0x01, 0x49, 0x03, 0x67, 0x04, 0x78, 0x06, 0x3d, 0x06, 0x55,
+0x04, 0x50, 0x05, 0x5e, 0x05, 0x46, 0x04, 0x64, 0x01, 0x60, 0x03, 0x64,
+0x06, 0x4e, 0x05, 0x56, 0x12, 0x48, 0x06, 0x56, 0x05, 0x4e, 0x07, 0x64,
+0x06, 0x46, 0x04, 0x5e, 0x07, 0x50, 0x05, 0x55, 0x03, 0x3d, 0x00, 0x03,
+0x78, 0x3d, 0x3d, 0x00, 0x03, 0x78, 0x03, 0x67, 0x04, 0x49, 0x05, 0x41,
+0x01, 0x4c, 0x01, 0x4c, 0x06, 0x0f, 0x03, 0x2a, 0x05, 0x13, 0x03, 0x16,
+0x01, 0x10, 0x01, 0x10, 0x04, 0x21, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23,
+0x01, 0x23, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08,
+0x00, 0x05, 0x1f, 0x38, 0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62,
+0x03, 0x04, 0x03, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x0a, 0x02, 0x5a,
+0xaa, 0x91, 0x6c, 0x6c, 0x81, 0xd9, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00,
+0x87, 0x00, 0x00, 0x05, 0xb2, 0xea, 0xa8, 0xb4, 0xb4, 0x00, 0x03, 0xaf,
+0x01, 0xa8, 0x03, 0xaf, 0x00, 0x04, 0xb4, 0xb4, 0x12, 0x7b, 0x03, 0x5a,
+0x01, 0x02, 0x01, 0x12, 0x04, 0x02, 0x01, 0x14, 0x01, 0x14, 0x04, 0x0c,
+0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
+0x38, 0x38, 0x1f, 0x00, 0x05, 0x08, 0x00, 0x03, 0x1d, 0x54, 0x1d, 0x00,
+0x03, 0x06, 0x03, 0x23, 0x01, 0x18, 0x01, 0x18, 0x03, 0x47, 0x01, 0x21,
+0x01, 0x47, 0x04, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16, 0x04, 0x13,
+0x04, 0x2a, 0x05, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x05, 0x41, 0x04, 0x49,
+0x04, 0x67, 0x01, 0x78, 0x01, 0x78, 0x08, 0x3d, 0x05, 0x55, 0x05, 0x50,
+0x04, 0x5e, 0x07, 0x46, 0x04, 0x64, 0x08, 0x4e, 0x03, 0x56, 0x13, 0x48,
+0x06, 0x56, 0x06, 0x4e, 0x01, 0x64, 0x01, 0x4e, 0x04, 0x64, 0x07, 0x46,
+0x05, 0x5e, 0x04, 0x50, 0x04, 0x55, 0x01, 0x3d, 0x01, 0x55, 0x03, 0x3d,
+0x06, 0x78, 0x04, 0x67, 0x01, 0x49, 0x01, 0x49, 0x05, 0x41, 0x03, 0x4c,
+0x05, 0x0f, 0x04, 0x2a, 0x03, 0x13, 0x04, 0x16, 0x00, 0x04, 0x10, 0x10,
+0x21, 0x21, 0x05, 0x47, 0x01, 0x58, 0x01, 0x58, 0x03, 0x23, 0x04, 0x06,
+0x04, 0x1d, 0x04, 0x08, 0x03, 0x38, 0x00, 0x03, 0x32, 0x01, 0x01, 0x00,
+0x05, 0x04, 0x06, 0x0c, 0x07, 0x02, 0x00, 0x08, 0x5a, 0x5a, 0x74, 0x8f,
+0x8f, 0x80, 0xd0, 0x4d, 0x29, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x07,
+0x03, 0x00, 0x00, 0x0d, 0x75, 0x8b, 0x88, 0x00, 0x04, 0xaf, 0x06, 0xa8,
+0x03, 0xaf, 0x03, 0xaa, 0x03, 0x14, 0x0c, 0xaa, 0x01, 0x62, 0x06, 0x01,
+0x07, 0x1f, 0x06, 0x54, 0x01, 0x06, 0x04, 0xb7, 0x03, 0x18, 0x03, 0x16,
+0x01, 0x10, 0x03, 0x16, 0x04, 0xf3, 0x00, 0x04, 0x13, 0xf3, 0xf3, 0x2a,
+0x08, 0x0f, 0x00, 0x05, 0x4c, 0x4c, 0xfb, 0xfb, 0x41, 0x00, 0x06, 0x49,
+0x01, 0x67, 0x01, 0x67, 0x09, 0x78, 0x03, 0x3d, 0x07, 0x55, 0x05, 0x50,
+0x06, 0x5e, 0x06, 0x46, 0x03, 0x64, 0x05, 0x60, 0x07, 0x4e, 0x10, 0x56,
+0x04, 0x4e, 0x00, 0x04, 0x60, 0x60, 0x4e, 0x4e, 0x04, 0x60, 0x04, 0x64,
+0x0a, 0x46, 0x01, 0x5e, 0x01, 0x5e, 0x05, 0x50, 0x07, 0x55, 0x03, 0x3d,
+0x00, 0x03, 0x78, 0x3d, 0x3d, 0x00, 0x07, 0x78, 0x01, 0x67, 0x01, 0x67,
+0x06, 0x49, 0x01, 0x41, 0x07, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x06, 0x13,
+0x06, 0x16, 0x00, 0x03, 0xb7, 0xb7, 0x16, 0x00, 0x08, 0xb7, 0x06, 0x54,
+0x08, 0x1f, 0x04, 0x01, 0x00, 0x04, 0x62, 0xaa, 0x62, 0xaa, 0x03, 0x20,
+0x03, 0xaa, 0x00, 0x0b, 0x14, 0x14, 0x02, 0xf8, 0x8f, 0xcc, 0x8f, 0xcc,
+0xe7, 0x00, 0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x86, 0x00, 0x01, 0x0d,
+0x01, 0x11, 0x03, 0x00, 0x00, 0x05, 0x6b, 0x7e, 0xcf, 0x88, 0xa8, 0x00,
+0x03, 0xaf, 0x03, 0xa8, 0x03, 0x72, 0x06, 0xa8, 0x00, 0x06, 0x72, 0xa8,
+0xa8, 0x72, 0x72, 0xa8, 0x23, 0x72, 0x1d, 0x74, 0x13, 0x80, 0x00, 0x04,
+0x81, 0x80, 0x80, 0x81, 0x04, 0x80, 0x1b, 0x81, 0x00, 0x04, 0x91, 0x91,
+0x81, 0x91, 0x34, 0x6c, 0x03, 0x7a, 0x01, 0x6c, 0x22, 0x7a, 0x03, 0x77,
+0x00, 0x03, 0x7a, 0x7a, 0x77, 0x00, 0x03, 0x7a, 0x05, 0x77, 0x01, 0x7a,
+0x2a, 0x77, 0x03, 0xcc, 0x00, 0x04, 0x91, 0xd9, 0x00, 0x03, 0x27, 0x00,
+0x00, 0x00, 0x8e, 0x00, 0x00, 0x0b, 0x8e, 0x7e, 0xea, 0x8f, 0x88, 0xa8,
+0xaf, 0xaf, 0xa8, 0x72, 0x72, 0x00, 0x3d, 0x88, 0x2c, 0x81, 0x01, 0x6c,
+0x09, 0x81, 0x01, 0x6c, 0x03, 0x81, 0x2e, 0x6c, 0x28, 0x8f, 0x1c, 0xcc,
+0x01, 0xa7, 0x03, 0xcc, 0x00, 0x05, 0xa7, 0xcc, 0xa7, 0xa7, 0xcc, 0x00,
+0x14, 0xa7, 0x13, 0x9d, 0x00, 0x07, 0xa7, 0x9d, 0x9d, 0x77, 0xec, 0x00,
+0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x08, 0x6b, 0xb2,
+0x7d, 0xd0, 0xea, 0xcc, 0x81, 0x88, 0x12, 0xc1, 0x00, 0x03, 0x72, 0x72,
+0xc1, 0x00, 0x24, 0x72, 0x01, 0x74, 0x03, 0x72, 0x01, 0x74, 0x01, 0x72,
+0x27, 0x74, 0x2c, 0x80, 0x01, 0x91, 0x01, 0x80, 0x23, 0x91, 0x05, 0x7a,
+0x01, 0x91, 0x18, 0x7a, 0x04, 0x77, 0x01, 0x7a, 0x1b, 0x77, 0x01, 0x60,
+0x01, 0x64, 0x24, 0x60, 0x00, 0x05, 0x77, 0xfa, 0x6b, 0x00, 0x0d, 0x00,
+0x27, 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x08, 0x71, 0x7c, 0xe7, 0xec,
+0x7e, 0x7d, 0x68, 0x90, 0x45, 0x8b, 0x00, 0x03, 0x90, 0x90, 0x8b, 0x00,
+0x2b, 0x90, 0x01, 0x68, 0x04, 0x90, 0x4d, 0x68, 0x00, 0x03, 0x7d, 0x7d,
+0x68, 0x00, 0x4f, 0x7d, 0x00, 0x04, 0xd9, 0x8e, 0x00, 0x0d, 0x28, 0x00,
+0x00, 0x00, 0x9d, 0x00, 0xff, 0x0d, 0x18, 0x0d, 0x2c, 0x00, 0x00, 0x00,
+0x95, 0x00, 0x01, 0x0d, 0x03, 0x03, 0x00, 0x03, 0x11, 0x11, 0x0d, 0x00,
+0xff, 0x00, 0x1a, 0x00, 0x01, 0x0d, 0x2a, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x01
+};
+
diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h
index 063177b..484bc30 100644
--- a/include/stm32_rcc.h
+++ b/include/stm32_rcc.h
@@ -45,6 +45,11 @@
STM32F7,
};
+enum apb {
+ APB1,
+ APB2,
+};
+
struct stm32_rcc_clk {
char *drv_name;
enum soc_family soc;
diff --git a/include/tee/optee.h b/include/tee/optee.h
index 9ab0d08..4b9e94c 100644
--- a/include/tee/optee.h
+++ b/include/tee/optee.h
@@ -10,6 +10,8 @@
#ifndef _OPTEE_H
#define _OPTEE_H
+#include <linux/errno.h>
+
#define OPTEE_MAGIC 0x4554504f
#define OPTEE_VERSION 1
#define OPTEE_ARCH_ARM32 0
@@ -27,4 +29,43 @@
uint32_t paged_size;
};
+static inline uint32_t optee_image_get_entry_point(const image_header_t *hdr)
+{
+ struct optee_header *optee_hdr = (struct optee_header *)(hdr + 1);
+
+ return optee_hdr->init_load_addr_lo;
+}
+
+static inline uint32_t optee_image_get_load_addr(const image_header_t *hdr)
+{
+ return optee_image_get_entry_point(hdr) - sizeof(struct optee_header);
+}
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+ unsigned long tzdram_len, unsigned long image_len);
+#else
+static inline int optee_verify_image(struct optee_header *hdr,
+ unsigned long tzdram_start,
+ unsigned long tzdram_len,
+ unsigned long image_len)
+{
+ return -EPERM;
+}
+
+#endif
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_bootm_image(unsigned long image_addr,
+ unsigned long image_load_addr,
+ unsigned long image_len);
+#else
+static inline int optee_verify_bootm_image(unsigned long image_addr,
+ unsigned long image_load_addr,
+ unsigned long image_len)
+{
+ return -EPERM;
+}
+#endif
+
#endif /* _OPTEE_H */
diff --git a/include/video.h b/include/video.h
index 61ff653..ddc2eeb 100644
--- a/include/video.h
+++ b/include/video.h
@@ -67,6 +67,7 @@
* @flush_dcache: true to enable flushing of the data cache after
* the LCD is updated
* @cmap: Colour map for 8-bit-per-pixel displays
+ * @fg_col_idx: Foreground color code (bit 3 = bold, bit 0-2 = color)
*/
struct video_priv {
/* Things set up by the driver: */
@@ -84,10 +85,11 @@
void *fb;
int fb_size;
int line_length;
- int colour_fg;
- int colour_bg;
+ u32 colour_fg;
+ u32 colour_bg;
bool flush_dcache;
ushort *cmap;
+ u8 fg_col_idx;
};
/* Placeholder - there are no video operations at present */
@@ -183,6 +185,13 @@
*/
void video_set_flush_dcache(struct udevice *dev, bool flush);
+/**
+ * Set default colors and attributes
+ *
+ * @priv device information
+ */
+void video_set_default_colors(struct video_priv *priv);
+
#endif /* CONFIG_DM_VIDEO */
#ifndef CONFIG_DM_VIDEO
diff --git a/include/video_console.h b/include/video_console.h
index 9dce234..7621a18 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -7,11 +7,37 @@
#ifndef __video_console_h
#define __video_console_h
+#include <video.h>
+
#define VID_FRAC_DIV 256
#define VID_TO_PIXEL(x) ((x) / VID_FRAC_DIV)
#define VID_TO_POS(x) ((x) * VID_FRAC_DIV)
+/*
+ * The 16 colors supported by the console
+ */
+enum color_idx {
+ VID_BLACK = 0,
+ VID_RED,
+ VID_GREEN,
+ VID_BROWN,
+ VID_BLUE,
+ VID_MAGENTA,
+ VID_CYAN,
+ VID_LIGHT_GRAY,
+ VID_GRAY,
+ VID_LIGHT_RED,
+ VID_LIGTH_GREEN,
+ VID_YELLOW,
+ VID_LIGHT_BLUE,
+ VID_LIGHT_MAGENTA,
+ VID_LIGHT_CYAN,
+ VID_WHITE,
+
+ VID_COLOR_COUNT
+};
+
/**
* struct vidconsole_priv - uclass-private data about a console device
*
@@ -196,4 +222,21 @@
void vidconsole_position_cursor(struct udevice *dev, unsigned col,
unsigned row);
+#ifdef CONFIG_DM_VIDEO
+
+/**
+ * vid_console_color() - convert a color code to a pixel's internal
+ * representation
+ *
+ * The caller has to guarantee that the color index is less than
+ * VID_COLOR_COUNT.
+ *
+ * @priv private data of the console device
+ * @idx color index
+ * @return color value
+ */
+u32 vid_console_color(struct video_priv *priv, unsigned int idx);
+
+#endif
+
#endif
diff --git a/include/video_font_4x6.h b/include/video_font_4x6.h
index 6aeed09..64c5ed2 100644
--- a/include/video_font_4x6.h
+++ b/include/video_font_4x6.h
@@ -1,5 +1,5 @@
-/* Hand composed "Minuscule" 4x6 font, with binary data generated using
- * Perl stub.
+/* Hand composed "Minuscule" 4x6 font for code page 437, with binary data
+ * generated using Perl stub.
*
* Use 'perl -x mini_4x6.c < mini_4x6.c > new_version.c' to regenerate
* binary data.
diff --git a/include/video_font_data.h b/include/video_font_data.h
index 346a162..d52526a 100644
--- a/include/video_font_data.h
+++ b/include/video_font_data.h
@@ -3,6 +3,8 @@
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file contains an 8x16 bitmap font for code page 437.
*/
#ifndef _VIDEO_FONT_DATA_
diff --git a/include/watchdog.h b/include/watchdog.h
index 64b59f1..52f4c50 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -72,11 +72,6 @@
* Prototypes from $(CPU)/cpu.c.
*/
-/* MPC 8xx */
-#if defined(CONFIG_8xx) && !defined(__ASSEMBLY__)
- void reset_8xx_watchdog(immap_t __iomem *immr);
-#endif
-
#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
void hw_watchdog_init(void);
#endif
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index 4c8c2f8..8b3ce8e 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -12,6 +12,7 @@
#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
+#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017
#define ZYNQMP_FPGA_OP_INIT (1 << 0)
#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
#define ZYNQMP_FPGA_OP_DONE (1 << 2)
diff --git a/lib/Kconfig b/lib/Kconfig
index 4fd41c4..436b90f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -66,7 +66,6 @@
config REGEX
bool "Enable regular expression support"
- default n if ARCH_SUNXI
default y if NET
help
If this variable is defined, U-Boot is linked against the
@@ -310,5 +309,6 @@
source lib/efi/Kconfig
source lib/efi_loader/Kconfig
+source lib/optee/Kconfig
endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 0db41c1..35da570 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -18,6 +18,7 @@
obj-$(CONFIG_OF_LIVE) += of_live.o
obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
obj-$(CONFIG_ARCH_AT91) += at91/
+obj-$(CONFIG_OPTEE) += optee/
obj-$(CONFIG_AES) += aes.o
obj-y += charset.o
diff --git a/lib/efi/efi_stub.c b/lib/efi/efi_stub.c
index 2e8d409..205aa19 100644
--- a/lib/efi/efi_stub.c
+++ b/lib/efi/efi_stub.c
@@ -182,7 +182,7 @@
<< 16;
base <<= 12; /* 4KB granularity */
limit <<= 12;
- if ((desc & GDT_PRESENT) && (desc && GDT_NOTSYS) &&
+ if ((desc & GDT_PRESENT) && (desc & GDT_NOTSYS) &&
!(desc & GDT_LONG) && (desc & GDT_4KB) &&
(desc & GDT_32BIT) && (desc & GDT_CODE) &&
CONFIG_SYS_TEXT_BASE > base &&
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 2a87d9e..55c97c0 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -17,9 +17,10 @@
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
obj-y += efi_memory.o efi_device_path_to_text.o efi_device_path.o
-obj-y += efi_file.o efi_variable.o efi_bootmgr.o efi_watchdog.o
+obj-y += efi_device_path_utilities.o efi_file.o efi_variable.o efi_bootmgr.o
+obj-y += efi_watchdog.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_DM_VIDEO) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
-obj-$(CONFIG_CMD_NET) += efi_net.o
+obj-$(CONFIG_NET) += efi_net.o
obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 66e26fd..7a9449f 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -26,6 +26,9 @@
/* This list contains all the EFI objects our payload has access to */
LIST_HEAD(efi_obj_list);
+/* List of all events */
+LIST_HEAD(efi_events);
+
/*
* If we're running on nasty systems (32bit ARM booting into non-EFI Linux)
* we need to do trickery with caches. Since we don't want to break the EFI
@@ -56,10 +59,28 @@
static int entry_count;
static int nesting_level;
+/* GUID of the device tree table */
+const efi_guid_t efi_guid_fdt = EFI_FDT_GUID;
/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
const efi_guid_t efi_guid_driver_binding_protocol =
EFI_DRIVER_BINDING_PROTOCOL_GUID;
+/* event group ExitBootServices() invoked */
+const efi_guid_t efi_guid_event_group_exit_boot_services =
+ EFI_EVENT_GROUP_EXIT_BOOT_SERVICES;
+/* event group SetVirtualAddressMap() invoked */
+const efi_guid_t efi_guid_event_group_virtual_address_change =
+ EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE;
+/* event group memory map changed */
+const efi_guid_t efi_guid_event_group_memory_map_change =
+ EFI_EVENT_GROUP_MEMORY_MAP_CHANGE;
+/* event group boot manager about to boot */
+const efi_guid_t efi_guid_event_group_ready_to_boot =
+ EFI_EVENT_GROUP_READY_TO_BOOT;
+/* event group ResetSystem() invoked (before ExitBootServices) */
+const efi_guid_t efi_guid_event_group_reset_system =
+ EFI_EVENT_GROUP_RESET_SYSTEM;
+
static efi_status_t EFIAPI efi_disconnect_controller(
efi_handle_t controller_handle,
efi_handle_t driver_image_handle,
@@ -121,6 +142,7 @@
{
const char *indent = " ";
const int max = strlen(indent);
+
level = min(max, level * 2);
return &indent[max - level];
}
@@ -154,7 +176,7 @@
* @event event to signal
* @check_tpl check the TPL level
*/
-void efi_signal_event(struct efi_event *event, bool check_tpl)
+static void efi_queue_event(struct efi_event *event, bool check_tpl)
{
if (event->notify_function) {
event->is_queued = true;
@@ -168,6 +190,50 @@
}
/*
+ * Signal an EFI event.
+ *
+ * This function signals an event. If the event belongs to an event group
+ * all events of the group are signaled. If they are of type EVT_NOTIFY_SIGNAL
+ * their notification function is queued.
+ *
+ * For the SignalEvent service see efi_signal_event_ext.
+ *
+ * @event event to signal
+ * @check_tpl check the TPL level
+ */
+void efi_signal_event(struct efi_event *event, bool check_tpl)
+{
+ if (event->group) {
+ struct efi_event *evt;
+
+ /*
+ * The signaled state has to set before executing any
+ * notification function
+ */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (!evt->group || guidcmp(evt->group, event->group))
+ continue;
+ if (evt->is_signaled)
+ continue;
+ evt->is_signaled = true;
+ if (evt->type & EVT_NOTIFY_SIGNAL &&
+ evt->notify_function)
+ evt->is_queued = true;
+ }
+ list_for_each_entry(evt, &efi_events, link) {
+ if (!evt->group || guidcmp(evt->group, event->group))
+ continue;
+ if (evt->is_queued)
+ efi_queue_event(evt, check_tpl);
+ }
+ } else if (!event->is_signaled) {
+ event->is_signaled = true;
+ if (event->type & EVT_NOTIFY_SIGNAL)
+ efi_queue_event(event, check_tpl);
+ }
+}
+
+/*
* Raise the task priority level.
*
* This function implements the RaiseTpl service.
@@ -212,6 +278,11 @@
if (efi_tpl > TPL_HIGH_LEVEL)
efi_tpl = TPL_HIGH_LEVEL;
+ /*
+ * Lowering the TPL may have made queued events eligible for execution.
+ */
+ efi_timer_check();
+
EFI_EXIT(EFI_SUCCESS);
}
@@ -255,7 +326,7 @@
{
efi_status_t r;
- EFI_ENTRY("%"PRIx64", 0x%zx", memory, pages);
+ EFI_ENTRY("%" PRIx64 ", 0x%zx", memory, pages);
r = efi_free_pages(memory, pages);
return EFI_EXIT(r);
}
@@ -470,10 +541,23 @@
}
/*
- * Our event capabilities are very limited. Only a small limited
- * number of events is allowed to coexist.
+ * Check if a pointer is a valid event.
+ *
+ * @event pointer to check
+ * @return status code
*/
-static struct efi_event efi_events[16];
+static efi_status_t efi_is_event(const struct efi_event *event)
+{
+ const struct efi_event *evt;
+
+ if (!event)
+ return EFI_INVALID_PARAMETER;
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt == event)
+ return EFI_SUCCESS;
+ }
+ return EFI_INVALID_PARAMETER;
+}
/*
* Create an event.
@@ -494,9 +578,10 @@
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
- void *notify_context, struct efi_event **event)
+ void *notify_context, efi_guid_t *group,
+ struct efi_event **event)
{
- int i;
+ struct efi_event *evt;
if (event == NULL)
return EFI_INVALID_PARAMETER;
@@ -504,25 +589,25 @@
if ((type & EVT_NOTIFY_SIGNAL) && (type & EVT_NOTIFY_WAIT))
return EFI_INVALID_PARAMETER;
- if ((type & (EVT_NOTIFY_SIGNAL|EVT_NOTIFY_WAIT)) &&
+ if ((type & (EVT_NOTIFY_SIGNAL | EVT_NOTIFY_WAIT)) &&
notify_function == NULL)
return EFI_INVALID_PARAMETER;
- for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
- if (efi_events[i].type)
- continue;
- efi_events[i].type = type;
- efi_events[i].notify_tpl = notify_tpl;
- efi_events[i].notify_function = notify_function;
- efi_events[i].notify_context = notify_context;
- /* Disable timers on bootup */
- efi_events[i].trigger_next = -1ULL;
- efi_events[i].is_queued = false;
- efi_events[i].is_signaled = false;
- *event = &efi_events[i];
- return EFI_SUCCESS;
- }
- return EFI_OUT_OF_RESOURCES;
+ evt = calloc(1, sizeof(struct efi_event));
+ if (!evt)
+ return EFI_OUT_OF_RESOURCES;
+ evt->type = type;
+ evt->notify_tpl = notify_tpl;
+ evt->notify_function = notify_function;
+ evt->notify_context = notify_context;
+ evt->group = group;
+ /* Disable timers on bootup */
+ evt->trigger_next = -1ULL;
+ evt->is_queued = false;
+ evt->is_signaled = false;
+ list_add_tail(&evt->link, &efi_events);
+ *event = evt;
+ return EFI_SUCCESS;
}
/*
@@ -551,10 +636,8 @@
{
EFI_ENTRY("%d, 0x%zx, %p, %p, %pUl", type, notify_tpl, notify_function,
notify_context, event_group);
- if (event_group)
- return EFI_EXIT(EFI_UNSUPPORTED);
return EFI_EXIT(efi_create_event(type, notify_tpl, notify_function,
- notify_context, event));
+ notify_context, event_group, event));
}
/*
@@ -581,10 +664,9 @@
EFI_ENTRY("%d, 0x%zx, %p, %p", type, notify_tpl, notify_function,
notify_context);
return EFI_EXIT(efi_create_event(type, notify_tpl, notify_function,
- notify_context, event));
+ notify_context, NULL, event));
}
-
/*
* Check if a timer event has occurred or a queued notification function should
* be called.
@@ -594,30 +676,26 @@
*/
void efi_timer_check(void)
{
- int i;
+ struct efi_event *evt;
u64 now = timer_get_us();
- for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
- if (!efi_events[i].type)
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->is_queued)
+ efi_queue_event(evt, true);
+ if (!(evt->type & EVT_TIMER) || now < evt->trigger_next)
continue;
- if (efi_events[i].is_queued)
- efi_signal_event(&efi_events[i], true);
- if (!(efi_events[i].type & EVT_TIMER) ||
- now < efi_events[i].trigger_next)
- continue;
- switch (efi_events[i].trigger_type) {
+ switch (evt->trigger_type) {
case EFI_TIMER_RELATIVE:
- efi_events[i].trigger_type = EFI_TIMER_STOP;
+ evt->trigger_type = EFI_TIMER_STOP;
break;
case EFI_TIMER_PERIODIC:
- efi_events[i].trigger_next +=
- efi_events[i].trigger_time;
+ evt->trigger_next += evt->trigger_time;
break;
default:
continue;
}
- efi_events[i].is_signaled = true;
- efi_signal_event(&efi_events[i], true);
+ evt->is_signaled = false;
+ efi_signal_event(evt, true);
}
WATCHDOG_RESET();
}
@@ -636,7 +714,9 @@
efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
uint64_t trigger_time)
{
- int i;
+ /* Check that the event is valid */
+ if (efi_is_event(event) != EFI_SUCCESS || !(event->type & EVT_TIMER))
+ return EFI_INVALID_PARAMETER;
/*
* The parameter defines a multiple of 100ns.
@@ -644,30 +724,21 @@
*/
do_div(trigger_time, 10);
- for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
- if (event != &efi_events[i])
- continue;
-
- if (!(event->type & EVT_TIMER))
- break;
- switch (type) {
- case EFI_TIMER_STOP:
- event->trigger_next = -1ULL;
- break;
- case EFI_TIMER_PERIODIC:
- case EFI_TIMER_RELATIVE:
- event->trigger_next =
- timer_get_us() + trigger_time;
- break;
- default:
- return EFI_INVALID_PARAMETER;
- }
- event->trigger_type = type;
- event->trigger_time = trigger_time;
- event->is_signaled = false;
- return EFI_SUCCESS;
+ switch (type) {
+ case EFI_TIMER_STOP:
+ event->trigger_next = -1ULL;
+ break;
+ case EFI_TIMER_PERIODIC:
+ case EFI_TIMER_RELATIVE:
+ event->trigger_next = timer_get_us() + trigger_time;
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
}
- return EFI_INVALID_PARAMETER;
+ event->trigger_type = type;
+ event->trigger_time = trigger_time;
+ event->is_signaled = false;
+ return EFI_SUCCESS;
}
/*
@@ -686,7 +757,7 @@
enum efi_timer_delay type,
uint64_t trigger_time)
{
- EFI_ENTRY("%p, %d, %"PRIx64, event, type, trigger_time);
+ EFI_ENTRY("%p, %d, %" PRIx64, event, type, trigger_time);
return EFI_EXIT(efi_set_timer(event, type, trigger_time));
}
@@ -706,7 +777,7 @@
struct efi_event **event,
efi_uintn_t *index)
{
- int i, j;
+ int i;
EFI_ENTRY("%zd, %p, %p", num_events, event, index);
@@ -717,16 +788,12 @@
if (efi_tpl != TPL_APPLICATION)
return EFI_EXIT(EFI_UNSUPPORTED);
for (i = 0; i < num_events; ++i) {
- for (j = 0; j < ARRAY_SIZE(efi_events); ++j) {
- if (event[i] == &efi_events[j])
- goto known_event;
- }
- return EFI_EXIT(EFI_INVALID_PARAMETER);
-known_event:
+ if (efi_is_event(event[i]) != EFI_SUCCESS)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
if (!event[i]->type || event[i]->type & EVT_NOTIFY_SIGNAL)
return EFI_EXIT(EFI_INVALID_PARAMETER);
if (!event[i]->is_signaled)
- efi_signal_event(event[i], true);
+ efi_queue_event(event[i], true);
}
/* Wait for signal */
@@ -766,19 +833,10 @@
*/
static efi_status_t EFIAPI efi_signal_event_ext(struct efi_event *event)
{
- int i;
-
EFI_ENTRY("%p", event);
- for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
- if (event != &efi_events[i])
- continue;
- if (event->is_signaled)
- break;
- event->is_signaled = true;
- if (event->type & EVT_NOTIFY_SIGNAL)
- efi_signal_event(event, true);
- break;
- }
+ if (efi_is_event(event) != EFI_SUCCESS)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ efi_signal_event(event, true);
return EFI_EXIT(EFI_SUCCESS);
}
@@ -794,19 +852,12 @@
*/
static efi_status_t EFIAPI efi_close_event(struct efi_event *event)
{
- int i;
-
EFI_ENTRY("%p", event);
- for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
- if (event == &efi_events[i]) {
- event->type = 0;
- event->trigger_next = -1ULL;
- event->is_queued = false;
- event->is_signaled = false;
- return EFI_EXIT(EFI_SUCCESS);
- }
- }
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ if (efi_is_event(event) != EFI_SUCCESS)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ list_del(&event->link);
+ free(event);
+ return EFI_EXIT(EFI_SUCCESS);
}
/*
@@ -816,29 +867,26 @@
* See the Unified Extensible Firmware Interface (UEFI) specification
* for details.
*
- * If an event is not signaled yet the notification function is queued.
+ * If an event is not signaled yet, the notification function is queued.
+ * The signaled state is cleared.
*
* @event event to check
* @return status code
*/
static efi_status_t EFIAPI efi_check_event(struct efi_event *event)
{
- int i;
-
EFI_ENTRY("%p", event);
efi_timer_check();
- for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
- if (event != &efi_events[i])
- continue;
- if (!event->type || event->type & EVT_NOTIFY_SIGNAL)
- break;
- if (!event->is_signaled)
- efi_signal_event(event, true);
- if (event->is_signaled)
- return EFI_EXIT(EFI_SUCCESS);
- return EFI_EXIT(EFI_NOT_READY);
+ if (efi_is_event(event) != EFI_SUCCESS ||
+ event->type & EVT_NOTIFY_SIGNAL)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ if (!event->is_signaled)
+ efi_queue_event(event, true);
+ if (event->is_signaled) {
+ event->is_signaled = false;
+ return EFI_EXIT(EFI_SUCCESS);
}
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ return EFI_EXIT(EFI_NOT_READY);
}
/*
@@ -1259,7 +1307,7 @@
/* Count how much space we need */
list_for_each_entry(efiobj, &efi_obj_list, link) {
if (!efi_search(search_type, protocol, search_key, efiobj))
- size += sizeof(void*);
+ size += sizeof(void *);
}
if (*buffer_size < size) {
@@ -1310,7 +1358,7 @@
static void efi_remove_configuration_table(int i)
{
struct efi_configuration_table *this = &efi_conf_table[i];
- struct efi_configuration_table *next = &efi_conf_table[i+1];
+ struct efi_configuration_table *next = &efi_conf_table[i + 1];
struct efi_configuration_table *end = &efi_conf_table[systab.nr_tables];
memmove(this, next, (ulong)end - (ulong)next);
@@ -1327,10 +1375,15 @@
* @table table to be installed
* @return status code
*/
-efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table)
+efi_status_t efi_install_configuration_table(const efi_guid_t *guid,
+ void *table)
{
+ struct efi_event *evt;
int i;
+ if (!guid)
+ return EFI_INVALID_PARAMETER;
+
/* Check for guid override */
for (i = 0; i < systab.nr_tables; i++) {
if (!guidcmp(guid, &efi_conf_table[i].guid)) {
@@ -1338,7 +1391,7 @@
efi_conf_table[i].table = table;
else
efi_remove_configuration_table(i);
- return EFI_SUCCESS;
+ goto out;
}
}
@@ -1354,6 +1407,15 @@
efi_conf_table[i].table = table;
systab.nr_tables = i + 1;
+out:
+ /* Notify that the configuration table was changed */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group && !guidcmp(evt->group, guid)) {
+ efi_signal_event(evt, false);
+ break;
+ }
+ }
+
return EFI_SUCCESS;
}
@@ -1420,14 +1482,15 @@
if (ret != EFI_SUCCESS)
goto failure;
- ret = efi_add_protocol(obj->handle, &efi_guid_console_control,
- (void *)&efi_console_control);
+ ret = efi_add_protocol(obj->handle,
+ &efi_guid_device_path_to_text_protocol,
+ (void *)&efi_device_path_to_text);
if (ret != EFI_SUCCESS)
goto failure;
ret = efi_add_protocol(obj->handle,
- &efi_guid_device_path_to_text_protocol,
- (void *)&efi_device_path_to_text);
+ &efi_guid_device_path_utilities_protocol,
+ (void *)&efi_device_path_utilities);
if (ret != EFI_SUCCESS)
goto failure;
@@ -1450,7 +1513,7 @@
struct efi_file_info *info = NULL;
struct efi_file_handle *f;
static efi_status_t ret;
- uint64_t bs;
+ efi_uintn_t bs;
f = efi_file_from_path(file_path);
if (!f)
@@ -1471,7 +1534,8 @@
if (ret)
goto error;
- EFI_CALL(ret = f->read(f, &info->file_size, *buffer));
+ bs = info->file_size;
+ EFI_CALL(ret = f->read(f, &bs, *buffer));
error:
free(info);
@@ -1505,18 +1569,37 @@
efi_handle_t parent_image,
struct efi_device_path *file_path,
void *source_buffer,
- unsigned long source_size,
+ efi_uintn_t source_size,
efi_handle_t *image_handle)
{
struct efi_loaded_image *info;
struct efi_object *obj;
efi_status_t ret;
- EFI_ENTRY("%d, %p, %pD, %p, %ld, %p", boot_policy, parent_image,
+ EFI_ENTRY("%d, %p, %pD, %p, %zd, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
+ if (!image_handle || !parent_image) {
+ ret = EFI_INVALID_PARAMETER;
+ goto error;
+ }
+
+ if (!source_buffer && !file_path) {
+ ret = EFI_NOT_FOUND;
+ goto error;
+ }
+
info = calloc(1, sizeof(*info));
+ if (!info) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto error;
+ }
obj = calloc(1, sizeof(*obj));
+ if (!obj) {
+ free(info);
+ ret = EFI_OUT_OF_RESOURCES;
+ goto error;
+ }
if (!source_buffer) {
struct efi_device_path *dp, *fp;
@@ -1552,6 +1635,7 @@
failure:
free(info);
efi_delete_handle(obj);
+error:
return EFI_EXIT(ret);
}
@@ -1635,8 +1719,9 @@
* @return status code
*/
static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle,
- efi_status_t exit_status, unsigned long exit_data_size,
- int16_t *exit_data)
+ efi_status_t exit_status,
+ unsigned long exit_data_size,
+ int16_t *exit_data)
{
/*
* We require that the handle points to the original loaded
@@ -1649,7 +1734,7 @@
* TODO: We should call the unload procedure of the loaded
* image protocol.
*/
- struct efi_loaded_image *loaded_image_info = (void*)image_handle;
+ struct efi_loaded_image *loaded_image_info = (void *)image_handle;
EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status,
exit_data_size, exit_data);
@@ -1724,7 +1809,7 @@
static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
unsigned long map_key)
{
- int i;
+ struct efi_event *evt;
EFI_ENTRY("%p, %ld", image_handle, map_key);
@@ -1735,12 +1820,19 @@
if (!systab.boottime)
return EFI_EXIT(EFI_SUCCESS);
+ /* Add related events to the event group */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->type == EVT_SIGNAL_EXIT_BOOT_SERVICES)
+ evt->group = &efi_guid_event_group_exit_boot_services;
+ }
/* Notify that ExitBootServices is invoked. */
- for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
- if (efi_events[i].type != EVT_SIGNAL_EXIT_BOOT_SERVICES)
- continue;
- efi_events[i].is_signaled = true;
- efi_signal_event(&efi_events[i], false);
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_exit_boot_services)) {
+ efi_signal_event(evt, false);
+ break;
+ }
}
/* TODO Should persist EFI variables here */
@@ -1786,7 +1878,8 @@
*/
static efi_status_t EFIAPI efi_get_next_monotonic_count(uint64_t *count)
{
- static uint64_t mono = 0;
+ static uint64_t mono;
+
EFI_ENTRY("%p", count);
*count = mono++;
return EFI_EXIT(EFI_SUCCESS);
@@ -1827,7 +1920,7 @@
unsigned long data_size,
uint16_t *watchdog_data)
{
- EFI_ENTRY("%ld, 0x%"PRIx64", %ld, %p", timeout, watchdog_code,
+ EFI_ENTRY("%ld, 0x%" PRIx64 ", %ld, %p", timeout, watchdog_code,
data_size, watchdog_data);
return EFI_EXIT(efi_set_watchdog(timeout));
}
@@ -1892,8 +1985,8 @@
* @entry_count number of entries available in the buffer
* @return status code
*/
-static efi_status_t EFIAPI efi_open_protocol_information(efi_handle_t handle,
- const efi_guid_t *protocol,
+static efi_status_t EFIAPI efi_open_protocol_information(
+ efi_handle_t handle, const efi_guid_t *protocol,
struct efi_open_protocol_info_entry **entry_buffer,
efi_uintn_t *entry_count)
{
@@ -2878,15 +2971,16 @@
.protocols_per_handle = efi_protocols_per_handle,
.locate_handle_buffer = efi_locate_handle_buffer,
.locate_protocol = efi_locate_protocol,
- .install_multiple_protocol_interfaces = efi_install_multiple_protocol_interfaces,
- .uninstall_multiple_protocol_interfaces = efi_uninstall_multiple_protocol_interfaces,
+ .install_multiple_protocol_interfaces =
+ efi_install_multiple_protocol_interfaces,
+ .uninstall_multiple_protocol_interfaces =
+ efi_uninstall_multiple_protocol_interfaces,
.calculate_crc32 = efi_calculate_crc32,
.copy_mem = efi_copy_mem,
.set_mem = efi_set_mem,
.create_event_ex = efi_create_event_ex,
};
-
static uint16_t __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
struct efi_system_table __efi_runtime_data systab = {
@@ -2896,11 +2990,11 @@
.headersize = sizeof(struct efi_table_hdr),
},
.fw_vendor = (long)firmware_vendor,
- .con_in = (void*)&efi_con_in,
- .con_out = (void*)&efi_con_out,
- .std_err = (void*)&efi_con_out,
- .runtime = (void*)&efi_runtime_services,
- .boottime = (void*)&efi_boot_services,
+ .con_in = (void *)&efi_con_in,
+ .con_out = (void *)&efi_con_out,
+ .std_err = (void *)&efi_con_out,
+ .runtime = (void *)&efi_runtime_services,
+ .boottime = (void *)&efi_boot_services,
.nr_tables = 0,
- .tables = (void*)efi_conf_table,
+ .tables = (void *)efi_conf_table,
};
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 28d6363..5d1a9a8 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -45,7 +45,6 @@
},
};
-const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
const efi_guid_t efi_guid_text_output_protocol =
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID;
const efi_guid_t efi_guid_text_input_protocol =
@@ -54,43 +53,6 @@
#define cESC '\x1b'
#define ESC "\x1b"
-static efi_status_t EFIAPI efi_cin_get_mode(
- struct efi_console_control_protocol *this,
- int *mode, char *uga_exists, char *std_in_locked)
-{
- EFI_ENTRY("%p, %p, %p, %p", this, mode, uga_exists, std_in_locked);
-
- if (mode)
- *mode = EFI_CONSOLE_MODE_TEXT;
- if (uga_exists)
- *uga_exists = 0;
- if (std_in_locked)
- *std_in_locked = 0;
-
- return EFI_EXIT(EFI_SUCCESS);
-}
-
-static efi_status_t EFIAPI efi_cin_set_mode(
- struct efi_console_control_protocol *this, int mode)
-{
- EFI_ENTRY("%p, %d", this, mode);
- return EFI_EXIT(EFI_UNSUPPORTED);
-}
-
-static efi_status_t EFIAPI efi_cin_lock_std_in(
- struct efi_console_control_protocol *this,
- uint16_t *password)
-{
- EFI_ENTRY("%p, %p", this, password);
- return EFI_EXIT(EFI_UNSUPPORTED);
-}
-
-struct efi_console_control_protocol efi_console_control = {
- .get_mode = efi_cin_get_mode,
- .set_mode = efi_cin_set_mode,
- .lock_std_in = efi_cin_lock_std_in,
-};
-
/* Default to mode 0 */
static struct simple_text_output_mode efi_con_mode = {
.max_mode = 1,
@@ -399,6 +361,48 @@
return EFI_EXIT(EFI_UNSUPPORTED);
}
+/*
+ * Analyze modifiers (shift, alt, ctrl) for function keys.
+ * This gets called when we have already parsed CSI.
+ *
+ * @modifiers: bitmask (shift, alt, ctrl)
+ * @return: the unmodified code
+ */
+static char skip_modifiers(int *modifiers)
+{
+ char c, mod = 0, ret = 0;
+
+ c = getc();
+
+ if (c != ';') {
+ ret = c;
+ if (c == '~')
+ goto out;
+ c = getc();
+ }
+ for (;;) {
+ switch (c) {
+ case '0'...'9':
+ mod *= 10;
+ mod += c - '0';
+ /* fall through */
+ case ';':
+ c = getc();
+ break;
+ default:
+ goto out;
+ }
+ }
+out:
+ if (mod)
+ --mod;
+ if (modifiers)
+ *modifiers = mod;
+ if (!ret)
+ ret = c;
+ return ret;
+}
+
static efi_status_t EFIAPI efi_cin_read_key_stroke(
struct efi_simple_input_interface *this,
struct efi_input_key *key)
@@ -421,14 +425,21 @@
ch = getc();
if (ch == cESC) {
- /* Escape Sequence */
+ /*
+ * Xterm Control Sequences
+ * https://www.xfree86.org/4.8.0/ctlseqs.html
+ */
ch = getc();
switch (ch) {
case cESC: /* ESC */
pressed_key.scan_code = 23;
break;
case 'O': /* F1 - F4 */
- pressed_key.scan_code = getc() - 'P' + 11;
+ ch = getc();
+ /* skip modifiers */
+ if (ch <= '9')
+ ch = getc();
+ pressed_key.scan_code = ch - 'P' + 11;
break;
case 'a'...'z':
ch = ch - 'a';
@@ -445,17 +456,51 @@
case 'H': /* Home */
pressed_key.scan_code = 5;
break;
- case '1': /* F5 - F8 */
- pressed_key.scan_code = getc() - '0' + 11;
- getc();
+ case '1':
+ ch = skip_modifiers(NULL);
+ switch (ch) {
+ case '1'...'5': /* F1 - F5 */
+ pressed_key.scan_code = ch - '1' + 11;
+ break;
+ case '7'...'9': /* F6 - F8 */
+ pressed_key.scan_code = ch - '7' + 16;
+ break;
+ case 'A'...'D': /* up, down right, left */
+ pressed_key.scan_code = ch - 'A' + 1;
+ break;
+ case 'F':
+ pressed_key.scan_code = 6; /* End */
+ break;
+ case 'H':
+ pressed_key.scan_code = 5; /* Home */
+ break;
+ }
break;
- case '2': /* F9 - F12 */
- pressed_key.scan_code = getc() - '0' + 19;
- getc();
+ case '2':
+ ch = skip_modifiers(NULL);
+ switch (ch) {
+ case '0'...'1': /* F9 - F10 */
+ pressed_key.scan_code = ch - '0' + 19;
+ break;
+ case '3'...'4': /* F11 - F12 */
+ pressed_key.scan_code = ch - '3' + 21;
+ break;
+ case '~': /* INS */
+ pressed_key.scan_code = 7;
+ break;
+ }
break;
case '3': /* DEL */
pressed_key.scan_code = 8;
- getc();
+ skip_modifiers(NULL);
+ break;
+ case '5': /* PG UP */
+ pressed_key.scan_code = 9;
+ skip_modifiers(NULL);
+ break;
+ case '6': /* PG DOWN */
+ pressed_key.scan_code = 10;
+ skip_modifiers(NULL);
break;
}
break;
@@ -464,7 +509,8 @@
/* Backspace */
ch = 0x08;
}
- pressed_key.unicode_char = ch;
+ if (!pressed_key.scan_code)
+ pressed_key.unicode_char = ch;
*key = pressed_key;
return EFI_EXIT(EFI_SUCCESS);
@@ -506,18 +552,10 @@
int efi_console_register(void)
{
efi_status_t r;
- struct efi_object *efi_console_control_obj;
struct efi_object *efi_console_output_obj;
struct efi_object *efi_console_input_obj;
/* Create handles */
- r = efi_create_handle((efi_handle_t *)&efi_console_control_obj);
- if (r != EFI_SUCCESS)
- goto out_of_memory;
- r = efi_add_protocol(efi_console_control_obj->handle,
- &efi_guid_console_control, &efi_console_control);
- if (r != EFI_SUCCESS)
- goto out_of_memory;
r = efi_create_handle((efi_handle_t *)&efi_console_output_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
@@ -534,14 +572,14 @@
goto out_of_memory;
/* Create console events */
- r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK,
- efi_key_notify, NULL, &efi_con_in.wait_for_key);
+ r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK, efi_key_notify,
+ NULL, NULL, &efi_con_in.wait_for_key);
if (r != EFI_SUCCESS) {
printf("ERROR: Failed to register WaitForKey event\n");
return r;
}
r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
- efi_console_timer_notify, NULL,
+ efi_console_timer_notify, NULL, NULL,
&console_timer_event);
if (r != EFI_SUCCESS) {
printf("ERROR: Failed to register console event\n");
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 3c735e6..e965f1d 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -66,6 +66,7 @@
return NULL;
}
+ memset(buf, 0, sz);
return buf;
}
@@ -746,10 +747,12 @@
return start;
}
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_NET
struct efi_device_path *efi_dp_from_eth(void)
{
+#ifndef CONFIG_DM_ETH
struct efi_device_path_mac_addr *ndp;
+#endif
void *buf, *start;
unsigned dpsize = 0;
@@ -759,8 +762,8 @@
dpsize += dp_size(eth_get_dev());
#else
dpsize += sizeof(ROOT);
-#endif
dpsize += sizeof(*ndp);
+#endif
start = buf = dp_alloc(dpsize + sizeof(END));
if (!buf)
@@ -771,14 +774,15 @@
#else
memcpy(buf, &ROOT, sizeof(ROOT));
buf += sizeof(ROOT);
-#endif
ndp = buf;
ndp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
ndp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR;
ndp->dp.length = sizeof(*ndp);
+ ndp->if_type = 1; /* Ethernet */
memcpy(ndp->mac.addr, eth_get_ethaddr(), ARP_HLEN);
buf = &ndp[1];
+#endif
*((struct efi_device_path *)buf) = END;
diff --git a/lib/efi_loader/efi_device_path_utilities.c b/lib/efi_loader/efi_device_path_utilities.c
new file mode 100644
index 0000000..bc97eee
--- /dev/null
+++ b/lib/efi_loader/efi_device_path_utilities.c
@@ -0,0 +1,89 @@
+/*
+ * EFI device path interface
+ *
+ * Copyright (c) 2017 Leif Lindholm
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+
+const efi_guid_t efi_guid_device_path_utilities_protocol =
+ EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID;
+
+static efi_uintn_t EFIAPI get_device_path_size(
+ const struct efi_device_path *device_path)
+{
+ efi_uintn_t sz = 0;
+
+ EFI_ENTRY("%p", device_path);
+ /* size includes the END node: */
+ if (device_path)
+ sz = efi_dp_size(device_path) + sizeof(struct efi_device_path);
+ return EFI_EXIT(sz);
+}
+
+static struct efi_device_path * EFIAPI duplicate_device_path(
+ const struct efi_device_path *device_path)
+{
+ EFI_ENTRY("%p", device_path);
+ return EFI_EXIT(efi_dp_dup(device_path));
+}
+
+static struct efi_device_path * EFIAPI append_device_path(
+ const struct efi_device_path *src1,
+ const struct efi_device_path *src2)
+{
+ EFI_ENTRY("%p, %p", src1, src2);
+ return EFI_EXIT(efi_dp_append(src1, src2));
+}
+
+static struct efi_device_path * EFIAPI append_device_node(
+ const struct efi_device_path *device_path,
+ const struct efi_device_path *device_node)
+{
+ EFI_ENTRY("%p, %p", device_path, device_node);
+ return EFI_EXIT(efi_dp_append_node(device_path, device_node));
+}
+
+static struct efi_device_path * EFIAPI append_device_path_instance(
+ const struct efi_device_path *device_path,
+ const struct efi_device_path *device_path_instance)
+{
+ EFI_ENTRY("%p, %p", device_path, device_path_instance);
+ return EFI_EXIT(NULL);
+}
+
+static struct efi_device_path * EFIAPI get_next_device_path_instance(
+ struct efi_device_path **device_path_instance,
+ efi_uintn_t *device_path_instance_size)
+{
+ EFI_ENTRY("%p, %p", device_path_instance, device_path_instance_size);
+ return EFI_EXIT(NULL);
+}
+
+static bool EFIAPI is_device_path_multi_instance(
+ const struct efi_device_path *device_path)
+{
+ EFI_ENTRY("%p", device_path);
+ return EFI_EXIT(false);
+}
+
+static struct efi_device_path * EFIAPI create_device_node(
+ uint8_t node_type, uint8_t node_sub_type, uint16_t node_length)
+{
+ EFI_ENTRY("%u, %u, %u", node_type, node_sub_type, node_length);
+ return EFI_EXIT(NULL);
+}
+
+const struct efi_device_path_utilities_protocol efi_device_path_utilities = {
+ .get_device_path_size = get_device_path_size,
+ .duplicate_device_path = duplicate_device_path,
+ .append_device_path = append_device_path,
+ .append_device_node = append_device_node,
+ .append_device_path_instance = append_device_path_instance,
+ .get_next_device_path_instance = get_next_device_path_instance,
+ .is_device_path_multi_instance = is_device_path_multi_instance,
+ .create_device_node = create_device_node,
+};
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 52a4e74..cec8347 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -12,6 +12,9 @@
#include <malloc.h>
#include <fs.h>
+/* GUID for file system information */
+const efi_guid_t efi_file_system_info_guid = EFI_FILE_SYSTEM_INFO_GUID;
+
struct file_system {
struct efi_simple_file_system_protocol base;
struct efi_device_path *dp;
@@ -314,29 +317,41 @@
}
static efi_status_t EFIAPI efi_file_read(struct efi_file_handle *file,
- u64 *buffer_size, void *buffer)
+ efi_uintn_t *buffer_size, void *buffer)
{
struct file_handle *fh = to_fh(file);
efi_status_t ret = EFI_SUCCESS;
+ u64 bs;
EFI_ENTRY("%p, %p, %p", file, buffer_size, buffer);
+ if (!buffer_size || !buffer) {
+ ret = EFI_INVALID_PARAMETER;
+ goto error;
+ }
+
if (set_blk_dev(fh)) {
ret = EFI_DEVICE_ERROR;
goto error;
}
+ bs = *buffer_size;
if (fh->isdir)
- ret = dir_read(fh, buffer_size, buffer);
+ ret = dir_read(fh, &bs, buffer);
else
- ret = file_read(fh, buffer_size, buffer);
+ ret = file_read(fh, &bs, buffer);
+ if (bs <= SIZE_MAX)
+ *buffer_size = bs;
+ else
+ *buffer_size = SIZE_MAX;
error:
return EFI_EXIT(ret);
}
static efi_status_t EFIAPI efi_file_write(struct efi_file_handle *file,
- u64 *buffer_size, void *buffer)
+ efi_uintn_t *buffer_size,
+ void *buffer)
{
struct file_handle *fh = to_fh(file);
efi_status_t ret = EFI_SUCCESS;
@@ -363,21 +378,27 @@
}
static efi_status_t EFIAPI efi_file_getpos(struct efi_file_handle *file,
- u64 *pos)
+ efi_uintn_t *pos)
{
struct file_handle *fh = to_fh(file);
+
EFI_ENTRY("%p, %p", file, pos);
- *pos = fh->offset;
- return EFI_EXIT(EFI_SUCCESS);
+
+ if (fh->offset <= SIZE_MAX) {
+ *pos = fh->offset;
+ return EFI_EXIT(EFI_SUCCESS);
+ } else {
+ return EFI_EXIT(EFI_DEVICE_ERROR);
+ }
}
static efi_status_t EFIAPI efi_file_setpos(struct efi_file_handle *file,
- u64 pos)
+ efi_uintn_t pos)
{
struct file_handle *fh = to_fh(file);
efi_status_t ret = EFI_SUCCESS;
- EFI_ENTRY("%p, %llu", file, pos);
+ EFI_ENTRY("%p, %zu", file, pos);
if (fh->isdir) {
if (pos != 0) {
@@ -411,7 +432,9 @@
}
static efi_status_t EFIAPI efi_file_getinfo(struct efi_file_handle *file,
- efi_guid_t *info_type, u64 *buffer_size, void *buffer)
+ const efi_guid_t *info_type,
+ efi_uintn_t *buffer_size,
+ void *buffer)
{
struct file_handle *fh = to_fh(file);
efi_status_t ret = EFI_SUCCESS;
@@ -452,6 +475,41 @@
info->attribute |= EFI_FILE_DIRECTORY;
ascii2unicode((u16 *)info->file_name, filename);
+ } else if (!guidcmp(info_type, &efi_file_system_info_guid)) {
+ struct efi_file_system_info *info = buffer;
+ disk_partition_t part;
+ efi_uintn_t required_size;
+ int r;
+
+ if (fh->fs->part >= 1)
+ r = part_get_info(fh->fs->desc, fh->fs->part, &part);
+ else
+ r = part_get_info_whole_disk(fh->fs->desc, &part);
+ if (r < 0) {
+ ret = EFI_DEVICE_ERROR;
+ goto error;
+ }
+ required_size = sizeof(info) + 2 *
+ (strlen((const char *)part.name) + 1);
+ if (*buffer_size < required_size) {
+ *buffer_size = required_size;
+ ret = EFI_BUFFER_TOO_SMALL;
+ goto error;
+ }
+
+ memset(info, 0, required_size);
+
+ info->size = required_size;
+ info->read_only = true;
+ info->volume_size = part.size * part.blksz;
+ info->free_space = 0;
+ info->block_size = part.blksz;
+ /*
+ * TODO: The volume label is not available in U-Boot.
+ * Use the partition name as substitute.
+ */
+ ascii2unicode((u16 *)info->volume_label,
+ (const char *)part.name);
} else {
ret = EFI_UNSUPPORTED;
}
@@ -461,9 +519,12 @@
}
static efi_status_t EFIAPI efi_file_setinfo(struct efi_file_handle *file,
- efi_guid_t *info_type, u64 buffer_size, void *buffer)
+ const efi_guid_t *info_type,
+ efi_uintn_t buffer_size,
+ void *buffer)
{
- EFI_ENTRY("%p, %p, %llu, %p", file, info_type, buffer_size, buffer);
+ EFI_ENTRY("%p, %p, %zu, %p", file, info_type, buffer_size, buffer);
+
return EFI_EXIT(EFI_UNSUPPORTED);
}
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index 3caddd5..363ccbb 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -56,27 +56,166 @@
return EFI_EXIT(EFI_SUCCESS);
}
-efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
- u32 operation, efi_uintn_t sx,
- efi_uintn_t sy, efi_uintn_t dx,
- efi_uintn_t dy, efi_uintn_t width,
- efi_uintn_t height, efi_uintn_t delta)
+static __always_inline struct efi_gop_pixel efi_vid16_to_blt_col(u16 vid)
+{
+ struct efi_gop_pixel blt = {
+ .reserved = 0,
+ };
+
+ blt.blue = (vid & 0x1f) << 3;
+ vid >>= 5;
+ blt.green = (vid & 0x3f) << 2;
+ vid >>= 6;
+ blt.red = (vid & 0x1f) << 3;
+ return blt;
+}
+
+static __always_inline u16 efi_blt_col_to_vid16(struct efi_gop_pixel *blt)
+{
+ return (u16)(blt->red >> 3) << 11 |
+ (u16)(blt->green >> 2) << 5 |
+ (u16)(blt->blue >> 3);
+}
+
+static __always_inline efi_status_t gop_blt_int(struct efi_gop *this,
+ struct efi_gop_pixel *bufferp,
+ u32 operation, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy,
+ efi_uintn_t width,
+ efi_uintn_t height,
+ efi_uintn_t delta,
+ efi_uintn_t vid_bpp)
{
struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops);
- int i, j, line_len16, line_len32;
- void *fb;
+ efi_uintn_t i, j, linelen, slineoff = 0, dlineoff, swidth, dwidth;
+ u32 *fb32 = gopobj->fb;
+ u16 *fb16 = gopobj->fb;
+ struct efi_gop_pixel *buffer = __builtin_assume_aligned(bufferp, 4);
- EFI_ENTRY("%p, %p, %u, %zu, %zu, %zu, %zu, %zu, %zu, %zu", this,
- buffer, operation, sx, sy, dx, dy, width, height, delta);
+ if (delta) {
+ /* Check for 4 byte alignment */
+ if (delta & 3)
+ return EFI_INVALID_PARAMETER;
+ linelen = delta >> 2;
+ } else {
+ linelen = width;
+ }
- if (operation != EFI_BLT_BUFFER_TO_VIDEO)
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ /* Check source rectangle */
+ switch (operation) {
+ case EFI_BLT_VIDEO_FILL:
+ break;
+ case EFI_BLT_BUFFER_TO_VIDEO:
+ if (sx + width > linelen)
+ return EFI_INVALID_PARAMETER;
+ break;
+ case EFI_BLT_VIDEO_TO_BLT_BUFFER:
+ case EFI_BLT_VIDEO_TO_VIDEO:
+ if (sx + width > gopobj->info.width ||
+ sy + height > gopobj->info.height)
+ return EFI_INVALID_PARAMETER;
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
- fb = gopobj->fb;
- line_len16 = gopobj->info.width * sizeof(u16);
- line_len32 = gopobj->info.width * sizeof(u32);
+ /* Check destination rectangle */
+ switch (operation) {
+ case EFI_BLT_VIDEO_FILL:
+ case EFI_BLT_BUFFER_TO_VIDEO:
+ case EFI_BLT_VIDEO_TO_VIDEO:
+ if (dx + width > gopobj->info.width ||
+ dy + height > gopobj->info.height)
+ return EFI_INVALID_PARAMETER;
+ break;
+ case EFI_BLT_VIDEO_TO_BLT_BUFFER:
+ if (dx + width > linelen)
+ return EFI_INVALID_PARAMETER;
+ break;
+ }
- /* Copy the contents line by line */
+ /* Calculate line width */
+ switch (operation) {
+ case EFI_BLT_BUFFER_TO_VIDEO:
+ swidth = linelen;
+ break;
+ case EFI_BLT_VIDEO_TO_BLT_BUFFER:
+ case EFI_BLT_VIDEO_TO_VIDEO:
+ swidth = gopobj->info.width;
+ if (!vid_bpp)
+ return EFI_UNSUPPORTED;
+ break;
+ case EFI_BLT_VIDEO_FILL:
+ swidth = 0;
+ break;
+ }
+
+ switch (operation) {
+ case EFI_BLT_BUFFER_TO_VIDEO:
+ case EFI_BLT_VIDEO_FILL:
+ case EFI_BLT_VIDEO_TO_VIDEO:
+ dwidth = gopobj->info.width;
+ if (!vid_bpp)
+ return EFI_UNSUPPORTED;
+ break;
+ case EFI_BLT_VIDEO_TO_BLT_BUFFER:
+ dwidth = linelen;
+ break;
+ }
+
+ slineoff = swidth * sy;
+ dlineoff = dwidth * dy;
+ for (i = 0; i < height; i++) {
+ for (j = 0; j < width; j++) {
+ struct efi_gop_pixel pix;
+
+ /* Read source pixel */
+ switch (operation) {
+ case EFI_BLT_VIDEO_FILL:
+ pix = *buffer;
+ break;
+ case EFI_BLT_BUFFER_TO_VIDEO:
+ pix = buffer[slineoff + j + sx];
+ break;
+ case EFI_BLT_VIDEO_TO_BLT_BUFFER:
+ case EFI_BLT_VIDEO_TO_VIDEO:
+ if (vid_bpp == 32)
+ pix = *(struct efi_gop_pixel *)&fb32[
+ slineoff + j + sx];
+ else
+ pix = efi_vid16_to_blt_col(fb16[
+ slineoff + j + sx]);
+ break;
+ }
+
+ /* Write destination pixel */
+ switch (operation) {
+ case EFI_BLT_VIDEO_TO_BLT_BUFFER:
+ buffer[dlineoff + j + dx] = pix;
+ break;
+ case EFI_BLT_BUFFER_TO_VIDEO:
+ case EFI_BLT_VIDEO_FILL:
+ case EFI_BLT_VIDEO_TO_VIDEO:
+ if (vid_bpp == 32)
+ fb32[dlineoff + j + dx] = *(u32 *)&pix;
+ else
+ fb16[dlineoff + j + dx] =
+ efi_blt_col_to_vid16(&pix);
+ break;
+ }
+ }
+ slineoff += swidth;
+ dlineoff += dwidth;
+ }
+
+ return EFI_SUCCESS;
+}
+
+static efi_uintn_t gop_get_bpp(struct efi_gop *this)
+{
+ struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops);
+ efi_uintn_t vid_bpp = 0;
switch (gopobj->bpix) {
#ifdef CONFIG_DM_VIDEO
@@ -84,38 +223,151 @@
#else
case LCD_COLOR32:
#endif
- for (i = 0; i < height; i++) {
- u32 *dest = fb + ((i + dy) * line_len32) +
- (dx * sizeof(u32));
- u32 *src = buffer + ((i + sy) * line_len32) +
- (sx * sizeof(u32));
-
- /* Same color format, just memcpy */
- memcpy(dest, src, width * sizeof(u32));
- }
+ vid_bpp = 32;
break;
#ifdef CONFIG_DM_VIDEO
case VIDEO_BPP16:
#else
case LCD_COLOR16:
#endif
- for (i = 0; i < height; i++) {
- u16 *dest = fb + ((i + dy) * line_len16) +
- (dx * sizeof(u16));
- u32 *src = buffer + ((i + sy) * line_len32) +
- (sx * sizeof(u32));
-
- /* Convert from rgb888 to rgb565 */
- for (j = 0; j < width; j++) {
- u32 rgb888 = src[j];
- dest[j] = ((((rgb888 >> (16 + 3)) & 0x1f) << 11) |
- (((rgb888 >> (8 + 2)) & 0x3f) << 5) |
- (((rgb888 >> (0 + 3)) & 0x1f) << 0));
- }
- }
+ vid_bpp = 16;
break;
}
+ return vid_bpp;
+}
+
+/*
+ * Gcc can't optimize our BLT function well, but we need to make sure that
+ * our 2-dimensional loop gets executed very quickly, otherwise the system
+ * will feel slow.
+ *
+ * By manually putting all obvious branch targets into functions which call
+ * our generic blt function with constants, the compiler can successfully
+ * optimize for speed.
+ */
+static efi_status_t gop_blt_video_fill(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta,
+ efi_uintn_t vid_bpp)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_VIDEO_FILL, sx, sy, dx,
+ dy, width, height, delta, vid_bpp);
+}
+
+static efi_status_t gop_blt_buf_to_vid16(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx,
+ dy, width, height, delta, 16);
+}
+
+static efi_status_t gop_blt_buf_to_vid32(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx,
+ dy, width, height, delta, 32);
+}
+
+static efi_status_t gop_blt_vid_to_vid(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta,
+ efi_uintn_t vid_bpp)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_VIDEO_TO_VIDEO, sx, sy, dx,
+ dy, width, height, delta, vid_bpp);
+}
+
+static efi_status_t gop_blt_vid_to_buf(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta,
+ efi_uintn_t vid_bpp)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_VIDEO_TO_BLT_BUFFER, sx, sy,
+ dx, dy, width, height, delta, vid_bpp);
+}
+
+/*
+ * Copy rectangle.
+ *
+ * This function implements the Blt service of the EFI_GRAPHICS_OUTPUT_PROTOCOL.
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @this: EFI_GRAPHICS_OUTPUT_PROTOCOL
+ * @buffer: pixel buffer
+ * @sx: source x-coordinate
+ * @sy: source y-coordinate
+ * @dx: destination x-coordinate
+ * @dy: destination y-coordinate
+ * @width: width of rectangle
+ * @height: height of rectangle
+ * @delta: length in bytes of a line in the pixel buffer (optional)
+ * @return: status code
+ */
+efi_status_t EFIAPI gop_blt(struct efi_gop *this, struct efi_gop_pixel *buffer,
+ u32 operation, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta)
+{
+ efi_status_t ret = EFI_INVALID_PARAMETER;
+ efi_uintn_t vid_bpp;
+
+ EFI_ENTRY("%p, %p, %u, %zu, %zu, %zu, %zu, %zu, %zu, %zu", this,
+ buffer, operation, sx, sy, dx, dy, width, height, delta);
+
+ vid_bpp = gop_get_bpp(this);
+
+ /* Allow for compiler optimization */
+ switch (operation) {
+ case EFI_BLT_VIDEO_FILL:
+ ret = gop_blt_video_fill(this, buffer, operation, sx, sy, dx,
+ dy, width, height, delta, vid_bpp);
+ break;
+ case EFI_BLT_BUFFER_TO_VIDEO:
+ /* This needs to be super-fast, so duplicate for 16/32bpp */
+ if (vid_bpp == 32)
+ ret = gop_blt_buf_to_vid32(this, buffer, operation, sx,
+ sy, dx, dy, width, height,
+ delta);
+ else
+ ret = gop_blt_buf_to_vid16(this, buffer, operation, sx,
+ sy, dx, dy, width, height,
+ delta);
+ break;
+ case EFI_BLT_VIDEO_TO_VIDEO:
+ ret = gop_blt_vid_to_vid(this, buffer, operation, sx, sy, dx,
+ dy, width, height, delta, vid_bpp);
+ break;
+ case EFI_BLT_VIDEO_TO_BLT_BUFFER:
+ ret = gop_blt_vid_to_buf(this, buffer, operation, sx, sy, dx,
+ dy, width, height, delta, vid_bpp);
+ break;
+ default:
+ ret = EFI_UNSUPPORTED;
+ }
+
+ if (ret != EFI_SUCCESS)
+ return EFI_EXIT(ret);
+
#ifdef CONFIG_DM_VIDEO
video_sync_all();
#else
@@ -125,8 +377,13 @@
return EFI_EXIT(EFI_SUCCESS);
}
-/* This gets called from do_bootefi_exec(). */
-int efi_gop_register(void)
+/*
+ * Install graphical output protocol.
+ *
+ * If no supported video device exists this is not considered as an
+ * error.
+ */
+efi_status_t efi_gop_register(void)
{
struct efi_gop_obj *gopobj;
u32 bpix, col, row;
@@ -136,12 +393,15 @@
#ifdef CONFIG_DM_VIDEO
struct udevice *vdev;
+ struct video_priv *priv;
/* We only support a single video output device for now */
- if (uclass_first_device(UCLASS_VIDEO, &vdev) || !vdev)
- return -1;
+ if (uclass_first_device(UCLASS_VIDEO, &vdev) || !vdev) {
+ debug("WARNING: No video device\n");
+ return EFI_SUCCESS;
+ }
- struct video_priv *priv = dev_get_uclass_priv(vdev);
+ priv = dev_get_uclass_priv(vdev);
bpix = priv->bpix;
col = video_get_xsize(vdev);
row = video_get_ysize(vdev);
@@ -170,13 +430,14 @@
break;
default:
/* So far, we only work in 16 or 32 bit mode */
- return -1;
+ debug("WARNING: Unsupported video mode\n");
+ return EFI_SUCCESS;
}
gopobj = calloc(1, sizeof(*gopobj));
if (!gopobj) {
printf("ERROR: Out of memory\n");
- return 1;
+ return EFI_OUT_OF_RESOURCES;
}
/* Hook up to the device list */
@@ -186,8 +447,8 @@
ret = efi_add_protocol(gopobj->parent.handle, &efi_gop_guid,
&gopobj->ops);
if (ret != EFI_SUCCESS) {
- printf("ERROR: Out of memory\n");
- return 1;
+ printf("ERROR: Failure adding gop protocol\n");
+ return ret;
}
gopobj->ops.query_mode = gop_query_mode;
gopobj->ops.set_mode = gop_set_mode;
@@ -199,10 +460,11 @@
gopobj->mode.info_size = sizeof(gopobj->info);
#ifdef CONFIG_DM_VIDEO
- if (bpix == VIDEO_BPP32) {
+ if (bpix == VIDEO_BPP32)
#else
- if (bpix == LCD_COLOR32) {
+ if (bpix == LCD_COLOR32)
#endif
+ {
/* With 32bit color space we can directly expose the fb */
gopobj->mode.fb_base = fb_base;
gopobj->mode.fb_size = fb_size;
@@ -217,5 +479,5 @@
gopobj->bpix = bpix;
gopobj->fb = fb;
- return 0;
+ return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index cac64ba..d5fbba3 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -22,6 +22,76 @@
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID;
+static int machines[] = {
+#if defined(CONFIG_ARM64)
+ IMAGE_FILE_MACHINE_ARM64,
+#elif defined(CONFIG_ARM)
+ IMAGE_FILE_MACHINE_ARM,
+ IMAGE_FILE_MACHINE_THUMB,
+ IMAGE_FILE_MACHINE_ARMNT,
+#endif
+
+#if defined(CONFIG_X86_64)
+ IMAGE_FILE_MACHINE_AMD64,
+#elif defined(CONFIG_X86)
+ IMAGE_FILE_MACHINE_I386,
+#endif
+
+#if defined(CONFIG_CPU_RISCV_32)
+ IMAGE_FILE_MACHINE_RISCV32,
+#endif
+
+#if defined(CONFIG_CPU_RISCV_64)
+ IMAGE_FILE_MACHINE_RISCV64,
+#endif
+ 0 };
+
+/*
+ * Print information about a loaded image.
+ *
+ * If the program counter is located within the image the offset to the base
+ * address is shown.
+ *
+ * @image: loaded image
+ * @pc: program counter (use NULL to suppress offset output)
+ * @return: status code
+ */
+efi_status_t efi_print_image_info(struct efi_loaded_image *image, void *pc)
+{
+ if (!image)
+ return EFI_INVALID_PARAMETER;
+ printf("UEFI image");
+ printf(" [0x%p:0x%p]",
+ image->reloc_base, image->reloc_base + image->reloc_size - 1);
+ if (pc && pc >= image->reloc_base &&
+ pc < image->reloc_base + image->reloc_size)
+ printf(" pc=0x%zx", pc - image->reloc_base);
+ if (image->file_path)
+ printf(" '%pD'", image->file_path);
+ printf("\n");
+ return EFI_SUCCESS;
+}
+
+/*
+ * Print information about all loaded images.
+ *
+ * @pc: program counter (use NULL to suppress offset output)
+ */
+void efi_print_image_infos(void *pc)
+{
+ struct efi_object *efiobj;
+ struct efi_handler *handler;
+
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ if (!guidcmp(handler->guid, &efi_guid_loaded_image)) {
+ efi_print_image_info(
+ handler->protocol_interface, pc);
+ }
+ }
+ }
+}
+
static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
unsigned long rel_size, void *efi_reloc)
{
@@ -126,14 +196,7 @@
void *entry;
uint64_t image_size;
unsigned long virt_size = 0;
- bool can_run_nt64 = true;
- bool can_run_nt32 = true;
-
-#if defined(CONFIG_ARM64)
- can_run_nt32 = false;
-#elif defined(CONFIG_ARM)
- can_run_nt64 = false;
-#endif
+ int supported = 0;
dos = efi;
if (dos->e_magic != IMAGE_DOS_SIGNATURE) {
@@ -147,6 +210,18 @@
return NULL;
}
+ for (i = 0; machines[i]; i++)
+ if (machines[i] == nt->FileHeader.Machine) {
+ supported = 1;
+ break;
+ }
+
+ if (!supported) {
+ printf("%s: Machine type 0x%04x is not supported\n",
+ __func__, nt->FileHeader.Machine);
+ return NULL;
+ }
+
/* Calculate upper virtual address boundary */
num_sections = nt->FileHeader.NumberOfSections;
sections = (void *)&nt->OptionalHeader +
@@ -159,8 +234,7 @@
}
/* Read 32/64bit specific header bits */
- if (can_run_nt64 &&
- (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC)) {
+ if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC) {
IMAGE_NT_HEADERS64 *nt64 = (void *)nt;
IMAGE_OPTIONAL_HEADER64 *opt = &nt64->OptionalHeader;
image_size = opt->SizeOfImage;
@@ -175,8 +249,8 @@
entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
- } else if (can_run_nt32 &&
- (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC)) {
+ virt_size = ALIGN(virt_size, opt->SectionAlignment);
+ } else if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC) {
IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader;
image_size = opt->SizeOfImage;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
@@ -190,6 +264,7 @@
entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
+ virt_size = ALIGN(virt_size, opt->SectionAlignment);
} else {
printf("%s: Invalid optional header magic %x\n", __func__,
nt->OptionalHeader.Magic);
@@ -221,6 +296,8 @@
/* Populate the loaded image interface bits */
loaded_image_info->image_base = efi;
loaded_image_info->image_size = image_size;
+ loaded_image_info->reloc_base = efi_reloc;
+ loaded_image_info->reloc_size = virt_size;
return entry;
}
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index ff0edf3..95f9ff0 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -8,12 +8,11 @@
#include <common.h>
#include <efi_loader.h>
-#include <malloc.h>
-#include <asm/global_data.h>
-#include <linux/libfdt_env.h>
-#include <linux/list_sort.h>
#include <inttypes.h>
+#include <malloc.h>
#include <watchdog.h>
+#include <asm/global_data.h>
+#include <linux/list_sort.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -292,7 +291,7 @@
uint64_t addr;
switch (type) {
- case 0:
+ case EFI_ALLOCATE_ANY_PAGES:
/* Any page */
addr = efi_find_free_memory(len, gd->start_addr_sp);
if (!addr) {
@@ -300,7 +299,7 @@
break;
}
break;
- case 1:
+ case EFI_ALLOCATE_MAX_ADDRESS:
/* Max address */
addr = efi_find_free_memory(len, *memory);
if (!addr) {
@@ -308,7 +307,7 @@
break;
}
break;
- case 2:
+ case EFI_ALLOCATE_ADDRESS:
/* Exact address, reserve it. The addr is already in *memory. */
addr = *memory;
break;
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index 8c5d5b4..9afe76c 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -54,14 +54,46 @@
return EFI_EXIT(EFI_SUCCESS);
}
+/*
+ * Initialize network adapter and allocate transmit and receive buffers.
+ *
+ * This function implements the Initialize service of the
+ * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @extra_rx: extra receive buffer to be allocated
+ * @extra_tx: extra transmit buffer to be allocated
+ * @return: status code
+ */
static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
ulong extra_rx, ulong extra_tx)
{
+ int ret;
+ efi_status_t r = EFI_SUCCESS;
+
EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx);
- eth_init();
+ if (!this) {
+ r = EFI_INVALID_PARAMETER;
+ goto error;
+ }
- return EFI_EXIT(EFI_SUCCESS);
+ /* Setup packet buffers */
+ net_init();
+ /* Disable hardware and put it into the reset state */
+ eth_halt();
+ /* Set current device according to environment variables */
+ eth_set_current();
+ /* Get hardware ready for send and receive operations */
+ ret = eth_init();
+ if (ret < 0) {
+ eth_halt();
+ r = EFI_DEVICE_ERROR;
+ }
+
+error:
+ return EFI_EXIT(r);
}
static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this,
@@ -280,20 +312,22 @@
}
/* This gets called from do_bootefi_exec(). */
-int efi_net_register(void)
+efi_status_t efi_net_register(void)
{
struct efi_net_obj *netobj;
efi_status_t r;
if (!eth_get_dev()) {
/* No eth device active, don't expose any */
- return 0;
+ return EFI_SUCCESS;
}
/* We only expose the "active" eth device, so one is enough */
netobj = calloc(1, sizeof(*netobj));
- if (!netobj)
- goto out_of_memory;
+ if (!netobj) {
+ printf("ERROR: Out of memory\n");
+ return EFI_OUT_OF_RESOURCES;
+ }
/* Hook net up to the device list */
efi_add_handle(&netobj->parent);
@@ -302,15 +336,15 @@
r = efi_add_protocol(netobj->parent.handle, &efi_net_guid,
&netobj->net);
if (r != EFI_SUCCESS)
- goto out_of_memory;
+ goto failure_to_add_protocol;
r = efi_add_protocol(netobj->parent.handle, &efi_guid_device_path,
efi_dp_from_eth());
if (r != EFI_SUCCESS)
- goto out_of_memory;
+ goto failure_to_add_protocol;
r = efi_add_protocol(netobj->parent.handle, &efi_pxe_guid,
&netobj->pxe);
if (r != EFI_SUCCESS)
- goto out_of_memory;
+ goto failure_to_add_protocol;
netobj->net.revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
netobj->net.start = efi_net_start;
netobj->net.stop = efi_net_stop;
@@ -339,7 +373,7 @@
* Create WaitForPacket event.
*/
r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK,
- efi_network_timer_notify, NULL,
+ efi_network_timer_notify, NULL, NULL,
&wait_for_packet);
if (r != EFI_SUCCESS) {
printf("ERROR: Failed to register network event\n");
@@ -351,9 +385,11 @@
*
* The notification function is used to check if a new network packet
* has been received.
+ *
+ * iPXE is running at TPL_CALLBACK most of the time. Use a higher TPL.
*/
- r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
- efi_network_timer_notify, NULL,
+ r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
+ efi_network_timer_notify, NULL, NULL,
&network_timer_event);
if (r != EFI_SUCCESS) {
printf("ERROR: Failed to register network event\n");
@@ -366,8 +402,8 @@
return r;
}
- return 0;
-out_of_memory:
- printf("ERROR: Out of memory\n");
- return 1;
+ return EFI_SUCCESS;
+failure_to_add_protocol:
+ printf("ERROR: Failure to add protocol\n");
+ return r;
}
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index ccb4fc6..8558124 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -74,12 +74,24 @@
efi_status_t reset_status,
unsigned long data_size, void *reset_data)
{
+ struct efi_event *evt;
+
EFI_ENTRY("%d %lx %lx %p", reset_type, reset_status, data_size,
reset_data);
+ /* Notify reset */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_reset_system)) {
+ efi_signal_event(evt, false);
+ break;
+ }
+ }
switch (reset_type) {
case EFI_RESET_COLD:
case EFI_RESET_WARM:
+ case EFI_RESET_PLATFORM_SPECIFIC:
do_reset(NULL, 0, 0, NULL);
break;
case EFI_RESET_SHUTDOWN:
@@ -134,8 +146,9 @@
while (1) { }
}
-void __weak efi_reset_system_init(void)
+efi_status_t __weak efi_reset_system_init(void)
{
+ return EFI_SUCCESS;
}
efi_status_t __weak __efi_runtime EFIAPI efi_get_time(
@@ -146,8 +159,9 @@
return EFI_DEVICE_ERROR;
}
-void __weak efi_get_time_init(void)
+efi_status_t __weak efi_get_time_init(void)
{
+ return EFI_SUCCESS;
}
struct efi_runtime_detach_list_struct {
@@ -332,18 +346,26 @@
return EFI_EXIT(EFI_INVALID_PARAMETER);
}
-void efi_add_runtime_mmio(void *mmio_ptr, u64 len)
+efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len)
{
struct efi_runtime_mmio_list *newmmio;
-
u64 pages = (len + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
- efi_add_memory_map(*(uintptr_t *)mmio_ptr, pages, EFI_MMAP_IO, false);
+ uint64_t addr = *(uintptr_t *)mmio_ptr;
+ uint64_t retaddr;
+
+ retaddr = efi_add_memory_map(addr, pages, EFI_MMAP_IO, false);
+ if (retaddr != addr)
+ return EFI_OUT_OF_RESOURCES;
newmmio = calloc(1, sizeof(*newmmio));
+ if (!newmmio)
+ return EFI_OUT_OF_RESOURCES;
newmmio->ptr = mmio_ptr;
newmmio->paddr = *(uintptr_t *)mmio_ptr;
newmmio->len = len;
list_add_tail(&newmmio->link, &efi_runtime_mmio);
+
+ return EFI_SUCCESS;
}
/*
diff --git a/lib/efi_loader/efi_smbios.c b/lib/efi_loader/efi_smbios.c
index ac412e7..62e9697 100644
--- a/lib/efi_loader/efi_smbios.c
+++ b/lib/efi_loader/efi_smbios.c
@@ -13,20 +13,27 @@
static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
-void efi_smbios_register(void)
+/*
+ * Install the SMBIOS table as a configuration table.
+ *
+ * @return status code
+ */
+efi_status_t efi_smbios_register(void)
{
/* Map within the low 32 bits, to allow for 32bit SMBIOS tables */
- uint64_t dmi = 0xffffffff;
- /* Reserve 4kb for SMBIOS */
- uint64_t pages = 1;
- int memtype = EFI_RUNTIME_SERVICES_DATA;
+ u64 dmi = U32_MAX;
+ efi_status_t ret;
- if (efi_allocate_pages(1, memtype, pages, &dmi) != EFI_SUCCESS)
- return;
+ /* Reserve 4kiB page for SMBIOS */
+ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RUNTIME_SERVICES_DATA, 1, &dmi);
+ if (ret != EFI_SUCCESS)
+ return ret;
/* Generate SMBIOS tables */
write_smbios_table(dmi);
/* And expose them to our EFI payload */
- efi_install_configuration_table(&smbios_guid, (void*)(uintptr_t)dmi);
+ return efi_install_configuration_table(&smbios_guid,
+ (void *)(uintptr_t)dmi);
}
diff --git a/lib/efi_loader/efi_watchdog.c b/lib/efi_loader/efi_watchdog.c
index 35a45de..d12e51d 100644
--- a/lib/efi_loader/efi_watchdog.c
+++ b/lib/efi_loader/efi_watchdog.c
@@ -59,7 +59,7 @@
*
* This function is called by efi_init_obj_list()
*/
-int efi_watchdog_register(void)
+efi_status_t efi_watchdog_register(void)
{
efi_status_t r;
@@ -67,7 +67,7 @@
* Create a timer event.
*/
r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
- efi_watchdog_timer_notify, NULL,
+ efi_watchdog_timer_notify, NULL, NULL,
&watchdog_timer_event);
if (r != EFI_SUCCESS) {
printf("ERROR: Failed to register watchdog event\n");
@@ -85,5 +85,5 @@
printf("ERROR: Failed to set watchdog timer\n");
return r;
}
- return 0;
+ return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c
index 1ec0179..6c539ba 100644
--- a/lib/efi_loader/helloworld.c
+++ b/lib/efi_loader/helloworld.c
@@ -46,9 +46,27 @@
struct efi_loaded_image *loaded_image;
efi_status_t ret;
efi_uintn_t i;
+ u16 rev[] = L"0.0.0";
con_out->output_string(con_out, L"Hello, world!\n");
+ /* Print the revision number */
+ rev[0] = (systable->hdr.revision >> 16) + '0';
+ rev[4] = systable->hdr.revision & 0xffff;
+ for (; rev[4] >= 10;) {
+ rev[4] -= 10;
+ ++rev[2];
+ }
+ /* Third digit is only to be shown if non-zero */
+ if (rev[4])
+ rev[4] += '0';
+ else
+ rev[3] = 0;
+
+ con_out->output_string(con_out, L"Running on UEFI ");
+ con_out->output_string(con_out, rev);
+ con_out->output_string(con_out, L"\n");
+
/* Get the loaded image protocol */
ret = boottime->handle_protocol(handle, &loaded_image_guid,
(void **)&loaded_image);
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index c4bdbdf..31b444f 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -14,14 +14,18 @@
obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \
efi_selftest.o \
+efi_selftest_bitblt.o \
efi_selftest_controllers.o \
efi_selftest_console.o \
efi_selftest_devicepath.o \
efi_selftest_events.o \
+efi_selftest_event_groups.o \
efi_selftest_exitbootservices.o \
+efi_selftest_fdt.o \
efi_selftest_gop.o \
efi_selftest_manageprotocols.o \
efi_selftest_snp.o \
+efi_selftest_textinput.o \
efi_selftest_textoutput.o \
efi_selftest_tpl.o \
efi_selftest_util.o \
diff --git a/lib/efi_selftest/efi_selftest_bitblt.c b/lib/efi_selftest/efi_selftest_bitblt.c
new file mode 100644
index 0000000..0fb76cc7
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_bitblt.c
@@ -0,0 +1,311 @@
+/*
+ * efi_selftest_bitblt
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Test the block image transfer in the graphical output protocol.
+ * An animated submarine is shown.
+ */
+
+#include <efi_selftest.h>
+
+#define WIDTH 200
+#define HEIGHT 120
+#define DEPTH 60
+
+static const struct efi_gop_pixel BLACK = { 0, 0, 0, 0};
+static const struct efi_gop_pixel RED = { 0, 0, 255, 0};
+static const struct efi_gop_pixel ORANGE = { 0, 128, 255, 0};
+static const struct efi_gop_pixel YELLOW = { 0, 255, 255, 0};
+static const struct efi_gop_pixel GREEN = { 0, 255, 0, 0};
+static const struct efi_gop_pixel DARK_BLUE = {128, 0, 0, 0};
+static const struct efi_gop_pixel LIGHT_BLUE = {255, 192, 192, 0};
+
+static struct efi_boot_services *boottime;
+static efi_guid_t efi_gop_guid = EFI_GOP_GUID;
+static struct efi_gop *gop;
+static struct efi_gop_pixel *bitmap;
+static struct efi_event *event;
+static efi_uintn_t xpos;
+
+static void ellipse(efi_uintn_t x, efi_uintn_t y,
+ efi_uintn_t x0, efi_uintn_t y0,
+ efi_uintn_t x1, efi_uintn_t y1,
+ const struct efi_gop_pixel col, struct efi_gop_pixel *pix)
+{
+ efi_uintn_t xm = x0 + x1;
+ efi_uintn_t ym = y0 + y1;
+ efi_uintn_t dx = x1 - x0 + 1;
+ efi_uintn_t dy = y1 - y0 + 1;
+
+ if (dy * dy * (2 * x - xm) * (2 * x - xm) +
+ dx * dx * (2 * y - ym) * (2 * y - ym) <= dx * dx * dy * dy)
+ *pix = col;
+}
+
+static void rectangle(efi_uintn_t x, efi_uintn_t y,
+ efi_uintn_t x0, efi_uintn_t y0,
+ efi_uintn_t x1, efi_uintn_t y1,
+ const struct efi_gop_pixel col, struct efi_gop_pixel *pix)
+{
+ if (x >= x0 && y >= y0 && x <= x1 && y <= y1)
+ *pix = col;
+}
+
+/*
+ * Notification function, copies image to video.
+ * The position is incremented in each call.
+ *
+ * @event notified event
+ * @context pointer to the notification count
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+ efi_uintn_t *pos = context;
+ efi_uintn_t dx, sx, width;
+
+ if (!pos)
+ return;
+
+ /* Increment position */
+ *pos += 5;
+ if (*pos >= WIDTH + gop->mode->info->width)
+ *pos = 0;
+
+ width = WIDTH;
+ dx = *pos - WIDTH;
+ sx = 0;
+ if (*pos >= gop->mode->info->width) {
+ width = WIDTH + gop->mode->info->width - *pos;
+ } else if (*pos < WIDTH) {
+ dx = 0;
+ sx = WIDTH - *pos;
+ width = *pos;
+ }
+
+ /* Copy image to video */
+ gop->blt(gop, bitmap, EFI_BLT_BUFFER_TO_VIDEO, sx, 0, dx, DEPTH,
+ width, HEIGHT, WIDTH * sizeof(struct efi_gop_pixel));
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ struct efi_gop_pixel pix;
+ efi_uintn_t x, y;
+
+ boottime = systable->boottime;
+
+ /* Create event */
+ ret = boottime->create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK, notify, (void *)&xpos,
+ &event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not create event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Get graphical output protocol */
+ ret = boottime->locate_protocol(&efi_gop_guid, NULL, (void **)&gop);
+ if (ret != EFI_SUCCESS) {
+ gop = NULL;
+ efi_st_printf("Graphical output protocol is not available.\n");
+ return EFI_ST_SUCCESS;
+ }
+
+ /* Prepare image of submarine */
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ sizeof(struct efi_gop_pixel) *
+ WIDTH * HEIGHT, (void **)&bitmap);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return EFI_ST_FAILURE;
+ }
+ for (y = 0; y < HEIGHT; ++y) {
+ for (x = 0; x < WIDTH; ++x) {
+ pix = DARK_BLUE;
+
+ /* Propeller */
+ ellipse(x, y, 35, 55, 43, 75, BLACK, &pix);
+ ellipse(x, y, 36, 56, 42, 74, LIGHT_BLUE, &pix);
+
+ ellipse(x, y, 35, 75, 43, 95, BLACK, &pix);
+ ellipse(x, y, 36, 76, 42, 94, LIGHT_BLUE, &pix);
+
+ /* Shaft */
+ rectangle(x, y, 35, 73, 100, 77, BLACK, &pix);
+
+ /* Periscope */
+ ellipse(x, y, 120, 10, 160, 50, BLACK, &pix);
+ ellipse(x, y, 121, 11, 159, 59, YELLOW, &pix);
+ ellipse(x, y, 130, 20, 150, 40, BLACK, &pix);
+ ellipse(x, y, 131, 21, 149, 49, DARK_BLUE, &pix);
+ rectangle(x, y, 135, 10, 160, 50, DARK_BLUE, &pix);
+ ellipse(x, y, 132, 10, 138, 20, BLACK, &pix);
+ ellipse(x, y, 133, 11, 139, 19, RED, &pix);
+
+ /* Rudder */
+ ellipse(x, y, 45, 40, 75, 70, BLACK, &pix);
+ ellipse(x, y, 46, 41, 74, 69, ORANGE, &pix);
+ ellipse(x, y, 45, 80, 75, 109, BLACK, &pix);
+ ellipse(x, y, 46, 81, 74, 108, RED, &pix);
+
+ /* Bridge */
+ ellipse(x, y, 100, 30, 120, 50, BLACK, &pix);
+ ellipse(x, y, 101, 31, 119, 49, GREEN, &pix);
+ ellipse(x, y, 140, 30, 160, 50, BLACK, &pix);
+ ellipse(x, y, 141, 31, 159, 49, GREEN, &pix);
+ rectangle(x, y, 110, 30, 150, 50, BLACK, &pix);
+ rectangle(x, y, 110, 31, 150, 50, GREEN, &pix);
+
+ /* Hull */
+ ellipse(x, y, 50, 40, 199, 109, BLACK, &pix);
+ ellipse(x, y, 51, 41, 198, 108, LIGHT_BLUE, &pix);
+
+ /* Port holes */
+ ellipse(x, y, 79, 57, 109, 82, BLACK, &pix);
+ ellipse(x, y, 80, 58, 108, 81, LIGHT_BLUE, &pix);
+ ellipse(x, y, 83, 61, 105, 78, BLACK, &pix);
+ ellipse(x, y, 84, 62, 104, 77, YELLOW, &pix);
+ /*
+ * This port hole is created by copying
+ * ellipse(x, y, 119, 57, 149, 82, BLACK, &pix);
+ * ellipse(x, y, 120, 58, 148, 81, LIGHT_BLUE, &pix);
+ * ellipse(x, y, 123, 61, 145, 78, BLACK, &pix);
+ * ellipse(x, y, 124, 62, 144, 77, YELLOW, &pix);
+ */
+ ellipse(x, y, 159, 57, 189, 82, BLACK, &pix);
+ ellipse(x, y, 160, 58, 188, 81, LIGHT_BLUE, &pix);
+ ellipse(x, y, 163, 61, 185, 78, BLACK, &pix);
+ ellipse(x, y, 164, 62, 184, 77, YELLOW, &pix);
+
+ bitmap[WIDTH * y + x] = pix;
+ }
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t ret;
+
+ if (bitmap) {
+ ret = boottime->free_pool(bitmap);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (event) {
+ ret = boottime->close_event(event);
+ event = NULL;
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not close event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ u32 max_mode;
+ efi_status_t ret;
+ struct efi_gop_mode_info *info;
+
+ if (!gop)
+ return EFI_ST_SUCCESS;
+
+ if (!gop->mode) {
+ efi_st_error("EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE missing\n");
+ return EFI_ST_FAILURE;
+ }
+ info = gop->mode->info;
+ max_mode = gop->mode->max_mode;
+ if (!max_mode) {
+ efi_st_error("No graphical mode available\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Fill background */
+ ret = gop->blt(gop, bitmap, EFI_BLT_VIDEO_FILL, 0, 0, 0, 0,
+ info->width, info->height, 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("EFI_BLT_VIDEO_FILL failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Copy image to video */
+ ret = gop->blt(gop, bitmap, EFI_BLT_BUFFER_TO_VIDEO, 0, 0, 0, DEPTH,
+ WIDTH, HEIGHT, 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("EFI_BLT_BUFFER_TO_VIDEO failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Copy left port hole */
+ ret = gop->blt(gop, bitmap, EFI_BLT_VIDEO_TO_VIDEO,
+ 79, 57 + DEPTH, 119, 57 + DEPTH,
+ 31, 26, 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("EFI_BLT_VIDEO_TO_VIDEO failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Copy port holes back to buffer */
+ ret = gop->blt(gop, bitmap, EFI_BLT_VIDEO_TO_BLT_BUFFER,
+ 94, 57 + DEPTH, 94, 57,
+ 90, 26, WIDTH * sizeof(struct efi_gop_pixel));
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("EFI_BLT_VIDEO_TO_BLT_BUFFER failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Set 250ms timer */
+ xpos = WIDTH;
+ ret = boottime->set_timer(event, EFI_TIMER_PERIODIC, 250000);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Could not set timer\n");
+ return EFI_ST_FAILURE;
+ }
+
+ con_out->set_cursor_position(con_out, 0, 0);
+ con_out->set_attribute(con_out, EFI_WHITE | EFI_BACKGROUND_BLUE);
+ efi_st_printf("The submarine should have three yellow port holes.\n");
+ efi_st_printf("Press any key to continue");
+ efi_st_get_key();
+ con_out->set_attribute(con_out, EFI_LIGHTGRAY);
+ efi_st_printf("\n");
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(bitblt) = {
+ .name = "block image transfer",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+ .on_request = true,
+};
diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c
index 9e4b93d..a8979ed 100644
--- a/lib/efi_selftest/efi_selftest_block_device.c
+++ b/lib/efi_selftest/efi_selftest_block_device.c
@@ -29,6 +29,7 @@
static const efi_guid_t guid_device_path = DEVICE_PATH_GUID;
static const efi_guid_t guid_simple_file_system_protocol =
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
+static const efi_guid_t guid_file_system_info = EFI_FILE_SYSTEM_INFO_GUID;
static efi_guid_t guid_vendor =
EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d,
0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xb7, 0xb8);
@@ -302,7 +303,11 @@
struct efi_device_path *dp_partition;
struct efi_simple_file_system_protocol *file_system;
struct efi_file_handle *root, *file;
- u64 buf_size;
+ struct {
+ struct efi_file_system_info info;
+ u16 label[12];
+ } system_info;
+ efi_uintn_t buf_size;
char buf[16] __aligned(ARCH_DMA_MINALIGN);
ret = boottime->connect_controller(disk_handle, NULL, NULL, 1);
@@ -356,6 +361,23 @@
efi_st_error("Failed to open volume\n");
return EFI_ST_FAILURE;
}
+ buf_size = sizeof(system_info);
+ ret = root->getinfo(root, &guid_file_system_info, &buf_size,
+ &system_info);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get file system info\n");
+ return EFI_ST_FAILURE;
+ }
+ if (system_info.info.block_size != 512) {
+ efi_st_error("Wrong block size %u, expected 512\n",
+ system_info.info.block_size);
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_strcmp_16_8(system_info.info.volume_label, "U-BOOT TEST")) {
+ efi_st_todo(
+ "Wrong volume label '%ps', expected 'U-BOOT TEST'\n",
+ system_info.info.volume_label);
+ }
ret = root->open(root, &file, (s16 *)L"hello.txt", EFI_FILE_MODE_READ,
0);
if (ret != EFI_SUCCESS) {
diff --git a/lib/efi_selftest/efi_selftest_disk_image.h b/lib/efi_selftest/efi_selftest_disk_image.h
index 4775dac..9c741ce 100644
--- a/lib/efi_selftest/efi_selftest_disk_image.h
+++ b/lib/efi_selftest/efi_selftest_disk_image.h
@@ -3,21 +3,21 @@
*
* Generated with tools/file2include
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#define EFI_ST_DISK_IMG { 0x00010000, { \
- {0x000001b8, "\x94\x37\x69\xfc\x00\x00\x00\x00"}, /* .7i..... */ \
- {0x000001c0, "\x02\x00\x83\x02\x02\x00\x01\x00"}, /* ........ */ \
+ {0x000001b8, "\x21\x5d\x53\xd1\x00\x00\x00\x00"}, /* !]S..... */ \
+ {0x000001c0, "\x02\x00\x01\x02\x02\x00\x01\x00"}, /* ........ */ \
{0x000001c8, "\x00\x00\x7f\x00\x00\x00\x00\x00"}, /* ........ */ \
{0x000001f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \
{0x00000200, "\xeb\x3c\x90\x6d\x6b\x66\x73\x2e"}, /* .<.mkfs. */ \
{0x00000208, "\x66\x61\x74\x00\x02\x04\x01\x00"}, /* fat..... */ \
{0x00000210, "\x02\x00\x02\x7f\x00\xf8\x01\x00"}, /* ........ */ \
{0x00000218, "\x20\x00\x40\x00\x00\x00\x00\x00"}, /* .@..... */ \
- {0x00000220, "\x00\x00\x00\x00\x80\x00\x29\x86"}, /* ......). */ \
- {0x00000228, "\xe8\x82\x80\x4e\x4f\x20\x4e\x41"}, /* ...NO NA */ \
- {0x00000230, "\x4d\x45\x20\x20\x20\x20\x46\x41"}, /* ME FA */ \
+ {0x00000220, "\x00\x00\x00\x00\x80\x00\x29\xc4"}, /* ......). */ \
+ {0x00000228, "\xc4\x88\x11\x55\x2d\x42\x4f\x4f"}, /* ...U-BOO */ \
+ {0x00000230, "\x54\x20\x54\x45\x53\x54\x46\x41"}, /* T TESTFA */ \
{0x00000238, "\x54\x31\x32\x20\x20\x20\x0e\x1f"}, /* T12 .. */ \
{0x00000240, "\xbe\x5b\x7c\xac\x22\xc0\x74\x0b"}, /* .[|.".t. */ \
{0x00000248, "\x56\xb4\x0e\xbb\x07\x00\xcd\x10"}, /* V....... */ \
@@ -36,34 +36,20 @@
{0x000002b0, "\x72\x79\x20\x61\x67\x61\x69\x6e"}, /* ry again */ \
{0x000002b8, "\x20\x2e\x2e\x2e\x20\x0d\x0a\x00"}, /* ... ... */ \
{0x000003f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \
- {0x00000400, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \
- {0x00000408, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
- {0x00000600, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \
- {0x00000608, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
- {0x00000800, "\xe5\x70\x00\x00\x00\xff\xff\xff"}, /* .p...... */ \
- {0x00000808, "\xff\xff\xff\x0f\x00\x0e\xff\xff"}, /* ........ */ \
- {0x00000810, "\xff\xff\xff\xff\xff\xff\xff\xff"}, /* ........ */ \
- {0x00000818, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \
- {0x00000820, "\xe5\x2e\x00\x68\x00\x65\x00\x6c"}, /* ...h.e.l */ \
- {0x00000828, "\x00\x6c\x00\x0f\x00\x0e\x6f\x00"}, /* .l....o. */ \
- {0x00000830, "\x2e\x00\x74\x00\x78\x00\x74\x00"}, /* ..t.x.t. */ \
- {0x00000838, "\x2e\x00\x00\x00\x73\x00\x77\x00"}, /* ....s.w. */ \
- {0x00000840, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \
- {0x00000848, "\x53\x57\x50\x20\x00\x64\xd0\x8a"}, /* SWP .d.. */ \
- {0x00000850, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \
- {0x00000858, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \
- {0x00000860, "\x41\x68\x00\x65\x00\x6c\x00\x6c"}, /* Ah.e.l.l */ \
- {0x00000868, "\x00\x6f\x00\x0f\x00\xf1\x2e\x00"}, /* .o...... */ \
- {0x00000870, "\x74\x00\x78\x00\x74\x00\x00\x00"}, /* t.x.t... */ \
- {0x00000878, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \
- {0x00000880, "\x48\x45\x4c\x4c\x4f\x20\x20\x20"}, /* HELLO */ \
- {0x00000888, "\x54\x58\x54\x20\x00\x64\xd4\x8a"}, /* TXT .d.. */ \
- {0x00000890, "\x92\x4b\x92\x4b\x00\x00\xd4\x8a"}, /* .K.K.... */ \
- {0x00000898, "\x92\x4b\x05\x00\x0d\x00\x00\x00"}, /* .K...... */ \
- {0x000008a0, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \
- {0x000008a8, "\x53\x57\x58\x20\x00\x64\xd0\x8a"}, /* SWX .d.. */ \
- {0x000008b0, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \
- {0x000008b8, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \
- {0x00006000, "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"}, /* Hello wo */ \
- {0x00006008, "\x72\x6c\x64\x21\x0a\x00\x00\x00"}, /* rld!.... */ \
+ {0x00000400, "\xf8\xff\xff\x00\xf0\xff\x00\x00"}, /* ........ */ \
+ {0x00000600, "\xf8\xff\xff\x00\xf0\xff\x00\x00"}, /* ........ */ \
+ {0x00000800, "\x55\x2d\x42\x4f\x4f\x54\x20\x54"}, /* U-BOOT T */ \
+ {0x00000808, "\x45\x53\x54\x08\x00\x00\xaa\x56"}, /* EST....V */ \
+ {0x00000810, "\x84\x4c\x84\x4c\x00\x00\xaa\x56"}, /* .L.L...V */ \
+ {0x00000818, "\x84\x4c\x00\x00\x00\x00\x00\x00"}, /* .L...... */ \
+ {0x00000820, "\x41\x68\x00\x65\x00\x6c\x00\x6c"}, /* Ah.e.l.l */ \
+ {0x00000828, "\x00\x6f\x00\x0f\x00\xf1\x2e\x00"}, /* .o...... */ \
+ {0x00000830, "\x74\x00\x78\x00\x74\x00\x00\x00"}, /* t.x.t... */ \
+ {0x00000838, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \
+ {0x00000840, "\x48\x45\x4c\x4c\x4f\x20\x20\x20"}, /* HELLO */ \
+ {0x00000848, "\x54\x58\x54\x20\x00\x64\xd7\x46"}, /* TXT .d.F */ \
+ {0x00000850, "\x84\x4c\x84\x4c\x00\x00\xd7\x46"}, /* .L.L...F */ \
+ {0x00000858, "\x84\x4c\x03\x00\x0d\x00\x00\x00"}, /* .L...... */ \
+ {0x00005000, "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"}, /* Hello wo */ \
+ {0x00005008, "\x72\x6c\x64\x21\x0a\x00\x00\x00"}, /* rld!.... */ \
{0, NULL} } }
diff --git a/lib/efi_selftest/efi_selftest_event_groups.c b/lib/efi_selftest/efi_selftest_event_groups.c
new file mode 100644
index 0000000..79e4ea1
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_event_groups.c
@@ -0,0 +1,140 @@
+/*
+ * efi_selftest_event_groups
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This test checks the notification of group events and the
+ * following services:
+ * CreateEventEx, CloseEvent, SignalEvent, CheckEvent.
+ */
+
+#include <efi_selftest.h>
+
+#define GROUP_SIZE 16
+
+static struct efi_boot_services *boottime;
+static efi_guid_t event_group =
+ EFI_GUID(0x2335905b, 0xc3b9, 0x4221, 0xa3, 0x71,
+ 0x0e, 0x5b, 0x45, 0xc0, 0x56, 0x91);
+
+/*
+ * Notification function, increments the notfication count if parameter
+ * context is provided.
+ *
+ * @event notified event
+ * @context pointer to the notification count
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+ unsigned int *count = context;
+
+ if (count)
+ ++*count;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ boottime = systable->boottime;
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Create multiple events in an event group. Signal each event once and check
+ * that all events are notified once in each round.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ unsigned int counter[GROUP_SIZE] = {0};
+ struct efi_event *events[GROUP_SIZE];
+ size_t i, j;
+ efi_status_t ret;
+
+ for (i = 0; i < GROUP_SIZE; ++i) {
+ ret = boottime->create_event_ex(0, TPL_NOTIFY,
+ notify, (void *)&counter[i],
+ &event_group, &events[i]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to create event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ for (i = 0; i < GROUP_SIZE; ++i) {
+ ret = boottime->signal_event(events[i]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to signal event\n");
+ return EFI_ST_FAILURE;
+ }
+ for (j = 0; j < GROUP_SIZE; ++j) {
+ if (counter[j] != i) {
+ efi_st_printf("i %u, j %u, count %u\n",
+ (unsigned int)i, (unsigned int)j,
+ (unsigned int)counter[j]);
+ efi_st_error(
+ "Notification function was called\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Clear signaled state */
+ ret = boottime->check_event(events[j]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Event was not signaled\n");
+ return EFI_ST_FAILURE;
+ }
+ if (counter[j] != i) {
+ efi_st_printf("i %u, j %u, count %u\n",
+ (unsigned int)i, (unsigned int)j,
+ (unsigned int)counter[j]);
+ efi_st_error(
+ "Notification function was called\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Call notification function */
+ ret = boottime->check_event(events[j]);
+ if (ret != EFI_NOT_READY) {
+ efi_st_error(
+ "Signaled state not cleared\n");
+ return EFI_ST_FAILURE;
+ }
+ if (counter[j] != i + 1) {
+ efi_st_printf("i %u, j %u, count %u\n",
+ (unsigned int)i, (unsigned int)j,
+ (unsigned int)counter[j]);
+ efi_st_error(
+ "Nofification function not called\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ }
+
+ for (i = 0; i < GROUP_SIZE; ++i) {
+ ret = boottime->close_event(events[i]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(eventgoups) = {
+ .name = "event groups",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
diff --git a/lib/efi_selftest/efi_selftest_fdt.c b/lib/efi_selftest/efi_selftest_fdt.c
new file mode 100644
index 0000000..e5a8d6a
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_fdt.c
@@ -0,0 +1,188 @@
+/*
+ * efi_selftest_pos
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Test the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.
+ *
+ * The following services are tested:
+ * OutputString, TestString, SetAttribute.
+ */
+
+#include <efi_selftest.h>
+#include <linux/libfdt.h>
+
+static struct efi_boot_services *boottime;
+static const char *fdt;
+
+/* This should be sufficent for */
+#define BUFFERSIZE 0x100000
+
+static efi_guid_t fdt_guid = EFI_FDT_GUID;
+
+/*
+ * Convert FDT value to host endianness.
+ *
+ * @val FDT value
+ * @return converted value
+ */
+static uint32_t f2h(fdt32_t val)
+{
+ char *buf = (char *)&val;
+ char i;
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ /* Swap the bytes */
+ i = buf[0]; buf[0] = buf[3]; buf[3] = i;
+ i = buf[1]; buf[1] = buf[2]; buf[2] = i;
+#endif
+ return *(uint32_t *)buf;
+}
+
+/*
+ * Return the value of a property of the FDT root node.
+ *
+ * @name name of the property
+ * @return value of the property
+ */
+static char *get_property(const u16 *property)
+{
+ struct fdt_header *header = (struct fdt_header *)fdt;
+ const fdt32_t *pos;
+ const char *strings;
+
+ if (!header)
+ return NULL;
+
+ if (f2h(header->magic) != FDT_MAGIC) {
+ printf("Wrong magic\n");
+ return NULL;
+ }
+
+ pos = (fdt32_t *)(fdt + f2h(header->off_dt_struct));
+ strings = fdt + f2h(header->off_dt_strings);
+
+ for (;;) {
+ switch (f2h(pos[0])) {
+ case FDT_BEGIN_NODE: {
+ char *c = (char *)&pos[1];
+ size_t i;
+
+ for (i = 0; c[i]; ++i)
+ ;
+ pos = &pos[2 + (i >> 2)];
+ break;
+ }
+ case FDT_PROP: {
+ struct fdt_property *prop = (struct fdt_property *)pos;
+ const char *label = &strings[f2h(prop->nameoff)];
+ efi_status_t ret;
+
+ /* Check if this is the property to be returned */
+ if (!efi_st_strcmp_16_8(property, label)) {
+ char *str;
+ efi_uintn_t len = f2h(prop->len);
+
+ if (!len)
+ return NULL;
+ /*
+ * The string might not be 0 terminated.
+ * It is safer to make a copy.
+ */
+ ret = boottime->allocate_pool(
+ EFI_LOADER_DATA, len + 1,
+ (void **)&str);
+ if (ret != EFI_SUCCESS) {
+ efi_st_printf("AllocatePool failed\n");
+ return NULL;
+ }
+ boottime->copy_mem(str, &pos[3], len);
+ str[len] = 0;
+
+ return str;
+ }
+
+ pos = &pos[3 + ((f2h(prop->len) + 3) >> 2)];
+ break;
+ }
+ case FDT_NOP:
+ pos = &pos[1];
+ break;
+ default:
+ return NULL;
+ }
+ }
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ efi_uintn_t i;
+
+ boottime = systable->boottime;
+
+ /* Find configuration tables */
+ for (i = 0; i < systable->nr_tables; ++i) {
+ if (!efi_st_memcmp(&systable->tables[i].guid, &fdt_guid,
+ sizeof(efi_guid_t)))
+ fdt = systable->tables[i].table;
+ }
+ if (!fdt) {
+ efi_st_error("Missing device tree\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ char *str;
+ efi_status_t ret;
+
+ str = get_property(L"compatible");
+ if (str) {
+ efi_st_printf("compatible: %s\n", str);
+ ret = boottime->free_pool(str);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ } else {
+ efi_st_printf("Missing property 'compatible'\n");
+ return EFI_ST_FAILURE;
+ }
+ str = get_property(L"serial-number");
+ if (str) {
+ efi_st_printf("serial-number: %s\n", str);
+ ret = boottime->free_pool(str);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(fdt) = {
+ .name = "device tree",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .on_request = true,
+};
diff --git a/lib/efi_selftest/efi_selftest_textinput.c b/lib/efi_selftest/efi_selftest_textinput.c
new file mode 100644
index 0000000..c890ff8
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_textinput.c
@@ -0,0 +1,182 @@
+/*
+ * efi_selftest_textinput
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Provides a unit test for the EFI_SIMPLE_TEXT_INPUT_PROTOCOL.
+ * The unicode character and the scan code are printed for text
+ * input. To run the test:
+ *
+ * setenv efi_selftest text input
+ * bootefi selftest
+ */
+
+#include <efi_selftest.h>
+
+struct translate {
+ u16 code;
+ u16 *text;
+};
+
+static struct efi_boot_services *boottime;
+
+static struct translate control_characters[] = {
+ {0, L"Null"},
+ {8, L"BS"},
+ {9, L"TAB"},
+ {10, L"LF"},
+ {13, L"CR"},
+ {0, NULL},
+};
+
+static u16 ch[] = L"' '";
+static u16 unknown[] = L"unknown";
+
+static struct translate scan_codes[] = {
+ {0x00, L"Null"},
+ {0x01, L"Up"},
+ {0x02, L"Down"},
+ {0x03, L"Right"},
+ {0x04, L"Left"},
+ {0x05, L"Home"},
+ {0x06, L"End"},
+ {0x07, L"Insert"},
+ {0x08, L"Delete"},
+ {0x09, L"Page Up"},
+ {0x0a, L"Page Down"},
+ {0x0b, L"FN 1"},
+ {0x0c, L"FN 2"},
+ {0x0d, L"FN 3"},
+ {0x0e, L"FN 4"},
+ {0x0f, L"FN 5"},
+ {0x10, L"FN 6"},
+ {0x11, L"FN 7"},
+ {0x12, L"FN 8"},
+ {0x13, L"FN 9"},
+ {0x14, L"FN 10"},
+ {0x15, L"FN 11"},
+ {0x16, L"FN 12"},
+ {0x17, L"Escape"},
+ {0x68, L"FN 13"},
+ {0x69, L"FN 14"},
+ {0x6a, L"FN 15"},
+ {0x6b, L"FN 16"},
+ {0x6c, L"FN 17"},
+ {0x6d, L"FN 18"},
+ {0x6e, L"FN 19"},
+ {0x6f, L"FN 20"},
+ {0x70, L"FN 21"},
+ {0x71, L"FN 22"},
+ {0x72, L"FN 23"},
+ {0x73, L"FN 24"},
+ {0x7f, L"Mute"},
+ {0x80, L"Volume Up"},
+ {0x81, L"Volume Down"},
+ {0x100, L"Brightness Up"},
+ {0x101, L"Brightness Down"},
+ {0x102, L"Suspend"},
+ {0x103, L"Hibernate"},
+ {0x104, L"Toggle Display"},
+ {0x105, L"Recovery"},
+ {0x106, L"Reject"},
+ {0x0, NULL},
+};
+
+/*
+ * Translate a unicode character to a string.
+ *
+ * @code unicode character
+ * @return string
+ */
+static u16 *translate_char(u16 code)
+{
+ struct translate *tr;
+
+ if (code >= ' ') {
+ ch[1] = code;
+ return ch;
+ }
+ for (tr = control_characters; tr->text; ++tr) {
+ if (tr->code == code)
+ return tr->text;
+ }
+ return unknown;
+}
+
+/*
+ * Translate a scan code to a human readable string.
+ *
+ * @code unicode character
+ * @return string
+ */
+static u16 *translate_code(u16 code)
+{
+ struct translate *tr;
+
+ for (tr = scan_codes; tr->text; ++tr) {
+ if (tr->code == code)
+ return tr->text;
+ }
+ return unknown;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ boottime = systable->boottime;
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ struct efi_input_key input_key = {0};
+ efi_status_t ret;
+
+ efi_st_printf("Waiting for your input\n");
+ efi_st_printf("To terminate type 'x'\n");
+
+ for (;;) {
+ /* Wait for next key */
+ do {
+ ret = con_in->read_key_stroke(con_in, &input_key);
+ } while (ret == EFI_NOT_READY);
+
+ /* Allow 5 minutes until time out */
+ boottime->set_watchdog_timer(300, 0, 0, NULL);
+
+ efi_st_printf("Unicode char %u (%ps), scan code %u (%ps)\n",
+ (unsigned int)input_key.unicode_char,
+ translate_char(input_key.unicode_char),
+ (unsigned int)input_key.scan_code,
+ translate_code(input_key.scan_code));
+
+ switch (input_key.unicode_char) {
+ case 'x':
+ case 'X':
+ return EFI_ST_SUCCESS;
+ }
+ }
+}
+
+EFI_UNIT_TEST(textinput) = {
+ .name = "text input",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .on_request = true,
+};
diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c
index 70914a4..054c4b3 100644
--- a/lib/libfdt/fdt_region.c
+++ b/lib/libfdt/fdt_region.c
@@ -14,8 +14,6 @@
#include "fdt_host.h"
#endif
-#include "libfdt_internal.h"
-
#define FDT_MAX_DEPTH 32
static int str_in_list(const char *str, char * const list[], int count)
diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
new file mode 100644
index 0000000..1e5ab45
--- /dev/null
+++ b/lib/optee/Kconfig
@@ -0,0 +1,39 @@
+config OPTEE
+ bool "Support OPTEE images"
+ help
+ U-Boot can be configured to boot OPTEE images.
+ Selecting this option will enable shared OPTEE library code and
+ enable an OPTEE specific bootm command that will perform additional
+ OPTEE specific checks before booting an OPTEE image created with
+ mkimage.
+
+config OPTEE_LOAD_ADDR
+ hex "OPTEE load address"
+ default 0x00000000
+ help
+ The load address of the bootable OPTEE binary.
+
+config OPTEE_TZDRAM_SIZE
+ hex "Amount of Trust-Zone RAM for the OPTEE image"
+ depends on OPTEE
+ default 0x3000000
+ help
+ The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
+ runtime.
+
+config OPTEE_TZDRAM_BASE
+ hex "Base address of Trust-Zone RAM for the OPTEE image"
+ depends on OPTEE
+ default 0x9d000000
+ help
+ The base address of pre-allocated Trust Zone DRAM for
+ the OPTEE runtime.
+
+config BOOTM_OPTEE
+ bool "Support OPTEE bootm command"
+ select BOOTM_LINUX
+ default n
+ help
+ Select this command to enable chain-loading of a Linux kernel
+ via an OPTEE firmware.
+ The bootflow is BootROM -> u-boot -> OPTEE -> Linux in this case.
diff --git a/lib/optee/Makefile b/lib/optee/Makefile
new file mode 100644
index 0000000..03e832f
--- /dev/null
+++ b/lib/optee/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Linaro
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_OPTEE) += optee.o
diff --git a/lib/optee/optee.c b/lib/optee/optee.c
new file mode 100644
index 0000000..78a15e8
--- /dev/null
+++ b/lib/optee/optee.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2017 Linaro
+ * Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <tee/optee.h>
+
+#define optee_hdr_err_msg \
+ "OPTEE verification error:" \
+ "\n\thdr=%p image=0x%08lx magic=0x%08x tzdram 0x%08lx-0x%08lx " \
+ "\n\theader lo=0x%08x hi=0x%08x size=0x%08lx arch=0x%08x" \
+ "\n\tuimage params 0x%08lx-0x%08lx\n"
+
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+ unsigned long tzdram_len, unsigned long image_len)
+{
+ unsigned long tzdram_end = tzdram_start + tzdram_len;
+ uint32_t tee_file_size;
+
+ tee_file_size = hdr->init_size + hdr->paged_size +
+ sizeof(struct optee_header);
+
+ if (hdr->magic != OPTEE_MAGIC ||
+ hdr->version != OPTEE_VERSION ||
+ hdr->init_load_addr_hi > tzdram_end ||
+ hdr->init_load_addr_lo < tzdram_start ||
+ tee_file_size > tzdram_len ||
+ tee_file_size != image_len ||
+ (hdr->init_load_addr_lo + tee_file_size) > tzdram_end) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int optee_verify_bootm_image(unsigned long image_addr,
+ unsigned long image_load_addr,
+ unsigned long image_len)
+{
+ struct optee_header *hdr = (struct optee_header *)image_addr;
+ unsigned long tzdram_start = CONFIG_OPTEE_TZDRAM_BASE;
+ unsigned long tzdram_len = CONFIG_OPTEE_TZDRAM_SIZE;
+
+ int ret;
+
+ ret = optee_verify_image(hdr, tzdram_start, tzdram_len, image_len);
+ if (ret)
+ goto error;
+
+ if (image_load_addr + sizeof(*hdr) != hdr->init_load_addr_lo) {
+ ret = -EINVAL;
+ goto error;
+ }
+
+ return ret;
+error:
+ printf(optee_hdr_err_msg, hdr, image_addr, hdr->magic, tzdram_start,
+ tzdram_start + tzdram_len, hdr->init_load_addr_lo,
+ hdr->init_load_addr_hi, image_len, hdr->arch, image_load_addr,
+ image_load_addr + image_len);
+
+ return ret;
+}
diff --git a/net/Kconfig b/net/Kconfig
index 143c441..f2363e5 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -22,55 +22,4 @@
Support the 'nc' input/output device for networked console.
See README.NetConsole for details.
-config NET_TFTP_VARS
- bool "Control TFTP timeout and count through environment"
- depends on CMD_NET
- default y
- help
- If set, allows controlling the TFTP timeout through the
- environment variable tftptimeout, and the TFTP maximum
- timeout count through the variable tftptimeoutcountmax.
- If unset, timeout and maximum are hard-defined as 1 second
- and 10 timouts per TFTP transfer.
-
-config BOOTP_BOOTPATH
- bool "Enable BOOTP BOOTPATH"
- depends on CMD_NET
-
-config BOOTP_DNS
- bool "Enable bootp DNS"
- depends on CMD_NET
-
-config BOOTP_GATEWAY
- bool "Enable BOOTP gateway"
- depends on CMD_NET
-
-config BOOTP_HOSTNAME
- bool "Enable BOOTP hostname"
- depends on CMD_NET
-
-config BOOTP_PXE
- bool "Enable BOOTP PXE"
- depends on CMD_NET
-
-config BOOTP_SUBNETMASK
- bool "Enable BOOTP subnetmask"
- depends on CMD_NET
- depends on CMD_NET
-
-config BOOTP_PXE_CLIENTARCH
- hex
- depends on CMD_NET
- default 0x16 if ARM64
- default 0x15 if ARM
- default 0 if X86
-
-config BOOTP_VCI_STRING
- string
- depends on CMD_NET
- default "U-Boot.armv7" if CPU_V7 || CPU_V7M
- default "U-Boot.armv8" if ARM64
- default "U-Boot.arm" if ARM
- default "U-Boot"
-
endif # if NET
diff --git a/net/Makefile b/net/Makefile
index ae54eee..ce6e5ad 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -8,23 +8,23 @@
#ccflags-y += -DDEBUG
obj-y += checksum.o
-obj-$(CONFIG_CMD_NET) += arp.o
-obj-$(CONFIG_CMD_NET) += bootp.o
+obj-$(CONFIG_NET) += arp.o
+obj-$(CONFIG_CMD_BOOTP) += bootp.o
obj-$(CONFIG_CMD_CDP) += cdp.o
obj-$(CONFIG_CMD_DNS) += dns.o
ifdef CONFIG_DM_ETH
-obj-$(CONFIG_CMD_NET) += eth-uclass.o
+obj-$(CONFIG_NET) += eth-uclass.o
else
-obj-$(CONFIG_CMD_NET) += eth_legacy.o
+obj-$(CONFIG_NET) += eth_legacy.o
endif
-obj-$(CONFIG_CMD_NET) += eth_common.o
+obj-$(CONFIG_NET) += eth_common.o
obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
-obj-$(CONFIG_CMD_NET) += net.o
+obj-$(CONFIG_NET) += net.o
obj-$(CONFIG_CMD_NFS) += nfs.o
obj-$(CONFIG_CMD_PING) += ping.o
obj-$(CONFIG_CMD_RARP) += rarp.o
obj-$(CONFIG_CMD_SNTP) += sntp.o
-obj-$(CONFIG_CMD_NET) += tftp.o
+obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
# Disable this warning as it is triggered by:
# sprintf(buf, index ? "foo%d" : "foo", index)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index d30b04b..240b596 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -336,7 +336,7 @@
if (!current)
return -ENODEV;
- if (!device_active(current))
+ if (!eth_is_active(current))
return -EINVAL;
ret = eth_get_ops(current)->send(current, packet, length);
@@ -359,7 +359,7 @@
if (!current)
return -ENODEV;
- if (!device_active(current))
+ if (!eth_is_active(current))
return -EINVAL;
/* Process up to 32 packets at one time */
diff --git a/net/eth_common.c b/net/eth_common.c
index 66d0d22..0af91a9 100644
--- a/net/eth_common.c
+++ b/net/eth_common.c
@@ -8,40 +8,11 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <miiphy.h>
#include <net.h>
#include "eth_internal.h"
-void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
-{
- char *end;
- int i;
-
- for (i = 0; i < 6; ++i) {
- enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0;
- if (addr)
- addr = (*end) ? end + 1 : end;
- }
-}
-
-int eth_env_get_enetaddr(const char *name, uchar *enetaddr)
-{
- eth_parse_enetaddr(env_get(name), enetaddr);
- return is_valid_ethaddr(enetaddr);
-}
-
-int eth_env_set_enetaddr(const char *name, const uchar *enetaddr)
-{
- char buf[ARP_HLEN_ASCII + 1];
-
- if (eth_env_get_enetaddr(name, (uchar *)buf))
- return -EEXIST;
-
- sprintf(buf, "%pM", enetaddr);
-
- return env_set(name, buf);
-}
-
int eth_env_get_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr)
{
diff --git a/net/net.c b/net/net.c
index 4259c9e..8a9b69c 100644
--- a/net/net.c
+++ b/net/net.c
@@ -683,7 +683,7 @@
retry_forever = 0;
}
- if ((!retry_forever) && (net_try_count >= retrycnt)) {
+ if ((!retry_forever) && (net_try_count > retrycnt)) {
eth_halt();
net_set_state(NETLOOP_FAIL);
/*
diff --git a/scripts/check-config.sh b/scripts/check-config.sh
index 2677584..4848ca6 100755
--- a/scripts/check-config.sh
+++ b/scripts/check-config.sh
@@ -14,6 +14,9 @@
# For example:
# scripts/check-config.sh b/chromebook_link/u-boot.cfg kconfig_whitelist.txt .
+set -e
+set -u
+
path="$1"
whitelist="$2"
srctree="$3"
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index e450826..373094e 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -145,7 +145,8 @@
close($script);
my @types = ();
- for ($text =~ /\b(?:(?:CHK|WARN|ERROR)\s*\(\s*"([^"]+)")/g) {
+ # Also catch when type or level is passed through a variable
+ for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) {
push (@types, $_);
}
@types = sort(uniq(@types));
@@ -392,7 +393,7 @@
our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?};
our $Int = qr{[0-9]+$Int_type?};
our $Octal = qr{0[0-7]+$Int_type?};
-our $String = qr{(?:\bL)?"[X\t]*"};
+our $String = qr{"[X\t]*"};
our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?};
@@ -453,6 +454,7 @@
our $logFunctions = qr{(?x:
printk(?:_ratelimited|_once|_deferred_once|_deferred|)|
(?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
+ TP_printk|
WARN(?:_RATELIMIT|_ONCE|)|
panic|
MODULE_[A-Z_]+|
@@ -564,6 +566,7 @@
$mode_perms_search .= '|' if ($mode_perms_search ne "");
$mode_perms_search .= $entry->[0];
}
+$mode_perms_search = "(?:${mode_perms_search})";
our $mode_perms_world_writable = qr{
S_IWUGO |
@@ -598,6 +601,37 @@
$mode_perms_string_search .= '|' if ($mode_perms_string_search ne "");
$mode_perms_string_search .= $entry;
}
+our $single_mode_perms_string_search = "(?:${mode_perms_string_search})";
+our $multi_mode_perms_string_search = qr{
+ ${single_mode_perms_string_search}
+ (?:\s*\|\s*${single_mode_perms_string_search})*
+}x;
+
+sub perms_to_octal {
+ my ($string) = @_;
+
+ return trim($string) if ($string =~ /^\s*0[0-7]{3,3}\s*$/);
+
+ my $val = "";
+ my $oval = "";
+ my $to = 0;
+ my $curpos = 0;
+ my $lastpos = 0;
+ while ($string =~ /\b(($single_mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) {
+ $curpos = pos($string);
+ my $match = $2;
+ my $omatch = $1;
+ last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos));
+ $lastpos = $curpos;
+ $to |= $mode_permission_string_types{$match};
+ $val .= '\s*\|\s*' if ($val ne "");
+ $val .= $match;
+ $oval .= $omatch;
+ }
+ $oval =~ s/^\s*\|\s*//;
+ $oval =~ s/\s*\|\s*$//;
+ return sprintf("%04o", $to);
+}
our $allowed_asm_includes = qr{(?x:
irq|
@@ -757,7 +791,8 @@
our $declaration_macros = qr{(?x:
(?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(|
(?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(|
- (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(
+ (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(|
+ (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\(
)};
sub deparenthesize {
@@ -1041,7 +1076,7 @@
} elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) {
$address = $1;
$comment = $2 if defined $2;
- $formatted_email =~ s/$address.*$//;
+ $formatted_email =~ s/\Q$address\E.*$//;
$name = $formatted_email;
$name = trim($name);
$name =~ s/^\"|\"$//g;
@@ -1183,7 +1218,7 @@
for ($off = 1; $off < length($line); $off++) {
$c = substr($line, $off, 1);
- # Comments we are wacking completly including the begin
+ # Comments we are whacking completely including the begin
# and end, all to $;.
if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') {
$sanitise_quote = '*/';
@@ -1263,6 +1298,7 @@
sub get_quoted_string {
my ($line, $rawline) = @_;
+ return "" if (!defined($line) || !defined($rawline));
return "" if ($line !~ m/($String)/g);
return substr($rawline, $-[0], $+[0] - $-[0]);
}
@@ -1610,6 +1646,28 @@
return $line;
}
+sub get_stat_real {
+ my ($linenr, $lc) = @_;
+
+ my $stat_real = raw_line($linenr, 0);
+ for (my $count = $linenr + 1; $count <= $lc; $count++) {
+ $stat_real = $stat_real . "\n" . raw_line($count, 0);
+ }
+
+ return $stat_real;
+}
+
+sub get_stat_here {
+ my ($linenr, $cnt, $here) = @_;
+
+ my $herectx = $here . "\n";
+ for (my $n = 0; $n < $cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";
+ }
+
+ return $herectx;
+}
+
sub cat_vet {
my ($vet) = @_;
my ($res, $coded);
@@ -2223,6 +2281,8 @@
my $camelcase_file_seeded = 0;
+ my $checklicenseline = 1;
+
sanitise_line_reset();
my $line;
foreach my $rawline (@rawlines) {
@@ -2414,6 +2474,7 @@
} else {
$check = $check_orig;
}
+ $checklicenseline = 1;
next;
}
@@ -2715,10 +2776,10 @@
my $typo_fix = $spelling_fix{lc($typo)};
$typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/);
$typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/);
- my $msg_type = \&WARN;
- $msg_type = \&CHK if ($file);
- if (&{$msg_type}("TYPO_SPELLING",
- "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) &&
+ my $msg_level = \&WARN;
+ $msg_level = \&CHK if ($file);
+ if (&{$msg_level}("TYPO_SPELLING",
+ "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) &&
$fix) {
$fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/;
}
@@ -2753,17 +2814,20 @@
$rawline =~ /\b59\s+Temple\s+Pl/i ||
$rawline =~ /\b51\s+Franklin\s+St/i) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- my $msg_type = \&ERROR;
- $msg_type = \&CHK if ($file);
- &{$msg_type}("FSF_MAILING_ADDRESS",
- "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet)
+ my $msg_level = \&ERROR;
+ $msg_level = \&CHK if ($file);
+ &{$msg_level}("FSF_MAILING_ADDRESS",
+ "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet)
}
# check for Kconfig help text having a real description
# Only applies when adding the entry originally, after that we do not have
# sufficient context to determine whether it is indeed long enough.
if ($realfile =~ /Kconfig/ &&
- $line =~ /^\+\s*config\s+/) {
+ # 'choice' is usually the last thing on the line (though
+ # Kconfig supports named choices), so use a word boundary
+ # (\b) rather than a whitespace character (\s)
+ $line =~ /^\+\s*(?:config|menuconfig|choice)\b/) {
my $length = 0;
my $cnt = $realcnt;
my $ln = $linenr + 1;
@@ -2778,9 +2842,13 @@
next if ($f =~ /^-/);
last if (!$file && $f =~ /^\@\@/);
- if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate)\s*\"/) {
+ if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate|prompt)\s*["']/) {
$is_start = 1;
- } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) {
+ } elsif ($lines[$ln - 1] =~ /^\+\s*(?:help|---help---)\s*$/) {
+ if ($lines[$ln - 1] =~ "---help---") {
+ WARN("CONFIG_DESCRIPTION",
+ "prefer 'help' over '---help---' for new help texts\n" . $herecurr);
+ }
$length = -1;
}
@@ -2788,7 +2856,13 @@
$f =~ s/#.*//;
$f =~ s/^\s+//;
next if ($f =~ /^$/);
- if ($f =~ /^\s*config\s/) {
+
+ # This only checks context lines in the patch
+ # and so hopefully shouldn't trigger false
+ # positives, even though some of these are
+ # common words in help texts
+ if ($f =~ /^\s*(?:config|menuconfig|choice|endchoice|
+ if|endif|menu|endmenu|source)\b/x) {
$is_end = 1;
last;
}
@@ -2864,6 +2938,30 @@
}
}
+# check for using SPDX license tag at beginning of files
+ if ($realline == $checklicenseline) {
+ if ($rawline =~ /^[ \+]\s*\#\!\s*\//) {
+ $checklicenseline = 2;
+ } elsif ($rawline =~ /^\+/) {
+ my $comment = "";
+ if ($realfile =~ /\.(h|s|S)$/) {
+ $comment = '/*';
+ } elsif ($realfile =~ /\.(c|dts|dtsi)$/) {
+ $comment = '//';
+ } elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc)$/) {
+ $comment = '#';
+ } elsif ($realfile =~ /\.rst$/) {
+ $comment = '..';
+ }
+
+ if ($comment !~ /^$/ &&
+ $rawline !~ /^\+\Q$comment\E SPDX-License-Identifier: /) {
+ WARN("SPDX_LICENSE_TAG",
+ "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr);
+ }
+ }
+ }
+
# check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/);
@@ -2873,9 +2971,10 @@
# logging functions like pr_info that end in a string
# lines with a single string
# #defines that are a single string
+# lines with an RFC3986 like URL
#
# There are 3 different line length message types:
-# LONG_LINE_COMMENT a comment starts before but extends beyond $max_linelength
+# LONG_LINE_COMMENT a comment starts before but extends beyond $max_line_length
# LONG_LINE_STRING a string starts before but extends beyond $max_line_length
# LONG_LINE all other lines longer than $max_line_length
#
@@ -2899,8 +2998,13 @@
$line =~ /^\+\s*#\s*define\s+\w+\s+$String$/) {
$msg_type = "";
- # EFI_GUID is another special case
- } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/) {
+ # More special cases
+ } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/ ||
+ $line =~ /^\+\s*(?:\w+)?\s*DEFINE_PER_CPU/) {
+ $msg_type = "";
+
+ # URL ($rawline is used in case the URL is in a comment)
+ } elsif ($rawline =~ /^\+.*\b[a-z][\w\.\+\-]*:\/\/\S+/i) {
$msg_type = "";
# Otherwise set the alternate message types
@@ -2929,20 +3033,6 @@
"adding a line without newline at end of file\n" . $herecurr);
}
-# Blackfin: use hi/lo macros
- if ($realfile =~ m@arch/blackfin/.*\.S$@) {
- if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("LO_MACRO",
- "use the LO() macro, not (... & 0xFFFF)\n" . $herevet);
- }
- if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("HI_MACRO",
- "use the HI() macro, not (... >> 16)\n" . $herevet);
- }
- }
-
# check we are in a valid source file C or perl if not then ignore this hunk
next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/);
@@ -2980,7 +3070,7 @@
# check indentation starts on a tab stop
if ($^V && $^V ge 5.10.0 &&
- $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$))/) {
+ $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$)|$Declare\s*$Ident\s*[;=])/) {
my $indent = length($1);
if ($indent % 8) {
if (WARN("TABSTOP",
@@ -3102,6 +3192,7 @@
$line =~ /^\+[a-z_]*init/ ||
$line =~ /^\+\s*(?:static\s+)?[A-Z_]*ATTR/ ||
$line =~ /^\+\s*DECLARE/ ||
+ $line =~ /^\+\s*builtin_[\w_]*driver/ ||
$line =~ /^\+\s*__setup/)) {
if (CHK("LINE_SPACING",
"Please use a blank line after function/struct/union/enum declarations\n" . $hereprev) &&
@@ -3181,6 +3272,12 @@
# check we are in a valid C source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c)$/);
+# check for unusual line ending [ or (
+ if ($line =~ /^\+.*([\[\(])\s*$/) {
+ CHK("OPEN_ENDED_LINE",
+ "Lines should not end with a '$1'\n" . $herecurr);
+ }
+
# check if this appears to be the start function declaration, save the name
if ($sline =~ /^\+\{\s*$/ &&
$prevline =~ /^\+(?:(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*)?($Ident)\(/) {
@@ -3222,18 +3319,6 @@
"CVS style keyword markers, these will _not_ be updated\n". $herecurr);
}
-# Blackfin: don't use __builtin_bfin_[cs]sync
- if ($line =~ /__builtin_bfin_csync/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("CSYNC",
- "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
- }
- if ($line =~ /__builtin_bfin_ssync/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("SSYNC",
- "use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
- }
-
# check for old HOTPLUG __dev<foo> section markings
if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) {
WARN("HOTPLUG_SECTION",
@@ -3810,10 +3895,10 @@
# avoid BUG() or BUG_ON()
if ($line =~ /\b(?:BUG|BUG_ON)\b/) {
- my $msg_type = \&WARN;
- $msg_type = \&CHK if ($file);
- &{$msg_type}("AVOID_BUG",
- "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr);
+ my $msg_level = \&WARN;
+ $msg_level = \&CHK if ($file);
+ &{$msg_level}("AVOID_BUG",
+ "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr);
}
# avoid LINUX_VERSION_CODE
@@ -3828,28 +3913,10 @@
"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
}
-# printk should use KERN_* levels. Note that follow on printk's on the
-# same line do not need a level, so we use the current block context
-# to try and find and validate the current printk. In summary the current
-# printk includes all preceding printk's which have no newline on the end.
-# we assume the first bad printk is the one to report.
- if ($line =~ /\bprintk\((?!KERN_)\s*"/) {
- my $ok = 0;
- for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) {
- #print "CHECK<$lines[$ln - 1]\n";
- # we have a preceding printk if it ends
- # with "\n" ignore it, else it is to blame
- if ($lines[$ln - 1] =~ m{\bprintk\(}) {
- if ($rawlines[$ln - 1] !~ m{\\n"}) {
- $ok = 1;
- }
- last;
- }
- }
- if ($ok == 0) {
- WARN("PRINTK_WITHOUT_KERN_LEVEL",
- "printk() should include KERN_ facility level\n" . $herecurr);
- }
+# printk should use KERN_* levels
+ if ($line =~ /\bprintk\s*\(\s*(?!KERN_[A-Z]+\b)/) {
+ WARN("PRINTK_WITHOUT_KERN_LEVEL",
+ "printk() should include KERN_<LEVEL> facility level\n" . $herecurr);
}
if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) {
@@ -3890,10 +3957,12 @@
# function brace can't be on same line, except for #defines of do while,
# or if closed on same line
- if (($line=~/$Type\s*$Ident\(.*\).*\s*{/) and
- !($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) {
+ if ($^V && $^V ge 5.10.0 &&
+ $sline =~ /$Type\s*$Ident\s*$balanced_parens\s*\{/ &&
+ $sline !~ /\#\s*define\b.*do\s*\{/ &&
+ $sline !~ /}/) {
if (ERROR("OPEN_BRACE",
- "open brace '{' following function declarations go on the next line\n" . $herecurr) &&
+ "open brace '{' following function definitions go on the next line\n" . $herecurr) &&
$fix) {
fix_delete_line($fixlinenr, $rawline);
my $fixed_line = $rawline;
@@ -4339,11 +4408,11 @@
# messages are ERROR, but ?: are CHK
if ($ok == 0) {
- my $msg_type = \&ERROR;
- $msg_type = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/);
+ my $msg_level = \&ERROR;
+ $msg_level = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/);
- if (&{$msg_type}("SPACING",
- "spaces required around that '$op' $at\n" . $hereptr)) {
+ if (&{$msg_level}("SPACING",
+ "spaces required around that '$op' $at\n" . $hereptr)) {
$good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
if (defined $fix_elements[$n + 2]) {
$fix_elements[$n + 2] =~ s/^\s+//;
@@ -4496,6 +4565,32 @@
}
}
+# check for unnecessary parentheses around comparisons in if uses
+# when !drivers/staging or command-line uses --strict
+ if (($realfile !~ m@^(?:drivers/staging/)@ || $check_orig) &&
+ $^V && $^V ge 5.10.0 && defined($stat) &&
+ $stat =~ /(^.\s*if\s*($balanced_parens))/) {
+ my $if_stat = $1;
+ my $test = substr($2, 1, -1);
+ my $herectx;
+ while ($test =~ /(?:^|[^\w\&\!\~])+\s*\(\s*([\&\!\~]?\s*$Lval\s*(?:$Compare\s*$FuncArg)?)\s*\)/g) {
+ my $match = $1;
+ # avoid parentheses around potential macro args
+ next if ($match =~ /^\s*\w+\s*$/);
+ if (!defined($herectx)) {
+ $herectx = $here . "\n";
+ my $cnt = statement_rawlines($if_stat);
+ for (my $n = 0; $n < $cnt; $n++) {
+ my $rl = raw_line($linenr, $n);
+ $herectx .= $rl . "\n";
+ last if $rl =~ /^[ \+].*\{/;
+ }
+ }
+ CHK("UNNECESSARY_PARENTHESES",
+ "Unnecessary parentheses around '$match'\n" . $herectx);
+ }
+ }
+
#goto labels aren't indented, allow a single space however
if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
!($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
@@ -4884,12 +4979,8 @@
#print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
$ctx =~ s/\n*$//;
- my $herectx = $here . "\n";
my $stmt_cnt = statement_rawlines($ctx);
-
- for (my $n = 0; $n < $stmt_cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
+ my $herectx = get_stat_here($linenr, $stmt_cnt, $here);
if ($dstat ne '' &&
$dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(),
@@ -4961,12 +5052,9 @@
# check for macros with flow control, but without ## concatenation
# ## concatenation is commonly a macro that defines a function so ignore those
if ($has_flow_statement && !$has_arg_concat) {
- my $herectx = $here . "\n";
my $cnt = statement_rawlines($ctx);
+ my $herectx = get_stat_here($linenr, $cnt, $here);
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
WARN("MACRO_WITH_FLOW_CONTROL",
"Macros with flow control statements should be avoided\n" . "$herectx");
}
@@ -5006,11 +5094,7 @@
$ctx =~ s/\n*$//;
my $cnt = statement_rawlines($ctx);
- my $herectx = $here . "\n";
-
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
+ my $herectx = get_stat_here($linenr, $cnt, $here);
if (($stmts =~ tr/;/;/) == 1 &&
$stmts !~ /^\s*(if|while|for|switch)\b/) {
@@ -5024,11 +5108,7 @@
} elsif ($dstat =~ /^\+\s*#\s*define\s+$Ident.*;\s*$/) {
$ctx =~ s/\n*$//;
my $cnt = statement_rawlines($ctx);
- my $herectx = $here . "\n";
-
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
+ my $herectx = get_stat_here($linenr, $cnt, $here);
WARN("TRAILING_SEMICOLON",
"macros should not use a trailing semicolon\n" . "$herectx");
@@ -5151,12 +5231,8 @@
}
}
if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) {
- my $herectx = $here . "\n";
my $cnt = statement_rawlines($block);
-
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
+ my $herectx = get_stat_here($linenr, $cnt, $here);
WARN("BRACES",
"braces {} are not necessary for single statement blocks\n" . $herectx);
@@ -5254,14 +5330,13 @@
}
# concatenated string without spaces between elements
- if ($line =~ /$String[A-Z_]/ ||
- ($line =~ /([A-Za-z0-9_]+)$String/ && $1 !~ /^L$/)) {
+ if ($line =~ /$String[A-Z_]/ || $line =~ /[A-Za-z0-9_]$String/) {
CHK("CONCATENATED_STRING",
"Concatenated strings should use spaces between elements\n" . $herecurr);
}
# uncoalesced string fragments
- if ($line =~ /$String\s*L?"/) {
+ if ($line =~ /$String\s*"/) {
WARN("STRING_FRAGMENTS",
"Consecutive strings are generally better as a single string\n" . $herecurr);
}
@@ -5292,7 +5367,7 @@
}
# check for line continuations in quoted strings with odd counts of "
- if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
+ if ($rawline =~ /\\$/ && $sline =~ tr/"/"/ % 2) {
WARN("LINE_CONTINUATIONS",
"Avoid line continuations in quoted strings\n" . $herecurr);
}
@@ -5571,6 +5646,12 @@
}
}
+# check for smp_read_barrier_depends and read_barrier_depends
+ if (!$file && $line =~ /\b(smp_|)read_barrier_depends\s*\(/) {
+ WARN("READ_BARRIER_DEPENDS",
+ "$1read_barrier_depends should only be used in READ_ONCE or DEC Alpha code\n" . $herecurr);
+ }
+
# check of hardware specific defines
if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) {
CHK("ARCH_DEFINES",
@@ -5734,29 +5815,50 @@
}
}
- # check for vsprintf extension %p<foo> misuses
+# check for vsprintf extension %p<foo> misuses
if ($^V && $^V ge 5.10.0 &&
defined $stat &&
$stat =~ /^\+(?![^\{]*\{\s*).*\b(\w+)\s*\(.*$String\s*,/s &&
$1 !~ /^_*volatile_*$/) {
- my $bad_extension = "";
+ my $specifier;
+ my $extension;
+ my $bad_specifier = "";
+ my $stat_real;
+
my $lc = $stat =~ tr@\n@@;
$lc = $lc + $linenr;
for (my $count = $linenr; $count <= $lc; $count++) {
my $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0));
$fmt =~ s/%%//g;
- if ($fmt =~ /(\%[\*\d\.]*p(?![\WFfSsBKRraEhMmIiUDdgVCbGNO]).)/) {
- $bad_extension = $1;
- last;
+
+ while ($fmt =~ /(\%[\*\d\.]*p(\w))/g) {
+ $specifier = $1;
+ $extension = $2;
+ if ($extension !~ /[SsBKRraEhMmIiUDdgVCbGNOx]/) {
+ $bad_specifier = $specifier;
+ last;
+ }
+ if ($extension eq "x" && !defined($stat_real)) {
+ if (!defined($stat_real)) {
+ $stat_real = get_stat_real($linenr, $lc);
+ }
+ WARN("VSPRINTF_SPECIFIER_PX",
+ "Using vsprintf specifier '\%px' potentially exposes the kernel memory layout, if you don't really need the address please consider using '\%p'.\n" . "$here\n$stat_real\n");
+ }
}
- }
- if ($bad_extension ne "") {
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
+ if ($bad_specifier ne "") {
+ my $stat_real = get_stat_real($linenr, $lc);
+ my $ext_type = "Invalid";
+ my $use = "";
+ if ($bad_specifier =~ /p[Ff]/) {
+ $ext_type = "Deprecated";
+ $use = " - use %pS instead";
+ $use =~ s/pS/ps/ if ($bad_specifier =~ /pf/);
+ }
+
+ WARN("VSPRINTF_POINTER_EXTENSION",
+ "$ext_type vsprintf pointer extension '$bad_specifier'$use\n" . "$here\n$stat_real\n");
}
- WARN("VSPRINTF_POINTER_EXTENSION",
- "Invalid vsprintf pointer extension '$bad_extension'\n" . "$here\n$stat_real\n");
}
}
@@ -5869,10 +5971,7 @@
$stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) {
my $lc = $stat =~ tr@\n@@;
$lc = $lc + $linenr;
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
- }
+ my $stat_real = get_stat_real($linenr, $lc);
WARN("NAKED_SSCANF",
"unchecked sscanf return value\n" . "$here\n$stat_real\n");
}
@@ -5883,10 +5982,7 @@
$line =~ /\bsscanf\b/) {
my $lc = $stat =~ tr@\n@@;
$lc = $lc + $linenr;
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
- }
+ my $stat_real = get_stat_real($linenr, $lc);
if ($stat_real =~ /\bsscanf\b\s*\(\s*$FuncArg\s*,\s*("[^"]+")/) {
my $format = $6;
my $count = $format =~ tr@%@%@;
@@ -5940,7 +6036,7 @@
# check for function declarations that have arguments without identifier names
if (defined $stat &&
- $stat =~ /^.\s*(?:extern\s+)?$Type\s*$Ident\s*\(\s*([^{]+)\s*\)\s*;/s &&
+ $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s &&
$1 ne "void") {
my $args = trim($1);
while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) {
@@ -6016,12 +6112,9 @@
}
if ($r1 !~ /^sizeof\b/ && $r2 =~ /^sizeof\s*\S/ &&
!($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) {
- my $ctx = '';
- my $herectx = $here . "\n";
my $cnt = statement_rawlines($stat);
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
+ my $herectx = get_stat_here($linenr, $cnt, $here);
+
if (WARN("ALLOC_WITH_MULTIPLY",
"Prefer $newfunc over $oldfunc with multiply\n" . $herectx) &&
$cnt == 1 &&
@@ -6092,7 +6185,7 @@
next if ($fline =~ /^.[\s$;]*$/);
$has_statement = 1;
$count++;
- $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|return\b|goto\b|continue\b)/);
+ $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|exit\s*\(\b|return\b|goto\b|continue\b)/);
}
if (!$has_break && $has_statement) {
WARN("MISSING_BREAK",
@@ -6104,12 +6197,9 @@
if ($^V && $^V ge 5.10.0 &&
defined $stat &&
$stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) {
- my $ctx = '';
- my $herectx = $here . "\n";
my $cnt = statement_rawlines($stat);
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
+ my $herectx = get_stat_here($linenr, $cnt, $here);
+
WARN("DEFAULT_NO_BREAK",
"switch default: should use break\n" . $herectx);
}
@@ -6225,28 +6315,6 @@
}
}
-# whine about ACCESS_ONCE
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /\bACCESS_ONCE\s*$balanced_parens\s*(=(?!=))?\s*($FuncArg)?/) {
- my $par = $1;
- my $eq = $2;
- my $fun = $3;
- $par =~ s/^\(\s*(.*)\s*\)$/$1/;
- if (defined($eq)) {
- if (WARN("PREFER_WRITE_ONCE",
- "Prefer WRITE_ONCE(<FOO>, <BAR>) over ACCESS_ONCE(<FOO>) = <BAR>\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)\s*$eq\s*\Q$fun\E/WRITE_ONCE($par, $fun)/;
- }
- } else {
- if (WARN("PREFER_READ_ONCE",
- "Prefer READ_ONCE(<FOO>) over ACCESS_ONCE(<FOO>)\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)/READ_ONCE($par)/;
- }
- }
- }
-
# check for mutex_trylock_recursive usage
if ($line =~ /mutex_trylock_recursive/) {
ERROR("LOCKING",
@@ -6270,8 +6338,69 @@
"Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
}
+# check for DEVICE_ATTR uses that could be DEVICE_ATTR_<FOO>
+# and whether or not function naming is typical and if
+# DEVICE_ATTR permissions uses are unusual too
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /\bDEVICE_ATTR\s*\(\s*(\w+)\s*,\s*\(?\s*(\s*(?:${multi_mode_perms_string_search}|0[0-7]{3,3})\s*)\s*\)?\s*,\s*(\w+)\s*,\s*(\w+)\s*\)/) {
+ my $var = $1;
+ my $perms = $2;
+ my $show = $3;
+ my $store = $4;
+ my $octal_perms = perms_to_octal($perms);
+ if ($show =~ /^${var}_show$/ &&
+ $store =~ /^${var}_store$/ &&
+ $octal_perms eq "0644") {
+ if (WARN("DEVICE_ATTR_RW",
+ "Use DEVICE_ATTR_RW\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*$store\s*\)/DEVICE_ATTR_RW(${var})/;
+ }
+ } elsif ($show =~ /^${var}_show$/ &&
+ $store =~ /^NULL$/ &&
+ $octal_perms eq "0444") {
+ if (WARN("DEVICE_ATTR_RO",
+ "Use DEVICE_ATTR_RO\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*NULL\s*\)/DEVICE_ATTR_RO(${var})/;
+ }
+ } elsif ($show =~ /^NULL$/ &&
+ $store =~ /^${var}_store$/ &&
+ $octal_perms eq "0200") {
+ if (WARN("DEVICE_ATTR_WO",
+ "Use DEVICE_ATTR_WO\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*NULL\s*,\s*$store\s*\)/DEVICE_ATTR_WO(${var})/;
+ }
+ } elsif ($octal_perms eq "0644" ||
+ $octal_perms eq "0444" ||
+ $octal_perms eq "0200") {
+ my $newshow = "$show";
+ $newshow = "${var}_show" if ($show ne "NULL" && $show ne "${var}_show");
+ my $newstore = $store;
+ $newstore = "${var}_store" if ($store ne "NULL" && $store ne "${var}_store");
+ my $rename = "";
+ if ($show ne $newshow) {
+ $rename .= " '$show' to '$newshow'";
+ }
+ if ($store ne $newstore) {
+ $rename .= " '$store' to '$newstore'";
+ }
+ WARN("DEVICE_ATTR_FUNCTIONS",
+ "Consider renaming function(s)$rename\n" . $herecurr);
+ } else {
+ WARN("DEVICE_ATTR_PERMS",
+ "DEVICE_ATTR unusual permissions '$perms' used\n" . $herecurr);
+ }
+ }
+
# Mode permission misuses where it seems decimal should be octal
# This uses a shortcut match to avoid unnecessary uses of a slow foreach loop
+# o Ignore module_param*(...) uses with a decimal 0 permission as that has a
+# specific definition of not visible in sysfs.
+# o Ignore proc_create*(...) uses with a decimal 0 permission as that means
+# use the default permissions
if ($^V && $^V ge 5.10.0 &&
defined $stat &&
$line =~ /$mode_perms_search/) {
@@ -6281,10 +6410,7 @@
my $lc = $stat =~ tr@\n@@;
$lc = $lc + $linenr;
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
- }
+ my $stat_real = get_stat_real($linenr, $lc);
my $skip_args = "";
if ($arg_pos > 1) {
@@ -6295,8 +6421,9 @@
if ($stat =~ /$test/) {
my $val = $1;
$val = $6 if ($skip_args ne "");
- if (($val =~ /^$Int$/ && $val !~ /^$Octal$/) ||
- ($val =~ /^$Octal$/ && length($val) ne 4)) {
+ if (!($func =~ /^(?:module_param|proc_create)/ && $val eq "0") &&
+ (($val =~ /^$Int$/ && $val !~ /^$Octal$/) ||
+ ($val =~ /^$Octal$/ && length($val) ne 4))) {
ERROR("NON_OCTAL_PERMISSIONS",
"Use 4 digit octal (0777) not decimal permissions\n" . "$here\n" . $stat_real);
}
@@ -6309,30 +6436,13 @@
}
# check for uses of S_<PERMS> that could be octal for readability
- if ($line =~ /\b$mode_perms_string_search\b/) {
- my $val = "";
- my $oval = "";
- my $to = 0;
- my $curpos = 0;
- my $lastpos = 0;
- while ($line =~ /\b(($mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) {
- $curpos = pos($line);
- my $match = $2;
- my $omatch = $1;
- last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos));
- $lastpos = $curpos;
- $to |= $mode_permission_string_types{$match};
- $val .= '\s*\|\s*' if ($val ne "");
- $val .= $match;
- $oval .= $omatch;
- }
- $oval =~ s/^\s*\|\s*//;
- $oval =~ s/\s*\|\s*$//;
- my $octal = sprintf("%04o", $to);
+ while ($line =~ m{\b($multi_mode_perms_string_search)\b}g) {
+ my $oval = $1;
+ my $octal = perms_to_octal($oval);
if (WARN("SYMBOLIC_PERMS",
"Symbolic permissions '$oval' are not preferred. Consider using octal permissions '$octal'.\n" . $herecurr) &&
$fix) {
- $fixed[$fixlinenr] =~ s/$val/$octal/;
+ $fixed[$fixlinenr] =~ s/\Q$oval\E/$octal/;
}
}
@@ -6373,7 +6483,7 @@
exit(0);
}
- if (!$is_patch && $file !~ /cover-letter\.patch$/) {
+ if (!$is_patch && $filename !~ /cover-letter\.patch$/) {
ERROR("NOT_UNIFIED_DIFF",
"Does not appear to be a unified-diff format patch\n");
}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 3606585..84b5030 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -127,7 +127,6 @@
CONFIG_BOARDNAME_LOCAL
CONFIG_BOARD_AXM
CONFIG_BOARD_COMMON
-CONFIG_BOARD_EARLY_INIT_R
CONFIG_BOARD_ECC_SUPPORT
CONFIG_BOARD_IS_OPENRD_BASE
CONFIG_BOARD_IS_OPENRD_CLIENT
@@ -381,7 +380,6 @@
CONFIG_DISCONTIGMEM
CONFIG_DISCOVER_PHY
CONFIG_DISPLAY_AER_xxxx
-CONFIG_DISPLAY_BOARDINFO_LATE
CONFIG_DLVISION_10G
CONFIG_DM9000_BASE
CONFIG_DM9000_BYTE_SWAPPED
@@ -411,7 +409,6 @@
CONFIG_DRIVER_NE2000_CCR
CONFIG_DRIVER_NE2000_VAL
CONFIG_DRIVER_SMC911X_BASE
-CONFIG_DRIVER_TI_CPSW
CONFIG_DRIVER_TI_EMAC
CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
CONFIG_DRIVER_TI_EMAC_USE_RMII
@@ -538,7 +535,6 @@
CONFIG_ENV_UBIFS_OPTION
CONFIG_ENV_UBI_MTD
CONFIG_ENV_UBI_VOLUME_REDUND
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
CONFIG_ENV_VERSION
CONFIG_EP9302
CONFIG_EP9307
@@ -670,7 +666,6 @@
CONFIG_FSL_DIU_FB
CONFIG_FSL_DMA
CONFIG_FSL_DSPI1
-CONFIG_FSL_ESDHC
CONFIG_FSL_ESDHC_ADAPTER_IDENT
CONFIG_FSL_ESDHC_PIN_MUX
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -741,10 +736,6 @@
CONFIG_FTRTC010_BASE
CONFIG_FTRTC010_EXTCLK
CONFIG_FTRTC010_PCLK
-CONFIG_FTSDC010_BASE
-CONFIG_FTSDC010_BASE_LIST
-CONFIG_FTSDC010_NUMBER
-CONFIG_FTSDC010_SDIO
CONFIG_FTSDMC021
CONFIG_FTSDMC021_BASE
CONFIG_FTSMC020
@@ -1161,7 +1152,6 @@
CONFIG_L1_INIT_RAM
CONFIG_L2_CACHE
CONFIG_LAN91C96_USE_32_BIT
-CONFIG_LAST_STAGE_INIT
CONFIG_LAYERSCAPE_NS_ACCESS
CONFIG_LBA48
CONFIG_LBDAF
@@ -1335,7 +1325,6 @@
CONFIG_MTD_CONCAT
CONFIG_MTD_DEVICE
CONFIG_MTD_ECC_SOFT
-CONFIG_MTD_NAND_ECC_SMC
CONFIG_MTD_NAND_MUSEUM_IDS
CONFIG_MTD_NAND_VERIFY_WRITE
CONFIG_MTD_ONENAND_VERIFY_WRITE
@@ -1416,7 +1405,6 @@
CONFIG_NAND_LPC32XX_SLC
CONFIG_NAND_MODE_REG
CONFIG_NAND_MXC_V1_1
-CONFIG_NAND_NDFC
CONFIG_NAND_OMAP_ECCSCHEME
CONFIG_NAND_OMAP_GPMC_WSCFG
CONFIG_NAND_SECBOOT
@@ -1541,7 +1529,6 @@
CONFIG_PERIF3_FREQ
CONFIG_PERIF4_FREQ
CONFIG_PHYSMEM
-CONFIG_PHY_ADDR
CONFIG_PHY_BASE_ADR
CONFIG_PHY_BCM5421S
CONFIG_PHY_ET1011C_TX_CLK_FIX
@@ -1633,10 +1620,6 @@
CONFIG_PROG_UBOOT2
CONFIG_PROOF_POINTS
CONFIG_PRPMC_PCI_ALIAS
-CONFIG_PS2KBD
-CONFIG_PS2MULT
-CONFIG_PS2MULT_DELAY
-CONFIG_PS2SERIAL
CONFIG_PSRAM_SCFG
CONFIG_PWM
CONFIG_PWM_IMX
@@ -1950,7 +1933,6 @@
CONFIG_SPLASH_SOURCE
CONFIG_SPLL_FREQ
CONFIG_SPL_
-CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
CONFIG_SPL_ATMEL_SIZE
CONFIG_SPL_BOARD_LOAD_IMAGE
CONFIG_SPL_BOOTROM_SAVE
@@ -2006,7 +1988,6 @@
CONFIG_SPL_SPAACT_ADDR
CONFIG_SPL_SPI_BOOT
CONFIG_SPL_SPI_FLASH_MINIMAL
-CONFIG_SPL_SPI_LOAD
CONFIG_SPL_STACK
CONFIG_SPL_STACK_ADDR
CONFIG_SPL_STACK_SIZE
@@ -2093,7 +2074,6 @@
CONFIG_SYS_ADV7611_I2C
CONFIG_SYS_ALT_BOOT
CONFIG_SYS_ALT_FLASH
-CONFIG_SYS_ALT_MEMTEST
CONFIG_SYS_AMASK0
CONFIG_SYS_AMASK0_FINAL
CONFIG_SYS_AMASK1
@@ -4607,7 +4587,6 @@
CONFIG_TSEC4_NAME
CONFIG_TSECV2
CONFIG_TSECV2_1
-CONFIG_TSEC_ENET
CONFIG_TSEC_TBI
CONFIG_TSEC_TBICR_SETTINGS
CONFIG_TSI108_ETH_NUM_PORTS
@@ -4630,10 +4609,8 @@
CONFIG_UART_BR_PRELIM
CONFIG_UART_OR_PRELIM
CONFIG_UBIBLOCK
-CONFIG_UBIFS_SILENCE_MSG
CONFIG_UBIFS_VOLUME
CONFIG_UBI_PART
-CONFIG_UBI_SILENCE_MSG
CONFIG_UBI_SIZE
CONFIG_UBOOT1_ENV_ADDR
CONFIG_UBOOT2_ENV_ADDR
diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index 07800e6..e3b4161 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -57,6 +57,7 @@
my $file_emails = 0;
my $from_filename = 0;
my $pattern_depth = 0;
+my $self_test = undef;
my $version = 0;
my $help = 0;
my $find_maintainer_files = 1;
@@ -136,6 +137,7 @@
"subject_pattern" => "^GitSubject: (.*)",
"stat_pattern" => "^(\\d+)\\t(\\d+)\\t\$file\$",
"file_exists_cmd" => "git ls-files \$file",
+ "list_files_cmd" => "git ls-files \$file",
);
my %VCS_cmds_hg = (
@@ -165,6 +167,7 @@
"subject_pattern" => "^HgSubject: (.*)",
"stat_pattern" => "^(\\d+)\t(\\d+)\t\$file\$",
"file_exists_cmd" => "hg files \$file",
+ "list_files_cmd" => "hg manifest -R \$file",
);
my $conf = which_conf(".get_maintainer.conf");
@@ -214,6 +217,14 @@
close($ignore);
}
+if ($#ARGV > 0) {
+ foreach (@ARGV) {
+ if ($_ =~ /^-{1,2}self-test(?:=|$)/) {
+ die "$P: using --self-test does not allow any other option or argument\n";
+ }
+ }
+}
+
if (!GetOptions(
'email!' => \$email,
'git!' => \$email_git,
@@ -250,6 +261,7 @@
'fe|file-emails!' => \$file_emails,
'f|file' => \$from_filename,
'find-maintainer-files' => \$find_maintainer_files,
+ 'self-test:s' => \$self_test,
'v|version' => \$version,
'h|help|usage' => \$help,
)) {
@@ -266,6 +278,12 @@
exit 0;
}
+if (defined $self_test) {
+ read_all_maintainer_files();
+ self_test();
+ exit 0;
+}
+
if (-t STDIN && !@ARGV) {
# We're talking to a terminal, but have no command line arguments.
die "$P: missing patchfile or -f file - use --help if necessary\n";
@@ -309,14 +327,17 @@
my @typevalue = ();
my %keyword_hash;
my @mfiles = ();
+my @self_test_info = ();
sub read_maintainer_file {
my ($file) = @_;
open (my $maint, '<', "$file")
or die "$P: Can't open MAINTAINERS file '$file': $!\n";
+ my $i = 1;
while (<$maint>) {
my $line = $_;
+ chomp $line;
if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
@@ -336,9 +357,12 @@
}
push(@typevalue, "$type:$value");
} elsif (!(/^\s*$/ || /^\s*\#/)) {
- $line =~ s/\n$//g;
push(@typevalue, $line);
}
+ if (defined $self_test) {
+ push(@self_test_info, {file=>$file, linenr=>$i, line=>$line});
+ }
+ $i++;
}
close($maint);
}
@@ -355,26 +379,30 @@
return grep { $_ !~ /^\.git$/; } @_;
}
-if (-d "${lk_path}MAINTAINERS") {
- opendir(DIR, "${lk_path}MAINTAINERS") or die $!;
- my @files = readdir(DIR);
- closedir(DIR);
- foreach my $file (@files) {
- push(@mfiles, "${lk_path}MAINTAINERS/$file") if ($file !~ /^\./);
+read_all_maintainer_files();
+
+sub read_all_maintainer_files {
+ if (-d "${lk_path}MAINTAINERS") {
+ opendir(DIR, "${lk_path}MAINTAINERS") or die $!;
+ my @files = readdir(DIR);
+ closedir(DIR);
+ foreach my $file (@files) {
+ push(@mfiles, "${lk_path}MAINTAINERS/$file") if ($file !~ /^\./);
+ }
}
-}
-if ($find_maintainer_files) {
- find( { wanted => \&find_is_maintainer_file,
- preprocess => \&find_ignore_git,
- no_chdir => 1,
- }, "${lk_path}");
-} else {
- push(@mfiles, "${lk_path}MAINTAINERS") if -f "${lk_path}MAINTAINERS";
-}
+ if ($find_maintainer_files) {
+ find( { wanted => \&find_is_maintainer_file,
+ preprocess => \&find_ignore_git,
+ no_chdir => 1,
+ }, "${lk_path}");
+ } else {
+ push(@mfiles, "${lk_path}MAINTAINERS") if -f "${lk_path}MAINTAINERS";
+ }
-foreach my $file (@mfiles) {
- read_maintainer_file("$file");
+ foreach my $file (@mfiles) {
+ read_maintainer_file("$file");
+ }
}
#
@@ -584,6 +612,135 @@
exit($exit);
+sub self_test {
+ my @lsfiles = ();
+ my @good_links = ();
+ my @bad_links = ();
+ my @section_headers = ();
+ my $index = 0;
+
+ @lsfiles = vcs_list_files($lk_path);
+
+ for my $x (@self_test_info) {
+ $index++;
+
+ ## Section header duplication and missing section content
+ if (($self_test eq "" || $self_test =~ /\bsections\b/) &&
+ $x->{line} =~ /^\S[^:]/ &&
+ defined $self_test_info[$index] &&
+ $self_test_info[$index]->{line} =~ /^([A-Z]):\s*\S/) {
+ my $has_S = 0;
+ my $has_F = 0;
+ my $has_ML = 0;
+ my $status = "";
+ if (grep(m@^\Q$x->{line}\E@, @section_headers)) {
+ print("$x->{file}:$x->{linenr}: warning: duplicate section header\t$x->{line}\n");
+ } else {
+ push(@section_headers, $x->{line});
+ }
+ my $nextline = $index;
+ while (defined $self_test_info[$nextline] &&
+ $self_test_info[$nextline]->{line} =~ /^([A-Z]):\s*(\S.*)/) {
+ my $type = $1;
+ my $value = $2;
+ if ($type eq "S") {
+ $has_S = 1;
+ $status = $value;
+ } elsif ($type eq "F" || $type eq "N") {
+ $has_F = 1;
+ } elsif ($type eq "M" || $type eq "R" || $type eq "L") {
+ $has_ML = 1;
+ }
+ $nextline++;
+ }
+ if (!$has_ML && $status !~ /orphan|obsolete/i) {
+ print("$x->{file}:$x->{linenr}: warning: section without email address\t$x->{line}\n");
+ }
+ if (!$has_S) {
+ print("$x->{file}:$x->{linenr}: warning: section without status \t$x->{line}\n");
+ }
+ if (!$has_F) {
+ print("$x->{file}:$x->{linenr}: warning: section without file pattern\t$x->{line}\n");
+ }
+ }
+
+ next if ($x->{line} !~ /^([A-Z]):\s*(.*)/);
+
+ my $type = $1;
+ my $value = $2;
+
+ ## Filename pattern matching
+ if (($type eq "F" || $type eq "X") &&
+ ($self_test eq "" || $self_test =~ /\bpatterns\b/)) {
+ $value =~ s@\.@\\\.@g; ##Convert . to \.
+ $value =~ s/\*/\.\*/g; ##Convert * to .*
+ $value =~ s/\?/\./g; ##Convert ? to .
+ ##if pattern is a directory and it lacks a trailing slash, add one
+ if ((-d $value)) {
+ $value =~ s@([^/])$@$1/@;
+ }
+ if (!grep(m@^$value@, @lsfiles)) {
+ print("$x->{file}:$x->{linenr}: warning: no file matches\t$x->{line}\n");
+ }
+
+ ## Link reachability
+ } elsif (($type eq "W" || $type eq "Q" || $type eq "B") &&
+ $value =~ /^https?:/ &&
+ ($self_test eq "" || $self_test =~ /\blinks\b/)) {
+ next if (grep(m@^\Q$value\E$@, @good_links));
+ my $isbad = 0;
+ if (grep(m@^\Q$value\E$@, @bad_links)) {
+ $isbad = 1;
+ } else {
+ my $output = `wget --spider -q --no-check-certificate --timeout 10 --tries 1 $value`;
+ if ($? == 0) {
+ push(@good_links, $value);
+ } else {
+ push(@bad_links, $value);
+ $isbad = 1;
+ }
+ }
+ if ($isbad) {
+ print("$x->{file}:$x->{linenr}: warning: possible bad link\t$x->{line}\n");
+ }
+
+ ## SCM reachability
+ } elsif ($type eq "T" &&
+ ($self_test eq "" || $self_test =~ /\bscm\b/)) {
+ next if (grep(m@^\Q$value\E$@, @good_links));
+ my $isbad = 0;
+ if (grep(m@^\Q$value\E$@, @bad_links)) {
+ $isbad = 1;
+ } elsif ($value !~ /^(?:git|quilt|hg)\s+\S/) {
+ print("$x->{file}:$x->{linenr}: warning: malformed entry\t$x->{line}\n");
+ } elsif ($value =~ /^git\s+(\S+)(\s+([^\(]+\S+))?/) {
+ my $url = $1;
+ my $branch = "";
+ $branch = $3 if $3;
+ my $output = `git ls-remote --exit-code -h "$url" $branch > /dev/null 2>&1`;
+ if ($? == 0) {
+ push(@good_links, $value);
+ } else {
+ push(@bad_links, $value);
+ $isbad = 1;
+ }
+ } elsif ($value =~ /^(?:quilt|hg)\s+(https?:\S+)/) {
+ my $url = $1;
+ my $output = `wget --spider -q --no-check-certificate --timeout 10 --tries 1 $url`;
+ if ($? == 0) {
+ push(@good_links, $value);
+ } else {
+ push(@bad_links, $value);
+ $isbad = 1;
+ }
+ }
+ if ($isbad) {
+ print("$x->{file}:$x->{linenr}: warning: possible bad link\t$x->{line}\n");
+ }
+ }
+ }
+}
+
sub ignore_email_address {
my ($address) = @_;
@@ -861,6 +1018,7 @@
--sections => print all of the subsystem sections with pattern matches
--letters => print all matching 'letter' types from all matching sections
--mailmap => use .mailmap file (default: $email_use_mailmap)
+ --self-test => show potential issues with MAINTAINERS file content
--version => show version
--help => show this help information
@@ -2192,6 +2350,23 @@
return $exists;
}
+sub vcs_list_files {
+ my ($file) = @_;
+
+ my @lsfiles = ();
+
+ my $vcs_used = vcs_exists();
+ return 0 if (!$vcs_used);
+
+ my $cmd = $VCS_cmds{"list_files_cmd"};
+ $cmd =~ s/(\$\w+)/$1/eeg; # interpolate $cmd
+ @lsfiles = &{$VCS_cmds{"execute_cmd"}}($cmd);
+
+ return () if ($? != 0);
+
+ return @lsfiles;
+}
+
sub uniq {
my (@parms) = @_;
diff --git a/test/dm/clk.c b/test/dm/clk.c
index 712a1e6..d364910 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -101,3 +101,40 @@
return 0;
}
DM_TEST(dm_test_clk, DM_TESTF_SCAN_FDT);
+
+static int dm_test_clk_bulk(struct unit_test_state *uts)
+{
+ struct udevice *dev_clk, *dev_test;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
+ &dev_clk));
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
+ &dev_test));
+ ut_assertok(sandbox_clk_test_get_bulk(dev_test));
+
+ ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+ ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+ /* Fixed clock does not support enable, thus should not fail */
+ ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
+ ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+ ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+ /* Fixed clock does not support disable, thus should not fail */
+ ut_assertok(sandbox_clk_test_disable_bulk(dev_test));
+ ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+ ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+ /* Fixed clock does not support enable, thus should not fail */
+ ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
+ ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+ ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+ /* Fixed clock does not support disable, thus should not fail */
+ ut_assertok(sandbox_clk_test_release_bulk(dev_test));
+ ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+ ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+ return 0;
+}
+DM_TEST(dm_test_clk_bulk, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/reset.c b/test/dm/reset.c
index 0ae8031..8dc0023 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c
@@ -13,6 +13,9 @@
/* This must match the specifier for mbox-names="test" in the DT node */
#define TEST_RESET_ID 2
+/* This is the other reset phandle specifier handled by bulk */
+#define OTHER_RESET_ID 2
+
static int dm_test_reset(struct unit_test_state *uts)
{
struct udevice *dev_reset;
@@ -37,3 +40,33 @@
return 0;
}
DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
+
+static int dm_test_reset_bulk(struct unit_test_state *uts)
+{
+ struct udevice *dev_reset;
+ struct udevice *dev_test;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl",
+ &dev_reset));
+ ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+ ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
+ &dev_test));
+ ut_assertok(sandbox_reset_test_get_bulk(dev_test));
+
+ ut_assertok(sandbox_reset_test_assert_bulk(dev_test));
+ ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+ ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+ ut_assertok(sandbox_reset_test_deassert_bulk(dev_test));
+ ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+ ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+ ut_assertok(sandbox_reset_test_release_bulk(dev_test));
+ ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+ ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+ return 0;
+}
+DM_TEST(dm_test_reset_bulk, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 920ccbf..0d11bfd 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -419,3 +419,46 @@
return 0;
}
DM_TEST(dm_test_first_next_ok_device, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static const struct udevice_id fdt_dummy_ids[] = {
+ { .compatible = "denx,u-boot-fdt-dummy", },
+ { }
+};
+
+UCLASS_DRIVER(fdt_dummy) = {
+ .name = "fdt_dummy",
+ .id = UCLASS_TEST_DUMMY,
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
+
+U_BOOT_DRIVER(fdt_dummy_drv) = {
+ .name = "fdt_dummy_drv",
+ .of_match = fdt_dummy_ids,
+ .id = UCLASS_TEST_DUMMY,
+};
+
+static int dm_test_fdt_translation(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ /* Some simple translations */
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
+ ut_asserteq_str("dev@0,0", dev->name);
+ ut_asserteq(0x8000, dev_read_addr(dev));
+
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 1, true, &dev));
+ ut_asserteq_str("dev@1,100", dev->name);
+ ut_asserteq(0x9000, dev_read_addr(dev));
+
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 2, true, &dev));
+ ut_asserteq_str("dev@2,200", dev->name);
+ ut_asserteq(0xA000, dev_read_addr(dev));
+
+ /* No translation for busses with #size-cells == 0 */
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 3, true, &dev));
+ ut_asserteq_str("dev@42", dev->name);
+ ut_asserteq(0x42, dev_read_addr(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_fdt_translation, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/video.c b/test/dm/video.c
index 29917d0..caca496 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -186,7 +186,7 @@
/* test colors (30-37 fg color, 40-47 bg color) */
vidconsole_put_string(con, ANSI_ESC"[30;41mfoo"); /* black on red */
vidconsole_put_string(con, ANSI_ESC"[33;44mbar"); /* yellow on blue */
- ut_asserteq(268, compress_frame_buffer(dev));
+ ut_asserteq(265, compress_frame_buffer(dev));
return 0;
}
diff --git a/test/py/README.md b/test/py/README.md
index eefac37..aed2fd0 100644
--- a/test/py/README.md
+++ b/test/py/README.md
@@ -150,7 +150,7 @@
option takes a single argument which is used to filter test names. Simple
logical operators are supported. For example:
- `'ums'` runs only tests with "ums" in their name.
- - ``ut_dm'` runs only tests with "ut_dm" in their name. Note that in this
+ - `'ut_dm'` runs only tests with "ut_dm" in their name. Note that in this
case, "ut_dm" is a parameter to a test rather than the test name. The full
test name is e.g. "test_ut[ut_dm_leak]".
- `'not reset'` runs everything except tests with "reset" in their name.
@@ -320,7 +320,7 @@
```bash
PATH=$HOME/ubtest/bin:$PATH \
- PYTHONPATH=${HOME}/ubtest/py:${PYTHONPATH} \
+ PYTHONPATH=${HOME}/ubtest/py/${HOSTNAME}:${PYTHONPATH} \
./test/py/test.py --bd seaboard
```
@@ -331,7 +331,7 @@
```bash
CROSS_COMPILE=arm-none-eabi- \
PATH=$HOME/ubtest/bin:$PATH \
- PYTHONPATH=${HOME}/ubtest/py:${PYTHONPATH} \
+ PYTHONPATH=${HOME}/ubtest/py/${HOSTNAME}:${PYTHONPATH} \
./test/py/test.py --bd seaboard --build
```
diff --git a/test/py/conftest.py b/test/py/conftest.py
index 3fe91e8..83eaca4 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -344,6 +344,7 @@
tests_xpassed = []
tests_xfailed = []
tests_skipped = []
+tests_warning = []
tests_passed = []
def pytest_itemcollected(item):
@@ -380,6 +381,11 @@
if log:
with log.section('Status Report', 'status_report'):
log.status_pass('%d passed' % len(tests_passed))
+ if tests_warning:
+ log.status_warning('%d passed with warning' % len(tests_warning))
+ for test in tests_warning:
+ anchor = anchors.get(test, None)
+ log.status_warning('... ' + test, anchor)
if tests_skipped:
log.status_skipped('%d skipped' % len(tests_skipped))
for test in tests_skipped:
@@ -520,7 +526,9 @@
A list of pytest reports (test result data).
"""
+ log.get_and_reset_warning()
reports = runtestprotocol(item, nextitem=nextitem)
+ was_warning = log.get_and_reset_warning()
# In pytest 3, runtestprotocol() may not call pytest_runtest_setup() if
# the test is skipped. That call is required to create the test's section
@@ -531,9 +539,14 @@
start_test_section(item)
failure_cleanup = False
- test_list = tests_passed
- msg = 'OK'
- msg_log = log.status_pass
+ if not was_warning:
+ test_list = tests_passed
+ msg = 'OK'
+ msg_log = log.status_pass
+ else:
+ test_list = tests_warning
+ msg = 'OK (with warning)'
+ msg_log = log.status_warning
for report in reports:
if report.outcome == 'failed':
if hasattr(report, 'wasxfail'):
diff --git a/test/py/multiplexed_log.css b/test/py/multiplexed_log.css
index 9b7c44f..562f69f 100644
--- a/test/py/multiplexed_log.css
+++ b/test/py/multiplexed_log.css
@@ -70,6 +70,10 @@
color: #00ff00
}
+.status-warning {
+ color: #ffff00
+}
+
.status-skipped {
color: #ffff00
}
diff --git a/test/py/multiplexed_log.py b/test/py/multiplexed_log.py
index 8ca5153..a2cfd71 100644
--- a/test/py/multiplexed_log.py
+++ b/test/py/multiplexed_log.py
@@ -224,6 +224,7 @@
self.timestamp_start = self._get_time()
self.timestamp_prev = self.timestamp_start
self.timestamp_blocks = []
+ self.seen_warning = False
shutil.copy(mod_dir + '/multiplexed_log.css', os.path.dirname(fn))
self.f.write('''\
@@ -252,6 +253,7 @@
passed_bcs = passed_bcs.not(":has(.status-xfail)");
passed_bcs = passed_bcs.not(":has(.status-xpass)");
passed_bcs = passed_bcs.not(":has(.status-skipped)");
+ passed_bcs = passed_bcs.not(":has(.status-warning)");
// Hide the passed blocks
passed_bcs.addClass("hidden");
// Flip the expand/contract button hiding for those blocks.
@@ -478,8 +480,23 @@
Nothing.
"""
+ self.seen_warning = True
self._note("warning", msg)
+ def get_and_reset_warning(self):
+ """Get and reset the log warning flag.
+
+ Args:
+ None
+
+ Returns:
+ Whether a warning was seen since the last call.
+ """
+
+ ret = self.seen_warning
+ self.seen_warning = False
+ return ret
+
def info(self, msg):
"""Write an informational note to the log file.
@@ -542,6 +559,19 @@
self._note("status-pass", msg, anchor)
+ def status_warning(self, msg, anchor=None):
+ """Write a note to the log file describing test(s) which passed.
+
+ Args:
+ msg: A message describing the passed test(s).
+ anchor: Optional internal link target.
+
+ Returns:
+ Nothing.
+ """
+
+ self._note("status-warning", msg, anchor)
+
def status_skipped(self, msg, anchor=None):
"""Write a note to the log file describing skipped test(s).
diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py
index 66b799b..b1ef6bd 100644
--- a/test/py/tests/test_efi_selftest.py
+++ b/test/py/tests/test_efi_selftest.py
@@ -25,6 +25,20 @@
u_boot_console.restart_uboot();
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
+@pytest.mark.buildconfigspec('of_control')
+def test_efi_selftest_device_tree(u_boot_console):
+ u_boot_console.run_command(cmd='setenv efi_selftest list')
+ output = u_boot_console.run_command('bootefi selftest')
+ assert '\'device tree\'' in output
+ u_boot_console.run_command(cmd='setenv efi_selftest device tree')
+ u_boot_console.run_command(cmd='setenv -f serial# Testing DT')
+ u_boot_console.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False)
+ m = u_boot_console.p.expect(['serial-number: Testing DT', 'U-Boot'])
+ if m != 0:
+ raise Exception('Reset failed in \'device tree\' test')
+ u_boot_console.restart_uboot();
+
+@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
def test_efi_selftest_watchdog_reboot(u_boot_console):
u_boot_console.run_command(cmd='setenv efi_selftest list')
output = u_boot_console.run_command('bootefi selftest')
diff --git a/test/py/tests/test_mmc_rd.py b/test/py/tests/test_mmc_rd.py
new file mode 100644
index 0000000..7ff7622
--- /dev/null
+++ b/test/py/tests/test_mmc_rd.py
@@ -0,0 +1,129 @@
+# Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+# Test U-Boot's "mmc read" command. The test reads data from the eMMC or SD
+# card, and validates the no errors occurred, and that the expected data was
+# read if the test configuration contains a CRC of the expected data.
+
+import pytest
+import u_boot_utils
+
+"""
+This test relies on boardenv_* to containing configuration values to define
+which MMC devices should be tested. For example:
+
+env__mmc_rd_configs = (
+ {
+ "fixture_id": "emmc-boot0",
+ "is_emmc": True,
+ "devid": 0,
+ "partid": 1,
+ "sector": 0x10,
+ "count": 1,
+ },
+ {
+ "fixture_id": "emmc-boot1",
+ "is_emmc": True,
+ "devid": 0,
+ "partid": 2,
+ "sector": 0x10,
+ "count": 1,
+ },
+ {
+ "fixture_id": "emmc-data",
+ "is_emmc": True,
+ "devid": 0,
+ "partid": 0,
+ "sector": 0x10,
+ "count": 0x1000,
+ },
+ {
+ "fixture_id": "sd-mbr",
+ "is_emmc": False,
+ "devid": 1,
+ "partid": None,
+ "sector": 0,
+ "count": 1,
+ "crc32": "8f6ecf0d",
+ },
+ {
+ "fixture_id": "sd-large",
+ "is_emmc": False,
+ "devid": 1,
+ "partid": None,
+ "sector": 0x10,
+ "count": 0x1000,
+ },
+)
+"""
+
+@pytest.mark.buildconfigspec('cmd_mmc')
+def test_mmc_rd(u_boot_console, env__mmc_rd_config):
+ """Test the "mmc read" command.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ env__mmc_rd_config: The single MMC configuration on which
+ to run the test. See the file-level comment above for details
+ of the format.
+
+ Returns:
+ Nothing.
+ """
+
+ is_emmc = env__mmc_rd_config['is_emmc']
+ devid = env__mmc_rd_config['devid']
+ partid = env__mmc_rd_config.get('partid', 0)
+ sector = env__mmc_rd_config.get('sector', 0)
+ count_sectors = env__mmc_rd_config.get('count', 1)
+ expected_crc32 = env__mmc_rd_config.get('crc32', None)
+
+ count_bytes = count_sectors * 512
+ bcfg = u_boot_console.config.buildconfig
+ has_cmd_memory = bcfg.get('config_cmd_memory', 'n') == 'y'
+ has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
+ ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ addr = '0x%08x' % ram_base
+
+ # Select MMC device
+ cmd = 'mmc dev %d' % devid
+ if is_emmc:
+ cmd += ' %d' % partid
+ response = u_boot_console.run_command(cmd)
+ assert 'no card present' not in response
+ if is_emmc:
+ partid_response = "(part %d)" % partid
+ else:
+ partid_response = ""
+ good_response = 'mmc%d%s is current device' % (devid, partid_response)
+ assert good_response in response
+
+ # Clear target RAM
+ if expected_crc32:
+ if has_cmd_memory and has_cmd_crc32:
+ cmd = 'mw.b %s 0 0x%x' % (addr, count_bytes)
+ u_boot_console.run_command(cmd)
+
+ cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ assert expected_crc32 not in response
+ else:
+ u_boot_console.log.warning(
+ 'CONFIG_CMD_MEMORY or CONFIG_CMD_CRC32 != y: Skipping RAM clear')
+
+ # Read data
+ cmd = 'mmc read %s %x %x' % (addr, sector, count_sectors)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (
+ devid, sector, count_sectors, count_sectors)
+ assert good_response in response
+
+ # Check target RAM
+ if expected_crc32:
+ if has_cmd_crc32:
+ cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ assert expected_crc32 in response
+ else:
+ u_boot_console.log.warning('CONFIG_CMD_CRC32 != y: Skipping check')
diff --git a/test/py/tests/test_sf.py b/test/py/tests/test_sf.py
new file mode 100644
index 0000000..95a7564
--- /dev/null
+++ b/test/py/tests/test_sf.py
@@ -0,0 +1,218 @@
+# Copyright (c) 2016, Xilinx Inc. Michal Simek
+# Copyright (c) 2017, Xiphos Systems Corp. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+import re
+import pytest
+import random
+import u_boot_utils
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+which SPI Flash areas are available for testing. Without this, this test will
+be automatically skipped.
+For example:
+
+# A list of sections of Flash memory to be tested.
+env__sf_configs = (
+ {
+ # Where in SPI Flash should the test operate.
+ 'offset': 0x00000000,
+ # This value is optional.
+ # If present, specifies the [[bus:]cs] argument used in `sf probe`
+ # If missing, defaults to 0.
+ 'id': '0:1',
+ # This value is optional.
+ # If set as a number, specifies the speed of the SPI Flash.
+ # If set as an array of 2, specifies a range for a random speed.
+ # If missing, defaults to 0.
+ 'speed': 1000000,
+ # This value is optional.
+ # If present, specifies the size to use for read/write operations.
+ # If missing, the SPI Flash page size is used as a default (based on
+ # the `sf probe` output).
+ 'len': 0x10000,
+ # This value is optional.
+ # If present, specifies if the test can write to Flash offset
+ # If missing, defaults to False.
+ 'writeable': False,
+ # This value is optional.
+ # If present, specifies the expected CRC32 value of the flash area.
+ # If missing, extra check is ignored.
+ 'crc32': 0xCAFECAFE,
+ },
+)
+"""
+
+def sf_prepare(u_boot_console, env__sf_config):
+ """Check global state of the SPI Flash before running any test.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ env__sf_config: The single SPI Flash device configuration on which to
+ run the tests.
+
+ Returns:
+ sf_params: a dictionary of SPI Flash parameters.
+ """
+
+ sf_params = {}
+ sf_params['ram_base'] = u_boot_utils.find_ram_base(u_boot_console)
+
+ probe_id = env__sf_config.get('id', 0)
+ speed = env__sf_config.get('speed', 0)
+ if isinstance(speed, int):
+ sf_params['speed'] = speed
+ else:
+ assert len(speed) == 2, "If speed is a list, it must have 2 entries"
+ sf_params['speed'] = random.randint(speed[0], speed[1])
+
+ cmd = 'sf probe %d %d' % (probe_id, sf_params['speed'])
+
+ output = u_boot_console.run_command(cmd)
+ assert 'SF: Detected' in output, 'No Flash device available'
+
+ m = re.search('page size (.+?) Bytes', output)
+ assert m, 'SPI Flash page size not recognized'
+ sf_params['page_size'] = int(m.group(1))
+
+ m = re.search('erase size (.+?) KiB', output)
+ assert m, 'SPI Flash erase size not recognized'
+ sf_params['erase_size'] = int(m.group(1))
+ sf_params['erase_size'] *= 1024
+
+ m = re.search('total (.+?) MiB', output)
+ assert m, 'SPI Flash total size not recognized'
+ sf_params['total_size'] = int(m.group(1))
+ sf_params['total_size'] *= 1024 * 1024
+
+ assert 'offset' in env__sf_config, \
+ '\'offset\' is required for this test.'
+ sf_params['len'] = env__sf_config.get('len', sf_params['erase_size'])
+
+ assert not env__sf_config['offset'] % sf_params['erase_size'], \
+ 'offset not multiple of erase size.'
+ assert not sf_params['len'] % sf_params['erase_size'], \
+ 'erase length not multiple of erase size.'
+
+ assert not (env__sf_config.get('writeable', False) and
+ 'crc32' in env__sf_config), \
+ 'Cannot check crc32 on writeable sections'
+
+ return sf_params
+
+def sf_read(u_boot_console, env__sf_config, sf_params):
+ """Helper function used to read and compute the CRC32 value of a section of
+ SPI Flash memory.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ env__sf_config: The single SPI Flash device configuration on which to
+ run the tests.
+ sf_params: SPI Flash parameters.
+
+ Returns:
+ CRC32 value of SPI Flash section
+ """
+
+ addr = sf_params['ram_base']
+ offset = env__sf_config['offset']
+ count = sf_params['len']
+ pattern = random.randint(0, 0xFF)
+ crc_expected = env__sf_config.get('crc32', None)
+
+ cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
+ u_boot_console.run_command(cmd)
+ crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+ if crc_expected:
+ assert crc_pattern != crc_expected
+
+ cmd = 'sf read %08x %08x %x' % (addr, offset, count)
+ response = u_boot_console.run_command(cmd)
+ assert 'Read: OK' in response, 'Read operation failed'
+ crc_readback = u_boot_utils.crc32(u_boot_console, addr, count)
+ assert crc_pattern != crc_readback, 'sf read did not update RAM content.'
+ if crc_expected:
+ assert crc_readback == crc_expected
+
+ return crc_readback
+
+def sf_update(u_boot_console, env__sf_config, sf_params):
+ """Helper function used to update a section of SPI Flash memory.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ env__sf_config: The single SPI Flash device configuration on which to
+ run the tests.
+
+ Returns:
+ CRC32 value of SPI Flash section
+ """
+
+ addr = sf_params['ram_base']
+ offset = env__sf_config['offset']
+ count = sf_params['len']
+ pattern = int(random.random() * 0xFF)
+
+ cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
+ u_boot_console.run_command(cmd)
+ crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+
+ cmd = 'sf update %08x %08x %x' % (addr, offset, count)
+ u_boot_console.run_command(cmd)
+ crc_readback = sf_read(u_boot_console, env__sf_config, sf_params)
+
+ assert crc_readback == crc_pattern
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_read(u_boot_console, env__sf_config):
+ sf_params = sf_prepare(u_boot_console, env__sf_config)
+ sf_read(u_boot_console, env__sf_config, sf_params)
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_read_twice(u_boot_console, env__sf_config):
+ sf_params = sf_prepare(u_boot_console, env__sf_config)
+
+ crc1 = sf_read(u_boot_console, env__sf_config, sf_params)
+ sf_params['ram_base'] += 0x100
+ crc2 = sf_read(u_boot_console, env__sf_config, sf_params)
+
+ assert crc1 == crc2, 'CRC32 of two successive read operation do not match'
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_erase(u_boot_console, env__sf_config):
+ if not env__sf_config.get('writeable', False):
+ pytest.skip('Flash config is tagged as not writeable')
+
+ sf_params = sf_prepare(u_boot_console, env__sf_config)
+ addr = sf_params['ram_base']
+ offset = env__sf_config['offset']
+ count = sf_params['len']
+
+ cmd = 'sf erase %08x %x' % (offset, count)
+ output = u_boot_console.run_command(cmd)
+ assert 'Erased: OK' in output, 'Erase operation failed'
+
+ cmd = 'mw.b %08x ff %x' % (addr, count)
+ u_boot_console.run_command(cmd)
+ crc_ffs = u_boot_utils.crc32(u_boot_console, addr, count)
+
+ crc_read = sf_read(u_boot_console, env__sf_config, sf_params)
+ assert crc_ffs == crc_read, 'Unexpected CRC32 after erase operation.'
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_update(u_boot_console, env__sf_config):
+ if not env__sf_config.get('writeable', False):
+ pytest.skip('Flash config is tagged as not writeable')
+
+ sf_params = sf_prepare(u_boot_console, env__sf_config)
+ sf_update(u_boot_console, env__sf_config, sf_params)
diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 9acb92d..de9ee26 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -11,7 +11,7 @@
import pytest
import sys
import time
-import pytest
+import re
def md5sum_data(data):
"""Calculate the MD5 hash of some data.
@@ -311,3 +311,25 @@
"""
return PersistentFileHelperCtxMgr(u_boot_log, filename)
+
+def crc32(u_boot_console, address, count):
+ """Helper function used to compute the CRC32 value of a section of RAM.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ address: Address where data starts.
+ count: Amount of data to use for calculation.
+
+ Returns:
+ CRC32 value
+ """
+
+ bcfg = u_boot_console.config.buildconfig
+ has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
+ assert has_cmd_crc32, 'Cannot compute crc32 without CONFIG_CMD_CRC32.'
+ output = u_boot_console.run_command('crc32 %08x %x' % (address, count))
+
+ m = re.search('==> ([0-9a-fA-F]{8})$', output)
+ assert m, 'CRC32 operation failed.'
+
+ return m.group(1)
diff --git a/tools/Makefile b/tools/Makefile
index f38f68e..8143c25 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -7,6 +7,7 @@
# Enable all the config-independent tools
ifneq ($(HOST_TOOLS_ALL),)
+CONFIG_KIRKWOOD = y
CONFIG_LCD_LOGO = y
CONFIG_CMD_LOADS = y
CONFIG_CMD_NET = y
@@ -103,6 +104,7 @@
pblimage.o \
pbl_crc32.o \
vybridimage.o \
+ stm32image.o \
$(ROCKCHIP_OBS) \
socfpgaimage.o \
lib/sha1.o \
diff --git a/tools/default_image.c b/tools/default_image.c
index 4e5568e..c67f66b 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -18,6 +18,7 @@
#include "mkimage.h"
#include <image.h>
+#include <tee/optee.h>
#include <u-boot/crc.h>
static image_header_t header;
@@ -90,6 +91,8 @@
uint32_t checksum;
time_t time;
uint32_t imagesize;
+ uint32_t ep;
+ uint32_t addr;
image_header_t * hdr = (image_header_t *)ptr;
@@ -99,18 +102,26 @@
sbuf->st_size - sizeof(image_header_t));
time = imagetool_get_source_date(params, sbuf->st_mtime);
+ ep = params->ep;
+ addr = params->addr;
+
if (params->type == IH_TYPE_FIRMWARE_IVT)
/* Add size of CSF minus IVT */
imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0;
else
imagesize = sbuf->st_size - sizeof(image_header_t);
+ if (params->os == IH_OS_TEE) {
+ addr = optee_image_get_load_addr(hdr);
+ ep = optee_image_get_entry_point(hdr);
+ }
+
/* Build new header */
image_set_magic(hdr, IH_MAGIC);
image_set_time(hdr, time);
image_set_size(hdr, imagesize);
- image_set_load(hdr, params->addr);
- image_set_ep(hdr, params->ep);
+ image_set_load(hdr, addr);
+ image_set_ep(hdr, ep);
image_set_dcrc(hdr, checksum);
image_set_os(hdr, params->os);
image_set_arch(hdr, params->arch);
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 0e3e343..77eac3d 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -14,6 +14,7 @@
#include <errno.h>
#include <env_flags.h>
#include <fcntl.h>
+#include <libgen.h>
#include <linux/fs.h>
#include <linux/stringify.h>
#include <ctype.h>
@@ -64,14 +65,14 @@
int is_ubi; /* set if we use UBI volume */
};
-static struct envdev_s envdevices[2] =
-{
+static struct envdev_s envdevices[2] = {
{
.mtd_type = MTD_ABSENT,
}, {
.mtd_type = MTD_ABSENT,
},
};
+
static int dev_current;
#define DEVNAME(i) envdevices[(i)].devname
@@ -88,14 +89,14 @@
#define ENV_SIZE usable_envsize
struct env_image_single {
- uint32_t crc; /* CRC32 over data bytes */
- char data[];
+ uint32_t crc; /* CRC32 over data bytes */
+ char data[];
};
struct env_image_redundant {
- uint32_t crc; /* CRC32 over data bytes */
- unsigned char flags; /* active or obsolete */
- char data[];
+ uint32_t crc; /* CRC32 over data bytes */
+ unsigned char flags; /* active or obsolete */
+ char data[];
};
enum flag_scheme {
@@ -105,18 +106,18 @@
};
struct environment {
- void *image;
- uint32_t *crc;
- unsigned char *flags;
- char *data;
- enum flag_scheme flag_scheme;
+ void *image;
+ uint32_t *crc;
+ unsigned char *flags;
+ char *data;
+ enum flag_scheme flag_scheme;
};
static struct environment environment = {
.flag_scheme = FLAG_NONE,
};
-static int HaveRedundEnv = 0;
+static int have_redund_env;
static unsigned char active_flag = 1;
/* obsolete_flag must be 0 to efficiently set it on NOR flash without erasing */
@@ -347,11 +348,11 @@
return 0;
}
-static int flash_io (int mode);
+static int flash_io(int mode);
static int parse_config(struct env_opts *opts);
#if defined(CONFIG_FILE)
-static int get_config (char *);
+static int get_config(char *);
#endif
static char *skip_chars(char *s)
@@ -394,7 +395,7 @@
* Search the environment for a variable.
* Return the value, if found, or NULL, if not found.
*/
-char *fw_getenv (char *name)
+char *fw_getenv(char *name)
{
char *env, *nxt;
@@ -403,12 +404,12 @@
for (nxt = env; *nxt; ++nxt) {
if (nxt >= &environment.data[ENV_SIZE]) {
- fprintf (stderr, "## Error: "
+ fprintf(stderr, "## Error: "
"environment not terminated\n");
return NULL;
}
}
- val = envmatch (name, env);
+ val = envmatch(name, env);
if (!val)
continue;
return val;
@@ -462,18 +463,18 @@
if (fw_env_open(opts))
return -1;
- if (argc == 0) { /* Print all env variables */
+ if (argc == 0) { /* Print all env variables */
char *env, *nxt;
for (env = environment.data; *env; env = nxt + 1) {
for (nxt = env; *nxt; ++nxt) {
if (nxt >= &environment.data[ENV_SIZE]) {
- fprintf (stderr, "## Error: "
+ fprintf(stderr, "## Error: "
"environment not terminated\n");
return -1;
}
}
- printf ("%s\n", env);
+ printf("%s\n", env);
}
fw_env_close(opts);
return 0;
@@ -485,7 +486,7 @@
val = fw_getenv(name);
if (!val) {
- fprintf (stderr, "## Error: \"%s\" not defined\n", name);
+ fprintf(stderr, "## Error: \"%s\" not defined\n", name);
rc = -1;
continue;
}
@@ -515,15 +516,13 @@
/* write environment back to flash */
if (flash_io(O_RDWR)) {
- fprintf(stderr,
- "Error: can't write fw_env to flash\n");
- return -1;
+ fprintf(stderr, "Error: can't write fw_env to flash\n");
+ return -1;
}
return 0;
}
-
/*
* Set/Clear a single variable in the environment.
* This is called in sequence to update the environment
@@ -548,7 +547,8 @@
return -1;
}
}
- if ((oldval = envmatch (name, env)) != NULL)
+ oldval = envmatch(name, env);
+ if (oldval)
break;
}
@@ -571,7 +571,7 @@
errno = EROFS;
return -1;
} else if (env_flags_validate_varaccess(name,
- ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR)) {
+ ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR)) {
const char *defval = fw_getdefenv(name);
if (defval == NULL)
@@ -615,21 +615,21 @@
/*
* Append new definition at the end
*/
- for (env = environment.data; *env || *(env + 1); ++env);
+ for (env = environment.data; *env || *(env + 1); ++env)
+ ;
if (env > environment.data)
++env;
/*
* Overflow when:
* "name" + "=" + "val" +"\0\0" > CUR_ENVSIZE - (env-environment)
*/
- len = strlen (name) + 2;
+ len = strlen(name) + 2;
/* add '=' for first arg, ' ' for all others */
len += strlen(value) + 1;
if (len > (&environment.data[ENV_SIZE] - env)) {
- fprintf (stderr,
- "Error: environment overflow, \"%s\" deleted\n",
- name);
+ fprintf(stderr,
+ "Error: environment overflow, \"%s\" deleted\n", name);
return -1;
}
@@ -759,7 +759,7 @@
fp = fopen(fname, "r");
if (fp == NULL) {
fprintf(stderr, "I cannot open %s for reading\n",
- fname);
+ fname);
return -1;
}
}
@@ -774,7 +774,7 @@
*/
if (dump[len - 1] != '\n') {
fprintf(stderr,
- "Line %d not corrected terminated or too long\n",
+ "Line %d not corrected terminated or too long\n",
lineno);
ret = -1;
break;
@@ -807,7 +807,6 @@
else
val = NULL;
}
-
#ifdef DEBUG
fprintf(stderr, "Setting %s : %s\n",
name, val ? val : " removed");
@@ -824,7 +823,7 @@
*/
if (fw_env_write(name, val)) {
fprintf(stderr,
- "fw_env_write returns with error : %s\n",
+ "fw_env_write returns with error : %s\n",
strerror(errno));
ret = -1;
break;
@@ -867,13 +866,13 @@
int badblock = ioctl(fd, MEMGETBADBLOCK, &blockstart);
if (badblock < 0) {
- perror ("Cannot read bad block mark");
+ perror("Cannot read bad block mark");
return badblock;
}
if (badblock) {
#ifdef DEBUG
- fprintf (stderr, "Bad block at 0x%llx, skipping\n",
+ fprintf(stderr, "Bad block at 0x%llx, skipping\n",
(unsigned long long)blockstart);
#endif
return badblock;
@@ -888,8 +887,8 @@
* bad blocks but makes sure it stays within ENVSECTORS (dev) starting from
* the DEVOFFSET (dev) block. On NOR the loop is only run once.
*/
-static int flash_read_buf (int dev, int fd, void *buf, size_t count,
- off_t offset)
+static int flash_read_buf(int dev, int fd, void *buf, size_t count,
+ off_t offset)
{
size_t blocklen; /* erase / write length - one block on NAND,
0 on NOR */
@@ -901,7 +900,7 @@
MEMGETBADBLOCK needs 64 bits */
int rc;
- blockstart = (offset / DEVESIZE (dev)) * DEVESIZE (dev);
+ blockstart = (offset / DEVESIZE(dev)) * DEVESIZE(dev);
/* Offset inside a block */
block_seek = offset - blockstart;
@@ -911,7 +910,7 @@
* NAND: calculate which blocks we are reading. We have
* to read one block at a time to skip bad blocks.
*/
- blocklen = DEVESIZE (dev);
+ blocklen = DEVESIZE(dev);
/* Limit to one block for the first read */
if (readlen > blocklen - block_seek)
@@ -923,17 +922,16 @@
/* This only runs once on NOR flash */
while (processed < count) {
rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
- if (rc < 0) /* block test failed */
+ if (rc < 0) /* block test failed */
return -1;
if (blockstart + block_seek + readlen > environment_end(dev)) {
/* End of range is reached */
- fprintf (stderr,
- "Too few good blocks within range\n");
+ fprintf(stderr, "Too few good blocks within range\n");
return -1;
}
- if (rc) { /* block is bad */
+ if (rc) { /* block is bad */
blockstart += blocklen;
continue;
}
@@ -942,21 +940,21 @@
* If a block is bad, we retry in the next block at the same
* offset - see env/nand.c::writeenv()
*/
- lseek (fd, blockstart + block_seek, SEEK_SET);
+ lseek(fd, blockstart + block_seek, SEEK_SET);
- rc = read (fd, buf + processed, readlen);
+ rc = read(fd, buf + processed, readlen);
if (rc != readlen) {
- fprintf (stderr, "Read error on %s: %s\n",
- DEVNAME (dev), strerror (errno));
+ fprintf(stderr, "Read error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
return -1;
}
#ifdef DEBUG
fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
- rc, (unsigned long long) blockstart + block_seek,
+ rc, (unsigned long long)blockstart + block_seek,
DEVNAME(dev));
#endif
processed += readlen;
- readlen = min (blocklen, count - processed);
+ readlen = min(blocklen, count - processed);
block_seek = 0;
blockstart += blocklen;
}
@@ -1018,7 +1016,7 @@
* to the end of the block
*/
write_total = ((block_seek + count + blocklen - 1) /
- blocklen) * blocklen;
+ blocklen) * blocklen;
}
/*
@@ -1027,11 +1025,11 @@
* block back again.
*/
if (write_total > count) {
- data = malloc (erase_len);
+ data = malloc(erase_len);
if (!data) {
- fprintf (stderr,
- "Cannot malloc %zu bytes: %s\n",
- erase_len, strerror (errno));
+ fprintf(stderr,
+ "Cannot malloc %zu bytes: %s\n",
+ erase_len, strerror(errno));
return -1;
}
@@ -1047,13 +1045,13 @@
if (block_seek != 0)
fprintf(stderr, " and ");
fprintf(stderr, "0x%lx - 0x%lx",
- (unsigned long) block_seek + count,
- (unsigned long) write_total - 1);
+ (unsigned long)block_seek + count,
+ (unsigned long)write_total - 1);
}
fprintf(stderr, "\n");
#endif
/* Overwrite the old environment */
- memcpy (data + block_seek, buf, count);
+ memcpy(data + block_seek, buf, count);
} else {
/*
* We get here, iff offset is block-aligned and count is a
@@ -1077,15 +1075,15 @@
/* This only runs once on NOR flash and SPI-dataflash */
while (processed < write_total) {
rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
- if (rc < 0) /* block test failed */
+ if (rc < 0) /* block test failed */
return rc;
if (blockstart + erasesize > environment_end(dev)) {
- fprintf (stderr, "End of range reached, aborting\n");
+ fprintf(stderr, "End of range reached, aborting\n");
return -1;
}
- if (rc) { /* block is bad */
+ if (rc) { /* block is bad */
blockstart += blocklen;
continue;
}
@@ -1103,34 +1101,33 @@
}
}
- if (lseek (fd, blockstart, SEEK_SET) == -1) {
- fprintf (stderr,
- "Seek error on %s: %s\n",
- DEVNAME (dev), strerror (errno));
+ if (lseek(fd, blockstart, SEEK_SET) == -1) {
+ fprintf(stderr,
+ "Seek error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
return -1;
}
-
#ifdef DEBUG
fprintf(stderr, "Write 0x%llx bytes at 0x%llx\n",
- (unsigned long long) erasesize,
- (unsigned long long) blockstart);
+ (unsigned long long)erasesize,
+ (unsigned long long)blockstart);
#endif
- if (write (fd, data + processed, erasesize) != erasesize) {
- fprintf (stderr, "Write error on %s: %s\n",
- DEVNAME (dev), strerror (errno));
+ if (write(fd, data + processed, erasesize) != erasesize) {
+ fprintf(stderr, "Write error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
return -1;
}
if (DEVTYPE(dev) != MTD_ABSENT)
ioctl(fd, MEMLOCK, &erase);
- processed += erasesize;
+ processed += erasesize;
block_seek = 0;
blockstart += erasesize;
}
if (write_total > count)
- free (data);
+ free(data);
return processed;
}
@@ -1138,30 +1135,30 @@
/*
* Set obsolete flag at offset - NOR flash only
*/
-static int flash_flag_obsolete (int dev, int fd, off_t offset)
+static int flash_flag_obsolete(int dev, int fd, off_t offset)
{
int rc;
struct erase_info_user erase;
- erase.start = DEVOFFSET (dev);
- erase.length = DEVESIZE (dev);
+ erase.start = DEVOFFSET(dev);
+ erase.length = DEVESIZE(dev);
/* This relies on the fact, that obsolete_flag == 0 */
- rc = lseek (fd, offset, SEEK_SET);
+ rc = lseek(fd, offset, SEEK_SET);
if (rc < 0) {
- fprintf (stderr, "Cannot seek to set the flag on %s \n",
- DEVNAME (dev));
+ fprintf(stderr, "Cannot seek to set the flag on %s\n",
+ DEVNAME(dev));
return rc;
}
- ioctl (fd, MEMUNLOCK, &erase);
- rc = write (fd, &obsolete_flag, sizeof (obsolete_flag));
- ioctl (fd, MEMLOCK, &erase);
+ ioctl(fd, MEMUNLOCK, &erase);
+ rc = write(fd, &obsolete_flag, sizeof(obsolete_flag));
+ ioctl(fd, MEMLOCK, &erase);
if (rc < 0)
- perror ("Could not set obsolete flag");
+ perror("Could not set obsolete flag");
return rc;
}
-static int flash_write (int fd_current, int fd_target, int dev_target)
+static int flash_write(int fd_current, int fd_target, int dev_target)
{
int rc;
@@ -1175,14 +1172,14 @@
*environment.flags = active_flag;
break;
default:
- fprintf (stderr, "Unimplemented flash scheme %u \n",
- environment.flag_scheme);
+ fprintf(stderr, "Unimplemented flash scheme %u\n",
+ environment.flag_scheme);
return -1;
}
#ifdef DEBUG
fprintf(stderr, "Writing new environment at 0x%llx on %s\n",
- DEVOFFSET (dev_target), DEVNAME (dev_target));
+ DEVOFFSET(dev_target), DEVNAME(dev_target));
#endif
if (IS_UBI(dev_target)) {
@@ -1198,20 +1195,20 @@
if (environment.flag_scheme == FLAG_BOOLEAN) {
/* Have to set obsolete flag */
- off_t offset = DEVOFFSET (dev_current) +
- offsetof (struct env_image_redundant, flags);
+ off_t offset = DEVOFFSET(dev_current) +
+ offsetof(struct env_image_redundant, flags);
#ifdef DEBUG
fprintf(stderr,
"Setting obsolete flag in environment at 0x%llx on %s\n",
- DEVOFFSET (dev_current), DEVNAME (dev_current));
+ DEVOFFSET(dev_current), DEVNAME(dev_current));
#endif
- flash_flag_obsolete (dev_current, fd_current, offset);
+ flash_flag_obsolete(dev_current, fd_current, offset);
}
return 0;
}
-static int flash_read (int fd)
+static int flash_read(int fd)
{
int rc;
@@ -1229,72 +1226,153 @@
return 0;
}
-static int flash_io (int mode)
+static int flash_open_tempfile(const char **dname, const char **target_temp)
{
- int fd_current, fd_target, rc, dev_target;
+ char *dup_name = strdup(DEVNAME(dev_current));
+ char *temp_name = NULL;
+ int rc = -1;
+
+ if (!dup_name)
+ return -1;
+
+ *dname = dirname(dup_name);
+ if (!*dname)
+ goto err;
+
+ rc = asprintf(&temp_name, "%s/XXXXXX", *dname);
+ if (rc == -1)
+ goto err;
+
+ rc = mkstemp(temp_name);
+ if (rc == -1) {
+ /* fall back to in place write */
+ fprintf(stderr,
+ "Can't create %s: %s\n", temp_name, strerror(errno));
+ free(temp_name);
+ } else {
+ *target_temp = temp_name;
+ /* deliberately leak dup_name as dname /might/ point into
+ * it and we need it for our caller
+ */
+ dup_name = NULL;
+ }
+
+err:
+ if (dup_name)
+ free(dup_name);
+
+ return rc;
+}
+
+static int flash_io_write(int fd_current)
+{
+ int fd_target = -1, rc, dev_target;
+ const char *dname, *target_temp = NULL;
+
+ if (have_redund_env) {
+ /* switch to next partition for writing */
+ dev_target = !dev_current;
+ /* dev_target: fd_target, erase_target */
+ fd_target = open(DEVNAME(dev_target), O_RDWR);
+ if (fd_target < 0) {
+ fprintf(stderr,
+ "Can't open %s: %s\n",
+ DEVNAME(dev_target), strerror(errno));
+ rc = -1;
+ goto exit;
+ }
+ } else {
+ struct stat sb;
+
+ if (fstat(fd_current, &sb) == 0 && S_ISREG(sb.st_mode)) {
+ /* if any part of flash_open_tempfile() fails we fall
+ * back to in-place writes
+ */
+ fd_target = flash_open_tempfile(&dname, &target_temp);
+ }
+ dev_target = dev_current;
+ if (fd_target == -1)
+ fd_target = fd_current;
+ }
+
+ rc = flash_write(fd_current, fd_target, dev_target);
+
+ if (fsync(fd_current) && !(errno == EINVAL || errno == EROFS)) {
+ fprintf(stderr,
+ "fsync failed on %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
+ }
+
+ if (fd_current != fd_target) {
+ if (fsync(fd_target) &&
+ !(errno == EINVAL || errno == EROFS)) {
+ fprintf(stderr,
+ "fsync failed on %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
+ }
+
+ if (close(fd_target)) {
+ fprintf(stderr,
+ "I/O error on %s: %s\n",
+ DEVNAME(dev_target), strerror(errno));
+ rc = -1;
+ }
+
+ if (target_temp) {
+ int dir_fd;
+
+ dir_fd = open(dname, O_DIRECTORY | O_RDONLY);
+ if (dir_fd == -1)
+ fprintf(stderr,
+ "Can't open %s: %s\n",
+ dname, strerror(errno));
+
+ if (rename(target_temp, DEVNAME(dev_target))) {
+ fprintf(stderr,
+ "rename failed %s => %s: %s\n",
+ target_temp, DEVNAME(dev_target),
+ strerror(errno));
+ rc = -1;
+ }
+
+ if (dir_fd != -1 && fsync(dir_fd))
+ fprintf(stderr,
+ "fsync failed on %s: %s\n",
+ dname, strerror(errno));
+
+ if (dir_fd != -1 && close(dir_fd))
+ fprintf(stderr,
+ "I/O error on %s: %s\n",
+ dname, strerror(errno));
+ }
+ }
+ exit:
+ return rc;
+}
+
+static int flash_io(int mode)
+{
+ int fd_current, rc;
/* dev_current: fd_current, erase_current */
- fd_current = open (DEVNAME (dev_current), mode);
+ fd_current = open(DEVNAME(dev_current), mode);
if (fd_current < 0) {
- fprintf (stderr,
- "Can't open %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
+ fprintf(stderr,
+ "Can't open %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
return -1;
}
if (mode == O_RDWR) {
- if (HaveRedundEnv) {
- /* switch to next partition for writing */
- dev_target = !dev_current;
- /* dev_target: fd_target, erase_target */
- fd_target = open (DEVNAME (dev_target), mode);
- if (fd_target < 0) {
- fprintf (stderr,
- "Can't open %s: %s\n",
- DEVNAME (dev_target),
- strerror (errno));
- rc = -1;
- goto exit;
- }
- } else {
- dev_target = dev_current;
- fd_target = fd_current;
- }
-
- rc = flash_write (fd_current, fd_target, dev_target);
-
- if (fsync(fd_current) &&
- !(errno == EINVAL || errno == EROFS)) {
- fprintf (stderr,
- "fsync failed on %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
- }
-
- if (HaveRedundEnv) {
- if (fsync(fd_target) &&
- !(errno == EINVAL || errno == EROFS)) {
- fprintf (stderr,
- "fsync failed on %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
- }
-
- if (close (fd_target)) {
- fprintf (stderr,
- "I/O error on %s: %s\n",
- DEVNAME (dev_target),
- strerror (errno));
- rc = -1;
- }
- }
+ rc = flash_io_write(fd_current);
} else {
- rc = flash_read (fd_current);
+ rc = flash_read(fd_current);
}
-exit:
- if (close (fd_current)) {
- fprintf (stderr,
- "I/O error on %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
+ if (close(fd_current)) {
+ fprintf(stderr,
+ "I/O error on %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
return -1;
}
@@ -1322,7 +1400,7 @@
if (!opts)
opts = &default_opts;
- if (parse_config(opts)) /* should fill envdevices */
+ if (parse_config(opts)) /* should fill envdevices */
return -EINVAL;
addr0 = calloc(1, CUR_ENVSIZE);
@@ -1337,16 +1415,16 @@
/* read environment from FLASH to local buffer */
environment.image = addr0;
- if (HaveRedundEnv) {
+ if (have_redund_env) {
redundant = addr0;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
+ environment.crc = &redundant->crc;
+ environment.flags = &redundant->flags;
+ environment.data = redundant->data;
} else {
single = addr0;
- environment.crc = &single->crc;
- environment.flags = NULL;
- environment.data = single->data;
+ environment.crc = &single->crc;
+ environment.flags = NULL;
+ environment.data = single->data;
}
dev_current = 0;
@@ -1355,14 +1433,15 @@
goto open_cleanup;
}
- crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
+ crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE);
crc0_ok = (crc0 == *environment.crc);
- if (!HaveRedundEnv) {
+ if (!have_redund_env) {
if (!crc0_ok) {
- fprintf (stderr,
+ fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy(environment.data, default_environment, sizeof default_environment);
+ memcpy(environment.data, default_environment,
+ sizeof(default_environment));
}
} else {
flag0 = *environment.flags;
@@ -1406,12 +1485,12 @@
IS_UBI(dev_current) == IS_UBI(!dev_current)) {
environment.flag_scheme = FLAG_INCREMENTAL;
} else {
- fprintf (stderr, "Incompatible flash types!\n");
+ fprintf(stderr, "Incompatible flash types!\n");
ret = -EINVAL;
goto open_cleanup;
}
- crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
+ crc1 = crc32(0, (uint8_t *)redundant->data, ENV_SIZE);
crc1_ok = (crc1 == redundant->crc);
flag1 = redundant->flags;
@@ -1421,10 +1500,10 @@
} else if (!crc0_ok && crc1_ok) {
dev_current = 1;
} else if (!crc0_ok && !crc1_ok) {
- fprintf (stderr,
+ fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy (environment.data, default_environment,
- sizeof default_environment);
+ memcpy(environment.data, default_environment,
+ sizeof(default_environment));
dev_current = 0;
} else {
switch (environment.flag_scheme) {
@@ -1451,12 +1530,12 @@
else if ((flag1 == 255 && flag0 == 0) ||
flag0 >= flag1)
dev_current = 0;
- else /* flag1 > flag0 */
+ else /* flag1 > flag0 */
dev_current = 1;
break;
default:
- fprintf (stderr, "Unknown flag scheme %u \n",
- environment.flag_scheme);
+ fprintf(stderr, "Unknown flag scheme %u\n",
+ environment.flag_scheme);
return -1;
}
}
@@ -1467,15 +1546,15 @@
* flags before writing out
*/
if (dev_current) {
- environment.image = addr1;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
- free (addr0);
+ environment.image = addr1;
+ environment.crc = &redundant->crc;
+ environment.flags = &redundant->flags;
+ environment.data = redundant->data;
+ free(addr0);
} else {
- environment.image = addr0;
+ environment.image = addr0;
/* Other pointers are already set */
- free (addr1);
+ free(addr1);
}
#ifdef DEBUG
fprintf(stderr, "Selected env in %s\n", DEVNAME(dev_current));
@@ -1483,7 +1562,7 @@
}
return 0;
-open_cleanup:
+ open_cleanup:
if (addr0)
free(addr0);
@@ -1518,15 +1597,13 @@
fd = open(DEVNAME(dev), O_RDONLY);
if (fd < 0) {
fprintf(stderr,
- "Cannot open %s: %s\n",
- DEVNAME(dev), strerror(errno));
+ "Cannot open %s: %s\n", DEVNAME(dev), strerror(errno));
return -1;
}
rc = fstat(fd, &st);
if (rc < 0) {
- fprintf(stderr, "Cannot stat the file %s\n",
- DEVNAME(dev));
+ fprintf(stderr, "Cannot stat the file %s\n", DEVNAME(dev));
goto err;
}
@@ -1571,14 +1648,16 @@
if (DEVOFFSET(dev) < 0) {
rc = ioctl(fd, BLKGETSIZE64, &size);
if (rc < 0) {
- fprintf(stderr, "Could not get block device size on %s\n",
+ fprintf(stderr,
+ "Could not get block device size on %s\n",
DEVNAME(dev));
goto err;
}
DEVOFFSET(dev) = DEVOFFSET(dev) + size;
#ifdef DEBUG
- fprintf(stderr, "Calculated device offset 0x%llx on %s\n",
+ fprintf(stderr,
+ "Calculated device offset 0x%llx on %s\n",
DEVOFFSET(dev), DEVNAME(dev));
#endif
}
@@ -1589,18 +1668,20 @@
ENVSECTORS(dev) = DIV_ROUND_UP(ENVSIZE(dev), DEVESIZE(dev));
if (DEVOFFSET(dev) % DEVESIZE(dev) != 0) {
- fprintf(stderr, "Environment does not start on (erase) block boundary\n");
+ fprintf(stderr,
+ "Environment does not start on (erase) block boundary\n");
errno = EINVAL;
return -1;
}
if (ENVSIZE(dev) > ENVSECTORS(dev) * DEVESIZE(dev)) {
- fprintf(stderr, "Environment does not fit into available sectors\n");
+ fprintf(stderr,
+ "Environment does not fit into available sectors\n");
errno = EINVAL;
return -1;
}
-err:
+ err:
close(fd);
return rc;
}
@@ -1620,42 +1701,42 @@
return -1;
}
#else
- DEVNAME (0) = DEVICE1_NAME;
- DEVOFFSET (0) = DEVICE1_OFFSET;
- ENVSIZE (0) = ENV1_SIZE;
+ DEVNAME(0) = DEVICE1_NAME;
+ DEVOFFSET(0) = DEVICE1_OFFSET;
+ ENVSIZE(0) = ENV1_SIZE;
/* Set defaults for DEVESIZE, ENVSECTORS later once we
* know DEVTYPE
*/
#ifdef DEVICE1_ESIZE
- DEVESIZE (0) = DEVICE1_ESIZE;
+ DEVESIZE(0) = DEVICE1_ESIZE;
#endif
#ifdef DEVICE1_ENVSECTORS
- ENVSECTORS (0) = DEVICE1_ENVSECTORS;
+ ENVSECTORS(0) = DEVICE1_ENVSECTORS;
#endif
#ifdef HAVE_REDUND
- DEVNAME (1) = DEVICE2_NAME;
- DEVOFFSET (1) = DEVICE2_OFFSET;
- ENVSIZE (1) = ENV2_SIZE;
+ DEVNAME(1) = DEVICE2_NAME;
+ DEVOFFSET(1) = DEVICE2_OFFSET;
+ ENVSIZE(1) = ENV2_SIZE;
/* Set defaults for DEVESIZE, ENVSECTORS later once we
* know DEVTYPE
*/
#ifdef DEVICE2_ESIZE
- DEVESIZE (1) = DEVICE2_ESIZE;
+ DEVESIZE(1) = DEVICE2_ESIZE;
#endif
#ifdef DEVICE2_ENVSECTORS
- ENVSECTORS (1) = DEVICE2_ENVSECTORS;
+ ENVSECTORS(1) = DEVICE2_ENVSECTORS;
#endif
- HaveRedundEnv = 1;
+ have_redund_env = 1;
#endif
#endif
rc = check_device_config(0);
if (rc < 0)
return rc;
- if (HaveRedundEnv) {
+ if (have_redund_env) {
rc = check_device_config(1);
if (rc < 0)
return rc;
@@ -1668,14 +1749,14 @@
}
usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
- if (HaveRedundEnv)
+ if (have_redund_env)
usable_envsize -= sizeof(char);
return 0;
}
#if defined(CONFIG_FILE)
-static int get_config (char *fname)
+static int get_config(char *fname)
{
FILE *fp;
int i = 0;
@@ -1683,11 +1764,11 @@
char dump[128];
char *devname;
- fp = fopen (fname, "r");
+ fp = fopen(fname, "r");
if (fp == NULL)
return -1;
- while (i < 2 && fgets (dump, sizeof (dump), fp)) {
+ while (i < 2 && fgets(dump, sizeof(dump), fp)) {
/* Skip incomplete conversions and comment strings */
if (dump[0] == '#')
continue;
@@ -1695,9 +1776,7 @@
rc = sscanf(dump, "%ms %lli %lx %lx %lx",
&devname,
&DEVOFFSET(i),
- &ENVSIZE(i),
- &DEVESIZE(i),
- &ENVSECTORS(i));
+ &ENVSIZE(i), &DEVESIZE(i), &ENVSECTORS(i));
if (rc < 3)
continue;
@@ -1710,10 +1789,10 @@
i++;
}
- fclose (fp);
+ fclose(fp);
- HaveRedundEnv = i - 1;
- if (!i) { /* No valid entries found */
+ have_redund_env = i - 1;
+ if (!i) { /* No valid entries found */
errno = EINVAL;
return -1;
} else
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index d93a915..fb4afa5 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -239,7 +239,7 @@
argv += optind;
if (env_opts.lockname) {
- lockname = malloc(sizeof(env_opts.lockname) +
+ lockname = malloc(strlen(env_opts.lockname) +
sizeof(CMD_PRINTENV) + 10);
if (!lockname) {
fprintf(stderr, "Unable allocate memory");
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 3ca3b3b..26686ad 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1616,6 +1616,10 @@
struct image_tool_params *params)
{
uint8_t checksum;
+ size_t header_size = kwbimage_header_size(ptr);
+
+ if (header_size > image_size)
+ return -FDT_ERR_BADSTRUCTURE;
if (!main_hdr_checksum_ok(ptr))
return -FDT_ERR_BADSTRUCTURE;
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 28ff35e..4e56182 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -588,9 +588,8 @@
if (tparams->print_header)
tparams->print_header (ptr);
else {
- fprintf (stderr, "%s: Can't print header for %s: %s\n",
- params.cmdname, tparams->name, strerror(errno));
- exit (EXIT_FAILURE);
+ fprintf (stderr, "%s: Can't print header for %s\n",
+ params.cmdname, tparams->name);
}
(void) munmap((void *)ptr, sbuf.st_size);
diff --git a/tools/mxsimage.c b/tools/mxsimage.c
index 32a7978..c8f1f20 100644
--- a/tools/mxsimage.c
+++ b/tools/mxsimage.c
@@ -26,7 +26,8 @@
* OpenSSL 1.1.0 and newer compatibility functions:
* https://wiki.openssl.org/index.php/1.1_API_Changes
*/
-#if OPENSSL_VERSION_NUMBER < 0x10100000L
+#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
+ (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x2070000fL)
static void *OPENSSL_zalloc(size_t num)
{
void *ret = OPENSSL_malloc(num);
diff --git a/tools/stm32image.c b/tools/stm32image.c
new file mode 100644
index 0000000..437e384
--- /dev/null
+++ b/tools/stm32image.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <image.h>
+#include "imagetool.h"
+
+/* magic ='S' 'T' 'M' 0x32 */
+#define HEADER_MAGIC be32_to_cpu(0x53544D32)
+#define VER_MAJOR_IDX 2
+#define VER_MINOR_IDX 1
+#define VER_VARIANT_IDX 0
+#define HEADER_VERSION_V1 0x1
+/* default option : bit0 => no signature */
+#define HEADER_DEFAULT_OPTION (cpu_to_le32(0x00000001))
+
+struct stm32_header {
+ uint32_t magic_number;
+ uint32_t image_signature[64 / 4];
+ uint32_t image_checksum;
+ uint8_t header_version[4];
+ uint32_t image_length;
+ uint32_t image_entry_point;
+ uint32_t reserved1;
+ uint32_t load_address;
+ uint32_t reserved2;
+ uint32_t version_number;
+ uint32_t option_flags;
+ uint32_t ecdsa_algorithm;
+ uint32_t ecdsa_public_key[64 / 4];
+ uint32_t padding[84 / 4];
+};
+
+static struct stm32_header stm32image_header;
+
+static void stm32image_default_header(struct stm32_header *ptr)
+{
+ if (!ptr)
+ return;
+
+ ptr->magic_number = HEADER_MAGIC;
+ ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1;
+ ptr->option_flags = HEADER_DEFAULT_OPTION;
+ ptr->ecdsa_algorithm = 1;
+}
+
+static uint32_t stm32image_checksum(void *start, uint32_t len)
+{
+ uint32_t csum = 0;
+ uint32_t hdr_len = sizeof(struct stm32_header);
+ uint8_t *p;
+
+ if (len < hdr_len)
+ return 0;
+
+ p = start + hdr_len;
+ len -= hdr_len;
+
+ while (len > 0) {
+ csum += *p;
+ p++;
+ len--;
+ }
+
+ return csum;
+}
+
+static int stm32image_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_STM32IMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int stm32image_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+ int i;
+
+ if (image_size < sizeof(struct stm32_header))
+ return -1;
+ if (stm32hdr->magic_number != HEADER_MAGIC)
+ return -1;
+ if (stm32hdr->header_version[VER_MAJOR_IDX] != HEADER_VERSION_V1)
+ return -1;
+ if (stm32hdr->reserved1 || stm32hdr->reserved2)
+ return -1;
+ for (i = 0; i < (sizeof(stm32hdr->padding) / 4); i++) {
+ if (stm32hdr->padding[i] != 0)
+ return -1;
+ }
+
+ return 0;
+}
+
+static void stm32image_print_header(const void *ptr)
+{
+ struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+
+ printf("Image Type : STMicroelectronics STM32 V%d.%d\n",
+ stm32hdr->header_version[VER_MAJOR_IDX],
+ stm32hdr->header_version[VER_MINOR_IDX]);
+ printf("Image Size : %lu bytes\n",
+ (unsigned long)le32_to_cpu(stm32hdr->image_length));
+ printf("Image Load : 0x%08x\n",
+ le32_to_cpu(stm32hdr->load_address));
+ printf("Entry Point : 0x%08x\n",
+ le32_to_cpu(stm32hdr->image_entry_point));
+ printf("Checksum : 0x%08x\n",
+ le32_to_cpu(stm32hdr->image_checksum));
+ printf("Option : 0x%08x\n",
+ le32_to_cpu(stm32hdr->option_flags));
+}
+
+static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+
+ stm32image_default_header(stm32hdr);
+
+ stm32hdr->load_address = cpu_to_le32(params->addr);
+ stm32hdr->image_entry_point = cpu_to_le32(params->ep);
+ stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size -
+ sizeof(struct stm32_header));
+ stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size);
+}
+
+/*
+ * stm32image parameters
+ */
+U_BOOT_IMAGE_TYPE(
+ stm32image,
+ "STMicroelectronics STM32MP Image support",
+ sizeof(struct stm32_header),
+ (void *)&stm32image_header,
+ NULL,
+ stm32image_verify_header,
+ stm32image_print_header,
+ stm32image_set_header,
+ NULL,
+ stm32image_check_image_types,
+ NULL,
+ NULL
+);
diff --git a/tools/zynqimage.c b/tools/zynqimage.c
index 021d2d3..aa003a7 100644
--- a/tools/zynqimage.c
+++ b/tools/zynqimage.c
@@ -147,6 +147,12 @@
if (image_size < sizeof(struct zynq_header))
return -1;
+ if (zynqhdr->__reserved1 != 0)
+ return -1;
+
+ if (zynqhdr->__reserved2 != 0)
+ return -1;
+
if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
return -1;
if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
index f48ac6d..a61fb17 100644
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@@ -178,7 +178,7 @@
struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
int i;
- printf("Image Type : Xilinx Zynq Boot Image support\n");
+ printf("Image Type : Xilinx ZynqMP Boot Image support\n");
printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
printf("Image Size : %lu bytes (%lu bytes packed)\n",
(unsigned long)le32_to_cpu(zynqhdr->image_size),