[PATCH] Remove testing 4xx enet PHY setup
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 8c517ba..7a2483c 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -560,22 +560,7 @@
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
-#if defined(CONFIG_88E1111_CLK_DELAY)
- /*
- * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
- * the "RGMII transmit timing control" and "RGMII receive
- * timing control" bits set, so that Gbit communication works
- * without problems.
- * Also set the "Transmitter disable" to 1 to enable the
- * transmitter.
- * After setting these bits a soft-reset must occur for this
- * change to become active.
- */
- miiphy_read (dev->name, reg, 0x14, ®_short);
- reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
- miiphy_write (dev->name, reg, 0x14, reg_short);
-#endif
-#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
+#if defined(CONFIG_M88E1111_PHY)
miiphy_write (dev->name, reg, 0x14, 0x0ce3);
miiphy_write (dev->name, reg, 0x18, 0x4101);
miiphy_write (dev->name, reg, 0x09, 0x0e00);
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 60da820..bbe6b76 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -187,7 +187,7 @@
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */
+#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */