cmd/exception: test RISC-V 16 bit aligned instruction
A 16 bit aligned instruction should generated an exception if the C
extension is not available.
Provide an 'extension ialign16' command for testing exception handling.
For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with
qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
=> exception ialign16
Unhandled exception: Instruction address misaligned
EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted
Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
1 file changed