arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.:
a) Use the same functions for all cache ops (D$ Inv/Flush)
b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.
[2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.
[3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 0e11dcc..667f218 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -47,9 +47,12 @@
#endif
#define ARC_BCR_DC_BUILD 0x72
#define ARC_BCR_SLC 0xce
-#define ARC_AUX_SLC_CONTROL 0x903
+#define ARC_AUX_SLC_CONFIG 0x901
+#define ARC_AUX_SLC_CTRL 0x903
#define ARC_AUX_SLC_FLUSH 0x904
#define ARC_AUX_SLC_INVALIDATE 0x905
+#define ARC_AUX_SLC_IVDL 0x910
+#define ARC_AUX_SLC_FLDL 0x912
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */