| commit | ef87cab66492fe530bb6ec2e499b030c5ae60286 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Fri Sep 05 13:52:43 2014 +0800 |
| committer | York Sun <yorksun@freescale.com> | Mon Sep 08 10:30:34 2014 -0700 |
| tree | 5e96a47140a0a142c05e936ffbb66f8ff0c31c8c | |
| parent | 5cb27c5d44ac789f0f0583b57c15dc708ca55c69 [diff] |
driver/ddr/fsl: Add support of overriding chip select write leveling JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>