| commit | f06757324b2f2b0e062113a51f517a5361e6603c | [log] [tgz] |
|---|---|---|
| author | Michael Walle <mwalle@kernel.org> | Mon May 13 22:56:08 2024 +0200 |
| committer | Andre Przywara <andre.przywara@arm.com> | Mon Jul 15 22:18:16 2024 +0100 |
| tree | d65bba782032e9789ca6f55e1a2744094272ce94 | |
| parent | cee40d66a6924b9e40c9ece9cfb468d19a721144 [diff] |
clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC Add the clock gate registers as well as the reset register bits for the EMAC and EPHY for the V3s. These are needed by the sun8i network driver. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>