riscv: implement IPI platform functions using SBI
The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.
This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4d7a115..9da609b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -139,4 +139,9 @@
Stack memory is pre-allocated. U-Boot must therefore know the
maximum number of CPUs that may be present.
+config SBI_IPI
+ bool
+ default y if RISCV_SMODE
+ depends on SMP
+
endmenu