Coding style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds
index 5a6df7f..06dab59 100644
--- a/doc/README.mpc8572ds
+++ b/doc/README.mpc8572ds
@@ -97,70 +97,70 @@
-------------
1. Build kernel image for core0:
- a. $ make 85xx/mpc8572_ds_defconfig
+ a. $ make 85xx/mpc8572_ds_defconfig
- b. $ make menuconfig
- - un-select "Processor support"->"Symetric multi-processing support"
+ b. $ make menuconfig
+ - un-select "Processor support"->"Symetric multi-processing support"
- c. $ make uImage
+ c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
2. Build kernel image for core1:
- a. $ make 85xx/mpc8572_ds_defconfig
+ a. $ make 85xx/mpc8572_ds_defconfig
- b. $ make menuconfig
- - Un-select "Processor support"->"Symetric multi-processing support"
- - Select "Advanced setup" -> " Prompt for advanced kernel
- configuration options"
- - Select "Set physical address where the kernel is loaded" and
- set it to 0x20000000, asssuming core1 will start from 512MB.
- - Select "Set custom page offset address"
- - Select "Set custom kernel base address"
- - Select "Set maximum low memory"
- - "Exit" and save the selection.
+ b. $ make menuconfig
+ - Un-select "Processor support"->"Symetric multi-processing support"
+ - Select "Advanced setup" -> " Prompt for advanced kernel
+ configuration options"
+ - Select "Set physical address where the kernel is loaded" and
+ set it to 0x20000000, asssuming core1 will start from 512MB.
+ - Select "Set custom page offset address"
+ - Select "Set custom kernel base address"
+ - Select "Set maximum low memory"
+ - "Exit" and save the selection.
- c. $ make uImage
+ c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
3. Create dtb for core0:
- $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
+ $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
4. Create dtb for core1:
- $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
+ $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
5. Bring up two cores separately:
- a. Power on the board, under u-boot prompt:
- => setenv <serverip>
- => setenv <ipaddr>
- => setenv bootargs root=/dev/ram rw console=ttyS0,115200
- b. Bring up core1's kernel first:
- => setenv bootm_low 0x20000000
- => setenv bootm_size 0x10000000
- => tftp 21000000 8572/uImage.core1
- => tftp 22000000 8572/ramdiskfile
- => tftp 20c00000 8572/mpc8572ds_core1.dtb
- => interrupts off
- => bootm start 21000000 22000000 20c00000
- => bootm loados
- => bootm ramdisk
- => bootm fdt
- => fdt boardsetup
- => fdt chosen $initrd_start $initrd_end
- => bootm prep
- => cpu 1 release $bootm_low - $fdtaddr -
- c. Bring up core0's kernel(on the same u-boot console):
- => setenv bootm_low 0
- => setenv bootm_size 0x20000000
- => tftp 1000000 8572/uImage.core0
- => tftp 2000000 8572/ramdiskfile
- => tftp c00000 8572/mpc8572ds_core0.dtb
- => bootm 1000000 2000000 c00000
+ a. Power on the board, under u-boot prompt:
+ => setenv <serverip>
+ => setenv <ipaddr>
+ => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+ b. Bring up core1's kernel first:
+ => setenv bootm_low 0x20000000
+ => setenv bootm_size 0x10000000
+ => tftp 21000000 8572/uImage.core1
+ => tftp 22000000 8572/ramdiskfile
+ => tftp 20c00000 8572/mpc8572ds_core1.dtb
+ => interrupts off
+ => bootm start 21000000 22000000 20c00000
+ => bootm loados
+ => bootm ramdisk
+ => bootm fdt
+ => fdt boardsetup
+ => fdt chosen $initrd_start $initrd_end
+ => bootm prep
+ => cpu 1 release $bootm_low - $fdtaddr -
+ c. Bring up core0's kernel(on the same u-boot console):
+ => setenv bootm_low 0
+ => setenv bootm_size 0x20000000
+ => tftp 1000000 8572/uImage.core0
+ => tftp 2000000 8572/ramdiskfile
+ => tftp c00000 8572/mpc8572ds_core0.dtb
+ => bootm 1000000 2000000 c00000
Please note only core0 will run u-boot, core1 starts kernel directly after
"cpu release" command is issued.