arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/arch/arm/dts/cn9130-db-dev-info.dtsi b/arch/arm/dts/cn9130-db-dev-info.dtsi
new file mode 100644
index 0000000..68e9c0b
--- /dev/null
+++ b/arch/arm/dts/cn9130-db-dev-info.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+/ {
+ /* This should go only into devel boards */
+ compatible = "marvell,cp110";
+ sar {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sar_fields {
+ compatible = "marvell,sample-at-reset";
+ reg = <0x4c 0x4e>;
+ chip_count = <2>;
+ bit_width = <5>;
+ freq {
+ key = "freq";
+ description = "CPU/DDR and PIDI frequencies";
+ start-bit = <0>;
+ bit-length = <4>;
+ option-cnt = <3>;
+ options = "0x0", "CPU/DDR = 0x0: 2000/1200 Mhz, PIDI = 0: 1Ghz",
+ "0x2", "CPU/DDR = 0x6: 2200/1200 Mhz, PIDI = 0: 1Ghz",
+ "0x4", "CPU/DDR = 0xD: 1600/1200 Mhz, PIDI = 0: 1Ghz";
+ default = <0x2>;
+ status = "okay";
+ };
+ boot_mode {
+ key = "boot_mode";
+ description = "Boot mode options";
+ start-bit = <4>;
+ bit-length = <6>;
+ option-cnt = <4>;
+ options = "0xE", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-4bit\t(supported configuration: B)",
+ "0xF", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-8bit\t(supported configuration: B)",
+ "0x2A", "AP_EMMC",
+ "0x32", "CP1_SPI_1 24bits";
+ default = <0x32>;
+ status = "okay";
+ };
+ };
+ };
+};