| commit | f60c6fbbc658201f968a22addff7dd1acbe5eaca | [log] [tgz] |
|---|---|---|
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | Tue Oct 28 11:22:19 2014 +0530 |
| committer | Michal Simek <michal.simek@xilinx.com> | Mon Jan 26 08:55:57 2015 +0100 |
| tree | 36232fa5b868ef1572a9da4baebe235c84b5ac84 | |
| parent | 3ad87ca18203f8b0de0e30b7c12d2ffadf2d8553 [diff] |
ARM: zynq: slcr: Dont modify the reserved bits Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>