ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index b2fb51d..688289e 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -79,6 +79,10 @@
{
switch_to_main_crystal_osc();
+#ifdef CONFIG_SAMA5D2
+ configure_2nd_sram_as_l2_cache();
+#endif
+
/* disable watchdog */
at91_disable_wdt();