| commit | f7d190b1c0b3ab7fc53074ad2862f7de99de37ff | [log] [tgz] |
|---|---|---|
| author | Kumar Gala <galak@kernel.crashing.org> | Thu Oct 16 21:58:50 2008 -0500 |
| committer | Wolfgang Denk <wd@denx.de> | Fri Oct 17 10:51:35 2008 +0200 |
| tree | 522784dc12eeb2294ddc7b647889691764a3603d | |
| parent | 42653b826adb319a1df06e24ef26096b2a5d9d2a [diff] |
85xx: Using proper I2C source clock divider for MPC8544 The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being bit 26, instead it should be bit 28. This caused in incorrect interpretation of the i2c_clk which is the same as the SEC clk on MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported in PORDEVSR2. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>