commit f811eca9db05fc89fe52141b256231ff94859add
author Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Mon Jan 30 12:06:02 2017 +0530
committer Michal Simek <michal.simek@xilinx.com> Tue Nov 28 16:09:09 2017 +0100
tree b5be64c6e74426bddbeb5ba48705dee42846f7b9
parent d801ce553e84fded21060804f577b944da445317

arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arch/arm/dts/zynqmp-zcu102-revA.dts

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index fd7d646..df916d0 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -168,7 +168,7 @@
 		gtr_sel0 {
 			gpio-hog;
 			gpios = <0 0>;
-			output-high; /* PCIE = 0, DP = 1 */
+			output-low; /* PCIE = 0, DP = 1 */
 			line-name = "sel0";
 		};
 		gtr_sel1 {
@@ -551,7 +551,7 @@
 };
 
 &pcie {
-/*	status = "okay"; */
+	status = "okay";
 };
 
 &qspi {