| commit | f81aaa0b33bec4292838e75d14a0653775aea45d | [log] [tgz] |
|---|---|---|
| author | Masahisa Kojima <masahisa.kojima@linaro.org> | Tue May 17 17:41:39 2022 +0900 |
| committer | Tom Rini <trini@konsulko.com> | Fri Jun 10 13:37:32 2022 -0400 |
| tree | 5e5e53f7ec2e17ec8785f3dfd914b03638a44da2 | |
| parent | de9f2c9c2ed8ee4ffadc3909a46c17888fed619f [diff] |
spi: synquacer: simplify tx completion checking There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>