Merge tag 'u-boot-stm32-20240618' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
STM32MP15/13
------------
_ Reserve OPTEE area in EFI memory map
_ net: dwc_eth_qos: add support for phy-reset-gpios property
_ Add eth1/2 support for stm32mp13
_ Add PWR regulator support for stm32mp13
_ Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
_ Add support for STM32MP13xx DHCOR SoM and DHSBC board
_ Set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey
_ Use internal clock for Tx for stm32mp157c-odyssey
_ Fix incorrect PHY address for stm32mp157c-odyssey
_ Add phy-reset-gpios property to ethernet node for stm32mp157c-odyssey
_ Add generic SoM compatible to STM32MP15xx DH electronics DHSOM
_ Auto-detect second MAC on STM32MP15xx DH electronics DHCOM
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2be36cf..e034668 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1134,6 +1134,7 @@
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13X) += \
+ stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15X) += \
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 27e0c38..c01d39f 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,12 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ adc1_pins_a: adc1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
+ };
+ };
+
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
@@ -13,6 +19,104 @@
};
};
+ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
+ <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
+ };
+ };
+
+ eth1_rgmii_pins_a: eth1-rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+
+ };
+
+ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
+ };
+ };
+
+ eth2_rgmii_pins_a: eth2-rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -47,6 +151,63 @@
};
};
+ i2c5_pins_b: i2c5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_b: i2c5-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
+ };
+ };
+
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
+ <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
@@ -84,6 +245,21 @@
};
};
+ pwm5_pins_a: pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
+ };
+ };
+
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
@@ -99,6 +275,21 @@
};
};
+ pwm13_pins_a: pwm13-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm13_sleep_pins_a: pwm13-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
+ };
+ };
+
pwm14_pins_a: pwm14-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
@@ -114,6 +305,89 @@
};
};
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ sai1a_pins_a: sai1a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
+ <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
+ };
+ };
+
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -216,6 +490,73 @@
};
};
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ spi2_pins_a: spi2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
+ <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
+ bias-disable;
+ };
+ };
+
+ spi2_sleep_pins_a: spi2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
+ <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
+ <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
+ };
+ };
+
+ spi3_pins_a: spi3-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
+ <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
+ bias-disable;
+ };
+ };
+
+ spi3_sleep_pins_a: spi3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
@@ -276,6 +617,77 @@
};
};
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_idle_pins_b: uart4-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_sleep_pins_b: uart4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
+ <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
+ <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ uart7_idle_pins_a: uart7-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_sleep_pins_a: uart7-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
+ <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
+ };
+ };
+
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
@@ -347,6 +759,36 @@
};
};
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
@@ -387,4 +829,45 @@
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
+
+ usart2_pins_b: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_b: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_b: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 215ad92..ad331b7 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -1092,6 +1092,30 @@
<&scmi_clk CK_SCMI_LSI>;
};
+ pwr_regulators: pwr@50001000 {
+ compatible = "st,stm32mp1,pwr-reg";
+ reg = <0x50001000 0x10>;
+ status = "disabled";
+
+ reg11: reg11 {
+ regulator-name = "reg11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ reg18: reg18 {
+ regulator-name = "reg18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ usb33: usb33 {
+ regulator-name = "usb33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
@@ -1304,6 +1328,37 @@
status = "disabled";
};
+ eth1: eth1@5800a000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 68 1>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH1MAC>,
+ <&rcc ETH1TX>,
+ <&rcc ETH1RX>,
+ <&rcc ETH1STP>,
+ <&rcc ETH1CK_K>;
+ st,syscon = <&syscfg 0x4 0xff0000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_1>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_1: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
+
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
@@ -1380,6 +1435,12 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac1_address: mac1@e4 {
+ reg = <0xe4 0x6>;
+ };
+ ethernet_mac2_address: mac2@ea {
+ reg = <0xea 0x6>;
+ };
};
/*
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
index df451c3..5cd5bde 100644
--- a/arch/arm/dts/stm32mp133.dtsi
+++ b/arch/arm/dts/stm32mp133.dtsi
@@ -64,5 +64,35 @@
};
};
};
+
+ eth2: eth2@5800e000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800e000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH2MAC>,
+ <&rcc ETH2TX>,
+ <&rcc ETH2RX>,
+ <&rcc ETH2STP>,
+ <&rcc ETH2CK_K>;
+ st,syscon = <&syscfg 0x4 0xff000000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_2>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_2: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
new file mode 100644
index 0000000..d718aae
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp13xx-dhcor-u-boot.dtsi"
+
+&uart4 {
+ bootph-all;
+};
+
+&uart4_pins_b {
+ bootph-all;
+
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
+&usbphyc {
+ bootph-all;
+};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
new file mode 100644
index 0000000..fc1c48a
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ *
+ * DHCOR STM32MP13 variant:
+ * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
+ * DHCOR PCB number: 718-100 or newer
+ * DHSBC PCB number: 719-100 or newer
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13xx-dhcor-som.dtsi"
+
+/ {
+ model = "DH electronics STM32MP135F DHCOR DHSBC";
+ compatible = "dh,stm32mp135f-dhcor-dhsbc",
+ "dh,stm32mp135f-dhcor-som",
+ "st,stm32mp135";
+
+ aliases {
+ ethernet0 = ð1;
+ ethernet1 = ð2;
+ serial2 = &usart1;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&adc_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>;
+ vdda-supply = <&vdd_adc>;
+ vref-supply = <&vdd_adc>;
+ status = "okay";
+
+ adc1: adc@0 {
+ status = "okay";
+
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+ * Use arbitrary margin here (e.g. 5us).
+ *
+ * The pinmux pins must be set as ANALOG, use datasheet
+ * DS13483 Table 7. STM32MP135C/F ball definitions to
+ * find out which 'pin name' maps to which 'additional
+ * functions', which lists the mapping between pin and
+ * ADC channel. In this case, PA5 maps to ADC1_INP2 and
+ * PF13 maps to ADC1_INP11 .
+ */
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@11 {
+ reg = <11>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ /* Expansion connector: INP12:pin29 */
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+ð1 {
+ status = "okay";
+ pinctrl-0 = <ð1_rgmii_pins_a>;
+ pinctrl-1 = <ð1_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ st,ext-phyclk;
+ nvmem-cells = <ðernet_mac1_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ ethphy1: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpiog>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ reg = <1>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <55000>;
+ reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+ð2 {
+ status = "okay";
+ pinctrl-0 = <ð2_rgmii_pins_a>;
+ pinctrl-1 = <ð2_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ st,ext-phyclk;
+ nvmem-cells = <ðernet_mac2_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ ethphy2: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpiog>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ reg = <1>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <55000>;
+ reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpioa {
+ gpio-line-names = "", "", "", "",
+ "", "DHSBC_USB_PWR_CC1", "", "",
+ "", "", "", "DHSBC_nETH1_RST",
+ "", "DHCOR_HW-CODING_0", "", "";
+};
+
+&gpiob {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "DHCOR_BT_HOST_WAKE",
+ "", "", "", "",
+ "", "DHSBC_nTPM_CS", "", "";
+};
+
+&gpioc {
+ gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpiod {
+ gpio-line-names = "", "", "", "",
+ "", "DHCOR_RAM-CODING_0", "", "",
+ "", "DHCOR_RAM-CODING_1", "", "",
+ "", "", "", "";
+};
+
+&gpioe {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "DHSBC_nTPM_RST", "", "",
+ "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", "";
+};
+
+&gpiof {
+ gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "",
+ "", "", "", "",
+ "", "", "", "",
+ "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", "";
+};
+
+&gpiog {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "",
+ "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB";
+};
+
+&gpioi {
+ gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1",
+ "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT",
+ "DHSBC_BOOT0", "DHSBC_BOOT1",
+ "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS";
+};
+
+&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_b>;
+ pinctrl-1 = <&i2c5_sleep_pins_b>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can2_pins_a>;
+ pinctrl-1 = <&m_can2_sleep_pins_a>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ status = "okay";
+};
+
+&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */
+ clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>;
+ pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>;
+};
+
+&scmi_voltd {
+ status = "disabled";
+};
+
+&spi2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi2_pins_a>;
+ pinctrl-1 = <&spi2_sleep_pins_a>;
+ cs-gpios = <&gpiob 13 0>;
+ status = "okay";
+
+ st33htph: tpm@0 {
+ compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ };
+};
+
+&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi3_pins_a>;
+ pinctrl-1 = <&spi3_sleep_pins_a>;
+ cs-gpios = <&gpiof 3 0>;
+ status = "disabled";
+};
+
+&timers5 { /* Expansion connector: CH3:pin31 */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm5_pins_a>;
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@4 {
+ status = "okay";
+ };
+};
+
+&timers13 { /* Expansion connector: CH1:pin32 */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm13_pins_a>;
+ pinctrl-1 = <&pwm13_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@12 {
+ status = "okay";
+ };
+};
+
+&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_b>;
+ pinctrl-1 = <&usart1_sleep_pins_b>;
+ pinctrl-2 = <&usart1_idle_pins_b>;
+ status = "okay";
+};
+
+&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_b>;
+ pinctrl-1 = <&usart2_sleep_pins_b>;
+ pinctrl-2 = <&usart2_idle_pins_b>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbh_ohci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "peripheral";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb33d-supply = <&usb33>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vbus_sw>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ label = "Type-C";
+ self-powered;
+ type = "micro";
+ };
+};
diff --git a/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
new file mode 100644
index 0000000..ddad649
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
+#include "stm32mp13-pinctrl.dtsi"
+
+/ {
+ model = "DH electronics STM32MP13xx DHCOR SoM";
+ compatible = "dh,stm32mp131a-dhcor-som",
+ "st,stm32mp131";
+
+ aliases {
+ mmc0 = &sdmmc2;
+ mmc1 = &sdmmc1;
+ serial0 = &uart4;
+ serial1 = &uart7;
+ rtc0 = &rv3032;
+ spi0 = &qspi;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ optee@dd000000 {
+ reg = <0xdd000000 0x3000000>;
+ no-map;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo1-supply = <&vin>;
+ ldo2-supply = <&vin>;
+ ldo3-supply = <&vin>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&vin>;
+ ldo6-supply = <&vin>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcpu: buck1 { /* VDD_CPU_1V2 */
+ regulator-name = "vddcpu";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 { /* VDD_DDR_1V35 */
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 { /* VDD_3V3_1V8 */
+ regulator-name = "vdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vddcore: buck4 { /* VDD_CORE_1V2 */
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_adc: ldo1 { /* VDD_ADC_1V8 */
+ regulator-name = "vdd_adc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */
+ regulator-name = "vdd_ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vdd_ldo3: ldo3 { /* LDO3_OUT */
+ regulator-name = "vdd_ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO3 0>;
+ };
+
+ vdd_usb: ldo4 { /* VDD_USB_3V3 */
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ };
+
+ vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */
+ regulator-name = "vdd_sd2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr { /* VREF_DDR_0V675 */
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost { /* BST_OUT_5V2 */
+ regulator-name = "bst_out";
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c256"; /* ST M24256 */
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+
+ rv3032: rtc@51 {
+ compatible = "microcrystal,rv3032";
+ reg = <0x51>;
+ interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+/* Console UART */
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_b>;
+ pinctrl-1 = <&uart4_sleep_pins_b>;
+ pinctrl-2 = <&uart4_idle_pins_b>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+/* Bluetooth */
+&uart7 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-1 = <&uart7_sleep_pins_a>;
+ pinctrl-2 = <&uart7_idle_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
+ max-speed = <3000000>;
+ device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* SDIO WiFi */
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&vdd>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 { /* muRata 1YN */
+ reg = <1>;
+ compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpioe>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+/* eMMC */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ bus-width = <8>;
+ mmc-ddr-3_3v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&vdd>;
+ vqmmc-supply = <&vdd>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
new file mode 100644
index 0000000..30e3b91
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp13-u-boot.dtsi"
+
+/ {
+ aliases {
+ eeprom0 = &eeprom0;
+ };
+
+ config {
+ dh,ddr3-coding-gpios = <&gpiod 5 0>, <&gpiod 9 0>;
+ dh,som-coding-gpios = <&gpioa 13 0>, <&gpioi 1 0>;
+ };
+};
+
+&flash0 {
+ bootph-pre-ram;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "fsbl1";
+ reg = <0x00000000 0x00040000>;
+ };
+ partition@40000 {
+ label = "fsbl2";
+ reg = <0x00040000 0x00040000>;
+ };
+ partition@80000 {
+ label = "u-boot";
+ reg = <0x00080000 0x00360000>;
+ };
+ partition@3e0000 {
+ label = "u-boot-env-a";
+ reg = <0x003e0000 0x00010000>;
+ };
+ partition@3f0000 {
+ label = "u-boot-env-b";
+ reg = <0x003f0000 0x00010000>;
+ };
+ };
+};
+
+&sdmmc1 {
+ status = "disabled";
+};
+
+&usbotg_hs {
+ u-boot,force-b-session-valid;
+};
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
index b780dbd..d07fdcf 100644
--- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
@@ -115,11 +115,11 @@
bootph-all;
};
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+ /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+ cfg = < 3 124 5 9 9 PQR(1,1,1) >;
bootph-all;
};
};
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts
index 17bcf56..4cc5e07 100644
--- a/arch/arm/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/dts/stm32mp157c-odyssey.dts
@@ -75,13 +75,15 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ phy-reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
+ st,ext-phyclk;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
+ phy0: ethernet-phy@7 {
+ reg = <7>;
};
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
index 1ef9ac2..90625bf 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
@@ -11,5 +11,7 @@
/ {
model = "DH Electronics STM32MP15xx DHCOM DRC02";
- compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcom-drc02",
+ "dh,stm32mp15xx-dhcom-som",
+ "st,stm32mp1xx";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
index e2e01e2..b2e450a 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
@@ -11,5 +11,7 @@
/ {
model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
- compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
+ compatible = "dh,stm32mp15xx-dhcom-pdk2",
+ "dh,stm32mp15xx-dhcom-som",
+ "st,stm32mp15x";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
index 06770b4..3e90810 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
@@ -11,5 +11,7 @@
/ {
model = "DH Electronics STM32MP15xx DHCOM PicoITX";
- compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcom-picoitx",
+ "dh,stm32mp15xx-dhcom-som",
+ "st,stm32mp1xx";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 1b44561..d7b78cd 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -26,6 +26,7 @@
u-boot,error-led = "error";
dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
+ dh,mac-coding-gpios = <&gpioc 3 0>;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
index 76ac5a8..dd8fcec 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
@@ -14,5 +14,7 @@
/ {
model = "Arrow Electronics STM32MP15xx Avenger96 board";
- compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x";
+ compatible = "arrow,stm32mp15xx-avenger96",
+ "dh,stm32mp15xx-dhcor-som",
+ "st,stm32mp15x";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
index 77dd944..c1f99c1 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
@@ -12,5 +12,7 @@
/ {
model = "DH electronics STM32MP15xx DHCOR DRC Compact";
- compatible = "dh,stm32mp15xx-dhcor-drc-compact", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcor-drc-compact",
+ "dh,stm32mp15xx-dhcor-som",
+ "st,stm32mp1xx";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
index c9163e1..5fdd762 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
@@ -9,7 +9,9 @@
/ {
model = "DH electronics STM32MP15xx DHCOR Testbench";
- compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcor-testbench",
+ "dh,stm32mp15xx-dhcor-som",
+ "st,stm32mp1xx";
aliases {
ethernet0 = ðernet0;
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index b9af03d..d5934a9 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -155,4 +155,21 @@
source "arch/arm/mach-stm32mp/Kconfig.15x"
source "arch/arm/mach-stm32mp/Kconfig.25x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
+
+config STM32MP15_PWR
+ bool "Enable driver for STM32MP15x PWR"
+ depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X)
+ default y if STM32MP15X
+ help
+ This config enables implementation of driver-model pmic and
+ regulator uclass features for access to STM32MP15x PWR.
+
+config SPL_STM32MP15_PWR
+ bool "Enable driver for STM32MP15x PWR in SPL"
+ depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X)
+ default y if STM32MP15X
+ help
+ This config enables implementation of driver-model pmic and
+ regulator uclass features for access to STM32MP15x PWR in SPL.
+
endif
diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x
index 71c14eb..d99aa9f 100644
--- a/arch/arm/mach-stm32mp/Kconfig.15x
+++ b/arch/arm/mach-stm32mp/Kconfig.15x
@@ -77,22 +77,6 @@
endchoice
-config STM32MP15_PWR
- bool "Enable driver for STM32MP15x PWR"
- depends on DM_REGULATOR && DM_PMIC
- default y
- help
- This config enables implementation of driver-model pmic and
- regulator uclass features for access to STM32MP15x PWR.
-
-config SPL_STM32MP15_PWR
- bool "Enable driver for STM32MP15x PWR in SPL"
- depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC
- default y
- help
- This config enables implementation of driver-model pmic and
- regulator uclass features for access to STM32MP15x PWR in SPL.
-
config TEXT_BASE
default 0xC0100000
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 78b12fc..6024959 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -6,6 +6,7 @@
#define LOG_CATEGORY LOGC_ARCH
#include <dm.h>
+#include <efi_loader.h>
#include <image.h>
#include <init.h>
#include <lmb.h>
@@ -74,3 +75,14 @@
return reg + size;
}
+
+void efi_add_known_memory(void)
+{
+ if (IS_ENABLED(CONFIG_EFI_LOADER))
+ /*
+ * Memory over ram_top is reserved to OPTEE.
+ * Declare to EFI only memory area below ram_top
+ */
+ efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
+ EFI_CONVENTIONAL_MEMORY);
+}
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 20c9d70..ebd45f9 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -37,6 +37,7 @@
#include <power/regulator.h>
#include <remoteproc.h>
#include <reset.h>
+#include <spl.h>
#include <syscon.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
@@ -672,12 +673,69 @@
#endif
}
+static void dh_stm32_ks8851_fixup(void *blob)
+{
+ struct gpio_desc ks8851intrn;
+ bool compatible = false;
+ int ks8851intrn_value;
+ const char *prop;
+ ofnode node;
+ int idx = 0;
+ int offset;
+ int ret;
+
+ /* Do nothing if not STM32MP15xx DHCOM SoM */
+ while ((prop = fdt_stringlist_get(blob, 0, "compatible", idx++, NULL))) {
+ if (!strstr(prop, "dhcom-som"))
+ continue;
+ compatible = true;
+ break;
+ }
+
+ if (!compatible)
+ return;
+
+ /*
+ * Read state of INTRN pull up resistor, if this pull up is populated,
+ * KS8851-16MLL is populated as well and should be enabled, otherwise
+ * it should be disabled.
+ */
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node))
+ return;
+
+ ret = gpio_request_by_name_nodev(node, "dh,mac-coding-gpios", 0,
+ &ks8851intrn, GPIOD_IS_IN);
+ if (ret)
+ return;
+
+ ks8851intrn_value = dm_gpio_get_value(&ks8851intrn);
+
+ dm_gpio_free(NULL, &ks8851intrn);
+
+ /* Set the 'status' property into KS8851-16MLL DT node. */
+ offset = fdt_path_offset(blob, "ethernet1");
+ ret = fdt_node_check_compatible(blob, offset, "micrel,ks8851-mll");
+ if (ret) /* Not compatible */
+ return;
+
+ /* Add a bit of extra space for new 'status' property */
+ ret = fdt_shrink_to_minimum(blob, 4096);
+ if (!ret)
+ return;
+
+ fdt_setprop_string(blob, offset, "status",
+ ks8851intrn_value ? "okay" : "disabled");
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3";
int buck3off, ret, uv;
+ dh_stm32_ks8851_fixup(blob);
+
ret = board_get_regulator_buck3_nvm_uv_av96(&uv);
if (ret) /* Not Avenger96 board, do not patch Buck3 in DT. */
return 0;
@@ -698,6 +756,13 @@
}
#endif
+#if defined(CONFIG_SPL_BUILD)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image));
+}
+#endif
+
static void board_copro_image_process(ulong fw_image, size_t fw_size)
{
int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig
new file mode 100644
index 0000000..fb3d86d
--- /dev/null
+++ b/configs/stm32mp13_dhcor_defconfig
@@ -0,0 +1,148 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x1c0000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x3E0000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dhcor-dhsbc"
+CONFIG_STM32MP13X=y
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
+CONFIG_CMD_STM32KEY=y
+CONFIG_TARGET_ST_STM32MP13X=y
+CONFIG_ENV_OFFSET_REDUND=0x3F0000
+CONFIG_CMD_STM32PROG=y
+CONFIG_STM32MP15_PWR=y
+# CONFIG_ARMV7_NONSEC is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_SYS_MEMTEST_START=0xc0000000
+CONFIG_SYS_MEMTEST_END=0xc4000000
+CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTAGE_RECORD_COUNT=100
+CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_SETEXPR_FMT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_WGET=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LOG=y
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_LIVE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SPI_MAX_HZ=50000000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_CLK_SCMI=y
+CONFIG_SET_DFU_ALT_INFO=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_STM32_FMC2_EBI=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_DM_REGULATOR_SCMI=y
+CONFIG_RESET_SCMI=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_STM32=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="dh"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
+CONFIG_FAT_WRITE=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index fbc08bb..cffaa10 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -266,6 +266,12 @@
if (ret)
dev_warn(dev, "No phy clock provided %d\n", ret);
+ /* Get reset gpio pin (optional) */
+ ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
+ &eqos->phy_reset_gpio, GPIOD_IS_OUT);
+ if (ret)
+ pr_warn("No phy reset gpio provided: %d\n", ret);
+
dev_dbg(dev, "%s: OK\n", __func__);
return 0;
@@ -277,6 +283,21 @@
return ret;
}
+static int eqos_start_resets_stm32(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
+ udelay(2);
+ dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ }
+
+ return 0;
+}
+
static int eqos_remove_resources_stm32(struct udevice *dev)
{
dev_dbg(dev, "%s:\n", __func__);
@@ -292,7 +313,7 @@
.eqos_probe_resources = eqos_probe_resources_stm32,
.eqos_remove_resources = eqos_remove_resources_stm32,
.eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
+ .eqos_start_resets = eqos_start_resets_stm32,
.eqos_stop_clks = eqos_stop_clks_stm32,
.eqos_start_clks = eqos_start_clks_stm32,
.eqos_calibrate_pads = eqos_null_ops,