| commit | 328ce7fd505288949d83b72562586a139e025549 | [log] [tgz] |
|---|---|---|
| author | Chen-Yu Tsai <wens@csie.org> | Wed Nov 30 16:54:34 2016 +0800 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Thu Apr 20 13:30:01 2017 +0200 |
| tree | d3d2c0f2060c1a04e1ad9020c0bcd8be49c29958 | |
| parent | 8094a4a20b05827d6fa91786705b3f6917f7421c [diff] |
sunxi: Set PLL lock enable bits for R40 According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>