commit fb05f6da35ea1c15c553abe6f23f656bf18dc5db
author Michal Simek <monstr@monstr.eu> Mon May 07 23:58:31 2007 +0200
committer Michal Simek <monstr@monstr.eu> Mon May 07 23:58:31 2007 +0200
tree 97d017c2c93576570338cd2a5d2034981f131bc8
parent a7bac7e9b57ba948051beb19ec5be3a75ce75383

new: USE_MSR_INTR support

cpu/microblaze/cache.c

diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
old mode 100644
new mode 100755
index 683044c..4f36a84
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/asm.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_CACHE)
 
@@ -47,18 +48,18 @@
 }
 
 void	icache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x80");
+	MSRSET(0x20);
 }
 
 void	icache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x80");
+	MSRCLR(0x20);
 }
 
 void	dcache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x20");
+	MSRSET(0x80);
 }
 
 void	dcache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x20");
+	MSRCLR(0x80);
 }
 #endif