| commit | fb33eaa3a26cdc37826390b6db223509230ae8e2 | [log] [tgz] |
|---|---|---|
| author | Brad Kim <brad.kim@semifive.com> | Fri Nov 13 20:47:51 2020 +0900 |
| committer | Andes <uboot@andestech.com> | Mon Dec 14 15:16:34 2020 +0800 |
| tree | b25433aa4126fdba6a61ab50d6afcccdcb60a582 | |
| parent | 5a1a8a63be8f7262a300eddafb18020926b12fb6 [diff] |
riscv: fix the wrong swap value register Not s2 register, t1 register is correct Fortunately, it works because t1 register has a garbage value Signed-off-by: Brad Kim <brad.kim@semifive.com> Reviewed-by: Lukas Auer <lukas@auer.io> Reviewed-by: Leo Liang <ycliang@andestech.com>