riscv: fix the wrong swap value register
Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value
Signed-off-by: Brad Kim <brad.kim@semifive.com>
Reviewed-by: Lukas Auer <lukas@auer.io>
Reviewed-by: Leo Liang <ycliang@andestech.com>
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bbc737e..8589509 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -123,7 +123,7 @@
* wait for initialization to complete.
*/
la t0, hart_lottery
- li s2, 1
+ li t1, 1
amoswap.w s2, t1, 0(t0)
bnez s2, wait_for_gd_init
#else