| commit | fc3c6fd75298b69175cc4a0732759f5e1054dc21 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Tue Feb 02 13:33:22 2021 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Wed Feb 10 13:20:27 2021 +0100 |
| tree | 2f0bdc934071e1d44c144745d9fb4f8948776c77 | |
| parent | f1fd79afad97df76f0d84847d98d80d5a8c7e4ec [diff] |
xilinx: common: Fix CONFIG_XILINX_OF_BOARD_DTB_ADDR handling for ZynqMP
Fix bug introduced by commit listed below. It is for cases where Versal or
ZynqMP don't have DDR mapped. Later SPL was also excluded by
commit a672b9871b57 ("xilinx: common: Do not touch
CONFIG_XILINX_OF_BOARD_DTB_ADDR in SPL").
Fixes: 506009fc1022 ("xilinx: common: Change macro handling in board_fdt_blob_setup()")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>