Merge branch 'master' of git://git.denx.de/u-boot-socfpga
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 326d5c0..1f3fa15 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -807,7 +807,6 @@
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
- select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
imply CMD_DM
@@ -817,6 +816,7 @@
imply DM_SPI_FLASH
imply FAT_WRITE
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index d6b5949..114dd91 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -453,7 +453,7 @@
*/
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
- unsigned long status;
+ int status;
/* disable all signals from hps peripheral controller to fpga */
writel(0, &system_manager_base->fpgaintf_en_global);
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 184de74..6d16e0b 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -204,7 +204,7 @@
*/
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
- unsigned long status;
+ int status;
if ((uint32_t)rbf_data & 0x3) {
puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2330143..bd8f5c8 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -31,8 +31,21 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
#endif
+
+/*
+ * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
+ * SRAM as bootcounter storage. Make sure to not put the stack directly
+ * at this address to not overwrite the bootcounter by checking, if the
+ * bootcounter address is located in the internal SRAM.
+ */
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
+ (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE)))
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
+#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1