| commit | fdba86972f23cab99710e19a04f36f170d1870e0 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Thu Nov 29 10:31:02 2018 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Thu Nov 29 10:31:02 2018 +0100 |
| tree | f3d40f8eb70814b549f5d445fb1f602d8d9e9744 | |
| parent | 6bd13ee94ecf0e3124efdd51758df21db8100083 [diff] |
ARM: zynq: Wire SPL configuration for cse nor/nand targets These symlinks are here only for testing purpose where SPL is used for soc configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>