commit fe40bd4d8f62637aac0d2b3e6195d56dc96b1342
author Simon Glass <sjg@chromium.org> Sun Jan 17 16:11:12 2016 -0700
committer Bin Meng <bmeng.cn@gmail.com> Sun Jan 24 12:07:19 2016 +0800
tree ac67974d04d8688f01c60f90bf713560a39d7ae0
parent 788cd90864e469da7928a9efae3d017a09b2d035

x86: ivybridge: Move more init to the probe() function

Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

arch/x86/cpu/ivybridge/lpc.c

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9d089c7..9dad9e4 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -454,6 +454,42 @@
 	setbits_le32(RCB_REG(0x21a8), 0x3);
 }
 
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(struct udevice *pch)
+{
+	u8 reg8;
+
+	dm_pci_read_config8(pch, 0xdc, &reg8);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	dm_pci_write_config8(pch, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(struct udevice *pch)
+{
+	/* Enable port 80 POST on LPC */
+	dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+	clrbits_le32(RCB_REG(GCS), 4);
+}
+
+static void set_spi_speed(void)
+{
+	u32 fdod;
+
+	/* Observe SPI Descriptor Component Section 0 */
+	writel(0x1000, RCB_REG(SPI_DESC_COMP0));
+
+	/* Extract the1 Write/Erase SPI Frequency from descriptor */
+	fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
+	fdod >>= 24;
+	fdod &= 7;
+
+	/* Set Software Sequence frequency to match */
+	clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
+}
+
 /**
  * lpc_early_init() - set up LPC serial ports and other early things
  *
@@ -492,6 +528,13 @@
 		dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
 	}
 
+	enable_spi_prefetch(dev->parent);
+
+	/* This is already done in start.S, but let's do it in C */
+	enable_port80_on_lpc(dev->parent);
+
+	set_spi_speed();
+
 	return 0;
 }