Initial revision
diff --git a/drivers/3c589.c b/drivers/3c589.c
new file mode 100644
index 0000000..541f93b
--- /dev/null
+++ b/drivers/3c589.c
@@ -0,0 +1,522 @@
+/*------------------------------------------------------------------------
+ . 3c589.c
+ . This is a driver for 3Com's 3C589 (Etherlink III) PCMCIA Ethernet device.
+ .
+ . (C) Copyright 2002
+ . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ . Rolf Offermanns <rof@sysgo.de>
+ .
+ . This program is free software; you can redistribute it and/or modify
+ . it under the terms of the GNU General Public License as published by
+ . the Free Software Foundation; either version 2 of the License, or
+ . (at your option) any later version.
+ .
+ . This program is distributed in the hope that it will be useful,
+ . but WITHOUT ANY WARRANTY; without even the implied warranty of
+ . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ . GNU General Public License for more details.
+ .
+ . You should have received a copy of the GNU General Public License
+ . along with this program; if not, write to the Free Software
+ . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ .
+ ----------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+
+#ifdef CONFIG_DRIVER_3C589
+
+#include "3c589.h"
+
+
+/* Use power-down feature of the chip */
+#define POWER_DOWN 0
+
+#define NO_AUTOPROBE
+
+static const char version[] =
+ "Your ad here! :P\n";
+
+
+#undef EL_DEBUG
+
+typedef unsigned char byte;
+typedef unsigned short word;
+typedef unsigned long int dword;
+/*------------------------------------------------------------------------
+ .
+ . Configuration options, for the experienced user to change.
+ .
+ -------------------------------------------------------------------------*/
+
+/*
+ . Wait time for memory to be free. This probably shouldn't be
+ . tuned that much, as waiting for this means nothing else happens
+ . in the system
+*/
+#define MEMORY_WAIT_TIME 16
+
+
+#if (EL_DEBUG > 2 )
+#define PRINTK3(args...) printf(args)
+#else
+#define PRINTK3(args...)
+#endif
+
+#if EL_DEBUG > 1
+#define PRINTK2(args...) printf(args)
+#else
+#define PRINTK2(args...)
+#endif
+
+#ifdef EL_DEBUG
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+#define outb(args...) mmio_outb(args)
+#define mmio_outb(value, addr) (*((volatile byte *)(addr)) = value)
+
+#define inb(args...) mmio_inb(args)
+#define mmio_inb(addr) (*((volatile byte *)(addr)))
+
+#define outw(args...) mmio_outw(args)
+#define mmio_outw(value, addr) (*((volatile word *)(addr)) = value)
+
+#define inw(args...) mmio_inw(args)
+#define mmio_inw(addr) (*((volatile word *)(addr)))
+
+#define outsw(args...) mmio_outsw(args)
+#define mmio_outsw(r,b,l) ({ int __i; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ mmio_outw( *(__b2 + __i), r); \
+ } \
+ })
+
+#define insw(args...) mmio_insw(args)
+#define mmio_insw(r,b,l) ({ int __i ; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = mmio_inw(r); \
+ mmio_inw(0); \
+ }; \
+ })
+
+/*------------------------------------------------------------------------
+ .
+ . The internal workings of the driver. If you are changing anything
+ . here with the 3Com stuff, you should have the datasheet and know
+ . what you are doing.
+ .
+ -------------------------------------------------------------------------*/
+#define EL_BASE_ADDR 0x20000000
+
+
+/* Offsets from base I/O address. */
+#define EL3_DATA 0x00
+#define EL3_TIMER 0x0a
+#define EL3_CMD 0x0e
+#define EL3_STATUS 0x0e
+
+#define EEPROM_READ 0x0080
+
+#define EL3WINDOW(win_num) mmio_outw(SelectWindow + (win_num), EL_BASE_ADDR + EL3_CMD)
+
+/* The top five bits written to EL3_CMD are a command, the lower
+ 11 bits are the parameter, if applicable. */
+enum c509cmd {
+ TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
+ RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11,
+ TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
+ FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
+ SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
+ SetTxThreshold = 18<<11, SetTxStart = 19<<11, StatsEnable = 21<<11,
+ StatsDisable = 22<<11, StopCoax = 23<<11,
+};
+
+enum c509status {
+ IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
+ TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
+ IntReq = 0x0040, StatsFull = 0x0080, CmdBusy = 0x1000
+};
+
+/* The SetRxFilter command accepts the following classes: */
+enum RxFilter {
+ RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
+};
+
+/* Register window 1 offsets, the window used in normal operation. */
+#define TX_FIFO 0x00
+#define RX_FIFO 0x00
+#define RX_STATUS 0x08
+#define TX_STATUS 0x0B
+#define TX_FREE 0x0C /* Remaining free bytes in Tx buffer. */
+
+
+/*
+ Read a word from the EEPROM using the regular EEPROM access register.
+ Assume that we are in register window zero.
+*/
+static word read_eeprom(dword ioaddr, int index)
+{
+ int i;
+ outw(EEPROM_READ + index, ioaddr + 0xa);
+ /* Reading the eeprom takes 162 us */
+ for (i = 1620; i >= 0; i--)
+ if ((inw(ioaddr + 10) & EEPROM_BUSY) == 0)
+ break;
+ return inw(ioaddr + 0xc);
+}
+
+static void el_get_mac_addr( unsigned char *mac_addr )
+{
+ int i;
+ union
+ {
+ word w;
+ unsigned char b[2];
+ } wrd;
+ unsigned char old_window = inw( EL_BASE_ADDR + EL3_STATUS ) >> 13;
+ GO_WINDOW(0);
+ VX_BUSY_WAIT;
+ for (i = 0; i < 3; i++)
+ {
+ wrd.w = read_eeprom(EL_BASE_ADDR, 0xa+i);
+#ifdef __BIG_ENDIAN
+ mac_addr[2*i] = wrd.b[0];
+ mac_addr[2*i+1] = wrd.b[1];
+#else
+ mac_addr[2*i] = wrd.b[1];
+ mac_addr[2*i+1] = wrd.b[0];
+#endif
+ }
+ GO_WINDOW(old_window);
+ VX_BUSY_WAIT;
+}
+
+
+#if EL_DEBUG > 1
+static void print_packet( byte * buf, int length )
+{
+ int i;
+ int remainder;
+ int lines;
+
+ PRINTK2("Packet of length %d \n", length );
+
+ lines = length / 16;
+ remainder = length % 16;
+
+ for ( i = 0; i < lines ; i ++ ) {
+ int cur;
+
+ for ( cur = 0; cur < 8; cur ++ ) {
+ byte a, b;
+
+ a = *(buf ++ );
+ b = *(buf ++ );
+ PRINTK2("%02x%02x ", a, b );
+ }
+ PRINTK2("\n");
+ }
+ for ( i = 0; i < remainder/2 ; i++ ) {
+ byte a, b;
+
+ a = *(buf ++ );
+ b = *(buf ++ );
+ PRINTK2("%02x%02x ", a, b );
+ }
+ PRINTK2("\n");
+}
+#endif /* EL_DEBUG > 1 */
+
+
+
+/**************************************************************************
+ETH_RESET - Reset adapter
+***************************************************************************/
+static void el_reset(bd_t *bd)
+{
+ /***********************************************************
+ Reset 3Com 595 card
+ *************************************************************/
+ /* QUICK HACK
+ * - adjust timing for 3c589
+ * - enable io for PCMCIA */
+ outw(0x0004, 0xa0000018);
+ udelay(100);
+ outw(0x0041, 0x28010000);
+ udelay(100);
+
+ /* issue global reset */
+ outw(GLOBAL_RESET, BASE + VX_COMMAND);
+
+ /* must wait for at least 1ms */
+ udelay(100000000);
+
+ /* set mac addr */
+ {
+ unsigned char *mac_addr = bd->bi_enetaddr;
+ int i;
+
+ el_get_mac_addr( mac_addr );
+
+ GO_WINDOW(2);
+ VX_BUSY_WAIT;
+
+ printf("3C589 MAC Addr.: ");
+ for (i = 0; i < 6; i++)
+ {
+ printf("%02x", mac_addr[i]);
+ outb(mac_addr[i], BASE + VX_W2_ADDR_0 + i);
+ VX_BUSY_WAIT;
+ }
+ printf("\n\n");
+ }
+
+ /* set RX filter */
+ outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+
+ /* set irq mask and read_zero */
+ outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
+ S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+ outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
+ S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+ /* enable TP Linkbeat */
+ GO_WINDOW(4);
+ VX_BUSY_WAIT;
+
+ outw( ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
+ VX_BUSY_WAIT;
+
+
+/*
+ * Attempt to get rid of any stray interrupts that occured during
+ * configuration. On the i386 this isn't possible because one may
+ * already be queued. However, a single stray interrupt is
+ * unimportant.
+ */
+
+ outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+ /* enable TX and RX */
+ outw( RX_ENABLE, BASE + VX_COMMAND );
+ VX_BUSY_WAIT;
+
+ outw( TX_ENABLE, BASE + VX_COMMAND );
+ VX_BUSY_WAIT;
+
+
+ /* print the diag. regs. */
+ PRINTK2("Diag. Regs\n");
+ PRINTK2("--> MEDIA_TYPE: %04x\n", inw(BASE + VX_W4_MEDIA_TYPE));
+ PRINTK2("--> NET_DIAG: %04x\n", inw(BASE + VX_W4_NET_DIAG));
+ PRINTK2("--> FIFO_DIAG: %04x\n", inw(BASE + VX_W4_FIFO_DIAG));
+ PRINTK2("--> CTRLR_STATUS: %04x\n", inw(BASE + VX_W4_CTRLR_STATUS));
+ PRINTK2("\n\n");
+
+ /* enter working mode */
+ GO_WINDOW(1);
+ VX_BUSY_WAIT;
+
+ /* wait for another 1ms */
+ udelay(100000000);
+}
+
+
+/*-----------------------------------------------------------------
+ .
+ . The driver can be entered at any of the following entry points.
+ .
+ .------------------------------------------------------------------ */
+
+extern int eth_init(bd_t *bd);
+extern void eth_halt(void);
+extern int eth_rx(void);
+extern int eth_send(volatile void *packet, int length);
+
+
+/*
+ ------------------------------------------------------------
+ .
+ . Internal routines
+ .
+ ------------------------------------------------------------
+*/
+
+int eth_init(bd_t *bd)
+{
+ el_reset(bd);
+ return 0;
+}
+
+void eth_halt() {
+ return;
+}
+
+#define EDEBUG 1
+
+
+/**************************************************************************
+ETH_POLL - Wait for a frame
+***************************************************************************/
+
+int eth_rx()
+{
+ word status, rx_status, packet_size;
+
+ VX_BUSY_WAIT;
+
+ status = inw( BASE + VX_STATUS );
+
+ if ( (status & S_RX_COMPLETE) == 0 ) return 0; /* nothing to do */
+
+ /* Packet waiting -> check RX_STATUS */
+ rx_status = inw( BASE + VX_W1_RX_STATUS );
+
+ if ( rx_status & ERR_RX )
+ {
+ /* error in packet -> discard */
+ PRINTK("[ERROR] Invalid packet -> discarding\n");
+ PRINTK("-- error code 0x%02x\n", rx_status & ERR_MASK);
+ PRINTK("-- rx bytes 0x%04d\n", rx_status & ((1<<11) - 1));
+ PRINTK("[ERROR] Invalid packet -> discarding\n");
+ outw( RX_DISCARD_TOP_PACK, BASE + VX_COMMAND );
+ return 0;
+ }
+
+ /* correct pack. waiting in fifo */
+ packet_size = rx_status & RX_BYTES_MASK;
+
+ PRINTK("Correct packet waiting in fifo, size: %d\n", packet_size);
+
+ {
+ volatile word *packet_start = (word *)(BASE + VX_W1_RX_PIO_RD_1);
+ word *RcvBuffer = (word *)(NetRxPackets[0]);
+ int wcount = 0;
+
+ for (wcount = 0; wcount < (packet_size >> 1); wcount++)
+ {
+ *RcvBuffer++ = *(packet_start);
+ }
+
+ /* handle odd packets */
+ if ( packet_size & 1 )
+ {
+ *RcvBuffer++ = *(packet_start);
+ }
+ }
+
+ /* fifo should now be empty (besides the padding bytes) */
+ if ( ((*((word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK) > 3 )
+ {
+ PRINTK("[ERROR] Fifo not empty after packet read (remaining pkts: %d)\n",
+ (((*(word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK));
+ }
+
+ /* discard packet */
+ *((word *)(BASE + VX_COMMAND)) = RX_DISCARD_TOP_PACK;
+
+ /* Pass Packets to upper Layer */
+ NetReceive(NetRxPackets[0], packet_size);
+ return packet_size;
+}
+
+
+
+/**************************************************************************
+ETH_TRANSMIT - Transmit a frame
+***************************************************************************/
+static char padmap[] = {
+ 0, 3, 2, 1};
+
+
+int eth_send(volatile void *packet, int length) {
+ int pad;
+ int status;
+ volatile word *buf = (word *)packet;
+ int dummy = 0;
+
+ /* padding stuff */
+ pad = padmap[length & 3];
+
+ PRINTK("eth_send(), length: %d\n", length);
+ /* drop acknowledgements */
+ while(( status=inb(EL_BASE_ADDR + VX_W1_TX_STATUS) )& TXS_COMPLETE ) {
+ if(status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) {
+ outw(TX_RESET, EL_BASE_ADDR + VX_COMMAND);
+ outw(TX_ENABLE, EL_BASE_ADDR + VX_COMMAND);
+ PRINTK("Bad status, resetting and reenabling transmitter\n");
+ }
+
+ outb(0x0, EL_BASE_ADDR + VX_W1_TX_STATUS);
+ }
+
+
+ while (inw(EL_BASE_ADDR + VX_W1_FREE_TX) < length + pad + 4) {
+ /* no room in FIFO */
+ if (dummy == 0)
+ {
+ PRINTK("No room in FIFO, waiting...\n");
+ dummy++;
+ }
+
+ }
+
+ PRINTK(" ---> FIFO ready\n");
+
+
+ outw(length, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
+
+ /* Second dword meaningless */
+ outw(0x0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
+
+#if EL_DEBUG > 1
+ print_packet((byte *)buf, length);
+#endif
+
+ /* write packet */
+ {
+ unsigned int i, totw;
+
+ totw = ((length + 1) >> 1);
+ PRINTK("Buffer: (totw = %d)\n", totw);
+ for (i = 0; i < totw; i++) {
+ outw( *(buf+i), EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
+ udelay(10);
+ }
+ if(totw & 1)
+ { /* pad to double word length */
+ outw( 0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
+ udelay(10);
+ }
+ PRINTK("\n\n");
+ }
+
+ /* wait for Tx complete */
+ PRINTK("Waiting for Tx to complete...\n");
+ while(((status = inw(EL_BASE_ADDR + VX_STATUS)) & S_COMMAND_IN_PROGRESS) != 0)
+ {
+ udelay(10);
+ }
+ PRINTK(" ---> Tx completed, status = 0x%04x\n", status);
+
+ return length;
+}
+
+
+
+#endif /* CONFIG_DRIVER_3C589 */
diff --git a/drivers/bcm570x_autoneg.c b/drivers/bcm570x_autoneg.c
new file mode 100644
index 0000000..1818c6a
--- /dev/null
+++ b/drivers/bcm570x_autoneg.c
@@ -0,0 +1,444 @@
+/******************************************************************************/
+/* */
+/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2001 Broadcom */
+/* Corporation. */
+/* All rights reserved. */
+/* */
+/* This program is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU General Public License as published by */
+/* the Free Software Foundation, located in the file LICENSE. */
+/* */
+/* History: */
+/******************************************************************************/
+#if !defined(CONFIG_NET_MULTI)
+#if INCLUDE_TBI_SUPPORT
+#include "bcm570x_autoneg.h"
+#include "bcm570x_mm.h"
+
+
+
+/******************************************************************************/
+/* Description: */
+/* */
+/* Return: */
+/******************************************************************************/
+void
+MM_AnTxConfig(
+ PAN_STATE_INFO pAnInfo)
+{
+ PLM_DEVICE_BLOCK pDevice;
+
+ pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext;
+
+ REG_WR(pDevice, MacCtrl.TxAutoNeg, (LM_UINT32) pAnInfo->TxConfig.AsUSHORT);
+
+ pDevice->MacMode |= MAC_MODE_SEND_CONFIGS;
+ REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
+}
+
+
+
+/******************************************************************************/
+/* Description: */
+/* */
+/* Return: */
+/******************************************************************************/
+void
+MM_AnTxIdle(
+ PAN_STATE_INFO pAnInfo)
+{
+ PLM_DEVICE_BLOCK pDevice;
+
+ pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext;
+
+ pDevice->MacMode &= ~MAC_MODE_SEND_CONFIGS;
+ REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
+}
+
+
+
+/******************************************************************************/
+/* Description: */
+/* */
+/* Return: */
+/******************************************************************************/
+char
+MM_AnRxConfig(
+ PAN_STATE_INFO pAnInfo,
+ unsigned short *pRxConfig)
+{
+ PLM_DEVICE_BLOCK pDevice;
+ LM_UINT32 Value32;
+ char Retcode;
+
+ Retcode = AN_FALSE;
+
+ pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext;
+
+ Value32 = REG_RD(pDevice, MacCtrl.Status);
+ if(Value32 & MAC_STATUS_RECEIVING_CFG)
+ {
+ Value32 = REG_RD(pDevice, MacCtrl.RxAutoNeg);
+ *pRxConfig = (unsigned short) Value32;
+
+ Retcode = AN_TRUE;
+ }
+
+ return Retcode;
+}
+
+
+
+/******************************************************************************/
+/* Description: */
+/* */
+/* Return: */
+/******************************************************************************/
+void
+AutonegInit(
+ PAN_STATE_INFO pAnInfo)
+{
+ unsigned long j;
+
+ for(j = 0; j < sizeof(AN_STATE_INFO); j++)
+ {
+ ((unsigned char *) pAnInfo)[j] = 0;
+ }
+
+ /* Initialize the default advertisement register. */
+ pAnInfo->mr_adv_full_duplex = 1;
+ pAnInfo->mr_adv_sym_pause = 1;
+ pAnInfo->mr_adv_asym_pause = 1;
+ pAnInfo->mr_an_enable = 1;
+}
+
+
+
+/******************************************************************************/
+/* Description: */
+/* */
+/* Return: */
+/******************************************************************************/
+AUTONEG_STATUS
+Autoneg8023z(
+ PAN_STATE_INFO pAnInfo)
+{
+ unsigned short RxConfig;
+ unsigned long Delta_us;
+ AUTONEG_STATUS AnRet;
+
+ /* Get the current time. */
+ if(pAnInfo->State == AN_STATE_UNKNOWN)
+ {
+ pAnInfo->RxConfig.AsUSHORT = 0;
+ pAnInfo->CurrentTime_us = 0;
+ pAnInfo->LinkTime_us = 0;
+ pAnInfo->AbilityMatchCfg = 0;
+ pAnInfo->AbilityMatchCnt = 0;
+ pAnInfo->AbilityMatch = AN_FALSE;
+ pAnInfo->IdleMatch = AN_FALSE;
+ pAnInfo->AckMatch = AN_FALSE;
+ }
+
+ /* Increment the timer tick. This function is called every microsecon. */
+/* pAnInfo->CurrentTime_us++; */
+
+ /* Set the AbilityMatch, IdleMatch, and AckMatch flags if their */
+ /* corresponding conditions are satisfied. */
+ if(MM_AnRxConfig(pAnInfo, &RxConfig))
+ {
+ if(RxConfig != pAnInfo->AbilityMatchCfg)
+ {
+ pAnInfo->AbilityMatchCfg = RxConfig;
+ pAnInfo->AbilityMatch = AN_FALSE;
+ pAnInfo->AbilityMatchCnt = 0;
+ }
+ else
+ {
+ pAnInfo->AbilityMatchCnt++;
+ if(pAnInfo->AbilityMatchCnt > 1)
+ {
+ pAnInfo->AbilityMatch = AN_TRUE;
+ pAnInfo->AbilityMatchCfg = RxConfig;
+ }
+ }
+
+ if(RxConfig & AN_CONFIG_ACK)
+ {
+ pAnInfo->AckMatch = AN_TRUE;
+ }
+ else
+ {
+ pAnInfo->AckMatch = AN_FALSE;
+ }
+
+ pAnInfo->IdleMatch = AN_FALSE;
+ }
+ else
+ {
+ pAnInfo->IdleMatch = AN_TRUE;
+
+ pAnInfo->AbilityMatchCfg = 0;
+ pAnInfo->AbilityMatchCnt = 0;
+ pAnInfo->AbilityMatch = AN_FALSE;
+ pAnInfo->AckMatch = AN_FALSE;
+
+ RxConfig = 0;
+ }
+
+ /* Save the last Config. */
+ pAnInfo->RxConfig.AsUSHORT = RxConfig;
+
+ /* Default return code. */
+ AnRet = AUTONEG_STATUS_OK;
+
+ /* Autoneg state machine as defined in 802.3z section 37.3.1.5. */
+ switch(pAnInfo->State)
+ {
+ case AN_STATE_UNKNOWN:
+ if(pAnInfo->mr_an_enable || pAnInfo->mr_restart_an)
+ {
+ pAnInfo->CurrentTime_us = 0;
+ pAnInfo->State = AN_STATE_AN_ENABLE;
+ }
+
+ /* Fall through.*/
+
+ case AN_STATE_AN_ENABLE:
+ pAnInfo->mr_an_complete = AN_FALSE;
+ pAnInfo->mr_page_rx = AN_FALSE;
+
+ if(pAnInfo->mr_an_enable)
+ {
+ pAnInfo->LinkTime_us = 0;
+ pAnInfo->AbilityMatchCfg = 0;
+ pAnInfo->AbilityMatchCnt = 0;
+ pAnInfo->AbilityMatch = AN_FALSE;
+ pAnInfo->IdleMatch = AN_FALSE;
+ pAnInfo->AckMatch = AN_FALSE;
+
+ pAnInfo->State = AN_STATE_AN_RESTART_INIT;
+ }
+ else
+ {
+ pAnInfo->State = AN_STATE_DISABLE_LINK_OK;
+ }
+ break;
+
+ case AN_STATE_AN_RESTART_INIT:
+ pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us;
+ pAnInfo->mr_np_loaded = AN_FALSE;
+
+ pAnInfo->TxConfig.AsUSHORT = 0;
+ MM_AnTxConfig(pAnInfo);
+
+ AnRet = AUTONEG_STATUS_TIMER_ENABLED;
+
+ pAnInfo->State = AN_STATE_AN_RESTART;
+
+ /* Fall through.*/
+
+ case AN_STATE_AN_RESTART:
+ /* Get the current time and compute the delta with the saved */
+ /* link timer. */
+ Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us;
+ if(Delta_us > AN_LINK_TIMER_INTERVAL_US)
+ {
+ pAnInfo->State = AN_STATE_ABILITY_DETECT_INIT;
+ }
+ else
+ {
+ AnRet = AUTONEG_STATUS_TIMER_ENABLED;
+ }
+ break;
+
+ case AN_STATE_DISABLE_LINK_OK:
+ AnRet = AUTONEG_STATUS_DONE;
+ break;
+
+ case AN_STATE_ABILITY_DETECT_INIT:
+ /* Note: in the state diagram, this variable is set to */
+ /* mr_adv_ability<12>. Is this right?. */
+ pAnInfo->mr_toggle_tx = AN_FALSE;
+
+ /* Send the config as advertised in the advertisement register. */
+ pAnInfo->TxConfig.AsUSHORT = 0;
+ pAnInfo->TxConfig.D5_FD = pAnInfo->mr_adv_full_duplex;
+ pAnInfo->TxConfig.D6_HD = pAnInfo->mr_adv_half_duplex;
+ pAnInfo->TxConfig.D7_PS1 = pAnInfo->mr_adv_sym_pause;
+ pAnInfo->TxConfig.D8_PS2 = pAnInfo->mr_adv_asym_pause;
+ pAnInfo->TxConfig.D12_RF1 = pAnInfo->mr_adv_remote_fault1;
+ pAnInfo->TxConfig.D13_RF2 = pAnInfo->mr_adv_remote_fault2;
+ pAnInfo->TxConfig.D15_NP = pAnInfo->mr_adv_next_page;
+
+ MM_AnTxConfig(pAnInfo);
+
+ pAnInfo->State = AN_STATE_ABILITY_DETECT;
+
+ break;
+
+ case AN_STATE_ABILITY_DETECT:
+ if(pAnInfo->AbilityMatch == AN_TRUE &&
+ pAnInfo->RxConfig.AsUSHORT != 0)
+ {
+ pAnInfo->State = AN_STATE_ACK_DETECT_INIT;
+ }
+
+ break;
+
+ case AN_STATE_ACK_DETECT_INIT:
+ pAnInfo->TxConfig.D14_ACK = 1;
+ MM_AnTxConfig(pAnInfo);
+
+ pAnInfo->State = AN_STATE_ACK_DETECT;
+
+ /* Fall through. */
+
+ case AN_STATE_ACK_DETECT:
+ if(pAnInfo->AckMatch == AN_TRUE)
+ {
+ if((pAnInfo->RxConfig.AsUSHORT & ~AN_CONFIG_ACK) ==
+ (pAnInfo->AbilityMatchCfg & ~AN_CONFIG_ACK))
+ {
+ pAnInfo->State = AN_STATE_COMPLETE_ACK_INIT;
+ }
+ else
+ {
+ pAnInfo->State = AN_STATE_AN_ENABLE;
+ }
+ }
+ else if(pAnInfo->AbilityMatch == AN_TRUE &&
+ pAnInfo->RxConfig.AsUSHORT == 0)
+ {
+ pAnInfo->State = AN_STATE_AN_ENABLE;
+ }
+
+ break;
+
+ case AN_STATE_COMPLETE_ACK_INIT:
+ /* Make sure invalid bits are not set. */
+ if(pAnInfo->RxConfig.bits.D0 || pAnInfo->RxConfig.bits.D1 ||
+ pAnInfo->RxConfig.bits.D2 || pAnInfo->RxConfig.bits.D3 ||
+ pAnInfo->RxConfig.bits.D4 || pAnInfo->RxConfig.bits.D9 ||
+ pAnInfo->RxConfig.bits.D10 || pAnInfo->RxConfig.bits.D11)
+ {
+ AnRet = AUTONEG_STATUS_FAILED;
+ break;
+ }
+
+ /* Set up the link partner advertisement register. */
+ pAnInfo->mr_lp_adv_full_duplex = pAnInfo->RxConfig.D5_FD;
+ pAnInfo->mr_lp_adv_half_duplex = pAnInfo->RxConfig.D6_HD;
+ pAnInfo->mr_lp_adv_sym_pause = pAnInfo->RxConfig.D7_PS1;
+ pAnInfo->mr_lp_adv_asym_pause = pAnInfo->RxConfig.D8_PS2;
+ pAnInfo->mr_lp_adv_remote_fault1 = pAnInfo->RxConfig.D12_RF1;
+ pAnInfo->mr_lp_adv_remote_fault2 = pAnInfo->RxConfig.D13_RF2;
+ pAnInfo->mr_lp_adv_next_page = pAnInfo->RxConfig.D15_NP;
+
+ pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us;
+
+ pAnInfo->mr_toggle_tx = !pAnInfo->mr_toggle_tx;
+ pAnInfo->mr_toggle_rx = pAnInfo->RxConfig.bits.D11;
+ pAnInfo->mr_np_rx = pAnInfo->RxConfig.D15_NP;
+ pAnInfo->mr_page_rx = AN_TRUE;
+
+ pAnInfo->State = AN_STATE_COMPLETE_ACK;
+ AnRet = AUTONEG_STATUS_TIMER_ENABLED;
+
+ break;
+
+ case AN_STATE_COMPLETE_ACK:
+ if(pAnInfo->AbilityMatch == AN_TRUE &&
+ pAnInfo->RxConfig.AsUSHORT == 0)
+ {
+ pAnInfo->State = AN_STATE_AN_ENABLE;
+ break;
+ }
+
+ Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us;
+
+ if(Delta_us > AN_LINK_TIMER_INTERVAL_US)
+ {
+ if(pAnInfo->mr_adv_next_page == 0 ||
+ pAnInfo->mr_lp_adv_next_page == 0)
+ {
+ pAnInfo->State = AN_STATE_IDLE_DETECT_INIT;
+ }
+ else
+ {
+ if(pAnInfo->TxConfig.bits.D15 == 0 &&
+ pAnInfo->mr_np_rx == 0)
+ {
+ pAnInfo->State = AN_STATE_IDLE_DETECT_INIT;
+ }
+ else
+ {
+ AnRet = AUTONEG_STATUS_FAILED;
+ }
+ }
+ }
+
+ break;
+
+ case AN_STATE_IDLE_DETECT_INIT:
+ pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us;
+
+ MM_AnTxIdle(pAnInfo);
+
+ pAnInfo->State = AN_STATE_IDLE_DETECT;
+
+ AnRet = AUTONEG_STATUS_TIMER_ENABLED;
+
+ break;
+
+ case AN_STATE_IDLE_DETECT:
+ if(pAnInfo->AbilityMatch == AN_TRUE &&
+ pAnInfo->RxConfig.AsUSHORT == 0)
+ {
+ pAnInfo->State = AN_STATE_AN_ENABLE;
+ break;
+ }
+
+ Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us;
+ if(Delta_us > AN_LINK_TIMER_INTERVAL_US)
+ {
+#if 0
+/* if(pAnInfo->IdleMatch == AN_TRUE) */
+/* { */
+#endif
+ pAnInfo->State = AN_STATE_LINK_OK;
+#if 0
+/* } */
+/* else */
+/* { */
+/* AnRet = AUTONEG_STATUS_FAILED; */
+/* break; */
+/* } */
+#endif
+ }
+
+ break;
+
+ case AN_STATE_LINK_OK:
+ pAnInfo->mr_an_complete = AN_TRUE;
+ pAnInfo->mr_link_ok = AN_TRUE;
+ AnRet = AUTONEG_STATUS_DONE;
+
+ break;
+
+ case AN_STATE_NEXT_PAGE_WAIT_INIT:
+ break;
+
+ case AN_STATE_NEXT_PAGE_WAIT:
+ break;
+
+ default:
+ AnRet = AUTONEG_STATUS_FAILED;
+ break;
+ }
+
+ return AnRet;
+}
+#endif /* INCLUDE_TBI_SUPPORT */
+
+#endif /* !defined(CONFIG_NET_MULTI) */
diff --git a/drivers/cs8900.h b/drivers/cs8900.h
new file mode 100644
index 0000000..0a35ba6
--- /dev/null
+++ b/drivers/cs8900.h
@@ -0,0 +1,256 @@
+/*
+ * Cirrus Logic CS8900A Ethernet
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is loaded into SRAM in bootstrap mode, where it waits
+ * for commands on UART1 to read and write memory, jump to code etc.
+ * A design goal for this program is to be entirely independent of the
+ * target board. Anything with a CL-PS7111 or EP7211 should be able to run
+ * this code in bootstrap mode. All the board specifics can be handled on
+ * the host.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/types.h>
+#include <config.h>
+
+#ifdef CONFIG_DRIVER_CS8900
+
+/* although the registers are 16 bit, they are 32-bit aligned on the
+ EDB7111. so we have to read them as 32-bit registers and ignore the
+ upper 16-bits. i'm not sure if this holds for the EDB7211. */
+
+#ifdef CS8900_BUS16
+ /* 16 bit aligned registers, 16 bit wide */
+ #define CS8900_REG u16
+ #define CS8900_OFF 0x02
+ #define CS8900_BUS16_0 *(volatile u8 *)(CS8900_BASE+0x00)
+ #define CS8900_BUS16_1 *(volatile u8 *)(CS8900_BASE+0x01)
+#elif CS8900_BUS32
+ /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
+ #define CS8900_REG u32
+ #define CS8900_OFF 0x04
+#else
+ #error unknown bussize ...
+#endif
+
+#define CS8900_RTDATA *(volatile CS8900_REG *)(CS8900_BASE+0x00*CS8900_OFF)
+#define CS8900_TxCMD *(volatile CS8900_REG *)(CS8900_BASE+0x02*CS8900_OFF)
+#define CS8900_TxLEN *(volatile CS8900_REG *)(CS8900_BASE+0x03*CS8900_OFF)
+#define CS8900_ISQ *(volatile CS8900_REG *)(CS8900_BASE+0x04*CS8900_OFF)
+#define CS8900_PPTR *(volatile CS8900_REG *)(CS8900_BASE+0x05*CS8900_OFF)
+#define CS8900_PDATA *(volatile CS8900_REG *)(CS8900_BASE+0x06*CS8900_OFF)
+
+
+#define ISQ_RxEvent 0x04
+#define ISQ_TxEvent 0x08
+#define ISQ_BufEvent 0x0C
+#define ISQ_RxMissEvent 0x10
+#define ISQ_TxColEvent 0x12
+#define ISQ_EventMask 0x3F
+
+/* packet page register offsets */
+
+/* bus interface registers */
+#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
+#define PP_ChipRev 0x0002 /* Chip revision, model codes */
+
+#define PP_IntReg 0x0022 /* Interrupt configuration */
+#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
+#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */
+#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */
+#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */
+
+/* status and control registers */
+
+#define PP_RxCFG 0x0102 /* Receiver configuration */
+#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */
+#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */
+#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */
+#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */
+#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */
+#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */
+#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */
+#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */
+#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */
+
+#define PP_RxCTL 0x0104 /* Receiver control */
+#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */
+#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */
+#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */
+#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */
+#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */
+#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */
+#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */
+#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */
+#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */
+
+#define PP_TxCFG 0x0106 /* Transmit configuration */
+#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */
+#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */
+#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */
+#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */
+#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */
+#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */
+#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */
+
+#define PP_TxCmd 0x0108 /* Transmit command status */
+#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */
+#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */
+#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */
+#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */
+#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */
+#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */
+#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */
+#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */
+
+#define PP_BufCFG 0x010A /* Buffer configuration */
+#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */
+#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */
+#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */
+#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */
+#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */
+#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */
+#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */
+#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */
+#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */
+
+#define PP_LineCTL 0x0112 /* Line control */
+#define PP_LineCTL_Rx 0x0040 /* Enable receiver */
+#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */
+#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */
+#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */
+#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */
+#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */
+#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */
+#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */
+
+#define PP_SelfCTL 0x0114 /* Chip self control */
+#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */
+#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */
+#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */
+#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */
+#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */
+#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */
+#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */
+#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */
+
+#define PP_BusCTL 0x0116 /* Bus control */
+#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */
+#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */
+#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */
+#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */
+#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */
+#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */
+#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */
+#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */
+
+#define PP_TestCTL 0x0118 /* Test control */
+#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */
+#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */
+#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */
+#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */
+#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */
+
+#define PP_ISQ 0x0120 /* Interrupt Status Queue */
+
+#define PP_RER 0x0124 /* Receive event */
+#define PP_RER_IAHash 0x0040 /* Frame hash match */
+#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */
+#define PP_RER_RxOK 0x0100 /* Frame received with no errors */
+#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */
+#define PP_RER_IA 0x0400 /* Frame address matched IA */
+#define PP_RER_Broadcast 0x0800 /* Broadcast frame */
+#define PP_RER_CRC 0x1000 /* Frame had CRC error */
+#define PP_RER_RUNT 0x2000 /* Runt frame */
+#define PP_RER_EXTRA 0x4000 /* Frame was too long */
+
+#define PP_TER 0x0128 /* Transmit event */
+#define PP_TER_CRS 0x0040 /* Carrier lost */
+#define PP_TER_SQE 0x0080 /* Signal Quality Error */
+#define PP_TER_TxOK 0x0100 /* Packet sent without error */
+#define PP_TER_Late 0x0200 /* Out of window */
+#define PP_TER_Jabber 0x0400 /* Stuck transmit? */
+#define PP_TER_NumCollisions 0x7800 /* Number of collisions */
+#define PP_TER_16Collisions 0x8000 /* > 16 collisions */
+
+#define PP_BER 0x012C /* Buffer event */
+#define PP_BER_SWint 0x0040 /* Software interrupt */
+#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */
+#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */
+#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
+#define PP_BER_RxMiss 0x0400 /* Received frame missed */
+#define PP_BER_Rx128 0x0800 /* 128 bytes received */
+#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */
+
+#define PP_RxMiss 0x0130 /* Receiver miss counter */
+
+#define PP_TxCol 0x0132 /* Transmit collision counter */
+
+#define PP_LineSTAT 0x0134 /* Line status */
+#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */
+#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */
+#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */
+#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */
+#define PP_LineSTAT_CRS 0x4000 /* Frame being received */
+
+#define PP_SelfSTAT 0x0136 /* Chip self status */
+#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */
+#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */
+#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */
+#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */
+#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */
+#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */
+#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */
+
+#define PP_BusSTAT 0x0138 /* Bus status */
+#define PP_BusSTAT_TxBid 0x0080 /* Tx error */
+#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */
+
+#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */
+
+/* initiate transmit registers */
+
+#define PP_TxCommand 0x0144 /* Tx Command */
+#define PP_TxLength 0x0146 /* Tx Length */
+
+
+/* address filter registers */
+
+#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */
+#define PP_IA 0x0158 /* Individual address (MAC) */
+
+/* EEPROM Kram */
+#define SI_BUSY 0x0100
+#define PP_SelfST 0x0136 /* Self State register */
+#define PP_EECMD 0x0040 /* NVR Interface Command register */
+#define PP_EEData 0x0042 /* NVR Interface Data Register */
+#define EEPROM_WRITE_EN 0x00F0
+#define EEPROM_WRITE_DIS 0x0000
+#define EEPROM_WRITE_CMD 0x0100
+#define EEPROM_READ_CMD 0x0200
+
+
+
+#endif /* CONFIG_DRIVER_CS8900 */
diff --git a/drivers/natsemi.c b/drivers/natsemi.c
new file mode 100644
index 0000000..5a8c5b4
--- /dev/null
+++ b/drivers/natsemi.c
@@ -0,0 +1,881 @@
+/*
+ natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
+ Author: Mark A. Rakes (mark_rakes@vivato.net)
+
+ Adapted from an Etherboot driver written by:
+
+ Copyright (C) 2001 Entity Cyber, Inc.
+
+ This development of this Etherboot driver was funded by
+
+ Sicom Systems: http://www.sicompos.com/
+
+ Author: Marty Connor (mdc@thinguin.org)
+ Adapted from a Linux driver which was written by Donald Becker
+
+ This software may be used and distributed according to the terms
+ of the GNU Public License (GPL), incorporated herein by reference.
+
+ Original Copyright Notice:
+
+ Written/copyright 1999-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms of
+ the GNU General Public License (GPL), incorporated herein by reference.
+ Drivers based on or derived from this code fall under the GPL and must
+ retain the authorship, copyright and license notice. This file is not
+ a complete program and may only be used when the entire operating
+ system is licensed under the GPL. License for under other terms may be
+ available. Contact the original author for details.
+
+ The original author may be reached as becker@scyld.com, or at
+ Scyld Computing Corporation
+ 410 Severn Ave., Suite 210
+ Annapolis MD 21403
+
+ Support information and updates available at
+ http://www.scyld.com/network/netsemi.html
+
+ References:
+ http://www.scyld.com/expert/100mbps.html
+ http://www.scyld.com/expert/NWay.html
+ Datasheet is available from:
+ http://www.national.com/pf/DP/DP83815.html
+*/
+
+/* Revision History
+ * October 2002 mar 1.0
+ * Initial U-Boot Release. Tested with Netgear FA311 board
+ * and dp83815 chipset on custom board
+*/
+
+/* Includes */
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
+ defined(CONFIG_NATSEMI)
+
+/* defines */
+#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
+
+#define DSIZE 0x00000FFF
+#define ETH_ALEN 6
+#define CRC_SIZE 4
+#define TOUT_LOOP 500000
+#define TX_BUF_SIZE 1536
+#define RX_BUF_SIZE 1536
+#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
+
+/* Offsets to the device registers.
+ Unlike software-only systems, device drivers interact with complex hardware.
+ It's not useful to define symbolic names for every register bit in the
+ device. */
+enum register_offsets {
+ ChipCmd = 0x00,
+ ChipConfig = 0x04,
+ EECtrl = 0x08,
+ IntrMask = 0x14,
+ IntrEnable = 0x18,
+ TxRingPtr = 0x20,
+ TxConfig = 0x24,
+ RxRingPtr = 0x30,
+ RxConfig = 0x34,
+ ClkRun = 0x3C,
+ RxFilterAddr = 0x48,
+ RxFilterData = 0x4C,
+ SiliconRev = 0x58,
+ PCIPM = 0x44,
+ BasicControl = 0x80,
+ BasicStatus = 0x84,
+ /* These are from the spec, around page 78... on a separate table. */
+ PGSEL = 0xCC,
+ PMDCSR = 0xE4,
+ TSTDAT = 0xFC,
+ DSPCFG = 0xF4,
+ SDCFG = 0x8C
+};
+
+/* Bit in ChipCmd. */
+enum ChipCmdBits {
+ ChipReset = 0x100,
+ RxReset = 0x20,
+ TxReset = 0x10,
+ RxOff = 0x08,
+ RxOn = 0x04,
+ TxOff = 0x02,
+ TxOn = 0x01
+};
+
+enum ChipConfigBits {
+ LinkSts = 0x80000000,
+ HundSpeed = 0x40000000,
+ FullDuplex = 0x20000000,
+ TenPolarity = 0x10000000,
+ AnegDone = 0x08000000,
+ AnegEnBothBoth = 0x0000E000,
+ AnegDis100Full = 0x0000C000,
+ AnegEn100Both = 0x0000A000,
+ AnegDis100Half = 0x00008000,
+ AnegEnBothHalf = 0x00006000,
+ AnegDis10Full = 0x00004000,
+ AnegEn10Both = 0x00002000,
+ DuplexMask = 0x00008000,
+ SpeedMask = 0x00004000,
+ AnegMask = 0x00002000,
+ AnegDis10Half = 0x00000000,
+ ExtPhy = 0x00001000,
+ PhyRst = 0x00000400,
+ PhyDis = 0x00000200,
+ BootRomDisable = 0x00000004,
+ BEMode = 0x00000001,
+};
+
+enum TxConfig_bits {
+ TxDrthMask = 0x3f,
+ TxFlthMask = 0x3f00,
+ TxMxdmaMask = 0x700000,
+ TxMxdma_512 = 0x0,
+ TxMxdma_4 = 0x100000,
+ TxMxdma_8 = 0x200000,
+ TxMxdma_16 = 0x300000,
+ TxMxdma_32 = 0x400000,
+ TxMxdma_64 = 0x500000,
+ TxMxdma_128 = 0x600000,
+ TxMxdma_256 = 0x700000,
+ TxCollRetry = 0x800000,
+ TxAutoPad = 0x10000000,
+ TxMacLoop = 0x20000000,
+ TxHeartIgn = 0x40000000,
+ TxCarrierIgn = 0x80000000
+};
+
+enum RxConfig_bits {
+ RxDrthMask = 0x3e,
+ RxMxdmaMask = 0x700000,
+ RxMxdma_512 = 0x0,
+ RxMxdma_4 = 0x100000,
+ RxMxdma_8 = 0x200000,
+ RxMxdma_16 = 0x300000,
+ RxMxdma_32 = 0x400000,
+ RxMxdma_64 = 0x500000,
+ RxMxdma_128 = 0x600000,
+ RxMxdma_256 = 0x700000,
+ RxAcceptLong = 0x8000000,
+ RxAcceptTx = 0x10000000,
+ RxAcceptRunt = 0x40000000,
+ RxAcceptErr = 0x80000000
+};
+
+/* Bits in the RxMode register. */
+enum rx_mode_bits {
+ AcceptErr = 0x20,
+ AcceptRunt = 0x10,
+ AcceptBroadcast = 0xC0000000,
+ AcceptMulticast = 0x00200000,
+ AcceptAllMulticast = 0x20000000,
+ AcceptAllPhys = 0x10000000,
+ AcceptMyPhys = 0x08000000
+};
+
+typedef struct _BufferDesc {
+ u32 link;
+ vu_long cmdsts;
+ u32 bufptr;
+ u32 software_use;
+} BufferDesc;
+
+/* Bits in network_desc.status */
+enum desc_status_bits {
+ DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
+ DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
+ DescSizeMask = 0xfff,
+
+ DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
+ DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
+ DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
+ DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
+
+ DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
+ DescRxDest = 0x01800000, DescRxLong = 0x00400000,
+ DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
+ DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
+ DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
+};
+
+/* Globals */
+#ifdef NATSEMI_DEBUG
+static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
+#endif
+static u32 SavedClkRun;
+static unsigned int cur_rx;
+static unsigned int advertising;
+static unsigned int rx_config;
+static unsigned int tx_config;
+
+/* Note: transmit and receive buffers and descriptors must be
+ longword aligned */
+static BufferDesc txd __attribute__ ((aligned(4)));
+static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
+
+static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
+static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
+ __attribute__ ((aligned(4)));
+
+/* Function Prototypes */
+#if 0
+static void write_eeprom(struct eth_device *dev, long addr, int location,
+ short value);
+#endif
+static int read_eeprom(struct eth_device *dev, long addr, int location);
+static int mdio_read(struct eth_device *dev, int phy_id, int location);
+static int natsemi_init(struct eth_device *dev, bd_t * bis);
+static void natsemi_reset(struct eth_device *dev);
+static void natsemi_init_rxfilter(struct eth_device *dev);
+static void natsemi_init_txd(struct eth_device *dev);
+static void natsemi_init_rxd(struct eth_device *dev);
+static void natsemi_set_rx_mode(struct eth_device *dev);
+static void natsemi_check_duplex(struct eth_device *dev);
+static int natsemi_send(struct eth_device *dev, volatile void *packet,
+ int length);
+static int natsemi_poll(struct eth_device *dev);
+static void natsemi_disable(struct eth_device *dev);
+
+static struct pci_device_id supported[] = {
+ {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
+ {}
+};
+
+#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
+#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+
+static inline int
+INW(struct eth_device *dev, u_long addr)
+{
+ return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
+}
+
+static int
+INL(struct eth_device *dev, u_long addr)
+{
+ return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
+}
+
+static inline void
+OUTW(struct eth_device *dev, int command, u_long addr)
+{
+ *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
+}
+
+static inline void
+OUTL(struct eth_device *dev, int command, u_long addr)
+{
+ *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
+}
+
+/*
+ * Function: natsemi_initialize
+ *
+ * Description: Retrieves the MAC address of the card, and sets up some
+ * globals required by other routines, and initializes the NIC, making it
+ * ready to send and receive packets.
+ *
+ * Side effects:
+ * leaves the natsemi initialized, and ready to recieve packets.
+ *
+ * Returns: struct eth_device *: pointer to NIC data structure
+ */
+
+int
+natsemi_initialize(bd_t * bis)
+{
+ pci_dev_t devno;
+ int card_number = 0;
+ struct eth_device *dev;
+ u32 iobase, status, chip_config;
+ int i, idx = 0;
+ int prev_eedata;
+ u32 tmp;
+
+ while (1) {
+ /* Find PCI device(s) */
+ if ((devno = pci_find_devices(supported, idx++)) < 0) {
+ break;
+ }
+
+ pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
+ iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
+
+ pci_write_config_dword(devno, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Check if I/O accesses and Bus Mastering are enabled. */
+ pci_read_config_dword(devno, PCI_COMMAND, &status);
+ if (!(status & PCI_COMMAND_MEMORY)) {
+ printf("Error: Can not enable MEM access.\n");
+ continue;
+ } else if (!(status & PCI_COMMAND_MASTER)) {
+ printf("Error: Can not enable Bus Mastering.\n");
+ continue;
+ }
+
+ dev = (struct eth_device *) malloc(sizeof *dev);
+
+ sprintf(dev->name, "dp83815#%d", card_number);
+ dev->iobase = bus_to_phys(iobase);
+#ifdef NATSEMI_DEBUG
+ printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
+#endif
+ dev->priv = (void *) devno;
+ dev->init = natsemi_init;
+ dev->halt = natsemi_disable;
+ dev->send = natsemi_send;
+ dev->recv = natsemi_poll;
+
+ eth_register(dev);
+
+ card_number++;
+
+ /* Set the latency timer for value. */
+ pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
+
+ udelay(10 * 1000);
+
+ /* natsemi has a non-standard PM control register
+ * in PCI config space. Some boards apparently need
+ * to be brought to D0 in this manner. */
+ pci_read_config_dword(devno, PCIPM, &tmp);
+ if (tmp & (0x03 | 0x100)) {
+ /* D0 state, disable PME assertion */
+ u32 newtmp = tmp & ~(0x03 | 0x100);
+ pci_write_config_dword(devno, PCIPM, newtmp);
+ }
+
+ printf("natsemi: EEPROM contents:\n");
+ for (i = 0; i <= EEPROM_SIZE; i++) {
+ short eedata = read_eeprom(dev, EECtrl, i);
+ printf(" %04hx", eedata);
+ }
+ printf("\n");
+
+ /* get MAC address */
+ prev_eedata = read_eeprom(dev, EECtrl, 6);
+ for (i = 0; i < 3; i++) {
+ int eedata = read_eeprom(dev, EECtrl, i + 7);
+ dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
+ dev->enetaddr[i*2+1] = eedata >> 7;
+ prev_eedata = eedata;
+ }
+
+ /* Reset the chip to erase any previous misconfiguration. */
+ OUTL(dev, ChipReset, ChipCmd);
+
+ advertising = mdio_read(dev, 1, 4);
+ chip_config = INL(dev, ChipConfig);
+#ifdef NATSEMI_DEBUG
+ printf("%s: Transceiver status %#08X advertising %#08X\n",
+ dev->name, (int) INL(dev, BasicStatus), advertising);
+ printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
+ dev->name, chip_config & AnegMask ? "enabled, advertise" :
+ "disabled, force", chip_config & SpeedMask ? "0" : "",
+ chip_config & DuplexMask ? "full" : "half");
+#endif
+ chip_config |= AnegEnBothBoth;
+#ifdef NATSEMI_DEBUG
+ printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
+ dev->name, chip_config & AnegMask ? "enabled, advertise" :
+ "disabled, force", chip_config & SpeedMask ? "0" : "",
+ chip_config & DuplexMask ? "full" : "half");
+#endif
+ /*write new autoneg bits, reset phy*/
+ OUTL(dev, (chip_config | PhyRst), ChipConfig);
+ /*un-reset phy*/
+ OUTL(dev, chip_config, ChipConfig);
+
+ /* Disable PME:
+ * The PME bit is initialized from the EEPROM contents.
+ * PCI cards probably have PME disabled, but motherboard
+ * implementations may have PME set to enable WakeOnLan.
+ * With PME set the chip will scan incoming packets but
+ * nothing will be written to memory. */
+ SavedClkRun = INL(dev, ClkRun);
+ OUTL(dev, SavedClkRun & ~0x100, ClkRun);
+ }
+ return card_number;
+}
+
+/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
+ The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
+
+/* Delay between EEPROM clock transitions.
+ No extra delay is needed with 33Mhz PCI, but future 66Mhz
+ access may need a delay. */
+#define eeprom_delay(ee_addr) INL(dev, ee_addr)
+
+enum EEPROM_Ctrl_Bits {
+ EE_ShiftClk = 0x04,
+ EE_DataIn = 0x01,
+ EE_ChipSelect = 0x08,
+ EE_DataOut = 0x02
+};
+
+#define EE_Write0 (EE_ChipSelect)
+#define EE_Write1 (EE_ChipSelect | EE_DataIn)
+/* The EEPROM commands include the alway-set leading bit. */
+enum EEPROM_Cmds {
+ EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
+ EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
+};
+
+#if 0
+static void
+write_eeprom(struct eth_device *dev, long addr, int location, short value)
+{
+ int i;
+ int ee_addr = (typeof(ee_addr))addr;
+ short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
+ short write_cmd = location | EE_WriteCmd;
+
+#ifdef NATSEMI_DEBUG
+ printf("write_eeprom: %08x, %04hx, %04hx\n",
+ dev->iobase + ee_addr, write_cmd, value);
+#endif
+ /* Shift the write enable command bits out. */
+ for (i = 9; i >= 0; i--) {
+ short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
+ OUTL(dev, cmdval, ee_addr);
+ eeprom_delay(ee_addr);
+ OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+ }
+
+ OUTL(dev, 0, ee_addr); /*bring chip select low*/
+ OUTL(dev, EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+
+ /* Shift the write command bits out. */
+ for (i = 9; i >= 0; i--) {
+ short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
+ OUTL(dev, cmdval, ee_addr);
+ eeprom_delay(ee_addr);
+ OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+ }
+
+ for (i = 0; i < 16; i++) {
+ short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
+ OUTL(dev, cmdval, ee_addr);
+ eeprom_delay(ee_addr);
+ OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+ }
+
+ OUTL(dev, 0, ee_addr); /*bring chip select low*/
+ OUTL(dev, EE_ShiftClk, ee_addr);
+ for (i = 0; i < 200000; i++) {
+ OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
+ if (INL(dev, ee_addr) & EE_DataOut) {
+ break; /*finished*/
+ }
+ }
+ eeprom_delay(ee_addr);
+
+ /* Terminate the EEPROM access. */
+ OUTL(dev, EE_Write0, ee_addr);
+ OUTL(dev, 0, ee_addr);
+ return;
+}
+#endif
+
+static int
+read_eeprom(struct eth_device *dev, long addr, int location)
+{
+ int i;
+ int retval = 0;
+ int ee_addr = (typeof(ee_addr))addr;
+ int read_cmd = location | EE_ReadCmd;
+
+ OUTL(dev, EE_Write0, ee_addr);
+
+ /* Shift the read command bits out. */
+ for (i = 10; i >= 0; i--) {
+ short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
+ OUTL(dev, dataval, ee_addr);
+ eeprom_delay(ee_addr);
+ OUTL(dev, dataval | EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+ }
+ OUTL(dev, EE_ChipSelect, ee_addr);
+ eeprom_delay(ee_addr);
+
+ for (i = 0; i < 16; i++) {
+ OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+ retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
+ OUTL(dev, EE_ChipSelect, ee_addr);
+ eeprom_delay(ee_addr);
+ }
+
+ /* Terminate the EEPROM access. */
+ OUTL(dev, EE_Write0, ee_addr);
+ OUTL(dev, 0, ee_addr);
+#ifdef NATSEMI_DEBUG
+ if (natsemi_debug)
+ printf("read_eeprom: %08x, %08x, retval %08x\n",
+ dev->iobase + ee_addr, read_cmd, retval);
+#endif
+ return retval;
+}
+
+/* MII transceiver control section.
+ The 83815 series has an internal transceiver, and we present the
+ management registers as if they were MII connected. */
+
+static int
+mdio_read(struct eth_device *dev, int phy_id, int location)
+{
+ if (phy_id == 1 && location < 32)
+ return INL(dev, BasicControl+(location<<2))&0xffff;
+ else
+ return 0xffff;
+}
+
+/* Function: natsemi_init
+ *
+ * Description: resets the ethernet controller chip and configures
+ * registers and data structures required for sending and receiving packets.
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * returns: int.
+ */
+
+static int
+natsemi_init(struct eth_device *dev, bd_t * bis)
+{
+
+ natsemi_reset(dev);
+
+ /* Disable PME:
+ * The PME bit is initialized from the EEPROM contents.
+ * PCI cards probably have PME disabled, but motherboard
+ * implementations may have PME set to enable WakeOnLan.
+ * With PME set the chip will scan incoming packets but
+ * nothing will be written to memory. */
+ OUTL(dev, SavedClkRun & ~0x100, ClkRun);
+
+ natsemi_init_rxfilter(dev);
+ natsemi_init_txd(dev);
+ natsemi_init_rxd(dev);
+
+ /* Configure the PCI bus bursts and FIFO thresholds. */
+ tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
+ rx_config = RxMxdma_256 | 0x20;
+
+#ifdef NATSEMI_DEBUG
+ printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
+ printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
+#endif
+ OUTL(dev, tx_config, TxConfig);
+ OUTL(dev, rx_config, RxConfig);
+
+ natsemi_check_duplex(dev);
+ natsemi_set_rx_mode(dev);
+
+ OUTL(dev, (RxOn | TxOn), ChipCmd);
+ return 1;
+}
+
+/*
+ * Function: natsemi_reset
+ *
+ * Description: soft resets the controller chip
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * Returns: void.
+ */
+static void
+natsemi_reset(struct eth_device *dev)
+{
+ OUTL(dev, ChipReset, ChipCmd);
+
+ /* On page 78 of the spec, they recommend some settings for "optimum
+ performance" to be done in sequence. These settings optimize some
+ of the 100Mbit autodetection circuitry. Also, we only want to do
+ this for rev C of the chip. */
+ if (INL(dev, SiliconRev) == 0x302) {
+ OUTW(dev, 0x0001, PGSEL);
+ OUTW(dev, 0x189C, PMDCSR);
+ OUTW(dev, 0x0000, TSTDAT);
+ OUTW(dev, 0x5040, DSPCFG);
+ OUTW(dev, 0x008C, SDCFG);
+ }
+ /* Disable interrupts using the mask. */
+ OUTL(dev, 0, IntrMask);
+ OUTL(dev, 0, IntrEnable);
+}
+
+/* Function: natsemi_init_rxfilter
+ *
+ * Description: sets receive filter address to our MAC address
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * returns: void.
+ */
+
+static void
+natsemi_init_rxfilter(struct eth_device *dev)
+{
+ int i;
+
+ for (i = 0; i < ETH_ALEN; i += 2) {
+ OUTL(dev, i, RxFilterAddr);
+ OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
+ RxFilterData);
+ }
+}
+
+/*
+ * Function: natsemi_init_txd
+ *
+ * Description: initializes the Tx descriptor
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * returns: void.
+ */
+
+static void
+natsemi_init_txd(struct eth_device *dev)
+{
+ txd.link = (u32) 0;
+ txd.cmdsts = (u32) 0;
+ txd.bufptr = (u32) & txb[0];
+
+ /* load Transmit Descriptor Register */
+ OUTL(dev, (u32) & txd, TxRingPtr);
+#ifdef NATSEMI_DEBUG
+ printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
+ INL(dev, TxRingPtr));
+#endif
+}
+
+/* Function: natsemi_init_rxd
+ *
+ * Description: initializes the Rx descriptor ring
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * Returns: void.
+ */
+
+static void
+natsemi_init_rxd(struct eth_device *dev)
+{
+ int i;
+
+ cur_rx = 0;
+
+ /* init RX descriptor */
+ for (i = 0; i < NUM_RX_DESC; i++) {
+ rxd[i].link =
+ cpu_to_le32((i + 1 <
+ NUM_RX_DESC) ? (u32) & rxd[i +
+ 1] : (u32) &
+ rxd[0]);
+ rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
+ rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
+#ifdef NATSEMI_DEBUG
+ printf
+ ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
+ i, &rxd[i], le32_to_cpu(rxd[i].link),
+ rxd[i].cmdsts, rxd[i].bufptr);
+#endif
+ }
+
+ /* load Receive Descriptor Register */
+ OUTL(dev, (u32) & rxd[0], RxRingPtr);
+
+#ifdef NATSEMI_DEBUG
+ printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
+ INL(dev, RxRingPtr));
+#endif
+}
+
+/* Function: natsemi_set_rx_mode
+ *
+ * Description:
+ * sets the receive mode to accept all broadcast packets and packets
+ * with our MAC address, and reject all multicast packets.
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * Returns: void.
+ */
+
+static void
+natsemi_set_rx_mode(struct eth_device *dev)
+{
+ u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
+
+ OUTL(dev, rx_mode, RxFilterAddr);
+}
+
+static void
+natsemi_check_duplex(struct eth_device *dev)
+{
+ int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
+
+#ifdef NATSEMI_DEBUG
+ printf("%s: Setting %s-duplex based on negotiated link"
+ " capability.\n", dev->name, duplex ? "full" : "half");
+#endif
+ if (duplex) {
+ rx_config |= RxAcceptTx;
+ tx_config |= (TxCarrierIgn | TxHeartIgn);
+ } else {
+ rx_config &= ~RxAcceptTx;
+ tx_config &= ~(TxCarrierIgn | TxHeartIgn);
+ }
+ OUTL(dev, tx_config, TxConfig);
+ OUTL(dev, rx_config, RxConfig);
+}
+
+/* Function: natsemi_send
+ *
+ * Description: transmits a packet and waits for completion or timeout.
+ *
+ * Returns: void. */
+static int
+natsemi_send(struct eth_device *dev, volatile void *packet, int length)
+{
+ u32 i, status = 0;
+ u32 tx_status = 0;
+
+ /* Stop the transmitter */
+ OUTL(dev, TxOff, ChipCmd);
+
+#ifdef NATSEMI_DEBUG
+ if (natsemi_debug)
+ printf("natsemi_send: sending %d bytes\n", (int) length);
+#endif
+
+ /* set the transmit buffer descriptor and enable Transmit State Machine */
+ txd.link = cpu_to_le32(0);
+ txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
+ txd.cmdsts = cpu_to_le32(DescOwn | length);
+
+ /* load Transmit Descriptor Register */
+ OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
+#ifdef NATSEMI_DEBUG
+ if (natsemi_debug)
+ printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
+ INL(dev, TxRingPtr));
+#endif
+ /* restart the transmitter */
+ OUTL(dev, TxOn, ChipCmd);
+
+ for (i = 0;
+ ((vu_long)tx_status = le32_to_cpu(txd.cmdsts)) & DescOwn;
+ i++) {
+ if (i >= TOUT_LOOP) {
+ printf
+ ("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
+ dev->name, tx_status);
+ goto Done;
+ }
+ }
+
+ if (!(tx_status & DescPktOK)) {
+ printf("natsemi_send: Transmit error, Tx status %X.\n",
+ tx_status);
+ goto Done;
+ }
+
+ status = 1;
+ Done:
+ return status;
+}
+
+/* Function: natsemi_poll
+ *
+ * Description: checks for a received packet and returns it if found.
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * Returns: 1 if packet was received.
+ * 0 if no packet was received.
+ *
+ * Side effects:
+ * Returns (copies) the packet to the array dev->packet.
+ * Returns the length of the packet.
+ */
+
+static int
+natsemi_poll(struct eth_device *dev)
+{
+ int retstat = 0;
+ int length = 0;
+ u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
+
+ if (!(rx_status & (u32) DescOwn))
+ return retstat;
+#ifdef NATSEMI_DEBUG
+ if (natsemi_debug)
+ printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
+ cur_rx, rx_status);
+#endif
+ length = (rx_status & DSIZE) - CRC_SIZE;
+
+ if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
+ printf
+ ("natsemi_poll: Corrupted packet received, buffer status = %X\n",
+ rx_status);
+ retstat = 0;
+ } else { /* give packet to higher level routine */
+ NetReceive((rxb + cur_rx * RX_BUF_SIZE), length);
+ retstat = 1;
+ }
+
+ /* return the descriptor and buffer to receive ring */
+ rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
+ rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
+
+ if (++cur_rx == NUM_RX_DESC)
+ cur_rx = 0;
+
+ /* re-enable the potentially idle receive state machine */
+ OUTL(dev, RxOn, ChipCmd);
+
+ return retstat;
+}
+
+/* Function: natsemi_disable
+ *
+ * Description: Turns off interrupts and stops Tx and Rx engines
+ *
+ * Arguments: struct eth_device *dev: NIC data structure
+ *
+ * Returns: void.
+ */
+
+static void
+natsemi_disable(struct eth_device *dev)
+{
+ /* Disable interrupts using the mask. */
+ OUTL(dev, 0, IntrMask);
+ OUTL(dev, 0, IntrEnable);
+
+ /* Stop the chip's Tx and Rx processes. */
+ OUTL(dev, RxOff | TxOff, ChipCmd);
+
+ /* Restore PME enable bit */
+ OUTL(dev, SavedClkRun, ClkRun);
+}
+
+#endif
diff --git a/drivers/nicext.h b/drivers/nicext.h
new file mode 100644
index 0000000..0879dc2
--- /dev/null
+++ b/drivers/nicext.h
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Name: nicext.h
+ *
+ * Description: Broadcom Network Interface Card Extension (NICE) is an
+ * extension to Linux NET device kernel mode drivers.
+ * NICE is designed to provide additional functionalities,
+ * such as receive packet intercept. To support Broadcom NICE,
+ * the network device driver can be modified by adding an
+ * device ioctl handler and by indicating receiving packets
+ * to the NICE receive handler. Broadcom NICE will only be
+ * enabled by a NICE-aware intermediate driver, such as
+ * Broadcom Advanced Server Program Driver (BASP). When NICE
+ * is not enabled, the modified network device drivers
+ * functions exactly as other non-NICE aware drivers.
+ *
+ * Author: Frankie Fan
+ *
+ * Created: September 17, 2000
+ *
+ ****************************************************************************/
+#ifndef _nicext_h_
+#define _nicext_h_
+
+/*
+ * ioctl for NICE
+ */
+#define SIOCNICE SIOCDEVPRIVATE+7
+
+/*
+ * SIOCNICE:
+ *
+ * The following structure needs to be less than IFNAMSIZ (16 bytes) because
+ * we're overloading ifreq.ifr_ifru.
+ *
+ * If 16 bytes is not enough, we should consider relaxing this because
+ * this is no field after ifr_ifru in the ifreq structure. But we may
+ * run into future compatiability problem in case of changing struct ifreq.
+ */
+struct nice_req
+{
+ __u32 cmd;
+
+ union
+ {
+#ifdef __KERNEL__
+ /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */
+ struct
+ {
+ void (*nrqus1_rx)( struct sk_buff*, void* );
+ void* nrqus1_ctx;
+ } nrqu_nrqus1;
+
+ /* cmd = NICE_CMD_QUERY_SUPPORT */
+ struct
+ {
+ __u32 nrqus2_magic;
+ __u32 nrqus2_support_rx:1;
+ __u32 nrqus2_support_vlan:1;
+ __u32 nrqus2_support_get_speed:1;
+ } nrqu_nrqus2;
+#endif
+
+ /* cmd = NICE_CMD_GET_SPEED */
+ struct
+ {
+ unsigned int nrqus3_speed; /* 0 if link is down, */
+ /* otherwise speed in Mbps */
+ } nrqu_nrqus3;
+
+ /* cmd = NICE_CMD_BLINK_LED */
+ struct
+ {
+ unsigned int nrqus4_blink_time; /* blink duration in seconds */
+ } nrqu_nrqus4;
+
+ } nrq_nrqu;
+};
+
+#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx
+#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx
+#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx
+#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic
+#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan
+#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed
+#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed
+#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time
+
+/*
+ * magic constants
+ */
+#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */
+#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */
+
+/*
+ * command field
+ */
+#define NICE_CMD_QUERY_SUPPORT 0x00000001
+#define NICE_CMD_SET_RX 0x00000002
+#define NICE_CMD_GET_RX 0x00000003
+#define NICE_CMD_GET_SPEED 0x00000004
+#define NICE_CMD_BLINK_LED 0x00000005
+
+#endif /* _nicext_h_ */
+
diff --git a/drivers/ns8382x.c b/drivers/ns8382x.c
new file mode 100644
index 0000000..978080e
--- /dev/null
+++ b/drivers/ns8382x.c
@@ -0,0 +1,863 @@
+/*
+ ns8382x.c: A U-Boot driver for the NatSemi DP8382[01].
+ ported by: Mark A. Rakes (mark_rakes@vivato.net)
+
+ Adapted from:
+ 1. an Etherboot driver for DP8381[56] written by:
+ Copyright (C) 2001 Entity Cyber, Inc.
+
+ This development of this Etherboot driver was funded by
+ Sicom Systems: http://www.sicompos.com/
+
+ Author: Marty Connor (mdc@thinguin.org)
+ Adapted from a Linux driver which was written by Donald Becker
+
+ This software may be used and distributed according to the terms
+ of the GNU Public License (GPL), incorporated herein by reference.
+
+ 2. A Linux driver by Donald Becker, ns820.c:
+ Written/copyright 1999-2002 by Donald Becker.
+
+ This software may be used and distributed according to the terms of
+ the GNU General Public License (GPL), incorporated herein by reference.
+ Drivers based on or derived from this code fall under the GPL and must
+ retain the authorship, copyright and license notice. This file is not
+ a complete program and may only be used when the entire operating
+ system is licensed under the GPL. License for under other terms may be
+ available. Contact the original author for details.
+
+ The original author may be reached as becker@scyld.com, or at
+ Scyld Computing Corporation
+ 410 Severn Ave., Suite 210
+ Annapolis MD 21403
+
+ Support information and updates available at
+ http://www.scyld.com/network/netsemi.html
+
+ Datasheets available from:
+ http://www.national.com/pf/DP/DP83820.html
+ http://www.national.com/pf/DP/DP83821.html
+*/
+
+/* Revision History
+ * October 2002 mar 1.0
+ * Initial U-Boot Release.
+ * Tested with Netgear GA622T (83820)
+ * and SMC9452TX (83821)
+ * NOTE: custom boards with these chips may (likely) require
+ * a programmed EEPROM device (if present) in order to work
+ * correctly.
+*/
+
+/* Includes */
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
+ defined(CONFIG_NS8382X)
+
+/* defines */
+#define DSIZE 0x00000FFF
+#define ETH_ALEN 6
+#define CRC_SIZE 4
+#define TOUT_LOOP 500000
+#define TX_BUF_SIZE 1536
+#define RX_BUF_SIZE 1536
+#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
+
+enum register_offsets {
+ ChipCmd = 0x00,
+ ChipConfig = 0x04,
+ EECtrl = 0x08,
+ IntrMask = 0x14,
+ IntrEnable = 0x18,
+ TxRingPtr = 0x20,
+ TxRingPtrHi = 0x24,
+ TxConfig = 0x28,
+ RxRingPtr = 0x30,
+ RxRingPtrHi = 0x34,
+ RxConfig = 0x38,
+ PriQueue = 0x3C,
+ RxFilterAddr = 0x48,
+ RxFilterData = 0x4C,
+ ClkRun = 0xCC,
+ PCIPM = 0x44,
+};
+
+enum ChipCmdBits {
+ ChipReset = 0x100,
+ RxReset = 0x20,
+ TxReset = 0x10,
+ RxOff = 0x08,
+ RxOn = 0x04,
+ TxOff = 0x02,
+ TxOn = 0x01
+};
+
+enum ChipConfigBits {
+ LinkSts = 0x80000000,
+ GigSpeed = 0x40000000,
+ HundSpeed = 0x20000000,
+ FullDuplex = 0x10000000,
+ TBIEn = 0x01000000,
+ Mode1000 = 0x00400000,
+ T64En = 0x00004000,
+ D64En = 0x00001000,
+ M64En = 0x00000800,
+ PhyRst = 0x00000400,
+ PhyDis = 0x00000200,
+ ExtStEn = 0x00000100,
+ BEMode = 0x00000001,
+};
+#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
+
+enum TxConfig_bits {
+ TxDrthMask = 0x000000ff,
+ TxFlthMask = 0x0000ff00,
+ TxMxdmaMask = 0x00700000,
+ TxMxdma_8 = 0x00100000,
+ TxMxdma_16 = 0x00200000,
+ TxMxdma_32 = 0x00300000,
+ TxMxdma_64 = 0x00400000,
+ TxMxdma_128 = 0x00500000,
+ TxMxdma_256 = 0x00600000,
+ TxMxdma_512 = 0x00700000,
+ TxMxdma_1024 = 0x00000000,
+ TxCollRetry = 0x00800000,
+ TxAutoPad = 0x10000000,
+ TxMacLoop = 0x20000000,
+ TxHeartIgn = 0x40000000,
+ TxCarrierIgn = 0x80000000
+};
+
+enum RxConfig_bits {
+ RxDrthMask = 0x0000003e,
+ RxMxdmaMask = 0x00700000,
+ RxMxdma_8 = 0x00100000,
+ RxMxdma_16 = 0x00200000,
+ RxMxdma_32 = 0x00300000,
+ RxMxdma_64 = 0x00400000,
+ RxMxdma_128 = 0x00500000,
+ RxMxdma_256 = 0x00600000,
+ RxMxdma_512 = 0x00700000,
+ RxMxdma_1024 = 0x00000000,
+ RxAcceptLenErr = 0x04000000,
+ RxAcceptLong = 0x08000000,
+ RxAcceptTx = 0x10000000,
+ RxStripCRC = 0x20000000,
+ RxAcceptRunt = 0x40000000,
+ RxAcceptErr = 0x80000000,
+};
+
+/* Bits in the RxMode register. */
+enum rx_mode_bits {
+ RxFilterEnable = 0x80000000,
+ AcceptAllBroadcast = 0x40000000,
+ AcceptAllMulticast = 0x20000000,
+ AcceptAllUnicast = 0x10000000,
+ AcceptPerfectMatch = 0x08000000,
+};
+
+typedef struct _BufferDesc {
+ u32 link;
+ u32 bufptr;
+ vu_long cmdsts;
+ u32 extsts; /*not used here */
+} BufferDesc;
+
+/* Bits in network_desc.status */
+enum desc_status_bits {
+ DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
+ DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
+ DescSizeMask = 0xfff,
+
+ DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
+ DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
+ DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
+ DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
+
+ DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
+ DescRxDest = 0x01800000, DescRxLong = 0x00400000,
+ DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
+ DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
+ DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
+};
+
+/* Bits in MEAR */
+enum mii_reg_bits {
+ MDIO_ShiftClk = 0x0040,
+ MDIO_EnbOutput = 0x0020,
+ MDIO_Data = 0x0010,
+};
+
+/* PHY Register offsets. */
+enum phy_reg_offsets {
+ BMCR = 0x00,
+ BMSR = 0x01,
+ PHYIDR1 = 0x02,
+ PHYIDR2 = 0x03,
+ ANAR = 0x04,
+ KTCR = 0x09,
+};
+
+/* basic mode control register bits */
+enum bmcr_bits {
+ Bmcr_Reset = 0x8000,
+ Bmcr_Loop = 0x4000,
+ Bmcr_Speed0 = 0x2000,
+ Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */
+ Bmcr_RstAutoNeg = 0x0200,
+ Bmcr_Duplex = 0x0100,
+ Bmcr_Speed1 = 0x0040,
+ Bmcr_Force10H = 0x0000,
+ Bmcr_Force10F = 0x0100,
+ Bmcr_Force100H = 0x2000,
+ Bmcr_Force100F = 0x2100,
+ Bmcr_Force1000H = 0x0040,
+ Bmcr_Force1000F = 0x0140,
+};
+
+/* auto negotiation advertisement register */
+enum anar_bits {
+ anar_adv_100F = 0x0100,
+ anar_adv_100H = 0x0080,
+ anar_adv_10F = 0x0040,
+ anar_adv_10H = 0x0020,
+ anar_ieee_8023 = 0x0001,
+};
+
+/* 1K-base T control register */
+enum ktcr_bits {
+ ktcr_adv_1000H = 0x0100,
+ ktcr_adv_1000F = 0x0200,
+};
+
+/* Globals */
+static u32 SavedClkRun;
+static unsigned int cur_rx;
+static unsigned int rx_config;
+static unsigned int tx_config;
+
+/* Note: transmit and receive buffers and descriptors must be
+ long long word aligned */
+static BufferDesc txd __attribute__ ((aligned(8)));
+static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
+static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
+static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
+ __attribute__ ((aligned(8)));
+
+/* Function Prototypes */
+static int mdio_read(struct eth_device *dev, int phy_id, int addr);
+static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value);
+static void mdio_sync(struct eth_device *dev, u32 offset);
+static int ns8382x_init(struct eth_device *dev, bd_t * bis);
+static void ns8382x_reset(struct eth_device *dev);
+static void ns8382x_init_rxfilter(struct eth_device *dev);
+static void ns8382x_init_txd(struct eth_device *dev);
+static void ns8382x_init_rxd(struct eth_device *dev);
+static void ns8382x_set_rx_mode(struct eth_device *dev);
+static void ns8382x_check_duplex(struct eth_device *dev);
+static int ns8382x_send(struct eth_device *dev, volatile void *packet,
+ int length);
+static int ns8382x_poll(struct eth_device *dev);
+static void ns8382x_disable(struct eth_device *dev);
+
+static struct pci_device_id supported[] = {
+ {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_8382x},
+ {}
+};
+
+#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
+#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+
+static inline int
+INW(struct eth_device *dev, u_long addr)
+{
+ return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
+}
+
+static int
+INL(struct eth_device *dev, u_long addr)
+{
+ return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
+}
+
+static inline void
+OUTW(struct eth_device *dev, int command, u_long addr)
+{
+ *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
+}
+
+static inline void
+OUTL(struct eth_device *dev, int command, u_long addr)
+{
+ *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
+}
+
+/* Function: ns8382x_initialize
+ * Description: Retrieves the MAC address of the card, and sets up some
+ * globals required by other routines, and initializes the NIC, making it
+ * ready to send and receive packets.
+ * Side effects: initializes ns8382xs, ready to recieve packets.
+ * Returns: int: number of cards found
+ */
+
+int
+ns8382x_initialize(bd_t * bis)
+{
+ pci_dev_t devno;
+ int card_number = 0;
+ struct eth_device *dev;
+ u32 iobase, status;
+ int i, idx = 0;
+ u32 phyAddress;
+ u32 tmp;
+ u32 chip_config;
+
+ while (1) { /* Find PCI device(s) */
+ if ((devno = pci_find_devices(supported, idx++)) < 0)
+ break;
+
+ pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
+ iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
+
+#ifdef NS8382X_DEBUG
+ printf("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
+#endif
+
+ pci_write_config_dword(devno, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Check if I/O accesses and Bus Mastering are enabled. */
+ pci_read_config_dword(devno, PCI_COMMAND, &status);
+ if (!(status & PCI_COMMAND_MEMORY)) {
+ printf("Error: Can not enable MEM access.\n");
+ continue;
+ } else if (!(status & PCI_COMMAND_MASTER)) {
+ printf("Error: Can not enable Bus Mastering.\n");
+ continue;
+ }
+
+ dev = (struct eth_device *) malloc(sizeof *dev);
+
+ sprintf(dev->name, "dp8382x#%d", card_number);
+ dev->iobase = bus_to_phys(iobase);
+ dev->priv = (void *) devno;
+ dev->init = ns8382x_init;
+ dev->halt = ns8382x_disable;
+ dev->send = ns8382x_send;
+ dev->recv = ns8382x_poll;
+
+ /* ns8382x has a non-standard PM control register
+ * in PCI config space. Some boards apparently need
+ * to be brought to D0 in this manner. */
+ pci_read_config_dword(devno, PCIPM, &tmp);
+ if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
+ u32 newtmp = tmp & ~(0x03 | 0x100);
+ pci_write_config_dword(devno, PCIPM, newtmp);
+ }
+
+ /* get MAC address */
+ for (i = 0; i < 3; i++) {
+ u32 data;
+ char *mac = &dev->enetaddr[i * 2];
+
+ OUTL(dev, i * 2, RxFilterAddr);
+ data = INL(dev, RxFilterData);
+ *mac++ = data;
+ *mac++ = data >> 8;
+ }
+ /* get PHY address, can't be zero */
+ for (phyAddress = 1; phyAddress < 32; phyAddress++) {
+ u32 rev, phy1;
+
+ phy1 = mdio_read(dev, phyAddress, PHYIDR1);
+ if (phy1 == 0x2000) { /*check for 83861/91 */
+ rev = mdio_read(dev, phyAddress, PHYIDR2);
+ if ((rev & ~(0x000f)) == 0x00005c50 ||
+ (rev & ~(0x000f)) == 0x00005c60) {
+#ifdef NS8382X_DEBUG
+ printf("phy rev is %x\n", rev);
+ printf("phy address is %x\n",
+ phyAddress);
+#endif
+ break;
+ }
+ }
+ }
+
+ /* set phy to autonegotiate && advertise everything */
+ mdio_write(dev, phyAddress, KTCR,
+ (ktcr_adv_1000H | ktcr_adv_1000F));
+ mdio_write(dev, phyAddress, ANAR,
+ (anar_adv_100F | anar_adv_100H | anar_adv_10H |
+ anar_adv_10F | anar_ieee_8023));
+ mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
+ mdio_write(dev, phyAddress, BMCR,
+ (Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
+ /* Reset the chip to erase any previous misconfiguration. */
+ OUTL(dev, (ChipReset), ChipCmd);
+
+ chip_config = INL(dev, ChipConfig);
+ /* reset the phy */
+ OUTL(dev, (chip_config | PhyRst), ChipConfig);
+ /* power up and initialize transceiver */
+ OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
+
+ mdio_sync(dev, EECtrl);
+#ifdef NS8382X_DEBUG
+ {
+ u32 chpcfg =
+ INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
+
+ printf("%s: Transceiver 10%s %s duplex.\n", dev->name,
+ (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
+ ? "0" : "",
+ chpcfg & FullDuplex ? "full" : "half");
+ printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
+ dev->enetaddr[0], dev->enetaddr[1],
+ dev->enetaddr[2], dev->enetaddr[3],
+ dev->enetaddr[4], dev->enetaddr[5]);
+ }
+#endif
+ /* Disable PME:
+ * The PME bit is initialized from the EEPROM contents.
+ * PCI cards probably have PME disabled, but motherboard
+ * implementations may have PME set to enable WakeOnLan.
+ * With PME set the chip will scan incoming packets but
+ * nothing will be written to memory. */
+ SavedClkRun = INL(dev, ClkRun);
+ OUTL(dev, SavedClkRun & ~0x100, ClkRun);
+
+ eth_register(dev);
+
+ card_number++;
+
+ pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
+
+ udelay(10 * 1000);
+ }
+ return card_number;
+}
+
+/* MII transceiver control section.
+ Read and write MII registers using software-generated serial MDIO
+ protocol. See the MII specifications or DP83840A data sheet for details.
+
+ The maximum data clock rate is 2.5 Mhz. To meet minimum timing we
+ must flush writes to the PCI bus with a PCI read. */
+#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
+
+#define MDIO_EnbIn (0)
+#define MDIO_WRITE0 (MDIO_EnbOutput)
+#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
+
+/* Generate the preamble required for initial synchronization and
+ a few older transceivers. */
+static void
+mdio_sync(struct eth_device *dev, u32 offset)
+{
+ int bits = 32;
+
+ /* Establish sync by sending at least 32 logic ones. */
+ while (--bits >= 0) {
+ OUTL(dev, MDIO_WRITE1, offset);
+ mdio_delay(offset);
+ OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
+ mdio_delay(offset);
+ }
+}
+
+static int
+mdio_read(struct eth_device *dev, int phy_id, int addr)
+{
+ int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
+ int i, retval = 0;
+
+ /* Shift the read command bits out. */
+ for (i = 15; i >= 0; i--) {
+ int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
+
+ OUTL(dev, dataval, EECtrl);
+ mdio_delay(EECtrl);
+ OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
+ mdio_delay(EECtrl);
+ }
+ /* Read the two transition, 16 data, and wire-idle bits. */
+ for (i = 19; i > 0; i--) {
+ OUTL(dev, MDIO_EnbIn, EECtrl);
+ mdio_delay(EECtrl);
+ retval =
+ (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
+ OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
+ mdio_delay(EECtrl);
+ }
+ return (retval >> 1) & 0xffff;
+}
+
+static void
+mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
+{
+ int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
+ int i;
+
+ /* Shift the command bits out. */
+ for (i = 31; i >= 0; i--) {
+ int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
+
+ OUTL(dev, dataval, EECtrl);
+ mdio_delay(EECtrl);
+ OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
+ mdio_delay(EECtrl);
+ }
+ /* Clear out extra bits. */
+ for (i = 2; i > 0; i--) {
+ OUTL(dev, MDIO_EnbIn, EECtrl);
+ mdio_delay(EECtrl);
+ OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
+ mdio_delay(EECtrl);
+ }
+ return;
+}
+
+/* Function: ns8382x_init
+ * Description: resets the ethernet controller chip and configures
+ * registers and data structures required for sending and receiving packets.
+ * Arguments: struct eth_device *dev: NIC data structure
+ * returns: int.
+ */
+
+static int
+ns8382x_init(struct eth_device *dev, bd_t * bis)
+{
+ u32 config;
+
+ ns8382x_reset(dev);
+
+ /* Disable PME:
+ * The PME bit is initialized from the EEPROM contents.
+ * PCI cards probably have PME disabled, but motherboard
+ * implementations may have PME set to enable WakeOnLan.
+ * With PME set the chip will scan incoming packets but
+ * nothing will be written to memory. */
+ OUTL(dev, SavedClkRun & ~0x100, ClkRun);
+
+ ns8382x_init_rxfilter(dev);
+ ns8382x_init_txd(dev);
+ ns8382x_init_rxd(dev);
+
+ /*set up ChipConfig */
+ config = INL(dev, ChipConfig);
+ /*turn off 64 bit ops && Ten-bit interface
+ * && big-endian mode && extended status */
+ config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn);
+ OUTL(dev, config, ChipConfig);
+
+ /* Configure the PCI bus bursts and FIFO thresholds. */
+ tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
+ | TxCollRetry | TxMxdma_1024 | (0x1002);
+ rx_config = RxMxdma_1024 | 0x20;
+#ifdef NS8382X_DEBUG
+ printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
+ printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
+#endif
+ OUTL(dev, tx_config, TxConfig);
+ OUTL(dev, rx_config, RxConfig);
+
+ /*turn off priority queueing */
+ OUTL(dev, 0x0, PriQueue);
+
+ ns8382x_check_duplex(dev);
+ ns8382x_set_rx_mode(dev);
+
+ OUTL(dev, (RxOn | TxOn), ChipCmd);
+ return 1;
+}
+
+/* Function: ns8382x_reset
+ * Description: soft resets the controller chip
+ * Arguments: struct eth_device *dev: NIC data structure
+ * Returns: void.
+ */
+static void
+ns8382x_reset(struct eth_device *dev)
+{
+ OUTL(dev, ChipReset, ChipCmd);
+ while (INL(dev, ChipCmd))
+ /*wait until done */ ;
+ OUTL(dev, 0, IntrMask);
+ OUTL(dev, 0, IntrEnable);
+}
+
+/* Function: ns8382x_init_rxfilter
+ * Description: sets receive filter address to our MAC address
+ * Arguments: struct eth_device *dev: NIC data structure
+ * returns: void.
+ */
+
+static void
+ns8382x_init_rxfilter(struct eth_device *dev)
+{
+ int i;
+
+ for (i = 0; i < ETH_ALEN; i += 2) {
+ OUTL(dev, i, RxFilterAddr);
+ OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
+ RxFilterData);
+ }
+}
+
+/* Function: ns8382x_init_txd
+ * Description: initializes the Tx descriptor
+ * Arguments: struct eth_device *dev: NIC data structure
+ * returns: void.
+ */
+
+static void
+ns8382x_init_txd(struct eth_device *dev)
+{
+ txd.link = (u32) 0;
+ txd.bufptr = cpu_to_le32((u32) & txb[0]);
+ txd.cmdsts = (u32) 0;
+ txd.extsts = (u32) 0;
+
+ OUTL(dev, 0x0, TxRingPtrHi);
+ OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
+#ifdef NS8382X_DEBUG
+ printf("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
+ INL(dev, TxRingPtr), &txd);
+#endif
+}
+
+/* Function: ns8382x_init_rxd
+ * Description: initializes the Rx descriptor ring
+ * Arguments: struct eth_device *dev: NIC data structure
+ * Returns: void.
+ */
+
+static void
+ns8382x_init_rxd(struct eth_device *dev)
+{
+ int i;
+
+ OUTL(dev, 0x0, RxRingPtrHi);
+
+ cur_rx = 0;
+ for (i = 0; i < NUM_RX_DESC; i++) {
+ rxd[i].link =
+ cpu_to_le32((i + 1 <
+ NUM_RX_DESC) ? (u32) & rxd[i +
+ 1] : (u32) &
+ rxd[0]);
+ rxd[i].extsts = cpu_to_le32((u32) 0x0);
+ rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
+ rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
+#ifdef NS8382X_DEBUG
+ printf
+ ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
+ i, &rxd[i], le32_to_cpu(rxd[i].link),
+ le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
+#endif
+ }
+ OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
+
+#ifdef NS8382X_DEBUG
+ printf("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
+ INL(dev, RxRingPtr));
+#endif
+}
+
+/* Function: ns8382x_set_rx_mode
+ * Description:
+ * sets the receive mode to accept all broadcast packets and packets
+ * with our MAC address, and reject all multicast packets.
+ * Arguments: struct eth_device *dev: NIC data structure
+ * Returns: void.
+ */
+
+static void
+ns8382x_set_rx_mode(struct eth_device *dev)
+{
+ u32 rx_mode = 0x0;
+ /*spec says RxFilterEnable has to be 0 for rest of
+ * this stuff to be properly configured. Linux driver
+ * seems to support this*/
+/* OUTL(dev, rx_mode, RxFilterAddr);*/
+ rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
+ OUTL(dev, rx_mode, RxFilterAddr);
+ printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
+ /*now we turn RxFilterEnable back on */
+ /*rx_mode |= RxFilterEnable;
+ OUTL(dev, rx_mode, RxFilterAddr);*/
+}
+
+static void
+ns8382x_check_duplex(struct eth_device *dev)
+{
+ int gig = 0;
+ int hun = 0;
+ int duplex = 0;
+ int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
+
+ duplex = (config & FullDuplex) ? 1 : 0;
+ gig = (config & GigSpeed) ? 1 : 0;
+ hun = (config & HundSpeed) ? 1 : 0;
+#ifdef NS8382X_DEBUG
+ printf("%s: Setting 10%s %s-duplex based on negotiated link"
+ " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
+ duplex ? "full" : "half");
+#endif
+ if (duplex) {
+ rx_config |= RxAcceptTx;
+ tx_config |= (TxCarrierIgn | TxHeartIgn);
+ } else {
+ rx_config &= ~RxAcceptTx;
+ tx_config &= ~(TxCarrierIgn | TxHeartIgn);
+ }
+#ifdef NS8382X_DEBUG
+ printf("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
+ printf("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
+#endif
+ OUTL(dev, tx_config, TxConfig);
+ OUTL(dev, rx_config, RxConfig);
+
+ /*if speed is 10 or 100, remove MODE1000,
+ * if it's 1000, then set it */
+ config = INL(dev, ChipConfig);
+ if (gig)
+ config |= Mode1000;
+ else
+ config &= ~Mode1000;
+
+#ifdef NS8382X_DEBUG
+ printf("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
+#endif
+ OUTL(dev, config, ChipConfig);
+}
+
+/* Function: ns8382x_send
+ * Description: transmits a packet and waits for completion or timeout.
+ * Returns: void. */
+static int
+ns8382x_send(struct eth_device *dev, volatile void *packet, int length)
+{
+ u32 i, status = 0;
+ u32 tx_stat = 0;
+
+ /* Stop the transmitter */
+ OUTL(dev, TxOff, ChipCmd);
+#ifdef NS8382X_DEBUG
+ printf("ns8382x_send: sending %d bytes\n", (int)length);
+#endif
+
+ /* set the transmit buffer descriptor and enable Transmit State Machine */
+ txd.link = cpu_to_le32(0x0);
+ txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
+ txd.extsts = cpu_to_le32(0x0);
+ txd.cmdsts = cpu_to_le32(DescOwn | length);
+
+ /* load Transmit Descriptor Register */
+ OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
+#ifdef NS8382X_DEBUG
+ printf("ns8382x_send: TX descriptor register loaded with: %#08X\n",
+ INL(dev, TxRingPtr));
+ printf("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
+ le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
+ le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
+#endif
+ /* restart the transmitter */
+ OUTL(dev, TxOn, ChipCmd);
+
+ for (i = 0; ((vu_long)tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
+ if (i >= TOUT_LOOP) {
+ printf ("%s: tx error buffer not ready: txd.cmdsts %#X\n",
+ dev->name, tx_stat);
+ goto Done;
+ }
+ }
+
+ if (!(tx_stat & DescPktOK)) {
+ printf("ns8382x_send: Transmit error, Tx status %X.\n", tx_stat);
+ goto Done;
+ }
+#ifdef NS8382X_DEBUG
+ printf("ns8382x_send: tx_stat: %#08X\n", tx_stat);
+#endif
+
+ status = 1;
+ Done:
+ return status;
+}
+
+/* Function: ns8382x_poll
+ * Description: checks for a received packet and returns it if found.
+ * Arguments: struct eth_device *dev: NIC data structure
+ * Returns: 1 if packet was received.
+ * 0 if no packet was received.
+ * Side effects:
+ * Returns (copies) the packet to the array dev->packet.
+ * Returns the length of the packet.
+ */
+
+static int
+ns8382x_poll(struct eth_device *dev)
+{
+ int retstat = 0;
+ int length = 0;
+ vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
+
+ if (!(rx_status & (u32) DescOwn))
+ return retstat;
+#ifdef NS8382X_DEBUG
+ printf("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n",
+ cur_rx, rx_status);
+#endif
+ length = (rx_status & DSIZE) - CRC_SIZE;
+
+ if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
+ /* corrupted packet received */
+ printf("ns8382x_poll: Corrupted packet, status:%lx\n", rx_status);
+ retstat = 0;
+ } else {
+ /* give packet to higher level routine */
+ NetReceive((rxb + cur_rx * RX_BUF_SIZE), length);
+ retstat = 1;
+ }
+
+ /* return the descriptor and buffer to receive ring */
+ rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
+ rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
+
+ if (++cur_rx == NUM_RX_DESC)
+ cur_rx = 0;
+
+ /* re-enable the potentially idle receive state machine */
+ OUTL(dev, RxOn, ChipCmd);
+
+ return retstat;
+}
+
+/* Function: ns8382x_disable
+ * Description: Turns off interrupts and stops Tx and Rx engines
+ * Arguments: struct eth_device *dev: NIC data structure
+ * Returns: void.
+ */
+
+static void
+ns8382x_disable(struct eth_device *dev)
+{
+ /* Disable interrupts using the mask. */
+ OUTL(dev, 0, IntrMask);
+ OUTL(dev, 0, IntrEnable);
+
+ /* Stop the chip's Tx and Rx processes. */
+ OUTL(dev, (RxOff | TxOff), ChipCmd);
+
+ /* Restore PME enable bit */
+ OUTL(dev, SavedClkRun, ClkRun);
+}
+
+#endif
diff --git a/drivers/smc91111.c b/drivers/smc91111.c
new file mode 100644
index 0000000..62d2133
--- /dev/null
+++ b/drivers/smc91111.c
@@ -0,0 +1,1383 @@
+/*------------------------------------------------------------------------
+ . smc91111.c
+ . This is a driver for SMSC's 91C111 single-chip Ethernet device.
+ .
+ . (C) Copyright 2002
+ . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ . Rolf Offermanns <rof@sysgo.de>
+ .
+ . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
+ . Developed by Simple Network Magic Corporation (SNMC)
+ . Copyright (C) 1996 by Erik Stahlman (ES)
+ .
+ . This program is free software; you can redistribute it and/or modify
+ . it under the terms of the GNU General Public License as published by
+ . the Free Software Foundation; either version 2 of the License, or
+ . (at your option) any later version.
+ .
+ . This program is distributed in the hope that it will be useful,
+ . but WITHOUT ANY WARRANTY; without even the implied warranty of
+ . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ . GNU General Public License for more details.
+ .
+ . You should have received a copy of the GNU General Public License
+ . along with this program; if not, write to the Free Software
+ . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ .
+ . Information contained in this file was obtained from the LAN91C111
+ . manual from SMC. To get a copy, if you really want one, you can find
+ . information under www.smsc.com.
+ .
+ .
+ . "Features" of the SMC chip:
+ . Integrated PHY/MAC for 10/100BaseT Operation
+ . Supports internal and external MII
+ . Integrated 8K packet memory
+ . EEPROM interface for configuration
+ .
+ . Arguments:
+ . io = for the base address
+ . irq = for the IRQ
+ .
+ . author:
+ . Erik Stahlman ( erik@vt.edu )
+ . Daris A Nevil ( dnevil@snmc.com )
+ .
+ .
+ . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
+ .
+ . Sources:
+ . o SMSC LAN91C111 databook (www.smsc.com)
+ . o smc9194.c by Erik Stahlman
+ . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
+ .
+ . History:
+ . 10/17/01 Marco Hasewinkel Modify for DNP/1110
+ . 07/25/01 Woojung Huh Modify for ADS Bitsy
+ . 04/25/01 Daris A Nevil Initial public release through SMSC
+ . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
+ ----------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <command.h>
+#include "smc91111.h"
+#include <net.h>
+
+#ifdef CONFIG_DRIVER_SMC91111
+
+/* Use power-down feature of the chip */
+#define POWER_DOWN 0
+
+#define NO_AUTOPROBE
+
+static const char version[] =
+ "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
+
+#define SMC_DEBUG 0
+
+/*------------------------------------------------------------------------
+ .
+ . Configuration options, for the experienced user to change.
+ .
+ -------------------------------------------------------------------------*/
+
+/*
+ . Wait time for memory to be free. This probably shouldn't be
+ . tuned that much, as waiting for this means nothing else happens
+ . in the system
+*/
+#define MEMORY_WAIT_TIME 16
+
+
+#if (SMC_DEBUG > 2 )
+#define PRINTK3(args...) printf(args)
+#else
+#define PRINTK3(args...)
+#endif
+
+#if SMC_DEBUG > 1
+#define PRINTK2(args...) printf(args)
+#else
+#define PRINTK2(args...)
+#endif
+
+#ifdef SMC_DEBUG
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+
+/*------------------------------------------------------------------------
+ .
+ . The internal workings of the driver. If you are changing anything
+ . here with the SMC stuff, you should have the datasheet and know
+ . what you are doing.
+ .
+ -------------------------------------------------------------------------*/
+#define CARDNAME "LAN91C111"
+
+/* Memory sizing constant */
+#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
+
+#ifndef CONFIG_SMC91111_BASE
+#define CONFIG_SMC91111_BASE 0x20000300
+#endif
+
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+
+#define SMC_DEV_NAME "SMC91111"
+#define SMC_PHY_ADDR 0x0000
+#define SMC_ALLOC_MAX_TRY 5
+#define SMC_TX_TIMEOUT 30
+
+#define SMC_PHY_CLOCK_DELAY 1000
+
+#define ETH_ZLEN 60
+
+#ifdef CONFIG_SMC_USE_32_BIT
+#define USE_32_BIT 1
+#else
+#undef USE_32_BIT
+#endif
+/*-----------------------------------------------------------------
+ .
+ . The driver can be entered at any of the following entry points.
+ .
+ .------------------------------------------------------------------ */
+
+extern int eth_init(bd_t *bd);
+extern void eth_halt(void);
+extern int eth_rx(void);
+extern int eth_send(volatile void *packet, int length);
+
+
+
+
+
+/*
+ . This is called by register_netdev(). It is responsible for
+ . checking the portlist for the SMC9000 series chipset. If it finds
+ . one, then it will initialize the device, find the hardware information,
+ . and sets up the appropriate device parameters.
+ . NOTE: Interrupts are *OFF* when this procedure is called.
+ .
+ . NB:This shouldn't be static since it is referred to externally.
+*/
+int smc_init(void);
+
+/*
+ . This is called by unregister_netdev(). It is responsible for
+ . cleaning up before the driver is finally unregistered and discarded.
+*/
+void smc_destructor(void);
+
+/*
+ . The kernel calls this function when someone wants to use the device,
+ . typically 'ifconfig ethX up'.
+*/
+static int smc_open(void);
+
+
+/*
+ . This is called by the kernel in response to 'ifconfig ethX down'. It
+ . is responsible for cleaning up everything that the open routine
+ . does, and maybe putting the card into a powerdown state.
+*/
+static int smc_close(void);
+
+/*
+ . Configures the PHY through the MII Management interface
+*/
+#ifndef CONFIG_SMC91111_EXT_PHY
+static void smc_phy_configure(void);
+#endif /* !CONFIG_SMC91111_EXT_PHY */
+
+/*
+ . This is a separate procedure to handle the receipt of a packet, to
+ . leave the interrupt code looking slightly cleaner
+*/
+static int smc_rcv(void);
+
+
+
+/*
+ ------------------------------------------------------------
+ .
+ . Internal routines
+ .
+ ------------------------------------------------------------
+*/
+
+static char smc_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
+
+/*
+ * This function must be called before smc_open() if you want to override
+ * the default mac address.
+ */
+
+void smc_set_mac_addr(const char *addr) {
+ int i;
+
+ for (i=0; i < sizeof(smc_mac_addr); i++){
+ smc_mac_addr[i] = addr[i];
+ }
+}
+
+/*
+ * smc_get_macaddr is no longer used. If you want to override the default
+ * mac address, call smc_get_mac_addr as a part of the board initialisation.
+ */
+
+#if 0
+void smc_get_macaddr( byte *addr ) {
+ /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
+ unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
+ int i;
+
+
+ for (i=0; i<6; i++) {
+ addr[0] = *(dnp1110_mac+0);
+ addr[1] = *(dnp1110_mac+1);
+ addr[2] = *(dnp1110_mac+2);
+ addr[3] = *(dnp1110_mac+3);
+ addr[4] = *(dnp1110_mac+4);
+ addr[5] = *(dnp1110_mac+5);
+ }
+}
+#endif /* 0 */
+
+/***********************************************
+ * Show available memory *
+ ***********************************************/
+void dump_memory_info(void)
+{
+ word mem_info;
+ word old_bank;
+
+ old_bank = SMC_inw(BANK_SELECT)&0xF;
+
+ SMC_SELECT_BANK(0);
+ mem_info = SMC_inw( MIR_REG );
+ PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
+
+ SMC_SELECT_BANK(old_bank);
+}
+/*
+ . A rather simple routine to print out a packet for debugging purposes.
+*/
+#if SMC_DEBUG > 2
+static void print_packet( byte *, int );
+#endif
+
+#define tx_done(dev) 1
+
+
+
+/* this does a soft reset on the device */
+static void smc_reset( void );
+
+/* Enable Interrupts, Receive, and Transmit */
+static void smc_enable( void );
+
+/* this puts the device in an inactive state */
+static void smc_shutdown( void );
+
+/* Routines to Read and Write the PHY Registers across the
+ MII Management Interface
+*/
+
+#ifndef CONFIG_SMC91111_EXT_PHY
+static word smc_read_phy_register(byte phyreg);
+static void smc_write_phy_register(byte phyreg, word phydata);
+#endif /* !CONFIG_SMC91111_EXT_PHY */
+
+
+static int poll4int( byte mask, int timeout ) {
+ int tmo = get_timer(0) + timeout * CFG_HZ;
+ int is_timeout = 0;
+ word old_bank = SMC_inw(BSR_REG);
+
+ PRINTK2("Polling...\n");
+ SMC_SELECT_BANK(2);
+ while((SMC_inw(SMC91111_INT_REG) & mask) == 0)
+ {
+ if (get_timer(0) >= tmo) {
+ is_timeout = 1;
+ break;
+ }
+ }
+
+ /* restore old bank selection */
+ SMC_SELECT_BANK(old_bank);
+
+ if (is_timeout)
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ . Function: smc_reset( void )
+ . Purpose:
+ . This sets the SMC91111 chip to its normal state, hopefully from whatever
+ . mess that any other DOS driver has put it in.
+ .
+ . Maybe I should reset more registers to defaults in here? SOFTRST should
+ . do that for me.
+ .
+ . Method:
+ . 1. send a SOFT RESET
+ . 2. wait for it to finish
+ . 3. enable autorelease mode
+ . 4. reset the memory management unit
+ . 5. clear all interrupts
+ .
+*/
+static void smc_reset( void )
+{
+ PRINTK2("%s:smc_reset\n", SMC_DEV_NAME);
+
+ /* This resets the registers mostly to defaults, but doesn't
+ affect EEPROM. That seems unnecessary */
+ SMC_SELECT_BANK( 0 );
+ SMC_outw( RCR_SOFTRST, RCR_REG );
+
+ /* Setup the Configuration Register */
+ /* This is necessary because the CONFIG_REG is not affected */
+ /* by a soft reset */
+
+ SMC_SELECT_BANK( 1 );
+#if defined(CONFIG_SMC91111_EXT_PHY)
+ SMC_outw( CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
+#else
+ SMC_outw( CONFIG_DEFAULT, CONFIG_REG);
+#endif
+
+
+ /* Release from possible power-down state */
+ /* Configuration register is not affected by Soft Reset */
+ SMC_outw( SMC_inw( CONFIG_REG ) | CONFIG_EPH_POWER_EN, CONFIG_REG );
+
+ SMC_SELECT_BANK( 0 );
+
+ /* this should pause enough for the chip to be happy */
+ udelay(10);
+
+ /* Disable transmit and receive functionality */
+ SMC_outw( RCR_CLEAR, RCR_REG );
+ SMC_outw( TCR_CLEAR, TCR_REG );
+
+ /* set the control register */
+ SMC_SELECT_BANK( 1 );
+ SMC_outw( CTL_DEFAULT, CTL_REG );
+
+ /* Reset the MMU */
+ SMC_SELECT_BANK( 2 );
+ SMC_outw( MC_RESET, MMU_CMD_REG );
+ while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
+ udelay(1); /* Wait until not busy */
+
+ /* Note: It doesn't seem that waiting for the MMU busy is needed here,
+ but this is a place where future chipsets _COULD_ break. Be wary
+ of issuing another MMU command right after this */
+
+ /* Disable all interrupts */
+ SMC_outb( 0, IM_REG );
+}
+
+/*
+ . Function: smc_enable
+ . Purpose: let the chip talk to the outside work
+ . Method:
+ . 1. Enable the transmitter
+ . 2. Enable the receiver
+ . 3. Enable interrupts
+*/
+static void smc_enable()
+{
+ PRINTK2("%s:smc_enable\n", SMC_DEV_NAME);
+ SMC_SELECT_BANK( 0 );
+ /* see the header file for options in TCR/RCR DEFAULT*/
+ SMC_outw( TCR_DEFAULT, TCR_REG );
+ SMC_outw( RCR_DEFAULT, RCR_REG );
+
+ /* clear MII_DIS */
+/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
+}
+
+/*
+ . Function: smc_shutdown
+ . Purpose: closes down the SMC91xxx chip.
+ . Method:
+ . 1. zero the interrupt mask
+ . 2. clear the enable receive flag
+ . 3. clear the enable xmit flags
+ .
+ . TODO:
+ . (1) maybe utilize power down mode.
+ . Why not yet? Because while the chip will go into power down mode,
+ . the manual says that it will wake up in response to any I/O requests
+ . in the register space. Empirical results do not show this working.
+*/
+static void smc_shutdown()
+{
+ PRINTK2(CARDNAME ":smc_shutdown\n");
+
+ /* no more interrupts for me */
+ SMC_SELECT_BANK( 2 );
+ SMC_outb( 0, IM_REG );
+
+ /* and tell the card to stay away from that nasty outside world */
+ SMC_SELECT_BANK( 0 );
+ SMC_outb( RCR_CLEAR, RCR_REG );
+ SMC_outb( TCR_CLEAR, TCR_REG );
+}
+
+
+/*
+ . Function: smc_hardware_send_packet(struct net_device * )
+ . Purpose:
+ . This sends the actual packet to the SMC9xxx chip.
+ .
+ . Algorithm:
+ . First, see if a saved_skb is available.
+ . ( this should NOT be called if there is no 'saved_skb'
+ . Now, find the packet number that the chip allocated
+ . Point the data pointers at it in memory
+ . Set the length word in the chip's memory
+ . Dump the packet to chip memory
+ . Check if a last byte is needed ( odd length packet )
+ . if so, set the control flag right
+ . Tell the card to send it
+ . Enable the transmit interrupt, so I know if it failed
+ . Free the kernel data if I actually sent it.
+*/
+static int smc_send_packet(volatile void *packet, int packet_length)
+{
+ byte packet_no;
+ unsigned long ioaddr;
+ byte * buf;
+ int length;
+ int numPages;
+ int try = 0;
+ int time_out;
+ byte status;
+
+
+ PRINTK3("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
+
+ length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
+
+ /* allocate memory
+ ** The MMU wants the number of pages to be the number of 256 bytes
+ ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
+ **
+ ** The 91C111 ignores the size bits, but the code is left intact
+ ** for backwards and future compatibility.
+ **
+ ** Pkt size for allocating is data length +6 (for additional status
+ ** words, length and ctl!)
+ **
+ ** If odd size then last byte is included in this header.
+ */
+ numPages = ((length & 0xfffe) + 6);
+ numPages >>= 8; /* Divide by 256 */
+
+ if (numPages > 7 ) {
+ printf("%s: Far too big packet error. \n", SMC_DEV_NAME);
+ return 0;
+ }
+
+ /* now, try to allocate the memory */
+ SMC_SELECT_BANK( 2 );
+ SMC_outw( MC_ALLOC | numPages, MMU_CMD_REG );
+
+again:
+ try++;
+ time_out = MEMORY_WAIT_TIME;
+ do {
+ status = SMC_inb( SMC91111_INT_REG );
+ if ( status & IM_ALLOC_INT ) {
+ /* acknowledge the interrupt */
+ SMC_outb( IM_ALLOC_INT, SMC91111_INT_REG );
+ break;
+ }
+ } while ( -- time_out );
+
+ if ( !time_out ) {
+ PRINTK2("%s: memory allocation, try %d failed ...\n",
+ SMC_DEV_NAME, try);
+ if (try < SMC_ALLOC_MAX_TRY)
+ goto again;
+ else
+ return 0;
+ }
+
+ PRINTK2("%s: memory allocation, try %d succeeded ...\n",
+ SMC_DEV_NAME,
+ try);
+
+ /* I can send the packet now.. */
+
+ ioaddr = SMC_BASE_ADDRESS;
+
+ buf = (byte *)packet;
+
+ /* If I get here, I _know_ there is a packet slot waiting for me */
+ packet_no = SMC_inb( AR_REG );
+ if ( packet_no & AR_FAILED ) {
+ /* or isn't there? BAD CHIP! */
+ printf("%s: Memory allocation failed. \n",
+ SMC_DEV_NAME);
+ return 0;
+ }
+
+ /* we have a packet address, so tell the card to use it */
+ SMC_outb( packet_no, PN_REG );
+
+ /* point to the beginning of the packet */
+ SMC_outw( PTR_AUTOINC , PTR_REG );
+
+ PRINTK3("%s: Trying to xmit packet of length %x\n",
+ SMC_DEV_NAME, length);
+
+#if SMC_DEBUG > 2
+ printf("Transmitting Packet\n");
+ print_packet( buf, length );
+#endif
+
+ /* send the packet length ( +6 for status, length and ctl byte )
+ and the status word ( set to zeros ) */
+#ifdef USE_32_BIT
+ SMC_outl( (length +6 ) << 16 , SMC91111_DATA_REG );
+#else
+ SMC_outw( 0, SMC91111_DATA_REG );
+ /* send the packet length ( +6 for status words, length, and ctl*/
+ SMC_outw( (length+6), SMC91111_DATA_REG );
+#endif
+
+ /* send the actual data
+ . I _think_ it's faster to send the longs first, and then
+ . mop up by sending the last word. It depends heavily
+ . on alignment, at least on the 486. Maybe it would be
+ . a good idea to check which is optimal? But that could take
+ . almost as much time as is saved?
+ */
+#ifdef USE_32_BIT
+ SMC_outsl(SMC91111_DATA_REG, buf, length >> 2 );
+ if ( length & 0x2 )
+ SMC_outw(*((word *)(buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG);
+#else
+ SMC_outsw(SMC91111_DATA_REG , buf, (length ) >> 1);
+#endif /* USE_32_BIT */
+
+ /* Send the last byte, if there is one. */
+ if ( (length & 1) == 0 ) {
+ SMC_outw( 0, SMC91111_DATA_REG );
+ } else {
+ SMC_outw( buf[length -1 ] | 0x2000, SMC91111_DATA_REG );
+ }
+
+ /* and let the chipset deal with it */
+ SMC_outw( MC_ENQUEUE , MMU_CMD_REG );
+
+ /* poll for TX INT */
+ if (poll4int(IM_TX_INT, SMC_TX_TIMEOUT)) {
+ /* sending failed */
+ PRINTK2("%s: TX timeout, sending failed...\n",
+ SMC_DEV_NAME);
+
+ /* release packet */
+ SMC_outw(MC_FREEPKT, MMU_CMD_REG);
+
+ /* wait for MMU getting ready (low) */
+ while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
+ {
+ udelay(10);
+ }
+
+ PRINTK2("MMU ready\n");
+
+
+ return 0;
+ } else {
+ /* ack. int */
+ SMC_outw(IM_TX_INT, SMC91111_INT_REG);
+ PRINTK2("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
+
+ /* release packet */
+ SMC_outw(MC_FREEPKT, MMU_CMD_REG);
+
+ /* wait for MMU getting ready (low) */
+ while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
+ {
+ udelay(10);
+ }
+
+ PRINTK2("MMU ready\n");
+
+
+ }
+
+ return length;
+}
+
+/*-------------------------------------------------------------------------
+ |
+ | smc_destructor( struct net_device * dev )
+ | Input parameters:
+ | dev, pointer to the device structure
+ |
+ | Output:
+ | None.
+ |
+ ---------------------------------------------------------------------------
+*/
+void smc_destructor()
+{
+ PRINTK2(CARDNAME ":smc_destructor\n");
+}
+
+
+/*
+ * Open and Initialize the board
+ *
+ * Set up everything, reset the card, etc ..
+ *
+ */
+static int smc_open()
+{
+ int i; /* used to set hw ethernet address */
+
+ PRINTK2("%s:smc_open\n", SMC_DEV_NAME);
+
+ /* reset the hardware */
+
+ smc_reset();
+ smc_enable();
+
+ /* Configure the PHY */
+#ifndef CONFIG_SMC91111_EXT_PHY
+ smc_phy_configure();
+#endif
+
+
+ /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
+/* SMC_SELECT_BANK(0); */
+/* SMC_outw(0, RPC_REG); */
+
+#ifdef USE_32_BIT
+ for ( i = 0; i < 6; i += 2 ) {
+ word address;
+
+ address = smc_mac_addr[ i + 1 ] << 8 ;
+ address |= smc_mac_addr[ i ];
+ SMC_outw( address, ADDR0_REG + i );
+ }
+#else
+ for ( i = 0; i < 6; i ++ )
+ SMC_outb( smc_mac_addr[i], ADDR0_REG + i );
+#endif
+
+ return 0;
+}
+
+#if 0 /* dead code? -- wd */
+#ifdef USE_32_BIT
+void
+insl32(r,b,l)
+{
+ int __i ;
+ dword *__b2;
+
+ __b2 = (dword *) b;
+ for (__i = 0; __i < l; __i++) {
+ *(__b2 + __i) = *(dword *)(r+0x10000300);
+ }
+}
+#endif
+#endif
+
+/*-------------------------------------------------------------
+ .
+ . smc_rcv - receive a packet from the card
+ .
+ . There is ( at least ) a packet waiting to be read from
+ . chip-memory.
+ .
+ . o Read the status
+ . o If an error, record it
+ . o otherwise, read in the packet
+ --------------------------------------------------------------
+*/
+static int smc_rcv()
+{
+ int packet_number;
+ word status;
+ word packet_length;
+ int is_error = 0;
+#ifdef USE_32_BIT
+ dword stat_len;
+#endif
+
+
+ SMC_SELECT_BANK(2);
+ packet_number = SMC_inw( RXFIFO_REG );
+
+ if ( packet_number & RXFIFO_REMPTY ) {
+
+ return 0;
+ }
+
+ PRINTK3("%s:smc_rcv\n", SMC_DEV_NAME);
+ /* start reading from the start of the packet */
+ SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
+
+ /* First two words are status and packet_length */
+#ifdef USE_32_BIT
+ stat_len = SMC_inl(SMC91111_DATA_REG);
+ status = stat_len & 0xffff;
+ packet_length = stat_len >> 16;
+#else
+ status = SMC_inw( SMC91111_DATA_REG );
+ packet_length = SMC_inw( SMC91111_DATA_REG );
+#endif
+
+ packet_length &= 0x07ff; /* mask off top bits */
+
+ PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
+
+ if ( !(status & RS_ERRORS ) ){
+ /* Adjust for having already read the first two words */
+ packet_length -= 4; /*4; */
+
+
+
+ /* set odd length for bug in LAN91C111, */
+ /* which never sets RS_ODDFRAME */
+ /* TODO ? */
+
+
+#ifdef USE_32_BIT
+ PRINTK3(" Reading %d dwords (and %d bytes) \n",
+ packet_length >> 2, packet_length & 3 );
+ /* QUESTION: Like in the TX routine, do I want
+ to send the DWORDs or the bytes first, or some
+ mixture. A mixture might improve already slow PIO
+ performance */
+ SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
+ /* read the left over bytes */
+ if (packet_length & 3) {
+ int i;
+
+ byte *tail = NetRxPackets[0] + (packet_length & ~3);
+ dword leftover = SMC_inl(SMC91111_DATA_REG);
+ for (i=0; i<(packet_length & 3); i++)
+ *tail++ = (byte) (leftover >> (8*i)) & 0xff;
+ }
+#else
+ PRINTK3(" Reading %d words and %d byte(s) \n",
+ (packet_length >> 1 ), packet_length & 1 );
+ SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
+
+#endif /* USE_32_BIT */
+
+#if SMC_DEBUG > 2
+ printf("Receiving Packet\n");
+ print_packet( NetRxPackets[0], packet_length );
+#endif
+ } else {
+ /* error ... */
+ /* TODO ? */
+ is_error = 1;
+ }
+
+ while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
+ udelay(1); /* Wait until not busy */
+
+ /* error or good, tell the card to get rid of this packet */
+ SMC_outw( MC_RELEASE, MMU_CMD_REG );
+
+ while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
+ udelay(1); /* Wait until not busy */
+
+ if (!is_error) {
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[0], packet_length);
+ return packet_length;
+ } else {
+ return 0;
+ }
+
+}
+
+
+
+/*----------------------------------------------------
+ . smc_close
+ .
+ . this makes the board clean up everything that it can
+ . and not talk to the outside world. Caused by
+ . an 'ifconfig ethX down'
+ .
+ -----------------------------------------------------*/
+static int smc_close()
+{
+ PRINTK2("%s:smc_close\n", SMC_DEV_NAME);
+
+ /* clear everything */
+ smc_shutdown();
+
+ return 0;
+}
+
+
+#if 0
+/*------------------------------------------------------------
+ . Modify a bit in the LAN91C111 register set
+ .-------------------------------------------------------------*/
+static word smc_modify_regbit(int bank, int ioaddr, int reg,
+ unsigned int bit, int val)
+{
+ word regval;
+
+ SMC_SELECT_BANK( bank );
+
+ regval = SMC_inw( reg );
+ if (val)
+ regval |= bit;
+ else
+ regval &= ~bit;
+
+ SMC_outw( regval, 0 );
+ return(regval);
+}
+
+
+/*------------------------------------------------------------
+ . Retrieve a bit in the LAN91C111 register set
+ .-------------------------------------------------------------*/
+static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
+{
+ SMC_SELECT_BANK( bank );
+ if ( SMC_inw( reg ) & bit)
+ return(1);
+ else
+ return(0);
+}
+
+
+/*------------------------------------------------------------
+ . Modify a LAN91C111 register (word access only)
+ .-------------------------------------------------------------*/
+static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
+{
+ SMC_SELECT_BANK( bank );
+ SMC_outw( val, reg );
+}
+
+
+/*------------------------------------------------------------
+ . Retrieve a LAN91C111 register (word access only)
+ .-------------------------------------------------------------*/
+static int smc_get_reg(int bank, int ioaddr, int reg)
+{
+ SMC_SELECT_BANK( bank );
+ return(SMC_inw( reg ));
+}
+
+#endif /* 0 */
+
+/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
+
+#if (SMC_DEBUG > 2 )
+
+/*------------------------------------------------------------
+ . Debugging function for viewing MII Management serial bitstream
+ .-------------------------------------------------------------*/
+static void smc_dump_mii_stream(byte* bits, int size)
+{
+ int i;
+
+ printf("BIT#:");
+ for (i = 0; i < size; ++i)
+ {
+ printf("%d", i%10);
+ }
+
+ printf("\nMDOE:");
+ for (i = 0; i < size; ++i)
+ {
+ if (bits[i] & MII_MDOE)
+ printf("1");
+ else
+ printf("0");
+ }
+
+ printf("\nMDO :");
+ for (i = 0; i < size; ++i)
+ {
+ if (bits[i] & MII_MDO)
+ printf("1");
+ else
+ printf("0");
+ }
+
+ printf("\nMDI :");
+ for (i = 0; i < size; ++i)
+ {
+ if (bits[i] & MII_MDI)
+ printf("1");
+ else
+ printf("0");
+ }
+
+ printf("\n");
+}
+#endif
+
+/*------------------------------------------------------------
+ . Reads a register from the MII Management serial interface
+ .-------------------------------------------------------------*/
+#ifndef CONFIG_SMC91111_EXT_PHY
+static word smc_read_phy_register(byte phyreg)
+{
+ int oldBank;
+ int i;
+ byte mask;
+ word mii_reg;
+ byte bits[64];
+ int clk_idx = 0;
+ int input_idx;
+ word phydata;
+ byte phyaddr = SMC_PHY_ADDR;
+
+ /* 32 consecutive ones on MDO to establish sync */
+ for (i = 0; i < 32; ++i)
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+ /* Start code <01> */
+ bits[clk_idx++] = MII_MDOE;
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+ /* Read command <10> */
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+ bits[clk_idx++] = MII_MDOE;
+
+ /* Output the PHY address, msb first */
+ mask = (byte)0x10;
+ for (i = 0; i < 5; ++i)
+ {
+ if (phyaddr & mask)
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+ else
+ bits[clk_idx++] = MII_MDOE;
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* Output the phy register number, msb first */
+ mask = (byte)0x10;
+ for (i = 0; i < 5; ++i)
+ {
+ if (phyreg & mask)
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+ else
+ bits[clk_idx++] = MII_MDOE;
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* Tristate and turnaround (2 bit times) */
+ bits[clk_idx++] = 0;
+ /*bits[clk_idx++] = 0; */
+
+ /* Input starts at this bit time */
+ input_idx = clk_idx;
+
+ /* Will input 16 bits */
+ for (i = 0; i < 16; ++i)
+ bits[clk_idx++] = 0;
+
+ /* Final clock bit */
+ bits[clk_idx++] = 0;
+
+ /* Save the current bank */
+ oldBank = SMC_inw( BANK_SELECT );
+
+ /* Select bank 3 */
+ SMC_SELECT_BANK( 3 );
+
+ /* Get the current MII register value */
+ mii_reg = SMC_inw( MII_REG );
+
+ /* Turn off all MII Interface bits */
+ mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
+
+ /* Clock all 64 cycles */
+ for (i = 0; i < sizeof bits; ++i)
+ {
+ /* Clock Low - output data */
+ SMC_outw( mii_reg | bits[i], MII_REG );
+ udelay(SMC_PHY_CLOCK_DELAY);
+
+
+ /* Clock Hi - input data */
+ SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
+ udelay(SMC_PHY_CLOCK_DELAY);
+ bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
+ }
+
+ /* Return to idle state */
+ /* Set clock to low, data to low, and output tristated */
+ SMC_outw( mii_reg, MII_REG );
+ udelay(SMC_PHY_CLOCK_DELAY);
+
+ /* Restore original bank select */
+ SMC_SELECT_BANK( oldBank );
+
+ /* Recover input data */
+ phydata = 0;
+ for (i = 0; i < 16; ++i)
+ {
+ phydata <<= 1;
+
+ if (bits[input_idx++] & MII_MDI)
+ phydata |= 0x0001;
+ }
+
+#if (SMC_DEBUG > 2 )
+ printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
+ phyaddr, phyreg, phydata);
+ smc_dump_mii_stream(bits, sizeof bits);
+#endif
+
+ return(phydata);
+}
+
+
+/*------------------------------------------------------------
+ . Writes a register to the MII Management serial interface
+ .-------------------------------------------------------------*/
+static void smc_write_phy_register(byte phyreg, word phydata)
+{
+ int oldBank;
+ int i;
+ word mask;
+ word mii_reg;
+ byte bits[65];
+ int clk_idx = 0;
+ byte phyaddr = SMC_PHY_ADDR;
+
+ /* 32 consecutive ones on MDO to establish sync */
+ for (i = 0; i < 32; ++i)
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+ /* Start code <01> */
+ bits[clk_idx++] = MII_MDOE;
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+ /* Write command <01> */
+ bits[clk_idx++] = MII_MDOE;
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+ /* Output the PHY address, msb first */
+ mask = (byte)0x10;
+ for (i = 0; i < 5; ++i)
+ {
+ if (phyaddr & mask)
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+ else
+ bits[clk_idx++] = MII_MDOE;
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* Output the phy register number, msb first */
+ mask = (byte)0x10;
+ for (i = 0; i < 5; ++i)
+ {
+ if (phyreg & mask)
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+ else
+ bits[clk_idx++] = MII_MDOE;
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* Tristate and turnaround (2 bit times) */
+ bits[clk_idx++] = 0;
+ bits[clk_idx++] = 0;
+
+ /* Write out 16 bits of data, msb first */
+ mask = 0x8000;
+ for (i = 0; i < 16; ++i)
+ {
+ if (phydata & mask)
+ bits[clk_idx++] = MII_MDOE | MII_MDO;
+ else
+ bits[clk_idx++] = MII_MDOE;
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* Final clock bit (tristate) */
+ bits[clk_idx++] = 0;
+
+ /* Save the current bank */
+ oldBank = SMC_inw( BANK_SELECT );
+
+ /* Select bank 3 */
+ SMC_SELECT_BANK( 3 );
+
+ /* Get the current MII register value */
+ mii_reg = SMC_inw( MII_REG );
+
+ /* Turn off all MII Interface bits */
+ mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
+
+ /* Clock all cycles */
+ for (i = 0; i < sizeof bits; ++i)
+ {
+ /* Clock Low - output data */
+ SMC_outw( mii_reg | bits[i], MII_REG );
+ udelay(SMC_PHY_CLOCK_DELAY);
+
+
+ /* Clock Hi - input data */
+ SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
+ udelay(SMC_PHY_CLOCK_DELAY);
+ bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
+ }
+
+ /* Return to idle state */
+ /* Set clock to low, data to low, and output tristated */
+ SMC_outw( mii_reg, MII_REG );
+ udelay(SMC_PHY_CLOCK_DELAY);
+
+ /* Restore original bank select */
+ SMC_SELECT_BANK( oldBank );
+
+#if (SMC_DEBUG > 2 )
+ printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
+ phyaddr, phyreg, phydata);
+ smc_dump_mii_stream(bits, sizeof bits);
+#endif
+}
+#endif /* !CONFIG_SMC91111_EXT_PHY */
+
+
+
+/*------------------------------------------------------------
+ . Waits the specified number of milliseconds - kernel friendly
+ .-------------------------------------------------------------*/
+#ifndef CONFIG_SMC91111_EXT_PHY
+static void smc_wait_ms(unsigned int ms)
+{
+ udelay(ms*1000);
+}
+#endif /* !CONFIG_SMC91111_EXT_PHY */
+
+
+
+/*------------------------------------------------------------
+ . Configures the specified PHY using Autonegotiation. Calls
+ . smc_phy_fixed() if the user has requested a certain config.
+ .-------------------------------------------------------------*/
+#ifndef CONFIG_SMC91111_EXT_PHY
+static void smc_phy_configure()
+{
+ int timeout;
+ byte phyaddr;
+ word my_phy_caps; /* My PHY capabilities */
+ word my_ad_caps; /* My Advertised capabilities */
+ word status = 0; /*;my status = 0 */
+ int failed = 0;
+
+ PRINTK3("%s:smc_program_phy()\n", SMC_DEV_NAME);
+
+
+
+ /* Get the detected phy address */
+ phyaddr = SMC_PHY_ADDR;
+
+ /* Reset the PHY, setting all other bits to zero */
+ smc_write_phy_register(PHY_CNTL_REG, PHY_CNTL_RST);
+
+ /* Wait for the reset to complete, or time out */
+ timeout = 6; /* Wait up to 3 seconds */
+ while (timeout--)
+ {
+ if (!(smc_read_phy_register(PHY_CNTL_REG)
+ & PHY_CNTL_RST))
+ {
+ /* reset complete */
+ break;
+ }
+
+ smc_wait_ms(500); /* wait 500 millisecs */
+ }
+
+ if (timeout < 1)
+ {
+ printf("%s:PHY reset timed out\n", SMC_DEV_NAME);
+ goto smc_phy_configure_exit;
+ }
+
+ /* Read PHY Register 18, Status Output */
+ /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
+
+ /* Enable PHY Interrupts (for register 18) */
+ /* Interrupts listed here are disabled */
+ smc_write_phy_register(PHY_INT_REG, 0xffff);
+
+ /* Configure the Receive/Phy Control register */
+ SMC_SELECT_BANK( 0 );
+ SMC_outw( RPC_DEFAULT, RPC_REG );
+
+ /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
+ my_phy_caps = smc_read_phy_register(PHY_STAT_REG);
+ my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
+
+ if (my_phy_caps & PHY_STAT_CAP_T4)
+ my_ad_caps |= PHY_AD_T4;
+
+ if (my_phy_caps & PHY_STAT_CAP_TXF)
+ my_ad_caps |= PHY_AD_TX_FDX;
+
+ if (my_phy_caps & PHY_STAT_CAP_TXH)
+ my_ad_caps |= PHY_AD_TX_HDX;
+
+ if (my_phy_caps & PHY_STAT_CAP_TF)
+ my_ad_caps |= PHY_AD_10_FDX;
+
+ if (my_phy_caps & PHY_STAT_CAP_TH)
+ my_ad_caps |= PHY_AD_10_HDX;
+
+ /* Update our Auto-Neg Advertisement Register */
+ smc_write_phy_register( PHY_AD_REG, my_ad_caps);
+
+ PRINTK2("%s:phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
+ PRINTK2("%s:phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
+
+ /* Restart auto-negotiation process in order to advertise my caps */
+ smc_write_phy_register( PHY_CNTL_REG,
+ PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
+
+ /* Wait for the auto-negotiation to complete. This may take from */
+ /* 2 to 3 seconds. */
+ /* Wait for the reset to complete, or time out */
+ timeout = 20; /* Wait up to 10 seconds */
+ while (timeout--)
+ {
+ status = smc_read_phy_register( PHY_STAT_REG);
+ if (status & PHY_STAT_ANEG_ACK)
+ {
+ /* auto-negotiate complete */
+ break;
+ }
+
+ smc_wait_ms(500); /* wait 500 millisecs */
+
+ /* Restart auto-negotiation if remote fault */
+ if (status & PHY_STAT_REM_FLT)
+ {
+ printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
+
+ /* Restart auto-negotiation */
+ printf("%s:PHY restarting auto-negotiation\n",
+ SMC_DEV_NAME);
+ smc_write_phy_register( PHY_CNTL_REG,
+ PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
+ PHY_CNTL_SPEED | PHY_CNTL_DPLX);
+ }
+ }
+
+ if (timeout < 1)
+ {
+ printf("%s:PHY auto-negotiate timed out\n",
+ SMC_DEV_NAME);
+ printf("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
+ failed = 1;
+ }
+
+ /* Fail if we detected an auto-negotiate remote fault */
+ if (status & PHY_STAT_REM_FLT)
+ {
+ printf( "%s:PHY remote fault detected\n", SMC_DEV_NAME);
+ printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
+ failed = 1;
+ }
+
+ /* Re-Configure the Receive/Phy Control register */
+ SMC_outw( RPC_DEFAULT, RPC_REG );
+
+ smc_phy_configure_exit:
+
+}
+#endif /* !CONFIG_SMC91111_EXT_PHY */
+
+
+#if SMC_DEBUG > 2
+static void print_packet( byte * buf, int length )
+{
+#if 0
+ int i;
+ int remainder;
+ int lines;
+
+ printf("Packet of length %d \n", length );
+
+#if SMC_DEBUG > 3
+ lines = length / 16;
+ remainder = length % 16;
+
+ for ( i = 0; i < lines ; i ++ ) {
+ int cur;
+
+ for ( cur = 0; cur < 8; cur ++ ) {
+ byte a, b;
+
+ a = *(buf ++ );
+ b = *(buf ++ );
+ printf("%02x%02x ", a, b );
+ }
+ printf("\n");
+ }
+ for ( i = 0; i < remainder/2 ; i++ ) {
+ byte a, b;
+
+ a = *(buf ++ );
+ b = *(buf ++ );
+ printf("%02x%02x ", a, b );
+ }
+ printf("\n");
+#endif
+#endif
+}
+#endif
+
+int eth_init(bd_t *bd) {
+ smc_open();
+ return 0;
+}
+
+void eth_halt() {
+ smc_close();
+}
+
+int eth_rx() {
+ return smc_rcv();
+}
+
+int eth_send(volatile void *packet, int length) {
+ return smc_send_packet(packet, length);
+}
+
+#endif /* CONFIG_DRIVER_SMC91111 */
diff --git a/drivers/smc91111.h b/drivers/smc91111.h
new file mode 100644
index 0000000..a372c27
--- /dev/null
+++ b/drivers/smc91111.h
@@ -0,0 +1,619 @@
+/*------------------------------------------------------------------------
+ . smc91111.h - macros for the LAN91C111 Ethernet Driver
+ .
+ . (C) Copyright 2002
+ . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ . Rolf Offermanns <rof@sysgo.de>
+ . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
+ . Developed by Simple Network Magic Corporation (SNMC)
+ . Copyright (C) 1996 by Erik Stahlman (ES)
+ .
+ . This program is free software; you can redistribute it and/or modify
+ . it under the terms of the GNU General Public License as published by
+ . the Free Software Foundation; either version 2 of the License, or
+ . (at your option) any later version.
+ .
+ . This program is distributed in the hope that it will be useful,
+ . but WITHOUT ANY WARRANTY; without even the implied warranty of
+ . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ . GNU General Public License for more details.
+ .
+ . You should have received a copy of the GNU General Public License
+ . along with this program; if not, write to the Free Software
+ . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ .
+ . This file contains register information and access macros for
+ . the LAN91C111 single chip ethernet controller. It is a modified
+ . version of the smc9194.h file.
+ .
+ . Information contained in this file was obtained from the LAN91C111
+ . manual from SMC. To get a copy, if you really want one, you can find
+ . information under www.smsc.com.
+ .
+ . Authors
+ . Erik Stahlman ( erik@vt.edu )
+ . Daris A Nevil ( dnevil@snmc.com )
+ .
+ . History
+ . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
+ .
+ ---------------------------------------------------------------------------*/
+#ifndef _SMC91111_H_
+#define _SMC91111_H_
+
+#include <asm/types.h>
+#include <config.h>
+
+/*
+ * This function may be called by the board specific initialisation code
+ * in order to override the default mac address.
+ */
+
+void smc_set_mac_addr(const char *addr);
+
+
+/* I want some simple types */
+
+typedef unsigned char byte;
+typedef unsigned short word;
+typedef unsigned long int dword;
+
+/*
+ . DEBUGGING LEVELS
+ .
+ . 0 for normal operation
+ . 1 for slightly more details
+ . >2 for various levels of increasingly useless information
+ . 2 for interrupt tracking, status flags
+ . 3 for packet info
+ . 4 for complete packet dumps
+*/
+/*#define SMC_DEBUG 0 */
+
+/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
+
+#define SMC_IO_EXTENT 16
+
+#ifdef CONFIG_PXA250
+
+#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
+#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define SMC_inb(p) ({ \
+ unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \
+ unsigned int __v = *(volatile unsigned short *)((SMC_BASE_ADDRESS + __p) & ~1); \
+ if (__p & 1) __v >>= 8; \
+ else __v &= 0xff; \
+ __v; })
+
+#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outb(d,r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw((r)&~1); \
+ __w &= ((r)&1) ? 0x00FF : 0xFF00; \
+ __w |= ((r)&1) ? __d<<8 : __d; \
+ SMC_outw(__w,(r)&~1); \
+ })
+
+#define SMC_outsl(r,b,l) ({ int __i; \
+ dword *__b2; \
+ __b2 = (dword *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ SMC_outl( *(__b2 + __i), r); \
+ } \
+ })
+
+#define SMC_outsw(r,b,l) ({ int __i; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ SMC_outw( *(__b2 + __i), r); \
+ } \
+ })
+
+#define SMC_insl(r,b,l) ({ int __i ; \
+ dword *__b2; \
+ __b2 = (dword *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = SMC_inl(r); \
+ SMC_inl(0); \
+ }; \
+ })
+
+#define SMC_insw(r,b,l) ({ int __i ; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = SMC_inw(r); \
+ SMC_inw(0); \
+ }; \
+ })
+
+#define SMC_insb(r,b,l) ({ int __i ; \
+ byte *__b2; \
+ __b2 = (byte *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = SMC_inb(r); \
+ SMC_inb(0); \
+ }; \
+ })
+
+#else /* if not CONFIG_PXA250 */
+
+/*
+ * We have only 16 Bit PCMCIA access on Socket 0
+ */
+
+#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
+
+#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outb(d,r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw((r)&~1); \
+ __w &= ((r)&1) ? 0x00FF : 0xFF00; \
+ __w |= ((r)&1) ? __d<<8 : __d; \
+ SMC_outw(__w,(r)&~1); \
+ })
+#if 0
+#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l))
+#else
+#define SMC_outsw(r,b,l) ({ int __i; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ SMC_outw( *(__b2 + __i), r); \
+ } \
+ })
+#endif
+
+#if 0
+#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l))
+#else
+#define SMC_insw(r,b,l) ({ int __i ; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = SMC_inw(r); \
+ SMC_inw(0); \
+ }; \
+ })
+#endif
+
+#endif
+
+/*---------------------------------------------------------------
+ .
+ . A description of the SMSC registers is probably in order here,
+ . although for details, the SMC datasheet is invaluable.
+ .
+ . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
+ . are accessed by writing a number into the BANK_SELECT register
+ . ( I also use a SMC_SELECT_BANK macro for this ).
+ .
+ . The banks are configured so that for most purposes, bank 2 is all
+ . that is needed for simple run time tasks.
+ -----------------------------------------------------------------------*/
+
+/*
+ . Bank Select Register:
+ .
+ . yyyy yyyy 0000 00xx
+ . xx = bank number
+ . yyyy yyyy = 0x33, for identification purposes.
+*/
+#define BANK_SELECT 14
+
+/* Transmit Control Register */
+/* BANK 0 */
+#define TCR_REG 0x0000 /* transmit control register */
+#define TCR_ENABLE 0x0001 /* When 1 we can transmit */
+#define TCR_LOOP 0x0002 /* Controls output pin LBK */
+#define TCR_FORCOL 0x0004 /* When 1 will force a collision */
+#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
+#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
+#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
+#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
+#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
+#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
+#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
+
+#define TCR_CLEAR 0 /* do NOTHING */
+/* the default settings for the TCR register : */
+/* QUESTION: do I want to enable padding of short packets ? */
+#define TCR_DEFAULT TCR_ENABLE
+
+
+/* EPH Status Register */
+/* BANK 0 */
+#define EPH_STATUS_REG 0x0002
+#define ES_TX_SUC 0x0001 /* Last TX was successful */
+#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
+#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
+#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
+#define ES_16COL 0x0010 /* 16 Collisions Reached */
+#define ES_SQET 0x0020 /* Signal Quality Error Test */
+#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
+#define ES_TXDEFR 0x0080 /* Transmit Deferred */
+#define ES_LATCOL 0x0200 /* Late collision detected on last tx */
+#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
+#define ES_EXC_DEF 0x0800 /* Excessive Deferral */
+#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
+#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
+#define ES_TXUNRN 0x8000 /* Tx Underrun */
+
+
+/* Receive Control Register */
+/* BANK 0 */
+#define RCR_REG 0x0004
+#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
+#define RCR_PRMS 0x0002 /* Enable promiscuous mode */
+#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
+#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
+#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
+#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
+#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
+#define RCR_SOFTRST 0x8000 /* resets the chip */
+
+/* the normal settings for the RCR register : */
+#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
+#define RCR_CLEAR 0x0 /* set it to a base state */
+
+/* Counter Register */
+/* BANK 0 */
+#define COUNTER_REG 0x0006
+
+/* Memory Information Register */
+/* BANK 0 */
+#define MIR_REG 0x0008
+
+/* Receive/Phy Control Register */
+/* BANK 0 */
+#define RPC_REG 0x000A
+#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
+#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
+#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
+#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
+#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
+#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
+#define RPC_LED_RES (0x01) /* LED = Reserved */
+#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
+#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
+#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
+#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
+#define RPC_LED_TX (0x06) /* LED = TX packet occurred */
+#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
+#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
+
+/* Bank 0 0x000C is reserved */
+
+/* Bank Select Register */
+/* All Banks */
+#define BSR_REG 0x000E
+
+
+/* Configuration Reg */
+/* BANK 1 */
+#define CONFIG_REG 0x0000
+#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
+#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
+#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
+#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
+
+/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
+#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
+
+
+/* Base Address Register */
+/* BANK 1 */
+#define BASE_REG 0x0002
+
+
+/* Individual Address Registers */
+/* BANK 1 */
+#define ADDR0_REG 0x0004
+#define ADDR1_REG 0x0006
+#define ADDR2_REG 0x0008
+
+
+/* General Purpose Register */
+/* BANK 1 */
+#define GP_REG 0x000A
+
+
+/* Control Register */
+/* BANK 1 */
+#define CTL_REG 0x000C
+#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
+#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
+#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
+#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
+#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
+#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
+#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
+#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
+#define CTL_DEFAULT (0x1210)
+
+/* MMU Command Register */
+/* BANK 2 */
+#define MMU_CMD_REG 0x0000
+#define MC_BUSY 1 /* When 1 the last release has not completed */
+#define MC_NOP (0<<5) /* No Op */
+#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
+#define MC_RESET (2<<5) /* Reset MMU to initial state */
+#define MC_REMOVE (3<<5) /* Remove the current rx packet */
+#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
+#define MC_FREEPKT (5<<5) /* Release packet in PNR register */
+#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
+#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
+
+
+/* Packet Number Register */
+/* BANK 2 */
+#define PN_REG 0x0002
+
+
+/* Allocation Result Register */
+/* BANK 2 */
+#define AR_REG 0x0003
+#define AR_FAILED 0x80 /* Alocation Failed */
+
+
+/* RX FIFO Ports Register */
+/* BANK 2 */
+#define RXFIFO_REG 0x0004 /* Must be read as a word */
+#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
+
+
+/* TX FIFO Ports Register */
+/* BANK 2 */
+#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
+#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
+
+
+/* Pointer Register */
+/* BANK 2 */
+#define PTR_REG 0x0006
+#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
+#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
+#define PTR_READ 0x2000 /* When 1 the operation is a read */
+
+
+/* Data Register */
+/* BANK 2 */
+#define SMC91111_DATA_REG 0x0008
+
+
+/* Interrupt Status/Acknowledge Register */
+/* BANK 2 */
+#define SMC91111_INT_REG 0x000C
+
+
+/* Interrupt Mask Register */
+/* BANK 2 */
+#define IM_REG 0x000D
+#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
+#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
+#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
+#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
+#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
+#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
+#define IM_TX_INT 0x02 /* Transmit Interrrupt */
+#define IM_RCV_INT 0x01 /* Receive Interrupt */
+
+
+/* Multicast Table Registers */
+/* BANK 3 */
+#define MCAST_REG1 0x0000
+#define MCAST_REG2 0x0002
+#define MCAST_REG3 0x0004
+#define MCAST_REG4 0x0006
+
+
+/* Management Interface Register (MII) */
+/* BANK 3 */
+#define MII_REG 0x0008
+#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
+#define MII_MDOE 0x0008 /* MII Output Enable */
+#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
+#define MII_MDI 0x0002 /* MII Input, pin MDI */
+#define MII_MDO 0x0001 /* MII Output, pin MDO */
+
+
+/* Revision Register */
+/* BANK 3 */
+#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
+
+
+/* Early RCV Register */
+/* BANK 3 */
+/* this is NOT on SMC9192 */
+#define ERCV_REG 0x000C
+#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
+#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
+
+/* External Register */
+/* BANK 7 */
+#define EXT_REG 0x0000
+
+
+#define CHIP_9192 3
+#define CHIP_9194 4
+#define CHIP_9195 5
+#define CHIP_9196 6
+#define CHIP_91100 7
+#define CHIP_91100FD 8
+#define CHIP_91111FD 9
+
+#if 0
+static const char * chip_ids[ 15 ] = {
+ NULL, NULL, NULL,
+ /* 3 */ "SMC91C90/91C92",
+ /* 4 */ "SMC91C94",
+ /* 5 */ "SMC91C95",
+ /* 6 */ "SMC91C96",
+ /* 7 */ "SMC91C100",
+ /* 8 */ "SMC91C100FD",
+ /* 9 */ "SMC91C111",
+ NULL, NULL,
+ NULL, NULL, NULL};
+#endif
+
+/*
+ . Transmit status bits
+*/
+#define TS_SUCCESS 0x0001
+#define TS_LOSTCAR 0x0400
+#define TS_LATCOL 0x0200
+#define TS_16COL 0x0010
+
+/*
+ . Receive status bits
+*/
+#define RS_ALGNERR 0x8000
+#define RS_BRODCAST 0x4000
+#define RS_BADCRC 0x2000
+#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
+#define RS_TOOLONG 0x0800
+#define RS_TOOSHORT 0x0400
+#define RS_MULTICAST 0x0001
+#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
+
+
+/* PHY Types */
+enum {
+ PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
+ PHY_LAN83C180
+};
+
+
+/* PHY Register Addresses (LAN91C111 Internal PHY) */
+
+/* PHY Control Register */
+#define PHY_CNTL_REG 0x00
+#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
+#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
+#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
+#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
+#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
+#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
+#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
+#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
+#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
+
+/* PHY Status Register */
+#define PHY_STAT_REG 0x01
+#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
+#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
+#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
+#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
+#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
+#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
+#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
+#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
+#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
+#define PHY_STAT_LINK 0x0004 /* 1=valid link */
+#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
+#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
+
+/* PHY Identifier Registers */
+#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
+#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
+
+/* PHY Auto-Negotiation Advertisement Register */
+#define PHY_AD_REG 0x04
+#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
+#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
+#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
+#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
+#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
+#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
+#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
+#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
+#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
+
+/* PHY Auto-negotiation Remote End Capability Register */
+#define PHY_RMT_REG 0x05
+/* Uses same bit definitions as PHY_AD_REG */
+
+/* PHY Configuration Register 1 */
+#define PHY_CFG1_REG 0x10
+#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
+#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
+#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
+#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
+#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
+#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
+#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
+#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
+#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
+#define PHY_CFG1_TLVL_MASK 0x003C
+#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
+
+
+/* PHY Configuration Register 2 */
+#define PHY_CFG2_REG 0x11
+#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
+#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
+#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
+#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
+
+/* PHY Status Output (and Interrupt status) Register */
+#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
+#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
+#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
+#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
+#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
+#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
+#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
+#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
+#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
+#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
+#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
+
+/* PHY Interrupt/Status Mask Register */
+#define PHY_MASK_REG 0x13 /* Interrupt Mask */
+/* Uses the same bit definitions as PHY_INT_REG */
+
+
+
+/*-------------------------------------------------------------------------
+ . I define some macros to make it easier to do somewhat common
+ . or slightly complicated, repeated tasks.
+ --------------------------------------------------------------------------*/
+
+/* select a register bank, 0 to 3 */
+
+#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); }
+
+/* this enables an interrupt in the interrupt mask register */
+#define SMC_ENABLE_INT(x) {\
+ unsigned char mask;\
+ SMC_SELECT_BANK(2);\
+ mask = SMC_inb( IM_REG );\
+ mask |= (x);\
+ SMC_outb( mask, IM_REG ); \
+}
+
+/* this disables an interrupt from the interrupt mask register */
+
+#define SMC_DISABLE_INT(x) {\
+ unsigned char mask;\
+ SMC_SELECT_BANK(2);\
+ mask = SMC_inb( IM_REG );\
+ mask &= ~(x);\
+ SMC_outb( mask, IM_REG ); \
+}
+
+/*----------------------------------------------------------------------
+ . Define the interrupts that I want to receive from the card
+ .
+ . I want:
+ . IM_EPH_INT, for nasty errors
+ . IM_RCV_INT, for happy received packets
+ . IM_RX_OVRN_INT, because I have to kick the receiver
+ . IM_MDINT, for PHY Register 18 Status Changes
+ --------------------------------------------------------------------------*/
+#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
+ IM_MDINT)
+
+#endif /* _SMC_91111_H_ */
+