| commit | fefe9d06bd0917739822a4be4c702f1d5d0e0899 | [log] [tgz] |
|---|---|---|
| author | Romain Perier <romain.perier@collabora.com> | Fri Jun 02 11:19:43 2017 +0200 |
| committer | Simon Glass <sjg@chromium.org> | Wed Jun 07 21:30:48 2017 -0600 |
| tree | 8a91be7ed4a303cc512eebbdffd026f45a946025 | |
| parent | cf35242a3e6e15c36150c132b3da8032fa21f91b [diff] |
rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit 0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and introduces random delays and data lose. This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE with the right shift. Signed-off-by: Romain Perier <romain.perier@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>