| commit | dd75927059c51f1e1e9d443c8a3e78254ca2d4ab | [log] [tgz] |
|---|---|---|
| author | Aswath Govindraju <a-govindraju@ti.com> | Fri Jan 28 13:41:36 2022 +0530 |
| committer | Tom Rini <trini@konsulko.com> | Tue Feb 08 11:00:03 2022 -0500 |
| tree | dff7f5464313f1fef0434104682d2ef76632baaf | |
| parent | 6f46c7441a9f02133ae997238712819dab8c95ee [diff] |
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's possible to select one of these two inputs from device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>