| commit | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Mon Oct 08 07:44:30 2012 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Mon Oct 22 14:31:32 2012 -0500 |
| tree | 7d648c2c312b9cc7a75c0350101aacc67afca399 | |
| parent | 3f0997b3255c1498ac92453aa3a7a1cc95914dfd [diff] |
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>