blob: 05a69af6ae2f6e8de44edf52021802424ee79f24 [file] [log] [blame]
Andy Fleming67431052007-04-23 02:54:25 -05001/*
Kumar Gala5f7bbd12011-01-04 18:01:49 -06002 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
Andy Fleming67431052007-04-23 02:54:25 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8568mds board configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/* High Level Configuration Options */
30#define CONFIG_BOOKE 1 /* BOOKE */
Andy Flemingda9d4612007-08-14 00:14:25 -050031#define CONFIG_E500 1 /* BOOKE e500 family */
Andy Fleming67431052007-04-23 02:54:25 -050032#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
33#define CONFIG_MPC8568 1 /* MPC8568 specific */
34#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
35
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xfff80000
37
Kumar Gala5f7bbd12011-01-04 18:01:49 -060038#define CONFIG_SYS_SRIO
39#define CONFIG_SRIO1 /* SRIO port 1 */
40
Haiying Wang1563f562007-11-14 15:52:06 -050041#define CONFIG_PCI 1 /* Enable PCI/PCIE */
42#define CONFIG_PCI1 1 /* PCI controller */
43#define CONFIG_PCIE1 1 /* PCIE controller */
44#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000045#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ff3de62007-12-07 12:17:34 -060046#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050047#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingb96c83d2007-08-15 20:03:34 -050049#define CONFIG_QE /* Enable QE */
Andy Fleming67431052007-04-23 02:54:25 -050050#define CONFIG_ENV_OVERWRITE
Kumar Gala4d3521c2008-01-16 09:15:29 -060051#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Andy Fleming67431052007-04-23 02:54:25 -050052
Andy Fleming67431052007-04-23 02:54:25 -050053#ifndef __ASSEMBLY__
54extern unsigned long get_clock_freq(void);
55#endif /*Replace a call to get_clock_freq (after it is implemented)*/
56#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
57
58/*
59 * These can be toggled for performance analysis, otherwise use default.
60 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020061#define CONFIG_L2_CACHE /* toggle L2 cache */
Haiying Wang7a1ac412007-08-23 15:20:54 -040062#define CONFIG_BTB /* toggle branch predition */
Andy Fleming67431052007-04-23 02:54:25 -050063
64/*
65 * Only possible on E500 Version 2 or newer cores.
66 */
67#define CONFIG_ENABLE_36BIT_PHYS 1
68
69
70#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
71
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
73#define CONFIG_SYS_MEMTEST_END 0x00400000
Andy Fleming67431052007-04-23 02:54:25 -050074
Timur Tabie46fedf2011-08-04 18:03:41 -050075#define CONFIG_SYS_CCSRBAR 0xe0000000
76#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Andy Fleming67431052007-04-23 02:54:25 -050077
Jon Loeligere6f5b352008-03-18 13:51:05 -050078/* DDR Setup */
79#define CONFIG_FSL_DDR2
80#undef CONFIG_FSL_DDR_INTERACTIVE
81#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
82#define CONFIG_DDR_SPD
Dave Liu9b0ad1b2008-10-28 17:53:38 +080083#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere6f5b352008-03-18 13:51:05 -050084
85#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
88#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Andy Fleming67431052007-04-23 02:54:25 -050089
Jon Loeligere6f5b352008-03-18 13:51:05 -050090#define CONFIG_NUM_DDR_CONTROLLERS 1
91#define CONFIG_DIMM_SLOTS_PER_CTLR 1
92#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Andy Fleming67431052007-04-23 02:54:25 -050093
Jon Loeligere6f5b352008-03-18 13:51:05 -050094/* I2C addresses of SPD EEPROMs */
95#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
96
97/* Make sure required options are set */
Andy Fleming67431052007-04-23 02:54:25 -050098#ifndef CONFIG_SPD_EEPROM
99#error ("CONFIG_SPD_EEPROM is required")
100#endif
101
102#undef CONFIG_CLOCKS_IN_MHZ
103
Andy Fleming67431052007-04-23 02:54:25 -0500104/*
105 * Local Bus Definitions
106 */
107
108/*
109 * FLASH on the Local Bus
110 * Two banks, 8M each, using the CFI driver.
111 * Boot from BR0/OR0 bank at 0xff00_0000
112 * Alternate BR1/OR1 bank at 0xff80_0000
113 *
114 * BR0, BR1:
115 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
116 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
117 * Port Size = 16 bits = BRx[19:20] = 10
118 * Use GPCM = BRx[24:26] = 000
119 * Valid = BRx[31] = 1
120 *
121 * 0 4 8 12 16 20 24 28
122 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
123 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
124 *
125 * OR0, OR1:
126 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
127 * Reserved ORx[17:18] = 11, confusion here?
128 * CSNT = ORx[20] = 1
129 * ACS = half cycle delay = ORx[21:22] = 11
130 * SCY = 6 = ORx[24:27] = 0110
131 * TRLX = use relaxed timing = ORx[29] = 1
132 * EAD = use external address latch delay = OR[31] = 1
133 *
134 * 0 4 8 12 16 20 24 28
135 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BCSR_BASE 0xf8000000
Andy Fleming67431052007-04-23 02:54:25 -0500138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
Andy Fleming67431052007-04-23 02:54:25 -0500140
141/*Chip select 0 - Flash*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BR0_PRELIM 0xfe001001
143#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
Andy Fleming67431052007-04-23 02:54:25 -0500144
145/*Chip slelect 1 - BCSR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_BR1_PRELIM 0xf8000801
147#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
150#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
151#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
152#undef CONFIG_SYS_FLASH_CHECKSUM
153#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
154#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Andy Fleming67431052007-04-23 02:54:25 -0500155
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200156#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Andy Fleming67431052007-04-23 02:54:25 -0500157
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200158#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_CFI
160#define CONFIG_SYS_FLASH_EMPTY_INFO
Andy Fleming67431052007-04-23 02:54:25 -0500161
162
163/*
164 * SDRAM on the LocalBus
165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
167#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Andy Fleming67431052007-04-23 02:54:25 -0500168
169
170/*Chip select 2 - SDRAM*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_BR2_PRELIM 0xf0001861
172#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Andy Fleming67431052007-04-23 02:54:25 -0500173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
175#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
176#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
177#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Andy Fleming67431052007-04-23 02:54:25 -0500178
179/*
Andy Fleming67431052007-04-23 02:54:25 -0500180 * Common settings for all Local Bus SDRAM commands.
181 * At run time, either BSMA1516 (for CPU 1.1)
182 * or BSMA1617 (for CPU 1.0) (old)
183 * is OR'ed in too.
184 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500185#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
186 | LSDMR_PRETOACT7 \
187 | LSDMR_ACTTORW7 \
188 | LSDMR_BL8 \
189 | LSDMR_WRC4 \
190 | LSDMR_CL3 \
191 | LSDMR_RFEN \
Andy Fleming67431052007-04-23 02:54:25 -0500192 )
193
194/*
195 * The bcsr registers are connected to CS3 on MDS.
196 * The new memory map places bcsr at 0xf8000000.
197 *
198 * For BR3, need:
199 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
200 * port-size = 8-bits = BR[19:20] = 01
201 * no parity checking = BR[21:22] = 00
202 * GPMC for MSEL = BR[24:26] = 000
203 * Valid = BR[31] = 1
204 *
205 * 0 4 8 12 16 20 24 28
206 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
207 *
208 * For OR3, need:
209 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
210 * disable buffer ctrl OR[19] = 0
211 * CSNT OR[20] = 1
212 * ACS OR[21:22] = 11
213 * XACS OR[23] = 1
214 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
215 * SETA OR[28] = 0
216 * TRLX OR[29] = 1
217 * EHTR OR[30] = 1
218 * EAD extra time OR[31] = 1
219 *
220 * 0 4 8 12 16 20 24 28
221 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_BCSR (0xf8000000)
Andy Fleming67431052007-04-23 02:54:25 -0500224
225/*Chip slelect 4 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_BR4_PRELIM 0xf8008801
227#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500228
229/*Chip select 5 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BR5_PRELIM 0xf8010801
231#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
Andy Fleming67431052007-04-23 02:54:25 -0500232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_RAM_LOCK 1
234#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200235#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Andy Fleming67431052007-04-23 02:54:25 -0500236
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200237#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andy Fleming67431052007-04-23 02:54:25 -0500239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
241#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Andy Fleming67431052007-04-23 02:54:25 -0500242
243/* Serial Port */
244#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_NS16550
246#define CONFIG_SYS_NS16550_SERIAL
247#define CONFIG_SYS_NS16550_REG_SIZE 1
248#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andy Fleming67431052007-04-23 02:54:25 -0500249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_BAUDRATE_TABLE \
Andy Fleming67431052007-04-23 02:54:25 -0500251 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
254#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Andy Fleming67431052007-04-23 02:54:25 -0500255
256/* Use the HUSH parser*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_HUSH_PARSER
258#ifdef CONFIG_SYS_HUSH_PARSER
Andy Fleming67431052007-04-23 02:54:25 -0500259#endif
260
261/* pass open firmware flat tree */
Kumar Galac4808612007-11-29 01:06:19 -0600262#define CONFIG_OF_LIBFDT 1
263#define CONFIG_OF_BOARD_SETUP 1
264#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Andy Fleming67431052007-04-23 02:54:25 -0500265
266/*
267 * I2C
268 */
269#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
270#define CONFIG_HARD_I2C /* I2C with hardware support*/
Haiying Wangc59e4092007-06-19 14:18:34 -0400271#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
273#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
274#define CONFIG_SYS_I2C_SLAVE 0x7F
275#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
276#define CONFIG_SYS_I2C_OFFSET 0x3000
277#define CONFIG_SYS_I2C2_OFFSET 0x3100
Andy Fleming67431052007-04-23 02:54:25 -0500278
279/*
280 * General PCI
281 * Memory Addresses are mapped 1-1. I/O is mapped from 0
282 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600283#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600284#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600285#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600287#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600288#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
290#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500291
Kumar Gala3f6f9d72010-12-17 10:13:19 -0600292#define CONFIG_SYS_PCIE1_NAME "Slot"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600293#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600294#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600295#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600297#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600298#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
300#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500301
Kumar Gala5f7bbd12011-01-04 18:01:49 -0600302#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
303#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
304#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
305#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Andy Fleming67431052007-04-23 02:54:25 -0500306
Andy Flemingda9d4612007-08-14 00:14:25 -0500307#ifdef CONFIG_QE
308/*
309 * QE UEC ethernet configuration
310 */
311#define CONFIG_UEC_ETH
312#ifndef CONFIG_TSEC_ENET
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500313#define CONFIG_ETHPRIME "UEC0"
Andy Flemingda9d4612007-08-14 00:14:25 -0500314#endif
315#define CONFIG_PHY_MODE_NEED_CHANGE
316#define CONFIG_eTSEC_MDIO_BUS
317
318#ifdef CONFIG_eTSEC_MDIO_BUS
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200319#define CONFIG_MIIM_ADDRESS 0xE0024520
Andy Flemingda9d4612007-08-14 00:14:25 -0500320#endif
321
322#define CONFIG_UEC_ETH1 /* GETH1 */
323
324#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
326#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
327#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
328#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
329#define CONFIG_SYS_UEC1_PHY_ADDR 7
Andy Fleming865ff852011-04-13 00:37:12 -0500330#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100331#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500332#endif
333
334#define CONFIG_UEC_ETH2 /* GETH2 */
335
336#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
338#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
339#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
340#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
341#define CONFIG_SYS_UEC2_PHY_ADDR 1
Andy Fleming865ff852011-04-13 00:37:12 -0500342#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100343#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500344#endif
345#endif /* CONFIG_QE */
346
Haiying Wangf30ad492007-11-19 10:02:13 -0500347#if defined(CONFIG_PCI)
348
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200349#define CONFIG_PCI_PNP /* do pci plug-and-play */
Haiying Wangf30ad492007-11-19 10:02:13 -0500350
Andy Fleming67431052007-04-23 02:54:25 -0500351#undef CONFIG_EEPRO100
352#undef CONFIG_TULIP
353
354#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Andy Fleming67431052007-04-23 02:54:25 -0500356
357#endif /* CONFIG_PCI */
358
Andy Flemingda9d4612007-08-14 00:14:25 -0500359#if defined(CONFIG_TSEC_ENET)
360
Andy Fleming67431052007-04-23 02:54:25 -0500361#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500362#define CONFIG_TSEC1 1
363#define CONFIG_TSEC1_NAME "eTSEC0"
364#define CONFIG_TSEC2 1
365#define CONFIG_TSEC2_NAME "eTSEC1"
Andy Fleming67431052007-04-23 02:54:25 -0500366
367#define TSEC1_PHY_ADDR 2
368#define TSEC2_PHY_ADDR 3
369
370#define TSEC1_PHYIDX 0
371#define TSEC2_PHYIDX 0
372
Andy Fleming3a790132007-08-15 20:03:25 -0500373#define TSEC1_FLAGS TSEC_GIGABIT
374#define TSEC2_FLAGS TSEC_GIGABIT
375
Andy Flemingb96c83d2007-08-15 20:03:34 -0500376/* Options are: eTSEC[0-1] */
Andy Fleming67431052007-04-23 02:54:25 -0500377#define CONFIG_ETHPRIME "eTSEC0"
378
379#endif /* CONFIG_TSEC_ENET */
380
381/*
382 * Environment
383 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200384#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200386#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
387#define CONFIG_ENV_SIZE 0x2000
Andy Fleming67431052007-04-23 02:54:25 -0500388
389#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Andy Fleming67431052007-04-23 02:54:25 -0500391
Jon Loeliger2835e512007-06-13 13:22:08 -0500392
393/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500394 * BOOTP options
395 */
396#define CONFIG_BOOTP_BOOTFILESIZE
397#define CONFIG_BOOTP_BOOTPATH
398#define CONFIG_BOOTP_GATEWAY
399#define CONFIG_BOOTP_HOSTNAME
400
401
402/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500403 * Command line configuration.
404 */
405#include <config_cmd_default.h>
406
407#define CONFIG_CMD_PING
408#define CONFIG_CMD_I2C
409#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600410#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500411#define CONFIG_CMD_IRQ
412#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500413#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500414
Andy Fleming67431052007-04-23 02:54:25 -0500415#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500416 #define CONFIG_CMD_PCI
Andy Fleming67431052007-04-23 02:54:25 -0500417#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500418
Andy Fleming67431052007-04-23 02:54:25 -0500419
420#undef CONFIG_WATCHDOG /* watchdog disabled */
421
422/*
423 * Miscellaneous configurable options
424 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500426#define CONFIG_CMDLINE_EDITING /* Command-line editing */
427#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
429#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500430#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500432#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500434#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
436#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
437#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
438#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Andy Fleming67431052007-04-23 02:54:25 -0500439
440/*
441 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500442 * have to be in the first 64 MB of memory, since this is
Andy Fleming67431052007-04-23 02:54:25 -0500443 * the maximum mapped by the Linux kernel during initialization.
444 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500445#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
446#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Andy Fleming67431052007-04-23 02:54:25 -0500447
Jon Loeliger2835e512007-06-13 13:22:08 -0500448#if defined(CONFIG_CMD_KGDB)
Andy Fleming67431052007-04-23 02:54:25 -0500449#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
450#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
451#endif
452
453/*
454 * Environment Configuration
455 */
456
457/* The mac addresses for all ethernet interface */
Andy Flemingda9d4612007-08-14 00:14:25 -0500458#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
459#define CONFIG_HAS_ETH0
Andy Fleming67431052007-04-23 02:54:25 -0500460#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
461#define CONFIG_HAS_ETH1
462#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
463#define CONFIG_HAS_ETH2
464#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Andy Flemingda9d4612007-08-14 00:14:25 -0500465#define CONFIG_HAS_ETH3
466#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
Andy Fleming67431052007-04-23 02:54:25 -0500467#endif
468
469#define CONFIG_IPADDR 192.168.1.253
470
471#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000472#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000473#define CONFIG_BOOTFILE "your.uImage"
Andy Fleming67431052007-04-23 02:54:25 -0500474
475#define CONFIG_SERVERIP 192.168.1.1
476#define CONFIG_GATEWAYIP 192.168.1.1
477#define CONFIG_NETMASK 255.255.255.0
478
479#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
480
481#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
482#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
483
484#define CONFIG_BAUDRATE 115200
485
486#define CONFIG_EXTRA_ENV_SETTINGS \
487 "netdev=eth0\0" \
488 "consoledev=ttyS0\0" \
489 "ramdiskaddr=600000\0" \
490 "ramdiskfile=your.ramdisk.u-boot\0" \
491 "fdtaddr=400000\0" \
492 "fdtfile=your.fdt.dtb\0" \
493 "nfsargs=setenv bootargs root=/dev/nfs rw " \
494 "nfsroot=$serverip:$rootpath " \
495 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
496 "console=$consoledev,$baudrate $othbootargs\0" \
497 "ramargs=setenv bootargs root=/dev/ram rw " \
498 "console=$consoledev,$baudrate $othbootargs\0" \
499
500
501#define CONFIG_NFSBOOTCOMMAND \
502 "run nfsargs;" \
503 "tftp $loadaddr $bootfile;" \
504 "tftp $fdtaddr $fdtfile;" \
505 "bootm $loadaddr - $fdtaddr"
506
507
508#define CONFIG_RAMBOOTCOMMAND \
509 "run ramargs;" \
510 "tftp $ramdiskaddr $ramdiskfile;" \
511 "tftp $loadaddr $bootfile;" \
512 "bootm $loadaddr $ramdiskaddr"
513
514#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
515
516#endif /* __CONFIG_H */