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Michal Simek4ed97322020-01-09 10:28:56 +01001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP ZCU1285 RevA
4 *
Michal Simekd31f1c92020-02-18 08:38:06 +01005 * (C) Copyright 2018 - 2020, Xilinx, Inc.
Michal Simek4ed97322020-01-09 10:28:56 +01006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15
16/ {
17 model = "ZynqMP ZCU1285 RevA";
18 compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285",
19 "xlnx,zynqmp";
20
21 aliases {
22 serial0 = &uart0;
23 serial1 = &dcc;
24 spi0 = &qspi;
25 mmc0 = &sdhci1;
26 i2c = &i2c0; /* EMIO */
27 };
28
29 chosen {
30 bootargs = "earlycon";
31 stdout-path = "serial0:115200n8";
32 };
33
34 memory@0 {
35 device_type = "memory";
36 reg = <0x0 0x0 0x0 0x80000000>;
37 };
38
39 ina226-u60 {
40 compatible = "iio-hwmon";
41 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
42 };
43 ina226-u61 {
44 compatible = "iio-hwmon";
45 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
46 };
47 ina226-u63 {
48 compatible = "iio-hwmon";
49 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
50 };
51 ina226-u65 {
52 compatible = "iio-hwmon";
53 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
54 };
55 ina226-u64 {
56 compatible = "iio-hwmon";
57 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
58 };
59};
60
61&dcc {
62 status = "okay";
63};
64
65&i2c0 {
66 status = "okay";
67 clock-frequency = <400000>;
68
69 i2c-mux@75 {
70 compatible = "nxp,pca9548"; /* u22 */
71 #address-cells = <1>;
72 #size-cells = <0>;
73 reg = <0x75>;
74
75 i2c@0 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 reg = <0>;
79 /* PMBUS */
80 max20751@74 { /* u23 */
81 compatible = "maxim,max20751";
82 reg = <0x74>;
83 };
84 max20751@70 { /* u89 */
85 compatible = "maxim,max20751";
86 reg = <0x70>;
87 };
88 max15301@a { /* u28 */
89 compatible = "maxim,max15301";
90 reg = <0xa>;
91 };
92 max15303@b { /* u48 */
93 compatible = "maxim,max15303";
94 reg = <0xb>;
95 };
96 max15303@d { /* u27 */
97 compatible = "maxim,max15303";
98 reg = <0xd>;
99 };
100 max15303@e { /* u11 */
101 compatible = "maxim,max15303";
102 reg = <0xe>;
103 };
104 max15303@f { /* u96 */
105 compatible = "maxim,max15303";
106 reg = <0xf>;
107 };
108 max15303@11 { /* u47 */
109 compatible = "maxim,max15303";
110 reg = <0x11>;
111 };
112 max15303@12 { /* u24 */
113 compatible = "maxim,max15303";
114 reg = <0x12>;
115 };
116 max15301@13 { /* u29 */
117 compatible = "maxim,max15301";
118 reg = <0x13>;
119 };
120 max15303@14 { /* u51 */
121 compatible = "maxim,max15303";
122 reg = <0x14>;
123 };
124 max15303@15 { /* u30 */
125 compatible = "maxim,max15303";
126 reg = <0x15>;
127 };
128 max15303@16 { /* u102 */
129 compatible = "maxim,max15303";
130 reg = <0x16>;
131 };
132 max15301@17 { /* u50 */
133 compatible = "maxim,max15301";
134 reg = <0x17>;
135 };
136 max15301@18 { /* u31 */
137 compatible = "maxim,max15301";
138 reg = <0x18>;
139 };
140 };
141 i2c@1 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 reg = <1>;
145 /* CM_I2C */
146 };
147 i2c@2 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 reg = <2>;
151 /* SYS_EEPROM */
152 eeprom: eeprom@54 { /* u101 */
153 compatible = "atmel,24c32"; /* 24LC32A */
154 reg = <0x54>;
155 };
156 };
157 i2c@3 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 reg = <3>;
161 /* FMC1 */
162 };
163 i2c@4 {
164 #address-cells = <1>;
165 #size-cells = <0>;
166 reg = <4>;
167 /* FMC2 */
168 };
169 i2c@5 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg = <5>;
173 /* ANALOG_PMBUS */
174 u60: ina226@40 { /* u60 */
175 compatible = "ti,ina226";
176 #io-channel-cells = <1>;
177 label = "ina226-u60";
178 reg = <0x40>;
179 shunt-resistor = <1000>;
180 };
181 u61: ina226@41 { /* u61 */
182 compatible = "ti,ina226";
183 #io-channel-cells = <1>;
184 label = "ina226-u61";
185 reg = <0x41>;
186 shunt-resistor = <1000>;
187 };
188 u63: ina226@42 { /* u63 */
189 compatible = "ti,ina226";
190 #io-channel-cells = <1>;
191 label = "ina226-u63";
192 reg = <0x42>;
193 shunt-resistor = <1000>;
194 };
195 u65: ina226@43 { /* u65 */
196 compatible = "ti,ina226";
197 #io-channel-cells = <1>;
198 label = "ina226-u65";
199 reg = <0x43>;
200 shunt-resistor = <1000>;
201 };
202 u64: ina226@44 { /* u64 */
203 compatible = "ti,ina226";
204 #io-channel-cells = <1>;
205 label = "ina226-u64";
206 reg = <0x44>;
207 shunt-resistor = <1000>;
208 };
209 };
210 i2c@6 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <6>;
214 /* ANALOG_CM_I2C */
215 };
216 i2c@7 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 reg = <7>;
220 /* FMC3 */
221 };
222 };
223};
224
225&qspi {
226 status = "okay";
227 flash@0 {
228 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
229 #address-cells = <1>;
230 #size-cells = <1>;
231 reg = <0x0>;
232 spi-tx-bus-width = <1>;
233 spi-rx-bus-width = <1>;
234 spi-max-frequency = <108000000>; /* Based on DC1 spec */
235 };
236};
237
238&uart0 {
239 status = "okay";
240};
241
242&sdhci1 {
243 status = "okay";
Manish Narani12ffe752020-02-13 23:37:30 -0700244 /*
245 * This property should be removed for supporting UHS mode
246 */
247 no-1-8-v;
Michal Simek4ed97322020-01-09 10:28:56 +0100248 xlnx,mio_bank = <1>;
249};