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Wolfgang Denk72a087e2006-10-24 14:27:35 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22#include <common.h>
23#include <command.h>
24
25#include <asm/io.h>
26#include <asm/sections.h>
27#include <asm/sysreg.h>
28
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010029#include <asm/arch/clk.h>
Wolfgang Denk72a087e2006-10-24 14:27:35 +020030#include <asm/arch/memory-map.h>
Wolfgang Denk72a087e2006-10-24 14:27:35 +020031
32#include "hsmc3.h"
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010033#include "sm.h"
34
35/* Sanity checks */
36#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
37 || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
38 || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
39# error Constraint fCPU >= fHSB >= fPB{A,B} violated
40#endif
41#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
42# error Invalid PLL multiplier and/or divider
43#endif
Wolfgang Denk72a087e2006-10-24 14:27:35 +020044
45DECLARE_GLOBAL_DATA_PTR;
46
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010047static void pm_init(void)
48{
49 uint32_t cksel;
50
51#ifdef CONFIG_PLL
52 /* Initialize the PLL */
53 sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
54 | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
55 | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
56 | SM_BF(PLLOPT, CFG_PLL0_OPT)
57 | SM_BF(PLLOSC, 0)
58 | SM_BIT(PLLEN)));
59
60 /* Wait for lock */
61 while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
62#endif
63
64 /* Set up clocks for the CPU and all peripheral buses */
65 cksel = 0;
66 if (CFG_CLKDIV_CPU)
67 cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
68 if (CFG_CLKDIV_HSB)
69 cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
70 if (CFG_CLKDIV_PBA)
71 cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
72 if (CFG_CLKDIV_PBB)
73 cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
74 sm_writel(PM_CKSEL, cksel);
75
76 gd->cpu_hz = get_cpu_clk_rate();
77
78#ifdef CONFIG_PLL
79 /* Use PLL0 as main clock */
80 sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
81#endif
82}
83
Wolfgang Denk72a087e2006-10-24 14:27:35 +020084int cpu_init(void)
85{
Wolfgang Denk72a087e2006-10-24 14:27:35 +020086 extern void _evba(void);
87 char *p;
88
89 gd->cpu_hz = CFG_OSC0_HZ;
90
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010091 /* TODO: Move somewhere else, but needs to be run before we
92 * increase the clock frequency. */
93 hsmc3_writel(MODE0, 0x00031103);
94 hsmc3_writel(CYCLE0, 0x000c000d);
95 hsmc3_writel(PULSE0, 0x0b0a0906);
96 hsmc3_writel(SETUP0, 0x00010002);
Wolfgang Denk72a087e2006-10-24 14:27:35 +020097
98 pm_init();
99
100 sysreg_write(EVBA, (unsigned long)&_evba);
101 asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
Wolfgang Denk72a087e2006-10-24 14:27:35 +0200102
103 /* Lock everything that mess with the flash in the icache */
104 for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
105 p += CFG_ICACHE_LINESZ)
106 asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
107
108 return 0;
109}
110
111void prepare_to_boot(void)
112{
113 /* Flush both caches and the write buffer */
114 asm volatile("cache %0[4], 010\n\t"
115 "cache %0[0], 000\n\t"
116 "sync 0" : : "r"(0) : "memory");
117}
118
119int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
120{
121 /* This will reset the CPU core, caches, MMU and all internal busses */
122 __builtin_mtdr(8, 1 << 13); /* set DC:DBE */
123 __builtin_mtdr(8, 1 << 30); /* set DC:RES */
124
125 /* Flush the pipeline before we declare it a failure */
126 asm volatile("sub pc, pc, -4");
127
128 return -1;
129}