blob: 4220e8190de431aa0dfa5b8ee557db298134f0ba [file] [log] [blame]
Aubrey Li65458982007-03-20 18:16:24 +08001/*
2 * U-boot - u-boot.lds.S
3 *
Mike Frysinger9171fc82008-03-30 15:46:13 -04004 * Copyright (c) 2005-2008 Analog Device Inc.
Aubrey Li65458982007-03-20 18:16:24 +08005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -040029#include <asm/blackfin.h>
30#undef ALIGN
Mike Frysingerb9eecc32008-10-24 17:48:54 -040031#undef ENTRY
32#undef bfin
Mike Frysinger9171fc82008-03-30 15:46:13 -040033
34/* If we don't actually load anything into L1 data, this will avoid
35 * a syntax error. If we do actually load something into L1 data,
36 * we'll get a linker memory load error (which is what we'd want).
37 * This is here in the first place so we can quickly test building
38 * for different CPU's which may lack non-cache L1 data.
39 */
40#ifndef L1_DATA_B_SRAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
Mike Frysinger9171fc82008-03-30 15:46:13 -040042# define L1_DATA_B_SRAM_SIZE 0
43#endif
Aubrey Li65458982007-03-20 18:16:24 +080044
45OUTPUT_ARCH(bfin)
Mike Frysinger9171fc82008-03-30 15:46:13 -040046
Mike Frysinger9171fc82008-03-30 15:46:13 -040047MEMORY
48{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
Mike Frysinger7e1d2122008-10-18 04:04:49 -040050 l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
51 l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
Mike Frysinger9171fc82008-03-30 15:46:13 -040052}
53
Mike Frysingerb9eecc32008-10-24 17:48:54 -040054ENTRY(_start)
Aubrey Li65458982007-03-20 18:16:24 +080055SECTIONS
56{
Mike Frysinger9171fc82008-03-30 15:46:13 -040057 .text :
58 {
Mike Frysingerb9eecc32008-10-24 17:48:54 -040059 cpu/blackfin/start.o (.text .text.*)
Mike Frysingerc23bff62008-10-11 20:47:58 -040060
Mike Frysinger9171fc82008-03-30 15:46:13 -040061#ifdef ENV_IS_EMBEDDED
62 /* WARNING - the following is hand-optimized to fit within
63 * the sector before the environment sector. If it throws
64 * an error during compilation remove an object here to get
65 * it linked after the configuration sector.
66 */
Aubrey Li65458982007-03-20 18:16:24 +080067
Mike Frysingerb9eecc32008-10-24 17:48:54 -040068 cpu/blackfin/traps.o (.text .text.*)
69 cpu/blackfin/interrupt.o (.text .text.*)
70 cpu/blackfin/serial.o (.text .text.*)
71 common/dlmalloc.o (.text .text.*)
72 lib_generic/crc32.o (.text .text.*)
73 lib_generic/zlib.o (.text .text.*)
74 board/bf561-ezkit/bf561-ezkit.o (.text .text.*)
Aubrey Li65458982007-03-20 18:16:24 +080075
Mike Frysinger9171fc82008-03-30 15:46:13 -040076 . = DEFINED(env_offset) ? env_offset : .;
Mike Frysingerb9eecc32008-10-24 17:48:54 -040077 common/env_embedded.o (.text .text.*)
Mike Frysinger9171fc82008-03-30 15:46:13 -040078#endif
Aubrey Li65458982007-03-20 18:16:24 +080079
Mike Frysingerc23bff62008-10-11 20:47:58 -040080 __initcode_start = .;
Mike Frysingerb9eecc32008-10-24 17:48:54 -040081 cpu/blackfin/initcode.o (.text .text.*)
Mike Frysingerc23bff62008-10-11 20:47:58 -040082 __initcode_end = .;
83
Mike Frysinger9171fc82008-03-30 15:46:13 -040084 *(.text .text.*)
85 } >ram
Aubrey Li65458982007-03-20 18:16:24 +080086
Mike Frysinger9171fc82008-03-30 15:46:13 -040087 .rodata :
88 {
89 . = ALIGN(4);
90 *(.rodata .rodata.*)
91 *(.rodata1)
92 *(.eh_frame)
93 . = ALIGN(4);
94 } >ram
Aubrey Li65458982007-03-20 18:16:24 +080095
Mike Frysinger9171fc82008-03-30 15:46:13 -040096 .data :
97 {
98 . = ALIGN(256);
99 *(.data .data.*)
100 *(.data1)
101 *(.sdata)
102 *(.sdata2)
103 *(.dynamic)
104 CONSTRUCTORS
105 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800106
Mike Frysinger9171fc82008-03-30 15:46:13 -0400107 .u_boot_cmd :
108 {
109 ___u_boot_cmd_start = .;
110 *(.u_boot_cmd)
111 ___u_boot_cmd_end = .;
112 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800113
Mike Frysinger9171fc82008-03-30 15:46:13 -0400114 .text_l1 :
115 {
116 . = ALIGN(4);
117 __stext_l1 = .;
118 *(.l1.text)
119 . = ALIGN(4);
120 __etext_l1 = .;
121 } >l1_code AT>ram
122 __stext_l1_lma = LOADADDR(.text_l1);
Aubrey Li65458982007-03-20 18:16:24 +0800123
Mike Frysinger9171fc82008-03-30 15:46:13 -0400124 .data_l1 :
125 {
126 . = ALIGN(4);
127 __sdata_l1 = .;
128 *(.l1.data)
129 *(.l1.bss)
130 . = ALIGN(4);
131 __edata_l1 = .;
132 } >l1_data AT>ram
133 __sdata_l1_lma = LOADADDR(.data_l1);
Aubrey Li65458982007-03-20 18:16:24 +0800134
Mike Frysinger9171fc82008-03-30 15:46:13 -0400135 .bss :
136 {
137 . = ALIGN(4);
138 __bss_start = .;
139 *(.sbss) *(.scommon)
140 *(.dynbss)
141 *(.bss .bss.*)
142 *(COMMON)
143 __bss_end = .;
144 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800145}