blob: aa11a5d397e68f5c444234d505aaf56427a863c8 [file] [log] [blame]
Kumar Gala74121b42008-01-17 01:56:32 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
Kumar Gala74121b42008-01-17 01:56:32 -060032 MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
Kumar Gala74121b42008-01-17 01:56:32 -060035 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
Kumar Gala74121b42008-01-17 01:56:32 -060038 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
Kumar Gala74121b42008-01-17 01:56:32 -060041 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43
44 /*
45 * TLB 0: 16M Non-cacheable, guarded
46 * 0xff000000 16M FLASH
47 * Out of reset this entry is only 4K.
48 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
Kumar Gala74121b42008-01-17 01:56:32 -060050 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 0, BOOKE_PAGESZ_16M, 1),
52
53 /*
54 * TLB 1: 256M Non-cacheable, guarded
55 * 0x80000000 256M PCI1 MEM First half
56 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
Kumar Gala74121b42008-01-17 01:56:32 -060058 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 0, 1, BOOKE_PAGESZ_256M, 1),
60
61 /*
62 * TLB 2: 256M Non-cacheable, guarded
63 * 0x90000000 256M PCI1 MEM Second half
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
Kumar Gala74121b42008-01-17 01:56:32 -060066 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 0, 2, BOOKE_PAGESZ_256M, 1),
68
69 /*
70 * TLB 3: 256M Non-cacheable, guarded
71 * 0xc0000000 256M Rapid IO MEM First half
72 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
Kumar Gala74121b42008-01-17 01:56:32 -060074 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75 0, 3, BOOKE_PAGESZ_256M, 1),
76
77 /*
78 * TLB 4: 256M Non-cacheable, guarded
79 * 0xd0000000 256M Rapid IO MEM Second half
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081 SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
Kumar Gala74121b42008-01-17 01:56:32 -060082 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 0, 4, BOOKE_PAGESZ_256M, 1),
84
85 /*
86 * TLB 5: 64M Non-cacheable, guarded
87 * 0xe000_0000 1M CCSRBAR
88 * 0xe200_0000 16M PCI1 IO
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
Kumar Gala74121b42008-01-17 01:56:32 -060091 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 0, 5, BOOKE_PAGESZ_64M, 1),
93
94 /*
95 * TLB 6: 64M Cacheable, non-guarded
96 * 0xf000_0000 64M LBC SDRAM
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
Kumar Gala74121b42008-01-17 01:56:32 -060099 MAS3_SX|MAS3_SW|MAS3_SR, 0,
100 0, 6, BOOKE_PAGESZ_64M, 1),
101
102 /*
103 * TLB 7: 16K Non-cacheable, guarded
104 * 0xfc000000 16K Configuration Latch register
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
Kumar Gala74121b42008-01-17 01:56:32 -0600107 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
108 0, 7, BOOKE_PAGESZ_16K, 1),
109
110#if !defined(CONFIG_SPD_EEPROM)
111 /*
112 * TLB 8, 9: 128M DDR
113 * 0x00000000 64M DDR System memory
114 * 0x04000000 64M DDR System memory
115 * Without SPD EEPROM configured DDR, this must be setup manually.
116 * Make sure the TLB count at the top of this table is correct.
117 * Likely it needs to be increased by two for these entries.
118 */
119#error("Update the number of table entries in tlb1_entry")
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
Kumar Gala74121b42008-01-17 01:56:32 -0600121 MAS3_SX|MAS3_SW|MAS3_SR, 0,
122 0, 8, BOOKE_PAGESZ_64M, 1),
123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
Kumar Gala74121b42008-01-17 01:56:32 -0600125 MAS3_SX|MAS3_SW|MAS3_SR, 0,
126 0, 9, BOOKE_PAGESZ_64M, 1),
127#endif
128};
129
130int num_tlb_entries = ARRAY_SIZE(tlb_table);