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HeungJun, Kim89f95492012-01-16 21:13:05 +00001/*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 *
5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_SAMSUNG /* in a SAMSUNG core */
34#define CONFIG_S5P /* which is in a S5P Family */
35#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
36#define CONFIG_TRATS /* working with TRATS */
37
38#include <asm/arch/cpu.h> /* get chip and board defs */
39
40#define CONFIG_ARCH_CPU_INIT
41#define CONFIG_DISPLAY_CPUINFO
42#define CONFIG_DISPLAY_BOARDINFO
43
44/* Keep L2 Cache Disabled */
45#define CONFIG_SYS_L2CACHE_OFF
46
47#define CONFIG_SYS_SDRAM_BASE 0x40000000
48#define CONFIG_SYS_TEXT_BASE 0x63300000
49
50/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
51#define CONFIG_SYS_CLK_FREQ_C210 24000000
Chander Kashyap5e46f832012-02-05 23:01:45 +000052#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
HeungJun, Kim89f95492012-01-16 21:13:05 +000053
54#define CONFIG_SETUP_MEMORY_TAGS
55#define CONFIG_CMDLINE_TAG
HeungJun, Kim89f95492012-01-16 21:13:05 +000056#define CONFIG_REVISION_TAG
57#define CONFIG_CMDLINE_EDITING
58#define CONFIG_SKIP_LOWLEVEL_INIT
59#define CONFIG_BOARD_EARLY_INIT_F
60
61/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
62#define MACH_TYPE_TRATS 3928
63#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
64
65/* Size of malloc() pool */
66#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
67
68/* select serial console configuration */
69#define CONFIG_SERIAL_MULTI
70#define CONFIG_SERIAL2 /* use SERIAL 2 */
71#define CONFIG_BAUDRATE 115200
72
73/* MMC */
74#define CONFIG_GENERIC_MMC
75#define CONFIG_MMC
76#define CONFIG_S5P_MMC
77
78/* PWM */
79#define CONFIG_PWM
80
81/* It should define before config_cmd_default.h */
82#define CONFIG_SYS_NO_FLASH
83
84/* Command definition */
85#include <config_cmd_default.h>
86
87#undef CONFIG_CMD_FPGA
88#undef CONFIG_CMD_MISC
89#undef CONFIG_CMD_NET
90#undef CONFIG_CMD_NFS
91#undef CONFIG_CMD_XIMG
92#undef CONFIG_CMD_CACHE
93#undef CONFIG_CMD_ONENAND
94#undef CONFIG_CMD_MTDPARTS
95#define CONFIG_CMD_MMC
96
97#define CONFIG_BOOTDELAY 1
98#define CONFIG_ZERO_BOOTDELAY_CHECK
99#define CONFIG_BOOTARGS "Please use defined boot"
100#define CONFIG_BOOTCOMMAND "run mmcboot"
101
102#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
103#define CONFIG_BOOTBLOCK "10"
104#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
105
106#define CONFIG_ENV_OVERWRITE
107#define CONFIG_SYS_CONSOLE_INFO_QUIET
108#define CONFIG_SYS_CONSOLE_IS_IN_ENV
109
110#define CONFIG_EXTRA_ENV_SETTINGS \
111 "bootk=" \
112 "run loaduimage; bootm 0x40007FC0\0" \
113 "updatemmc=" \
114 "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
115 "mmc boot 0 1 1 0\0" \
116 "updatebackup=" \
117 "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
118 "mmc boot 0 1 1 0\0" \
119 "updatebootb=" \
120 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
121 "lpj=lpj=3981312\0" \
122 "nfsboot=" \
123 "set bootargs root=/dev/nfs rw " \
124 "nfsroot=${nfsroot},nolock,tcp " \
125 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
126 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
127 "; run bootk\0" \
128 "ramfsboot=" \
129 "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
130 "${console} ${meminfo} " \
131 "initrd=0x43000000,8M ramdisk=8192\0" \
132 "mmcboot=" \
133 "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
134 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
135 "run loaduimage; bootm 0x40007FC0\0" \
136 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
137 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
138 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
139 "verify=n\0" \
140 "rootfstype=ext4\0" \
141 "console=" CONFIG_DEFAULT_CONSOLE \
142 "meminfo=crashkernel=32M@0x50000000\0" \
143 "nfsroot=/nfsroot/arm\0" \
144 "bootblock=" CONFIG_BOOTBLOCK "\0" \
145 "mmcdev=0\0" \
146 "mmcbootpart=2\0" \
147 "mmcrootpart=3\0" \
148 "opts=always_resume=1"
149
150/* Miscellaneous configurable options */
151#define CONFIG_SYS_LONGHELP /* undef to save memory */
152#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
153#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
154#define CONFIG_SYS_PROMPT "TRATS # "
155#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
156#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
157#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
158/* Boot Argument Buffer Size */
159#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
160/* memtest works on */
161#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
162#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
163#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
164
165#define CONFIG_SYS_HZ 1000
166
167/* valid baudrates */
168#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
169
170/* Stack sizes */
171#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
172
173/* TRATS has 2 banks of DRAM */
174#define CONFIG_NR_DRAM_BANKS 2
175#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
Jaehoon Chunge687c5a2012-03-27 20:05:25 +0000176#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
HeungJun, Kim89f95492012-01-16 21:13:05 +0000177#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
Jaehoon Chunge687c5a2012-03-27 20:05:25 +0000178#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
HeungJun, Kim89f95492012-01-16 21:13:05 +0000179
180#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
181
182#define CONFIG_SYS_MONITOR_BASE 0x00000000
183#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
184
185#define CONFIG_ENV_IS_IN_MMC
186#define CONFIG_SYS_MMC_ENV_DEV 0
187#define CONFIG_ENV_SIZE 4096
188#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
189
190#define CONFIG_DOS_PARTITION
191
192#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
193#define CONFIG_SYS_CACHELINE_SIZE 32
194
195#include <asm/arch/gpio.h>
196/*
197 * I2C Settings
198 */
199#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
200#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
201
202#define CONFIG_SOFT_I2C
203#define CONFIG_SOFT_I2C_READ_REPEATED_START
204#define CONFIG_SYS_I2C_SPEED 50000
205#define CONFIG_I2C_MULTI_BUS
206#define CONFIG_SYS_MAX_I2C_BUS 7
207
208#define CONFIG_PMIC
209#define CONFIG_PMIC_I2C
210#define CONFIG_PMIC_MAX8998
211
212#define CONFIG_USB_GADGET
213#define CONFIG_USB_GADGET_S3C_UDC_OTG
214#define CONFIG_USB_GADGET_DUALSPEED
215
216#endif /* __CONFIG_H */