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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Thomas Choua54915d2015-10-22 22:28:53 +08002/*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
7 * Scott McNutt <smcnutt@psyent.com>
Thomas Choua54915d2015-10-22 22:28:53 +08008 */
9
10#include <common.h>
11#include <dm.h>
12#include <errno.h>
13#include <timer.h>
14#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Thomas Choua54915d2015-10-22 22:28:53 +080016
Thomas Chou1235e5a2015-10-31 20:54:16 +080017/* control register */
18#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
19#define ALTERA_TIMER_START BIT(2) /* Start timer */
20#define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
21
Thomas Choua54915d2015-10-22 22:28:53 +080022struct altera_timer_regs {
23 u32 status; /* Timer status reg */
24 u32 control; /* Timer control reg */
25 u32 periodl; /* Timeout period low */
26 u32 periodh; /* Timeout period high */
27 u32 snapl; /* Snapshot low */
28 u32 snaph; /* Snapshot high */
29};
30
31struct altera_timer_platdata {
32 struct altera_timer_regs *regs;
Thomas Choua54915d2015-10-22 22:28:53 +080033};
34
Bin Meng9ca07eb2015-11-24 13:31:17 -070035static int altera_timer_get_count(struct udevice *dev, u64 *count)
Thomas Choua54915d2015-10-22 22:28:53 +080036{
37 struct altera_timer_platdata *plat = dev->platdata;
38 struct altera_timer_regs *const regs = plat->regs;
39 u32 val;
40
41 /* Trigger update */
42 writel(0x0, &regs->snapl);
43
44 /* Read timer value */
45 val = readl(&regs->snapl) & 0xffff;
46 val |= (readl(&regs->snaph) & 0xffff) << 16;
Bin Meng9ca07eb2015-11-24 13:31:17 -070047 *count = timer_conv_64(~val);
Thomas Choua54915d2015-10-22 22:28:53 +080048
49 return 0;
50}
51
52static int altera_timer_probe(struct udevice *dev)
53{
Thomas Choua54915d2015-10-22 22:28:53 +080054 struct altera_timer_platdata *plat = dev->platdata;
55 struct altera_timer_regs *const regs = plat->regs;
56
Thomas Choua54915d2015-10-22 22:28:53 +080057 writel(0, &regs->status);
58 writel(0, &regs->control);
59 writel(ALTERA_TIMER_STOP, &regs->control);
60
61 writel(0xffff, &regs->periodl);
62 writel(0xffff, &regs->periodh);
63 writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control);
64
65 return 0;
66}
67
68static int altera_timer_ofdata_to_platdata(struct udevice *dev)
69{
70 struct altera_timer_platdata *plat = dev_get_platdata(dev);
71
Simon Glassa821c4a2017-05-17 17:18:05 -060072 plat->regs = map_physmem(devfdt_get_addr(dev),
Thomas Chou4c26ec12015-11-14 11:15:31 +080073 sizeof(struct altera_timer_regs),
74 MAP_NOCACHE);
Thomas Choua54915d2015-10-22 22:28:53 +080075
76 return 0;
77}
78
79static const struct timer_ops altera_timer_ops = {
80 .get_count = altera_timer_get_count,
81};
82
83static const struct udevice_id altera_timer_ids[] = {
Thomas Chou1235e5a2015-10-31 20:54:16 +080084 { .compatible = "altr,timer-1.0" },
85 {}
Thomas Choua54915d2015-10-22 22:28:53 +080086};
87
88U_BOOT_DRIVER(altera_timer) = {
89 .name = "altera_timer",
90 .id = UCLASS_TIMER,
91 .of_match = altera_timer_ids,
92 .ofdata_to_platdata = altera_timer_ofdata_to_platdata,
93 .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
94 .probe = altera_timer_probe,
95 .ops = &altera_timer_ops,
Thomas Choua54915d2015-10-22 22:28:53 +080096};