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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk945af8d2003-07-16 21:53:01 +00006 */
7
8#include <common.h>
9#include <mpc5xxx.h>
10#include <asm/processor.h>
11
Wolfgang Denkd87080b2006-03-31 18:32:53 +020012DECLARE_GLOBAL_DATA_PTR;
13
wdenk945af8d2003-07-16 21:53:01 +000014/* ------------------------------------------------------------------------- */
15
16/* Bus-to-Core Multipliers */
17
18static int bus2core[] = {
wdenk7cb22f92003-12-27 19:24:54 +000019 3, 2, 2, 2, 4, 4, 5, 9,
20 6, 11, 8, 10, 3, 12, 7, 0,
21 6, 5, 13, 2, 14, 4, 15, 9,
22 0, 11, 8, 10, 16, 12, 7, 0
wdenk945af8d2003-07-16 21:53:01 +000023};
24/* ------------------------------------------------------------------------- */
25
26/*
27 *
28 */
29
30int get_clocks (void)
31{
wdenk945af8d2003-07-16 21:53:01 +000032 ulong val, vco;
33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#if !defined(CONFIG_SYS_MPC5XXX_CLKIN)
35#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN
wdenk945af8d2003-07-16 21:53:01 +000036#endif
37
38 val = *(vu_long *)MPC5XXX_CDM_PORCFG;
39 if (val & (1 << 6)) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 vco = CONFIG_SYS_MPC5XXX_CLKIN * 12;
wdenk945af8d2003-07-16 21:53:01 +000041 } else {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 vco = CONFIG_SYS_MPC5XXX_CLKIN * 16;
wdenk945af8d2003-07-16 21:53:01 +000043 }
44 if (val & (1 << 5)) {
45 gd->bus_clk = vco / 8;
46 } else {
47 gd->bus_clk = vco / 4;
48 }
wdenk7cb22f92003-12-27 19:24:54 +000049 gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2;
wdenk945af8d2003-07-16 21:53:01 +000050
51 val = *(vu_long *)MPC5XXX_CDM_CFG;
52 if (val & (1 << 8)) {
Simon Glassb2877492012-12-13 20:48:53 +000053 gd->arch.ipb_clk = gd->bus_clk / 2;
wdenk945af8d2003-07-16 21:53:01 +000054 } else {
Simon Glassb2877492012-12-13 20:48:53 +000055 gd->arch.ipb_clk = gd->bus_clk;
wdenk945af8d2003-07-16 21:53:01 +000056 }
57 switch (val & 3) {
Simon Glassb2877492012-12-13 20:48:53 +000058 case 0:
59 gd->pci_clk = gd->arch.ipb_clk;
60 break;
61 case 1:
62 gd->pci_clk = gd->arch.ipb_clk / 2;
63 break;
64 default:
65 gd->pci_clk = gd->bus_clk / 4;
66 break;
wdenk945af8d2003-07-16 21:53:01 +000067 }
68
69 return (0);
70}
71
72int prt_mpc5xxx_clks (void)
73{
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020074 char buf1[32], buf2[32], buf3[32];
wdenk945af8d2003-07-16 21:53:01 +000075
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020076 printf (" Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
77 strmhz(buf1, gd->bus_clk),
Simon Glassb2877492012-12-13 20:48:53 +000078 strmhz(buf2, gd->arch.ipb_clk),
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020079 strmhz(buf3, gd->pci_clk)
80 );
wdenk945af8d2003-07-16 21:53:01 +000081 return (0);
82}
83
84/* ------------------------------------------------------------------------- */