| Bharat Gooty | 5a5bba0 | 2021-11-08 14:46:10 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2019-2021 Broadcom. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _BNXT_H_ |
| 7 | #define _BNXT_H_ |
| 8 | |
| 9 | #include <pci.h> |
| 10 | #include <linux/if_ether.h> |
| 11 | |
| 12 | #include "bnxt_hsi.h" |
| 13 | |
| 14 | union dma_addr64_t { |
| 15 | dma_addr_t addr; |
| 16 | u64 as_u64; |
| 17 | }; |
| 18 | |
| 19 | #define DRIVER_VERSION_MAJOR 1 |
| 20 | #define DRIVER_VERSION_MINOR 0 |
| 21 | #define DRIVER_VERSION_UPDATE 0 |
| 22 | |
| 23 | /* Broadcom ethernet driver defines. */ |
| 24 | #define FLAG_SET(f, b) ((f) |= (b)) |
| 25 | #define FLAG_TEST(f, b) ((f) & (b)) |
| 26 | #define FLAG_RESET(f, b) ((f) &= ~(b)) |
| 27 | #define BNXT_FLAG_HWRM_SHORT_CMD_SUPP BIT(0) |
| 28 | #define BNXT_FLAG_HWRM_SHORT_CMD_REQ BIT(1) |
| 29 | #define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT BIT(2) |
| 30 | #define BNXT_FLAG_MULTI_HOST BIT(3) |
| 31 | #define BNXT_FLAG_NPAR_MODE BIT(4) |
| 32 | /******************************************************************************* |
| 33 | * Status codes. |
| 34 | ******************************************************************************/ |
| 35 | #define STATUS_SUCCESS 0 |
| 36 | #define STATUS_FAILURE 1 |
| 37 | #define STATUS_LINK_ACTIVE 4 |
| 38 | #define STATUS_LINK_DOWN 5 |
| 39 | #define STATUS_TIMEOUT 0xffff |
| 40 | /******************************************************************************* |
| 41 | * Receive filter masks. |
| 42 | ******************************************************************************/ |
| 43 | #define RX_MASK_ACCEPT_NONE 0x0000 |
| 44 | #define RX_MASK_ACCEPT_MULTICAST 0x0002 |
| 45 | #define RX_MASK_ACCEPT_ALL_MULTICAST 0x0004 |
| 46 | #define RX_MASK_ACCEPT_BROADCAST 0x0008 |
| 47 | #define RX_MASK_PROMISCUOUS_MODE 0x10000 |
| 48 | /******************************************************************************* |
| 49 | * media speed. |
| 50 | ******************************************************************************/ |
| 51 | #define MEDIUM_SPEED_AUTONEG 0x0000L |
| 52 | #define MEDIUM_SPEED_1000MBPS 0x0300L |
| 53 | #define MEDIUM_SPEED_2500MBPS 0x0400L |
| 54 | #define MEDIUM_SPEED_10GBPS 0x0600L |
| 55 | #define MEDIUM_SPEED_25GBPS 0x0800L |
| 56 | #define MEDIUM_SPEED_40GBPS 0x0900L |
| 57 | #define MEDIUM_SPEED_50GBPS 0x0a00L |
| 58 | #define MEDIUM_SPEED_100GBPS 0x0b00L |
| 59 | #define MEDIUM_SPEED_200GBPS 0x0c00L |
| 60 | #define MEDIUM_SPEED_MASK 0xff00L |
| 61 | #define GET_MEDIUM_SPEED(m) ((m) & MEDIUM_SPEED_MASK) |
| 62 | #define SET_MEDIUM_SPEED(bp, s) (((bp)->medium & ~MEDIUM_SPEED_MASK) | (s)) |
| 63 | #define MEDIUM_UNKNOWN_DUPLEX 0x00000L |
| 64 | #define MEDIUM_FULL_DUPLEX 0x00000L |
| 65 | #define MEDIUM_HALF_DUPLEX 0x10000L |
| 66 | #define GET_MEDIUM_DUPLEX(m) ((m) & MEDIUM_HALF_DUPLEX) |
| 67 | #define SET_MEDIUM_DUPLEX(bp, d) (((bp)->medium & ~MEDIUM_HALF_DUPLEX) | (d)) |
| 68 | #define MEDIUM_SELECTIVE_AUTONEG 0x01000000L |
| 69 | #define GET_MEDIUM_AUTONEG_MODE(m) ((m) & 0xff000000L) |
| 70 | #define GRC_COM_CHAN_BASE 0 |
| 71 | #define GRC_COM_CHAN_TRIG 0x100 |
| 72 | #define HWRM_CMD_DEFAULT_TIMEOUT 500 /* in Miliseconds */ |
| 73 | #define HWRM_CMD_POLL_WAIT_TIME 100 /* In MicroeSconds */ |
| 74 | #define HWRM_CMD_DEFAULT_MULTIPLAYER(a) ((a) * 10) |
| 75 | #define HWRM_CMD_FLASH_MULTIPLAYER(a) ((a) * 100) |
| 76 | #define HWRM_CMD_FLASH_ERASE_MULTIPLAYER(a) ((a) * 1000) |
| 77 | #define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 |
| 78 | #define DEFAULT_NUMBER_OF_CMPL_RINGS 0x01 |
| 79 | #define DEFAULT_NUMBER_OF_TX_RINGS 0x01 |
| 80 | #define DEFAULT_NUMBER_OF_RX_RINGS 0x01 |
| 81 | #define DEFAULT_NUMBER_OF_RING_GRPS 0x01 |
| 82 | #define DEFAULT_NUMBER_OF_STAT_CTXS 0x01 |
| 83 | #define NUM_RX_BUFFERS 512 |
| 84 | #define MAX_RX_DESC_CNT 1024 |
| 85 | #define MAX_TX_DESC_CNT 512 |
| 86 | #define MAX_CQ_DESC_CNT 2048 |
| 87 | #define TX_RING_DMA_BUFFER_SIZE (MAX_TX_DESC_CNT * sizeof(struct tx_bd_short)) |
| 88 | #define RX_RING_DMA_BUFFER_SIZE \ |
| 89 | (MAX_RX_DESC_CNT * sizeof(struct rx_prod_pkt_bd)) |
| 90 | #define CQ_RING_DMA_BUFFER_SIZE (MAX_CQ_DESC_CNT * sizeof(struct cmpl_base)) |
| 91 | #define BNXT_DMA_ALIGNMENT 256 //64 |
| 92 | #define REQ_BUFFER_SIZE 1024 |
| 93 | #define RESP_BUFFER_SIZE 1024 |
| 94 | #define DMA_BUFFER_SIZE 1024 |
| 95 | #define LM_PAGE_BITS 8 |
| 96 | #define BNXT_RX_STD_DMA_SZ 1536 |
| 97 | #define NEXT_IDX(N, S) (((N) + 1) & ((S) - 1)) |
| 98 | #define BD_NOW(bd, entry, len) (&((u8 *)(bd))[(entry) * (len)]) |
| 99 | #define BNXT_CQ_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL |
| 100 | #define BNXT_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL |
| 101 | /* Set default link timeout period to 500 millseconds */ |
| 102 | #define LINK_DEFAULT_TIMEOUT 500 |
| 103 | #define RX_MASK \ |
| 104 | (RX_MASK_ACCEPT_BROADCAST | \ |
| 105 | RX_MASK_ACCEPT_ALL_MULTICAST | \ |
| 106 | RX_MASK_ACCEPT_MULTICAST) |
| 107 | #define TX_RING_QID ((u16)bp->port_idx * 10) |
| 108 | #define RX_RING_QID 0 |
| 109 | #define LM_PAGE_SIZE LM_PAGE_BITS |
| 110 | #define virt_to_bus(a) ((dma_addr_t)(a)) |
| 111 | #define REQ_BUF_SIZE_ALIGNED ALIGN(REQ_BUFFER_SIZE, BNXT_DMA_ALIGNMENT) |
| 112 | #define RESP_BUF_SIZE_ALIGNED ALIGN(RESP_BUFFER_SIZE, BNXT_DMA_ALIGNMENT) |
| 113 | #define DMA_BUF_SIZE_ALIGNED ALIGN(DMA_BUFFER_SIZE, BNXT_DMA_ALIGNMENT) |
| 114 | #define RX_STD_DMA_ALIGNED ALIGN(BNXT_RX_STD_DMA_SZ, BNXT_DMA_ALIGNMENT) |
| 115 | #define PCI_COMMAND_INTX_DISABLE 0x0400 /* Interrupt disable */ |
| 116 | #define TX_AVAIL(r) ((r) - 1) |
| 117 | #define NO_MORE_CQ_BD_TO_SERVICE 1 |
| 118 | #define SERVICE_NEXT_CQ_BD 0 |
| 119 | #define PHY_STATUS 0x0001 |
| 120 | #define PHY_SPEED 0x0002 |
| 121 | #define DETECT_MEDIA 0x0004 |
| 122 | #define SUPPORT_SPEEDS 0x0008 |
| 123 | #define str_1 "1" |
| 124 | #define str_2 "2" |
| 125 | #define str_2_5 "2.5" |
| 126 | #define str_10 "10" |
| 127 | #define str_20 "20" |
| 128 | #define str_25 "25" |
| 129 | #define str_40 "40" |
| 130 | #define str_50 "50" |
| 131 | #define str_100 "100" |
| 132 | #define str_gbps "Gbps" |
| 133 | #define str_mbps "Mbps" |
| 134 | #define str_unknown "Unknown" |
| 135 | /* Broadcom ethernet driver nvm defines. */ |
| 136 | /* nvm cfg 1 - MAC settings */ |
| 137 | #define FUNC_MAC_ADDR_NUM 1 |
| 138 | /* nvm cfg 203 - u32 link_settings */ |
| 139 | #define LINK_SPEED_DRV_NUM 203 |
| 140 | #define LINK_SPEED_DRV_MASK 0x0000000F |
| 141 | #define LINK_SPEED_DRV_SHIFT 0 |
| 142 | #define LINK_SPEED_DRV_AUTONEG 0x0 |
| 143 | #define LINK_SPEED_DRV_1G 0x1 |
| 144 | #define LINK_SPEED_DRV_10G 0x2 |
| 145 | #define LINK_SPEED_DRV_25G 0x3 |
| 146 | #define LINK_SPEED_DRV_40G 0x4 |
| 147 | #define LINK_SPEED_DRV_50G 0x5 |
| 148 | #define LINK_SPEED_DRV_100G 0x6 |
| 149 | #define LINK_SPEED_DRV_200G 0x7 |
| 150 | #define LINK_SPEED_DRV_2_5G 0xE |
| 151 | #define LINK_SPEED_DRV_100M 0xF |
| 152 | /* nvm cfg 201 - u32 speed_cap_mask */ |
| 153 | #define SPEED_CAPABILITY_DRV_1G 0x1 |
| 154 | #define SPEED_CAPABILITY_DRV_10G 0x2 |
| 155 | #define SPEED_CAPABILITY_DRV_25G 0x4 |
| 156 | #define SPEED_CAPABILITY_DRV_40G 0x8 |
| 157 | #define SPEED_CAPABILITY_DRV_50G 0x10 |
| 158 | #define SPEED_CAPABILITY_DRV_100G 0x20 |
| 159 | #define SPEED_CAPABILITY_DRV_100M 0x8000 |
| 160 | /* nvm cfg 202 */ |
| 161 | /* nvm cfg 205 */ |
| 162 | #define LINK_SPEED_FW_NUM 205 |
| 163 | /* nvm cfg 210 */ |
| 164 | /* nvm cfg 211 */ |
| 165 | /* nvm cfg 213 */ |
| 166 | #define SPEED_DRV_MASK LINK_SPEED_DRV_MASK |
| 167 | /****************************************************************************** |
| 168 | * Doorbell info. |
| 169 | *****************************************************************************/ |
| 170 | #define RX_DOORBELL_KEY_RX (0x1UL << 28) |
| 171 | #define TX_DOORBELL_KEY_TX (0x0UL << 28) |
| 172 | |
| 173 | #define CMPL_DOORBELL_IDX_VALID 0x4000000UL |
| 174 | #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) |
| 175 | |
| 176 | /****************************************************************************** |
| 177 | * Transmit info. |
| 178 | *****************************************************************************/ |
| 179 | struct tx_bd_short { |
| 180 | u16 flags_type; |
| 181 | #define TX_BD_SHORT_TYPE_TX_BD_SHORT 0x0UL |
| 182 | #define TX_BD_SHORT_FLAGS_PACKET_END 0x40UL |
| 183 | #define TX_BD_SHORT_FLAGS_NO_CMPL 0x80UL |
| 184 | #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8 |
| 185 | #define TX_BD_SHORT_FLAGS_LHINT_LT512 (0x0UL << 13) |
| 186 | #define TX_BD_SHORT_FLAGS_LHINT_LT1K (0x1UL << 13) |
| 187 | #define TX_BD_SHORT_FLAGS_LHINT_LT2K (0x2UL << 13) |
| 188 | #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (0x3UL << 13) |
| 189 | #define TX_BD_SHORT_FLAGS_COAL_NOW 0x8000UL |
| 190 | u16 len; |
| 191 | u32 opaque; |
| 192 | union dma_addr64_t dma; |
| 193 | }; |
| 194 | |
| 195 | struct lm_tx_info_t { |
| 196 | void *bd_virt; |
| 197 | u16 prod_id; /* Tx producer index. */ |
| 198 | u16 cons_id; |
| 199 | u16 ring_cnt; |
| 200 | u32 cnt; /* Tx statistics. */ |
| 201 | u32 cnt_req; |
| 202 | }; |
| 203 | |
| 204 | struct cmpl_base { |
| 205 | u16 type; |
| 206 | #define CMPL_BASE_TYPE_MASK 0x3fUL |
| 207 | #define CMPL_BASE_TYPE_TX_L2 0x0UL |
| 208 | #define CMPL_BASE_TYPE_RX_L2 0x11UL |
| 209 | #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL |
| 210 | #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL |
| 211 | u16 info1; |
| 212 | u32 info2; |
| 213 | u32 info3_v; |
| 214 | #define CMPL_BASE_V 0x1UL |
| 215 | u32 info4; |
| 216 | }; |
| 217 | |
| 218 | struct lm_cmp_info_t { |
| 219 | void *bd_virt; |
| 220 | u16 cons_idx; |
| 221 | u16 ring_cnt; |
| 222 | u8 completion_bit; |
| 223 | u8 res[3]; |
| 224 | }; |
| 225 | |
| 226 | struct rx_pkt_cmpl { |
| 227 | u16 flags_type; |
| 228 | u16 len; |
| 229 | u32 opaque; |
| 230 | u8 agg_bufs_v1; |
| 231 | u8 rss_hash_type; |
| 232 | u8 payload_offset; |
| 233 | u8 unused1; |
| 234 | u32 rss_hash; |
| 235 | }; |
| 236 | |
| 237 | struct rx_pkt_cmpl_hi { |
| 238 | u32 flags2; |
| 239 | u32 metadata; |
| 240 | u16 errors_v2; |
| 241 | #define RX_PKT_CMPL_V2 0x1UL |
| 242 | #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 |
| 243 | u16 cfa_code; |
| 244 | u32 reorder; |
| 245 | }; |
| 246 | |
| 247 | struct rx_prod_pkt_bd { |
| 248 | u16 flags_type; |
| 249 | #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT 0x4UL |
| 250 | u16 len; |
| 251 | u32 opaque; |
| 252 | union dma_addr64_t dma; |
| 253 | }; |
| 254 | |
| 255 | struct lm_rx_info_t { |
| 256 | void *bd_virt; |
| 257 | void *iob[NUM_RX_BUFFERS]; |
| 258 | void *iob_rx; |
| 259 | u16 iob_len; |
| 260 | u16 iob_recv; |
| 261 | u16 iob_cnt; |
| 262 | u16 buf_cnt; /* Total Rx buffer descriptors. */ |
| 263 | u16 ring_cnt; |
| 264 | u16 cons_idx; /* Last processed consumer index. */ |
| 265 | u32 rx_cnt; |
| 266 | u32 rx_buf_cnt; |
| 267 | u32 err; |
| 268 | u32 crc; |
| 269 | u32 dropped; |
| 270 | }; |
| 271 | |
| 272 | #define VALID_DRIVER_REG 0x0001 |
| 273 | #define VALID_STAT_CTX 0x0002 |
| 274 | #define VALID_RING_CQ 0x0004 |
| 275 | #define VALID_RING_TX 0x0008 |
| 276 | #define VALID_RING_RX 0x0010 |
| 277 | #define VALID_RING_GRP 0x0020 |
| 278 | #define VALID_VNIC_ID 0x0040 |
| 279 | #define VALID_RX_IOB 0x0080 |
| 280 | #define VALID_L2_FILTER 0x0100 |
| 281 | |
| 282 | enum RX_FLAGS { |
| 283 | PKT_DONE = 0, |
| 284 | PKT_RECEIVED = 1, |
| 285 | PKT_DROPPED = 2, |
| 286 | }; |
| 287 | |
| 288 | struct bnxt { |
| 289 | struct udevice *pdev; |
| 290 | const char *name; |
| 291 | unsigned int cardnum; |
| 292 | void *hwrm_addr_req; |
| 293 | void *hwrm_addr_resp; |
| 294 | void *hwrm_addr_data; |
| 295 | dma_addr_t data_addr_mapping; |
| 296 | dma_addr_t req_addr_mapping; |
| 297 | dma_addr_t resp_addr_mapping; |
| 298 | struct lm_tx_info_t tx; /* Tx info. */ |
| 299 | struct lm_rx_info_t rx; /* Rx info. */ |
| 300 | struct lm_cmp_info_t cq; /* completion info. */ |
| 301 | u16 last_resp_code; |
| 302 | u16 seq_id; |
| 303 | u32 flag_hwrm; |
| 304 | u32 flags; |
| 305 | u16 vendor_id; |
| 306 | u16 device_id; |
| 307 | u16 subsystem_vendor; |
| 308 | u16 subsystem_device; |
| 309 | u16 cmd_reg; |
| 310 | u8 irq; |
| 311 | void __iomem *bar0; |
| 312 | void __iomem *bar1; |
| 313 | void __iomem *bar2; |
| 314 | u16 chip_num; |
| 315 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
| 316 | u32 chip_id; |
| 317 | u32 hwrm_cmd_timeout; |
| 318 | u16 hwrm_spec_code; |
| 319 | u16 hwrm_max_req_len; |
| 320 | u16 hwrm_max_ext_req_len; |
| 321 | u8 fw_maj; |
| 322 | u8 fw_min; |
| 323 | u8 fw_bld; |
| 324 | u8 fw_rsvd; |
| 325 | u8 mac_addr[ETH_ALEN]; /* HW MAC address */ |
| 326 | u8 mac_set[ETH_ALEN]; /* NVM Configured MAC */ |
| 327 | u16 fid; |
| 328 | u8 port_idx; |
| 329 | u8 ordinal_value; |
| 330 | u16 mtu; |
| 331 | u16 ring_grp_id; |
| 332 | u16 cq_ring_id; |
| 333 | u16 tx_ring_id; |
| 334 | u16 rx_ring_id; |
| 335 | u16 current_link_speed; |
| 336 | u16 link_status; |
| 337 | u16 wait_link_timeout; |
| 338 | u64 l2_filter_id; |
| 339 | u16 vnic_id; |
| 340 | u16 stat_ctx_id; |
| 341 | u32 medium; |
| 342 | u16 support_speeds; |
| 343 | u32 link_set; |
| 344 | u8 media_detect; |
| 345 | u8 media_change; |
| 346 | u16 max_vfs; |
| 347 | u16 vf_res_strategy; |
| 348 | u16 min_vnics; |
| 349 | u16 max_vnics; |
| 350 | u16 max_msix; |
| 351 | u16 min_hw_ring_grps; |
| 352 | u16 max_hw_ring_grps; |
| 353 | u16 min_tx_rings; |
| 354 | u16 max_tx_rings; |
| 355 | u16 min_rx_rings; |
| 356 | u16 max_rx_rings; |
| 357 | u16 min_cp_rings; |
| 358 | u16 max_cp_rings; |
| 359 | u16 min_rsscos_ctxs; |
| 360 | u16 max_rsscos_ctxs; |
| 361 | u16 min_l2_ctxs; |
| 362 | u16 max_l2_ctxs; |
| 363 | u16 min_stat_ctxs; |
| 364 | u16 max_stat_ctxs; |
| 365 | u16 num_cmpl_rings; |
| 366 | u16 num_tx_rings; |
| 367 | u16 num_rx_rings; |
| 368 | u16 num_stat_ctxs; |
| 369 | u16 num_hw_ring_grps; |
| 370 | bool card_en; |
| 371 | }; |
| 372 | |
| 373 | #define SHORT_CMD_SUPPORTED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED |
| 374 | #define SHORT_CMD_REQUIRED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED |
| 375 | #define CQ_DOORBELL_KEY_IDX(a) \ |
| 376 | (CMPL_DOORBELL_KEY_CMPL | \ |
| 377 | CMPL_DOORBELL_IDX_VALID | \ |
| 378 | (u32)(a)) |
| 379 | #define TX_BD_FLAGS \ |
| 380 | (TX_BD_SHORT_TYPE_TX_BD_SHORT | \ |
| 381 | TX_BD_SHORT_FLAGS_NO_CMPL | \ |
| 382 | TX_BD_SHORT_FLAGS_COAL_NOW | \ |
| 383 | TX_BD_SHORT_FLAGS_PACKET_END | \ |
| 384 | (1 << TX_BD_SHORT_FLAGS_BD_CNT_SFT)) |
| 385 | #define MEM_HWRM_RESP memalign(BNXT_DMA_ALIGNMENT, RESP_BUF_SIZE_ALIGNED) |
| 386 | #define PORT_PHY_FLAGS (BNXT_FLAG_NPAR_MODE | BNXT_FLAG_MULTI_HOST) |
| 387 | #define RING_FREE(bp, rid, flag) bnxt_hwrm_ring_free(bp, rid, flag) |
| 388 | #define QCFG_PHY_ALL (SUPPORT_SPEEDS | DETECT_MEDIA | PHY_SPEED | PHY_STATUS) |
| 389 | |
| 390 | #endif /* _BNXT_H_ */ |