| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 1 | CONFIG_MIPS=y |
| 2 | CONFIG_SYS_TEXT_BASE=0xffffffff80000000 |
| Tom Rini | 9802154 | 2021-11-01 12:19:22 +0000 | [diff] [blame] | 3 | CONFIG_SYS_MALLOC_LEN=0x1000000 |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 4 | CONFIG_SYS_MALLOC_F_LEN=0x4000 |
| 5 | CONFIG_NR_DRAM_BANKS=2 |
| 6 | CONFIG_ENV_SIZE=0x2000 |
| 7 | CONFIG_ENV_OFFSET=0xe000 |
| 8 | CONFIG_ENV_SECT_SIZE=0x100 |
| 9 | CONFIG_DEBUG_UART_BASE=0x8001180000000800 |
| 10 | CONFIG_DEBUG_UART_CLOCK=800000000 |
| Tom Rini | d46e86d | 2022-04-08 13:36:51 -0400 | [diff] [blame] | 11 | CONFIG_SYS_LOAD_ADDR=0xffffffff80100000 |
| 12 | CONFIG_ENV_ADDR=0xe000 |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 13 | CONFIG_ARCH_OCTEON=y |
| 14 | CONFIG_TARGET_OCTEON_NIC23=y |
| 15 | # CONFIG_MIPS_CACHE_SETUP is not set |
| 16 | # CONFIG_MIPS_CACHE_DISABLE is not set |
| Stefan Roese | 1770808 | 2022-04-07 09:11:54 +0200 | [diff] [blame] | 17 | CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000 |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 18 | CONFIG_DEBUG_UART=y |
| 19 | CONFIG_AHCI=y |
| 20 | CONFIG_OF_BOARD_FIXUP=y |
| 21 | CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y |
| 22 | # CONFIG_SYS_DEVICE_NULLDEV is not set |
| Aaron Williams | 5ee0fa7 | 2022-09-02 13:57:52 +0200 | [diff] [blame] | 23 | CONFIG_CYCLIC=y |
| 24 | CONFIG_CYCLIC_MAX_CPU_TIME_US=5000 |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 25 | CONFIG_ARCH_MISC_INIT=y |
| Stefan Roese | 1770808 | 2022-04-07 09:11:54 +0200 | [diff] [blame] | 26 | CONFIG_BOARD_EARLY_INIT_F=y |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 27 | CONFIG_BOARD_LATE_INIT=y |
| Stefan Roese | 1770808 | 2022-04-07 09:11:54 +0200 | [diff] [blame] | 28 | CONFIG_LAST_STAGE_INIT=y |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 29 | CONFIG_HUSH_PARSER=y |
| Tom Rini | d31466b | 2022-05-11 18:01:06 -0400 | [diff] [blame] | 30 | CONFIG_SYS_CBSIZE=256 |
| Tom Rini | d0ee7f2 | 2022-05-11 17:38:09 -0400 | [diff] [blame] | 31 | CONFIG_SYS_PBSIZE=276 |
| Tom Rini | c45568c | 2022-06-25 19:29:46 -0400 | [diff] [blame] | 32 | CONFIG_SYS_BOOTM_LEN=0x4000000 |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 33 | # CONFIG_CMD_FLASH is not set |
| 34 | CONFIG_CMD_GPIO=y |
| 35 | CONFIG_CMD_I2C=y |
| 36 | CONFIG_CMD_MMC=y |
| 37 | CONFIG_CMD_MTD=y |
| 38 | CONFIG_CMD_PART=y |
| 39 | CONFIG_CMD_PCI=y |
| 40 | CONFIG_CMD_DHCP=y |
| 41 | CONFIG_CMD_PING=y |
| 42 | CONFIG_CMD_TIME=y |
| 43 | CONFIG_CMD_EXT4=y |
| 44 | CONFIG_CMD_FAT=y |
| 45 | CONFIG_CMD_FS_GENERIC=y |
| 46 | CONFIG_EFI_PARTITION=y |
| 47 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| Stefan Roese | 1770808 | 2022-04-07 09:11:54 +0200 | [diff] [blame] | 48 | CONFIG_TFTP_TSIZE=y |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 49 | CONFIG_SATA=y |
| 50 | CONFIG_AHCI_MVEBU=y |
| Tom Rini | aca1f67 | 2022-06-10 22:59:28 -0400 | [diff] [blame] | 51 | CONFIG_LBA48=y |
| 52 | CONFIG_SYS_64BIT_LBA=y |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 53 | CONFIG_CLK=y |
| 54 | # CONFIG_INPUT is not set |
| 55 | CONFIG_MISC=y |
| 56 | CONFIG_MMC=y |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 57 | CONFIG_MMC_OCTEONTX=y |
| 58 | CONFIG_MTD=y |
| 59 | CONFIG_DM_MTD=y |
| 60 | CONFIG_DM_SPI_FLASH=y |
| 61 | CONFIG_SPI_FLASH_ATMEL=y |
| 62 | CONFIG_SPI_FLASH_SPANSION=y |
| 63 | CONFIG_SPI_FLASH_STMICRO=y |
| Stefan Roese | 1770808 | 2022-04-07 09:11:54 +0200 | [diff] [blame] | 64 | CONFIG_PHYLIB=y |
| 65 | CONFIG_PHYLIB_10G=y |
| 66 | CONFIG_DM_MDIO=y |
| 67 | CONFIG_DM_ETH_PHY=y |
| 68 | CONFIG_NET_OCTEON=y |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 69 | CONFIG_PCI=y |
| Stefan Roese | ec85347 | 2021-04-07 09:12:38 +0200 | [diff] [blame] | 70 | CONFIG_DM_REGULATOR=y |
| 71 | CONFIG_DM_REGULATOR_FIXED=y |
| 72 | CONFIG_RAM=y |
| 73 | CONFIG_RAM_OCTEON=y |
| 74 | CONFIG_RAM_OCTEON_DDR4=y |
| 75 | CONFIG_SCSI=y |
| 76 | CONFIG_DEBUG_UART_SHIFT=3 |
| 77 | CONFIG_DEBUG_UART_ANNOUNCE=y |
| 78 | CONFIG_SYS_NS16550=y |
| 79 | CONFIG_OCTEON_SERIAL_BOOTCMD=y |
| 80 | CONFIG_OCTEON_SERIAL_PCIE_CONSOLE=y |
| 81 | CONFIG_SPI=y |
| 82 | CONFIG_OCTEON_SPI=y |
| 83 | CONFIG_SYSRESET=y |
| 84 | CONFIG_SYSRESET_OCTEON=y |
| 85 | CONFIG_HEXDUMP=y |