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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <commproc.h>
27#include <net.h>
28#include <command.h>
29
Wolfgang Denkd87080b2006-03-31 18:32:53 +020030DECLARE_GLOBAL_DATA_PTR;
31
wdenkc6097192002-11-03 00:24:07 +000032#undef ET_DEBUG
33
Jon Loeliger44312832007-07-09 19:06:00 -050034#if defined(CONFIG_CMD_NET) && \
wdenka6ab4bf2004-04-15 21:31:56 +000035 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
36
37/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
38#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
39#define CONFIG_ETHER_ON_FEC1 1
40#endif
41
42/* define WANT_MII when MII support is required */
43#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
44#define WANT_MII
45#else
46#undef WANT_MII
47#endif
48
49#if defined(WANT_MII)
50#include <miiphy.h>
Marian Balakowicz63ff0042005-10-28 22:30:33 +020051
Jon Loeliger44312832007-07-09 19:06:00 -050052#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
Marian Balakowicz63ff0042005-10-28 22:30:33 +020053#error "CONFIG_MII has to be defined!"
54#endif
55
wdenka6ab4bf2004-04-15 21:31:56 +000056#endif
57
58#if defined(CONFIG_RMII) && !defined(WANT_MII)
59#error RMII support is unusable without a working PHY.
60#endif
wdenkc6097192002-11-03 00:24:07 +000061
62#ifdef CFG_DISCOVER_PHY
wdenka6ab4bf2004-04-15 21:31:56 +000063static int mii_discover_phy(struct eth_device *dev);
wdenkc6097192002-11-03 00:24:07 +000064#endif
65
Marian Balakowicz63ff0042005-10-28 22:30:33 +020066int fec8xx_miiphy_read(char *devname, unsigned char addr,
67 unsigned char reg, unsigned short *value);
68int fec8xx_miiphy_write(char *devname, unsigned char addr,
69 unsigned char reg, unsigned short value);
70
wdenka6ab4bf2004-04-15 21:31:56 +000071static struct ether_fcc_info_s
72{
73 int ether_index;
74 int fecp_offset;
wdenka6ab4bf2004-04-15 21:31:56 +000075 int phy_addr;
76 int actual_phy_addr;
wdenkc26e4542004-04-18 10:13:26 +000077 int initialized;
wdenka6ab4bf2004-04-15 21:31:56 +000078}
79 ether_fcc_info[] = {
80#if defined(CONFIG_ETHER_ON_FEC1)
81 {
82 0,
83 offsetof(immap_t, im_cpm.cp_fec1),
wdenka6ab4bf2004-04-15 21:31:56 +000084#if defined(CONFIG_FEC1_PHY)
85 CONFIG_FEC1_PHY,
86#else
87 -1, /* discover */
88#endif
89 -1,
wdenkc26e4542004-04-18 10:13:26 +000090 0,
wdenka6ab4bf2004-04-15 21:31:56 +000091
92 },
93#endif
94#if defined(CONFIG_ETHER_ON_FEC2)
95 {
96 1,
97 offsetof(immap_t, im_cpm.cp_fec2),
wdenka6ab4bf2004-04-15 21:31:56 +000098#if defined(CONFIG_FEC2_PHY)
99 CONFIG_FEC2_PHY,
100#else
101 -1,
102#endif
103 -1,
wdenkc26e4542004-04-18 10:13:26 +0000104 0,
wdenka6ab4bf2004-04-15 21:31:56 +0000105 },
106#endif
107};
108
wdenkc6097192002-11-03 00:24:07 +0000109/* Ethernet Transmit and Receive Buffers */
110#define DBUF_LENGTH 1520
111
112#define TX_BUF_CNT 2
113
114#define TOUT_LOOP 100
115
116#define PKT_MAXBUF_SIZE 1518
117#define PKT_MINBUF_SIZE 64
118#define PKT_MAXBLR_SIZE 1520
119
wdenka6ab4bf2004-04-15 21:31:56 +0000120#ifdef __GNUC__
121static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
122#else
123#error txbuf must be aligned.
124#endif
wdenkc6097192002-11-03 00:24:07 +0000125
126static uint rxIdx; /* index of the current RX buffer */
127static uint txIdx; /* index of the current TX buffer */
128
129/*
130 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
131 * immr->udata_bd address on Dual-Port RAM
132 * Provide for Double Buffering
133 */
134
135typedef volatile struct CommonBufferDescriptor {
136 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
137 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
138} RTXBD;
139
140static RTXBD *rtx = NULL;
141
142static int fec_send(struct eth_device* dev, volatile void *packet, int length);
143static int fec_recv(struct eth_device* dev);
144static int fec_init(struct eth_device* dev, bd_t * bd);
145static void fec_halt(struct eth_device* dev);
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100146static void __mii_init(void);
wdenkc6097192002-11-03 00:24:07 +0000147
148int fec_initialize(bd_t *bis)
149{
150 struct eth_device* dev;
wdenka6ab4bf2004-04-15 21:31:56 +0000151 struct ether_fcc_info_s *efis;
152 int i;
wdenkc6097192002-11-03 00:24:07 +0000153
wdenka6ab4bf2004-04-15 21:31:56 +0000154 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
wdenkc6097192002-11-03 00:24:07 +0000155
wdenka6ab4bf2004-04-15 21:31:56 +0000156 dev = malloc(sizeof(*dev));
157 if (dev == NULL)
158 hang();
wdenkc6097192002-11-03 00:24:07 +0000159
wdenka6ab4bf2004-04-15 21:31:56 +0000160 memset(dev, 0, sizeof(*dev));
wdenkc6097192002-11-03 00:24:07 +0000161
wdenka6ab4bf2004-04-15 21:31:56 +0000162 /* for FEC1 make sure that the name of the interface is the same
163 as the old one for compatibility reasons */
164 if (i == 0) {
165 sprintf (dev->name, "FEC ETHERNET");
166 } else {
167 sprintf (dev->name, "FEC%d ETHERNET",
168 ether_fcc_info[i].ether_index + 1);
169 }
170
171 efis = &ether_fcc_info[i];
172
173 /*
174 * reset actual phy addr
175 */
176 efis->actual_phy_addr = -1;
177
178 dev->priv = efis;
179 dev->init = fec_init;
180 dev->halt = fec_halt;
181 dev->send = fec_send;
182 dev->recv = fec_recv;
183
184 eth_register(dev);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200185
Jon Loeliger44312832007-07-09 19:06:00 -0500186#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200187 miiphy_register(dev->name,
188 fec8xx_miiphy_read, fec8xx_miiphy_write);
189#endif
wdenka6ab4bf2004-04-15 21:31:56 +0000190 }
wdenkc6097192002-11-03 00:24:07 +0000191 return 1;
192}
193
194static int fec_send(struct eth_device* dev, volatile void *packet, int length)
195{
196 int j, rc;
wdenka6ab4bf2004-04-15 21:31:56 +0000197 struct ether_fcc_info_s *efis = dev->priv;
198 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
wdenkc6097192002-11-03 00:24:07 +0000199
200 /* section 16.9.23.3
201 * Wait for ready
202 */
203 j = 0;
204 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
205 udelay(1);
206 j++;
207 }
208 if (j>=TOUT_LOOP) {
209 printf("TX not ready\n");
210 }
211
212 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
213 rtx->txbd[txIdx].cbd_datlen = length;
214 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
215 __asm__ ("eieio");
216
217 /* Activate transmit Buffer Descriptor polling */
218 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
219
220 j = 0;
221 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
222#if defined(CONFIG_ICU862)
223 udelay(10);
224#else
225 udelay(1);
226#endif
227 j++;
228 }
229 if (j>=TOUT_LOOP) {
230 printf("TX timeout\n");
231 }
232#ifdef ET_DEBUG
233 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
234 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
235 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
236#endif
237 /* return only status bits */;
238 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
239
240 txIdx = (txIdx + 1) % TX_BUF_CNT;
241
242 return rc;
243}
244
wdenka6ab4bf2004-04-15 21:31:56 +0000245static int fec_recv (struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000246{
wdenka6ab4bf2004-04-15 21:31:56 +0000247 struct ether_fcc_info_s *efis = dev->priv;
248 volatile fec_t *fecp =
249 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
wdenkc6097192002-11-03 00:24:07 +0000250 int length;
wdenkc6097192002-11-03 00:24:07 +0000251
wdenka6ab4bf2004-04-15 21:31:56 +0000252 for (;;) {
253 /* section 16.9.23.2 */
254 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
255 length = -1;
256 break; /* nothing received - leave for() loop */
257 }
wdenkc6097192002-11-03 00:24:07 +0000258
wdenka6ab4bf2004-04-15 21:31:56 +0000259 length = rtx->rxbd[rxIdx].cbd_datlen;
wdenkc6097192002-11-03 00:24:07 +0000260
wdenka6ab4bf2004-04-15 21:31:56 +0000261 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
wdenkc6097192002-11-03 00:24:07 +0000262#ifdef ET_DEBUG
wdenka6ab4bf2004-04-15 21:31:56 +0000263 printf ("%s[%d] err: %x\n",
264 __FUNCTION__, __LINE__,
265 rtx->rxbd[rxIdx].cbd_sc);
wdenkc6097192002-11-03 00:24:07 +0000266#endif
wdenka6ab4bf2004-04-15 21:31:56 +0000267 } else {
268 volatile uchar *rx = NetRxPackets[rxIdx];
269
270 length -= 4;
271
Jon Loeliger44312832007-07-09 19:06:00 -0500272#if defined(CONFIG_CMD_CDP)
wdenka6ab4bf2004-04-15 21:31:56 +0000273 if ((rx[0] & 1) != 0
274 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
275 && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
276 rx = NULL;
277#endif
278 /*
279 * Pass the packet up to the protocol layers.
280 */
281 if (rx != NULL)
282 NetReceive (rx, length);
283 }
284
285 /* Give the buffer back to the FEC. */
286 rtx->rxbd[rxIdx].cbd_datlen = 0;
287
288 /* wrap around buffer index when necessary */
289 if ((rxIdx + 1) >= PKTBUFSRX) {
290 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
291 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
292 rxIdx = 0;
293 } else {
294 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
295 rxIdx++;
296 }
297
298 __asm__ ("eieio");
299
300 /* Try to fill Buffer Descriptors */
301 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
wdenkc6097192002-11-03 00:24:07 +0000302 }
303
wdenka6ab4bf2004-04-15 21:31:56 +0000304 return length;
wdenkc6097192002-11-03 00:24:07 +0000305}
306
307/**************************************************************
308 *
309 * FEC Ethernet Initialization Routine
310 *
311 *************************************************************/
312
313#define FEC_ECNTRL_PINMUX 0x00000004
314#define FEC_ECNTRL_ETHER_EN 0x00000002
315#define FEC_ECNTRL_RESET 0x00000001
316
317#define FEC_RCNTRL_BC_REJ 0x00000010
318#define FEC_RCNTRL_PROM 0x00000008
319#define FEC_RCNTRL_MII_MODE 0x00000004
320#define FEC_RCNTRL_DRT 0x00000002
321#define FEC_RCNTRL_LOOP 0x00000001
322
323#define FEC_TCNTRL_FDEN 0x00000004
324#define FEC_TCNTRL_HBC 0x00000002
325#define FEC_TCNTRL_GTS 0x00000001
326
327#define FEC_RESET_DELAY 50
328
wdenka6ab4bf2004-04-15 21:31:56 +0000329#if defined(CONFIG_RMII)
330
331static inline void fec_10Mbps(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000332{
wdenka6ab4bf2004-04-15 21:31:56 +0000333 struct ether_fcc_info_s *efis = dev->priv;
334 int fecidx = efis->ether_index;
335 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
wdenkc6097192002-11-03 00:24:07 +0000336
wdenka6ab4bf2004-04-15 21:31:56 +0000337 if ((unsigned int)fecidx >= 2)
338 hang();
339
340 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask;
341}
342
343static inline void fec_100Mbps(struct eth_device *dev)
344{
345 struct ether_fcc_info_s *efis = dev->priv;
346 int fecidx = efis->ether_index;
347 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
348
349 if ((unsigned int)fecidx >= 2)
350 hang();
351
352 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask;
353}
354
355#endif
356
357static inline void fec_full_duplex(struct eth_device *dev)
358{
359 struct ether_fcc_info_s *efis = dev->priv;
360 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
361
362 fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
363 fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
364}
365
366static inline void fec_half_duplex(struct eth_device *dev)
367{
368 struct ether_fcc_info_s *efis = dev->priv;
369 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
370
371 fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
372 fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
373}
374
375static void fec_pin_init(int fecidx)
376{
wdenka6ab4bf2004-04-15 21:31:56 +0000377 bd_t *bd = gd->bd;
wdenkc6097192002-11-03 00:24:07 +0000378 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenka6ab4bf2004-04-15 21:31:56 +0000379 volatile fec_t *fecp;
wdenkc6097192002-11-03 00:24:07 +0000380
wdenka6ab4bf2004-04-15 21:31:56 +0000381 /*
382 * only two FECs please
wdenkc6097192002-11-03 00:24:07 +0000383 */
wdenka6ab4bf2004-04-15 21:31:56 +0000384 if ((unsigned int)fecidx >= 2)
385 hang();
wdenkc6097192002-11-03 00:24:07 +0000386
wdenka6ab4bf2004-04-15 21:31:56 +0000387 if (fecidx == 0)
388 fecp = &immr->im_cpm.cp_fec1;
389 else
390 fecp = &immr->im_cpm.cp_fec2;
391
392 /*
393 * Set MII speed to 2.5 MHz or slightly below.
394 * * According to the MPC860T (Rev. D) Fast ethernet controller user
395 * * manual (6.2.14),
396 * * the MII management interface clock must be less than or equal
397 * * to 2.5 MHz.
398 * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
399 * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
Markus Klotzbuecherd6cc73e2006-07-12 09:08:36 +0200400 *
401 * All MII configuration is done via FEC1 registers:
wdenka6ab4bf2004-04-15 21:31:56 +0000402 */
Markus Klotzbuecherd6cc73e2006-07-12 09:08:36 +0200403 immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
wdenka6ab4bf2004-04-15 21:31:56 +0000404
wdenk79fa88f2004-06-07 23:46:25 +0000405#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
wdenkc26e4542004-04-18 10:13:26 +0000406 /* our PHYs are the limit at 2.5 MHz */
407 fecp->fec_mii_speed <<= 1;
408#endif
409
wdenk11142572004-06-06 21:35:06 +0000410#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
wdenka6ab4bf2004-04-15 21:31:56 +0000411 /* use MDC for MII */
412 immr->im_ioport.iop_pdpar |= 0x0080;
413 immr->im_ioport.iop_pddir &= ~0x0080;
414#endif
415
416 if (fecidx == 0) {
417#if defined(CONFIG_ETHER_ON_FEC1)
418
wdenk11142572004-06-06 21:35:06 +0000419#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
wdenka6ab4bf2004-04-15 21:31:56 +0000420
421#if !defined(CONFIG_RMII)
422
423 immr->im_ioport.iop_papar |= 0xf830;
424 immr->im_ioport.iop_padir |= 0x0830;
425 immr->im_ioport.iop_padir &= ~0xf000;
426
427 immr->im_cpm.cp_pbpar |= 0x00001001;
428 immr->im_cpm.cp_pbdir &= ~0x00001001;
429
430 immr->im_ioport.iop_pcpar |= 0x000c;
431 immr->im_ioport.iop_pcdir &= ~0x000c;
432
433 immr->im_cpm.cp_pepar |= 0x00000003;
434 immr->im_cpm.cp_pedir |= 0x00000003;
435 immr->im_cpm.cp_peso &= ~0x00000003;
436
437 immr->im_cpm.cp_cptr &= ~0x00000100;
438
439#else
440
441#if !defined(CONFIG_FEC1_PHY_NORXERR)
442 immr->im_ioport.iop_papar |= 0x1000;
443 immr->im_ioport.iop_padir &= ~0x1000;
444#endif
445 immr->im_ioport.iop_papar |= 0xe810;
446 immr->im_ioport.iop_padir |= 0x0810;
447 immr->im_ioport.iop_padir &= ~0xe000;
448
449 immr->im_cpm.cp_pbpar |= 0x00000001;
450 immr->im_cpm.cp_pbdir &= ~0x00000001;
451
452 immr->im_cpm.cp_cptr |= 0x00000100;
453 immr->im_cpm.cp_cptr &= ~0x00000050;
454
455#endif /* !CONFIG_RMII */
456
457#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
458 /*
459 * Configure all of port D for MII.
460 */
461 immr->im_ioport.iop_pdpar = 0x1fff;
462
463 /*
464 * Bits moved from Rev. D onward
465 */
466 if ((get_immr(0) & 0xffff) < 0x0501)
467 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
468 else
469 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
470#else
471 /*
472 * Configure port A for MII.
473 */
474
475#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
476
477 /*
478 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
479 * * of CPU, so for this board we need to configure Utopia and
480 * * enable PD8 to MII-MDC function
481 */
482 immr->im_ioport.iop_pdpar |= 0x4080;
483#endif
484
485 /*
486 * Has Utopia been configured?
487 */
488 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
489 /*
490 * YES - Use MUXED mode for UTOPIA bus.
491 * This frees Port A for use by MII (see 862UM table 41-6).
492 */
493 immr->im_ioport.utmode &= ~0x80;
494 } else {
495 /*
496 * NO - set SPLIT mode for UTOPIA bus.
497 *
498 * This doesn't really effect UTOPIA (which isn't
499 * enabled anyway) but just tells the 862
500 * to use port A for MII (see 862UM table 41-6).
501 */
502 immr->im_ioport.utmode |= 0x80;
503 }
504#endif /* !defined(CONFIG_ICU862) */
505
506#endif /* CONFIG_ETHER_ON_FEC1 */
507 } else if (fecidx == 1) {
508
509#if defined(CONFIG_ETHER_ON_FEC2)
510
wdenk11142572004-06-06 21:35:06 +0000511#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
wdenka6ab4bf2004-04-15 21:31:56 +0000512
513#if !defined(CONFIG_RMII)
wdenka6ab4bf2004-04-15 21:31:56 +0000514 immr->im_cpm.cp_pepar |= 0x0003fffc;
515 immr->im_cpm.cp_pedir |= 0x0003fffc;
516 immr->im_cpm.cp_peso &= ~0x000087fc;
517 immr->im_cpm.cp_peso |= 0x00037800;
518
519 immr->im_cpm.cp_cptr &= ~0x00000080;
520#else
521
522#if !defined(CONFIG_FEC2_PHY_NORXERR)
523 immr->im_cpm.cp_pepar |= 0x00000010;
524 immr->im_cpm.cp_pedir |= 0x00000010;
525 immr->im_cpm.cp_peso &= ~0x00000010;
526#endif
527 immr->im_cpm.cp_pepar |= 0x00039620;
528 immr->im_cpm.cp_pedir |= 0x00039620;
529 immr->im_cpm.cp_peso |= 0x00031000;
530 immr->im_cpm.cp_peso &= ~0x00008620;
531
532 immr->im_cpm.cp_cptr |= 0x00000080;
533 immr->im_cpm.cp_cptr &= ~0x00000028;
534#endif /* CONFIG_RMII */
535
wdenk11142572004-06-06 21:35:06 +0000536#endif /* CONFIG_MPC885_FAMILY */
wdenka6ab4bf2004-04-15 21:31:56 +0000537
538#endif /* CONFIG_ETHER_ON_FEC2 */
539
wdenkc6097192002-11-03 00:24:07 +0000540 }
wdenka6ab4bf2004-04-15 21:31:56 +0000541}
542
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100543static int fec_reset(volatile fec_t *fecp)
544{
545 int i;
546
547 /* Whack a reset.
548 * A delay is required between a reset of the FEC block and
549 * initialization of other FEC registers because the reset takes
550 * some time to complete. If you don't delay, subsequent writes
551 * to FEC registers might get killed by the reset routine which is
552 * still in progress.
553 */
554
555 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
556 for (i = 0;
557 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
558 ++i) {
559 udelay (1);
560 }
561 if (i == FEC_RESET_DELAY)
562 return -1;
563
564 return 0;
565}
566
wdenka6ab4bf2004-04-15 21:31:56 +0000567static int fec_init (struct eth_device *dev, bd_t * bd)
568{
569 struct ether_fcc_info_s *efis = dev->priv;
570 volatile immap_t *immr = (immap_t *) CFG_IMMR;
571 volatile fec_t *fecp =
572 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
573 int i;
574
575 if (efis->ether_index == 0) {
576#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
wdenk11142572004-06-06 21:35:06 +0000577#if defined(CONFIG_MPC885ADS)
wdenka6ab4bf2004-04-15 21:31:56 +0000578 *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
579#else
580 /* configure FADS for fast (FEC) ethernet, half-duplex */
581 /* The LXT970 needs about 50ms to recover from reset, so
582 * wait for it by discovering the PHY before leaving eth_init().
583 */
584 {
585 volatile uint *bcsr4 = (volatile uint *) BCSR4;
586
587 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
588 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
589 BCSR4_FETHRST);
590
591 /* reset the LXT970 PHY */
592 *bcsr4 &= ~BCSR4_FETHRST;
593 udelay (10);
594 *bcsr4 |= BCSR4_FETHRST;
595 udelay (10);
596 }
wdenk11142572004-06-06 21:35:06 +0000597#endif /* CONFIG_MPC885ADS */
wdenk180d3f72004-01-04 16:28:35 +0000598#endif /* CONFIG_FADS */
wdenka6ab4bf2004-04-15 21:31:56 +0000599 }
600
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100601#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
602 /* the MII interface is connected to FEC1
603 * so for the miiphy_xxx function to work we must
604 * call mii_init since fec_halt messes the thing up
wdenkc6097192002-11-03 00:24:07 +0000605 */
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100606 if (efis->ether_index != 0)
607 __mii_init();
608#endif
609
610 if (fec_reset(fecp) < 0)
wdenkc6097192002-11-03 00:24:07 +0000611 printf ("FEC_RESET_DELAY timeout\n");
wdenkc6097192002-11-03 00:24:07 +0000612
613 /* We use strictly polling mode only
614 */
615 fecp->fec_imask = 0;
616
617 /* Clear any pending interrupt
618 */
619 fecp->fec_ievent = 0xffc0;
620
621 /* No need to set the IVEC register */
622
623 /* Set station address
624 */
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100625#define ea dev->enetaddr
wdenka6ab4bf2004-04-15 21:31:56 +0000626 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
627 fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
wdenkc6097192002-11-03 00:24:07 +0000628#undef ea
629
Jon Loeliger44312832007-07-09 19:06:00 -0500630#if defined(CONFIG_CMD_CDP)
wdenka6ab4bf2004-04-15 21:31:56 +0000631 /*
632 * Turn on multicast address hash table
633 */
634 fecp->fec_hash_table_high = 0xffffffff;
635 fecp->fec_hash_table_low = 0xffffffff;
636#else
wdenkc6097192002-11-03 00:24:07 +0000637 /* Clear multicast address hash table
638 */
639 fecp->fec_hash_table_high = 0;
wdenka6ab4bf2004-04-15 21:31:56 +0000640 fecp->fec_hash_table_low = 0;
641#endif
wdenkc6097192002-11-03 00:24:07 +0000642
643 /* Set maximum receive buffer size.
644 */
645 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
646
647 /* Set maximum frame length
648 */
649 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
650
651 /*
652 * Setup Buffers and Buffer Desriptors
653 */
654 rxIdx = 0;
655 txIdx = 0;
656
657 if (!rtx) {
658#ifdef CFG_ALLOC_DPRAM
wdenka6ab4bf2004-04-15 21:31:56 +0000659 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
660 dpram_alloc_align (sizeof (RTXBD), 8));
wdenkc6097192002-11-03 00:24:07 +0000661#else
wdenka6ab4bf2004-04-15 21:31:56 +0000662 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
wdenkc6097192002-11-03 00:24:07 +0000663#endif
664 }
665 /*
666 * Setup Receiver Buffer Descriptors (13.14.24.18)
667 * Settings:
668 * Empty, Wrap
669 */
670 for (i = 0; i < PKTBUFSRX; i++) {
wdenka6ab4bf2004-04-15 21:31:56 +0000671 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
672 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
wdenkc6097192002-11-03 00:24:07 +0000673 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
674 }
675 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
676
677 /*
678 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
679 * Settings:
680 * Last, Tx CRC
681 */
682 for (i = 0; i < TX_BUF_CNT; i++) {
wdenka6ab4bf2004-04-15 21:31:56 +0000683 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
684 rtx->txbd[i].cbd_datlen = 0; /* Reset */
wdenkc6097192002-11-03 00:24:07 +0000685 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
686 }
687 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
688
689 /* Set receive and transmit descriptor base
690 */
691 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
692 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
693
694 /* Enable MII mode
695 */
wdenka6ab4bf2004-04-15 21:31:56 +0000696#if 0 /* Full duplex mode */
wdenkc6097192002-11-03 00:24:07 +0000697 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
698 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
wdenka6ab4bf2004-04-15 21:31:56 +0000699#else /* Half duplex mode */
wdenkc6097192002-11-03 00:24:07 +0000700 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
701 fecp->fec_x_cntrl = 0;
702#endif
703
704 /* Enable big endian and don't care about SDMA FC.
705 */
706 fecp->fec_fun_code = 0x78000000;
707
wdenka6ab4bf2004-04-15 21:31:56 +0000708 /*
709 * Setup the pin configuration of the FEC
wdenkc6097192002-11-03 00:24:07 +0000710 */
wdenka6ab4bf2004-04-15 21:31:56 +0000711 fec_pin_init (efis->ether_index);
wdenkc6097192002-11-03 00:24:07 +0000712
713 rxIdx = 0;
714 txIdx = 0;
715
wdenka6ab4bf2004-04-15 21:31:56 +0000716 /*
717 * Now enable the transmit and receive processing
wdenkc6097192002-11-03 00:24:07 +0000718 */
719 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
720
wdenka6ab4bf2004-04-15 21:31:56 +0000721 if (efis->phy_addr == -1) {
wdenkc6097192002-11-03 00:24:07 +0000722#ifdef CFG_DISCOVER_PHY
wdenka6ab4bf2004-04-15 21:31:56 +0000723 /*
724 * wait for the PHY to wake up after reset
725 */
726 efis->actual_phy_addr = mii_discover_phy (dev);
wdenk62b4ac92004-05-05 08:31:53 +0000727
wdenka6ab4bf2004-04-15 21:31:56 +0000728 if (efis->actual_phy_addr == -1) {
729 printf ("Unable to discover phy!\n");
Ben Warren422b1a02008-01-09 18:15:53 -0500730 return -1;
wdenka6ab4bf2004-04-15 21:31:56 +0000731 }
wdenk62b4ac92004-05-05 08:31:53 +0000732#else
733 efis->actual_phy_addr = -1;
734#endif
wdenka6ab4bf2004-04-15 21:31:56 +0000735 } else {
736 efis->actual_phy_addr = efis->phy_addr;
737 }
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100738
wdenka6ab4bf2004-04-15 21:31:56 +0000739#if defined(CONFIG_MII) && defined(CONFIG_RMII)
740 /*
741 * adapt the RMII speed to the speed of the phy
wdenkc6097192002-11-03 00:24:07 +0000742 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200743 if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
wdenka6ab4bf2004-04-15 21:31:56 +0000744 fec_100Mbps (dev);
745 } else {
746 fec_10Mbps (dev);
747 }
748#endif
749
750#if defined(CONFIG_MII)
751 /*
752 * adapt to the half/full speed settings
753 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200754 if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
wdenka6ab4bf2004-04-15 21:31:56 +0000755 fec_full_duplex (dev);
756 } else {
757 fec_half_duplex (dev);
758 }
wdenkc6097192002-11-03 00:24:07 +0000759#endif
760
761 /* And last, try to fill Rx Buffer Descriptors */
wdenka6ab4bf2004-04-15 21:31:56 +0000762 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
wdenkc6097192002-11-03 00:24:07 +0000763
wdenkc26e4542004-04-18 10:13:26 +0000764 efis->initialized = 1;
765
Ben Warren422b1a02008-01-09 18:15:53 -0500766 return 0;
wdenkc6097192002-11-03 00:24:07 +0000767}
768
769
wdenkc6097192002-11-03 00:24:07 +0000770static void fec_halt(struct eth_device* dev)
771{
wdenkc26e4542004-04-18 10:13:26 +0000772 struct ether_fcc_info_s *efis = dev->priv;
773 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
774 int i;
wdenkc6097192002-11-03 00:24:07 +0000775
wdenkc26e4542004-04-18 10:13:26 +0000776 /* avoid halt if initialized; mii gets stuck otherwise */
777 if (!efis->initialized)
778 return;
779
780 /* Whack a reset.
781 * A delay is required between a reset of the FEC block and
782 * initialization of other FEC registers because the reset takes
783 * some time to complete. If you don't delay, subsequent writes
784 * to FEC registers might get killed by the reset routine which is
785 * still in progress.
786 */
787
788 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
789 for (i = 0;
790 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
791 ++i) {
792 udelay (1);
793 }
794 if (i == FEC_RESET_DELAY) {
795 printf ("FEC_RESET_DELAY timeout\n");
796 return;
797 }
798
799 efis->initialized = 0;
wdenkc6097192002-11-03 00:24:07 +0000800}
wdenkc6097192002-11-03 00:24:07 +0000801
Jon Loeliger44312832007-07-09 19:06:00 -0500802#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
wdenkc6097192002-11-03 00:24:07 +0000803
804/* Make MII read/write commands for the FEC.
805*/
806
807#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
808 (REG & 0x1f) << 18))
809
810#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
811 (REG & 0x1f) << 18) | \
812 (VAL & 0xffff))
813
814/* Interrupt events/masks.
815*/
816#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
817#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
818#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
819#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
820#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
821#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
822#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
823#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
824#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
825#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
826
827/* PHY identification
828 */
829#define PHY_ID_LXT970 0x78100000 /* LXT970 */
830#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
831#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
832#define PHY_ID_QS6612 0x01814400 /* QS6612 */
833#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
834#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
835#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
wdenk180d3f72004-01-04 16:28:35 +0000836#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200837#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
wdenkc6097192002-11-03 00:24:07 +0000838
839/* send command to phy using mii, wait for result */
840static uint
841mii_send(uint mii_cmd)
842{
843 uint mii_reply;
844 volatile fec_t *ep;
wdenkc26e4542004-04-18 10:13:26 +0000845 int cnt;
wdenkc6097192002-11-03 00:24:07 +0000846
847 ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
848
849 ep->fec_mii_data = mii_cmd; /* command to phy */
850
851 /* wait for mii complete */
wdenkc26e4542004-04-18 10:13:26 +0000852 cnt = 0;
853 while (!(ep->fec_ievent & FEC_ENET_MII)) {
854 if (++cnt > 1000) {
855 printf("mii_send STUCK!\n");
856 break;
857 }
858 }
wdenkc6097192002-11-03 00:24:07 +0000859 mii_reply = ep->fec_mii_data; /* result from phy */
860 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
861#if 0
862 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
863 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
864#endif
865 return (mii_reply & 0xffff); /* data read from phy */
866}
Jon Loeliger44312832007-07-09 19:06:00 -0500867#endif
wdenkc6097192002-11-03 00:24:07 +0000868
869#if defined(CFG_DISCOVER_PHY)
wdenka6ab4bf2004-04-15 21:31:56 +0000870static int mii_discover_phy(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000871{
872#define MAX_PHY_PASSES 11
873 uint phyno;
874 int pass;
wdenka6ab4bf2004-04-15 21:31:56 +0000875 uint phytype;
876 int phyaddr;
wdenkc6097192002-11-03 00:24:07 +0000877
878 phyaddr = -1; /* didn't find a PHY yet */
879 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
880 if (pass > 1) {
881 /* PHY may need more time to recover from reset.
882 * The LXT970 needs 50ms typical, no maximum is
883 * specified, so wait 10ms before try again.
884 * With 11 passes this gives it 100ms to wake up.
885 */
886 udelay(10000); /* wait 10ms */
887 }
888 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100889 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
wdenkc6097192002-11-03 00:24:07 +0000890#ifdef ET_DEBUG
891 printf("PHY type 0x%x pass %d type ", phytype, pass);
892#endif
893 if (phytype != 0xffff) {
894 phyaddr = phyno;
wdenkc6097192002-11-03 00:24:07 +0000895 phytype |= mii_send(mk_mii_read(phyno,
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100896 PHY_PHYIDR1)) << 16;
wdenkc6097192002-11-03 00:24:07 +0000897
898#ifdef ET_DEBUG
899 printf("PHY @ 0x%x pass %d type ",phyno,pass);
900 switch (phytype & 0xfffffff0) {
901 case PHY_ID_LXT970:
902 printf("LXT970\n");
903 break;
904 case PHY_ID_LXT971:
905 printf("LXT971\n");
906 break;
907 case PHY_ID_82555:
908 printf("82555\n");
909 break;
910 case PHY_ID_QS6612:
911 printf("QS6612\n");
912 break;
913 case PHY_ID_AMD79C784:
914 printf("AMD79C784\n");
915 break;
916 case PHY_ID_LSI80225B:
917 printf("LSI L80225/B\n");
918 break;
wdenk180d3f72004-01-04 16:28:35 +0000919 case PHY_ID_DM9161:
920 printf("Davicom DM9161\n");
921 break;
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200922 case PHY_ID_KSM8995M:
923 printf("MICREL KS8995M\n");
924 break;
wdenkc6097192002-11-03 00:24:07 +0000925 default:
926 printf("0x%08x\n", phytype);
927 break;
928 }
929#endif
930 }
931 }
932 }
933 if (phyaddr < 0) {
934 printf("No PHY device found.\n");
935 }
wdenka6ab4bf2004-04-15 21:31:56 +0000936 return phyaddr;
wdenkc6097192002-11-03 00:24:07 +0000937}
938#endif /* CFG_DISCOVER_PHY */
939
Jon Loeliger44312832007-07-09 19:06:00 -0500940#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
wdenkc6097192002-11-03 00:24:07 +0000941
wdenkc6097192002-11-03 00:24:07 +0000942/****************************************************************************
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100943 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
wdenkc6097192002-11-03 00:24:07 +0000944 * This function is a subset of eth_init
945 ****************************************************************************
946 */
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100947static void __mii_init(void)
wdenkc6097192002-11-03 00:24:07 +0000948{
wdenkc6097192002-11-03 00:24:07 +0000949 volatile immap_t *immr = (immap_t *) CFG_IMMR;
950 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
wdenkc6097192002-11-03 00:24:07 +0000951
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100952 if (fec_reset(fecp) < 0)
wdenkc6097192002-11-03 00:24:07 +0000953 printf ("FEC_RESET_DELAY timeout\n");
wdenkc6097192002-11-03 00:24:07 +0000954
955 /* We use strictly polling mode only
956 */
957 fecp->fec_imask = 0;
958
959 /* Clear any pending interrupt
960 */
961 fecp->fec_ievent = 0xffc0;
962
wdenkc6097192002-11-03 00:24:07 +0000963 /* Now enable the transmit and receive processing
964 */
965 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
Guennadi Liakhovetskid197ffd2007-11-29 21:15:56 +0100966}
967
968void mii_init (void)
969{
970 int i;
971
972 __mii_init();
973
974 /* Setup the pin configuration of the FEC(s)
975 */
976 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
977 fec_pin_init(ether_fcc_info[i].ether_index);
wdenkc6097192002-11-03 00:24:07 +0000978}
wdenka6ab4bf2004-04-15 21:31:56 +0000979
wdenkc6097192002-11-03 00:24:07 +0000980/*****************************************************************************
981 * Read and write a MII PHY register, routines used by MII Utilities
982 *
983 * FIXME: These routines are expected to return 0 on success, but mii_send
984 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
985 * no PHY connected...
986 * For now always return 0.
987 * FIXME: These routines only work after calling eth_init() at least once!
988 * Otherwise they hang in mii_send() !!! Sorry!
989 *****************************************************************************/
990
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200991int fec8xx_miiphy_read(char *devname, unsigned char addr,
992 unsigned char reg, unsigned short *value)
wdenkc6097192002-11-03 00:24:07 +0000993{
994 short rdreg; /* register working value */
995
996#ifdef MII_DEBUG
997 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
998#endif
999 rdreg = mii_send(mk_mii_read(addr, reg));
1000
1001 *value = rdreg;
wdenkc6097192002-11-03 00:24:07 +00001002#ifdef MII_DEBUG
1003 printf ("0x%04x\n", *value);
1004#endif
wdenkc6097192002-11-03 00:24:07 +00001005 return 0;
1006}
1007
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001008int fec8xx_miiphy_write(char *devname, unsigned char addr,
1009 unsigned char reg, unsigned short value)
wdenkc6097192002-11-03 00:24:07 +00001010{
1011 short rdreg; /* register working value */
wdenkc6097192002-11-03 00:24:07 +00001012#ifdef MII_DEBUG
1013 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
1014#endif
wdenkc6097192002-11-03 00:24:07 +00001015 rdreg = mii_send(mk_mii_write(addr, reg, value));
1016
1017#ifdef MII_DEBUG
1018 printf ("0x%04x\n", value);
1019#endif
wdenkc6097192002-11-03 00:24:07 +00001020 return 0;
1021}
Jon Loeliger44312832007-07-09 19:06:00 -05001022#endif
wdenkc6097192002-11-03 00:24:07 +00001023
Jon Loeliger068b60a2007-07-10 10:27:39 -05001024#endif