Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Internal Definitions |
| 3 | */ |
Simon Glass | 1af3c7f | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 4 | #include <linux/stringify.h> |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 5 | #define BOOTFLASH_START 0xF0000000 |
| 6 | |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 7 | /* |
| 8 | * DDR Setup |
| 9 | */ |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 10 | #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 11 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 12 | #define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 13 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
| 14 | |
| 15 | #define CFG_83XX_DDR_USES_CS0 |
| 16 | |
| 17 | /* |
| 18 | * Manually set up DDR parameters |
| 19 | */ |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 20 | #define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * The reserved memory |
| 24 | */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 25 | #define CFG_SYS_FLASH_BASE 0xF0000000 |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 26 | |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 27 | /* Reserve 768 kB for Mon */ |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 28 | |
| 29 | /* |
| 30 | * Initial RAM Base Address Setup |
| 31 | */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 32 | #define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
| 33 | #define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 34 | /* |
| 35 | * Init Local Bus Memory Controller: |
| 36 | * |
| 37 | * Bank Bus Machine PortSz Size Device |
| 38 | * ---- --- ------- ------ ----- ------ |
| 39 | * 0 Local GPCM 16 bit 256MB FLASH |
| 40 | * 1 Local GPCM 8 bit 128MB GPIO/PIGGY |
| 41 | * |
| 42 | */ |
| 43 | |
| 44 | /* |
| 45 | * FLASH on the Local Bus |
| 46 | */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 47 | #define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 48 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 49 | #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 50 | |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 51 | #if defined(CONFIG_CMD_NAND) |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 52 | #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 53 | #endif |
| 54 | |
| 55 | /* |
| 56 | * For booting Linux, the board info and command line data |
| 57 | * have to be in the first 8 MB of memory, since this is |
| 58 | * the maximum mapped by the Linux kernel during initialization. |
| 59 | */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 60 | #define CFG_SYS_BOOTMAPSZ (8 << 20) |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 61 | |
| 62 | /* |
Mario Six | aed7d0e | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 63 | * QE UEC ethernet configuration |
| 64 | */ |
| 65 | #define CONFIG_UEC_ETH |