blob: 48c4b308bed2b824e6bef4ed59e0cd0060e52902 [file] [log] [blame]
Mingkai Hua8d97582013-07-04 17:33:43 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
York Sun3aab0cd2013-08-12 14:57:12 -07004 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hua8d97582013-07-04 17:33:43 +08005 */
6
7#include <common.h>
8#include <asm/processor.h>
9#include <asm/mmu.h>
10#include <asm/cache.h>
11#include <asm/immap_85xx.h>
12#include <asm/io.h>
13#include <miiphy.h>
14#include <libfdt.h>
15#include <fdt_support.h>
16#include <fsl_mdio.h>
17#include <tsec.h>
18#include <mmc.h>
19#include <netdev.h>
20#include <pci.h>
21#include <asm/fsl_ifc.h>
22#include <asm/fsl_pci.h>
23
24#include "cpld.h"
25
26DECLARE_GLOBAL_DATA_PTR;
27
28int checkboard(void)
29{
30 struct cpu_type *cpu = gd->arch.cpu;
31 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
32
33 printf("Board: %sPCIe, ", cpu->name);
34 printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
35
36 return 0;
37}
38
39int board_early_init_f(void)
40{
41 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
42
43 /* Clock configuration to access CPLD using IFC(GPCM) */
44 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
45
46 return 0;
47}
48
49int board_early_init_r(void)
50{
51 const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
52 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
53
54 /*
55 * Remap Boot flash region to caching-inhibited
56 * so that flash can be erased properly.
57 */
58
59 /* Flush d-cache and invalidate i-cache of any FLASH data */
60 flush_dcache();
61 invalidate_icache();
62
63 /* invalidate existing TLB entry for flash */
64 disable_tlb(flash_esel);
65
66 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
67 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, flash_esel, BOOKE_PAGESZ_64M, 1);
69
70 return 0;
71}
72
73#ifdef CONFIG_PCI
74void pci_init_board(void)
75{
76 fsl_pcie_init_board(0);
77}
78#endif /* ifdef CONFIG_PCI */
79
80#ifdef CONFIG_TSEC_ENET
81int board_eth_init(bd_t *bis)
82{
83 struct fsl_pq_mdio_info mdio_info;
84 struct tsec_info_struct tsec_info[2];
85 int num = 0;
86
87#ifdef CONFIG_TSEC1
88 SET_STD_TSEC_INFO(tsec_info[num], 1);
89 num++;
90#endif
91#ifdef CONFIG_TSEC2
92 SET_STD_TSEC_INFO(tsec_info[num], 2);
93 num++;
94#endif
95 if (!num) {
96 printf("No TSECs initialized\n");
97 return 0;
98 }
99
100 /* Register 1G MDIO bus */
101 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
102 mdio_info.name = DEFAULT_MII_NAME;
103
104 fsl_pq_mdio_init(bis, &mdio_info);
105
106 tsec_eth_init(bis, tsec_info, num);
107
108 return pci_eth_init(bis);
109}
110#endif
111
112#if defined(CONFIG_OF_BOARD_SETUP)
113void fdt_del_sec(void *blob, int offset)
114{
115 int nodeoff = 0;
116
117 while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
118 CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
119 + offset * 0x20000)) >= 0) {
120 fdt_del_node(blob, nodeoff);
121 offset++;
122 }
123}
124
125void ft_board_setup(void *blob, bd_t *bd)
126{
127 phys_addr_t base;
128 phys_size_t size;
129 struct cpu_type *cpu;
130
131 cpu = gd->arch.cpu;
132
133 ft_cpu_setup(blob, bd);
134
135 base = getenv_bootm_low();
136 size = getenv_bootm_size();
137
138#if defined(CONFIG_PCI)
139 FT_FSL_PCI_SETUP;
140#endif
141
142 fdt_fixup_memory(blob, (u64)base, (u64)size);
143 if (cpu->soc_ver == SVR_C291)
144 fdt_del_sec(blob, 1);
145 else if (cpu->soc_ver == SVR_C292)
146 fdt_del_sec(blob, 2);
147}
148#endif