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Wolfgang Denk8cba0902006-05-12 16:15:46 +02001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2006-2008
Wolfgang Denk8cba0902006-05-12 16:15:46 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
38#define CONFIG_TQM8xxL 1
39
Wolfgang Denk8cba0902006-05-12 16:15:46 +020040#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41#undef CONFIG_8xx_CONS_SMC2
42#undef CONFIG_8xx_CONS_NONE
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
45#define CONFIG_BOOTCOUNT_LIMIT
46
47#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010051#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
Wolfgang Denk8cba0902006-05-12 16:15:46 +020052
53#undef CONFIG_BOOTARGS
54
55#define CONFIG_EXTRA_ENV_SETTINGS \
56 "netdev=eth0\0" \
57 "nfsargs=setenv bootargs root=/dev/nfs rw " \
58 "nfsroot=${serverip}:${rootpath}\0" \
59 "ramargs=setenv bootargs root=/dev/ram rw\0" \
60 "addip=setenv bootargs ${bootargs} " \
61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
62 ":${hostname}:${netdev}:off panic=1\0" \
63 "flash_nfs=run nfsargs addip;" \
64 "bootm ${kernel_addr}\0" \
65 "flash_self=run ramargs addip;" \
66 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
67 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
68 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020069 "hostname=virtlab2\0" \
70 "bootfile=virtlab2/uImage\0" \
71 "fdt_addr=40040000\0" \
72 "kernel_addr=40060000\0" \
73 "ramdisk_addr=40200000\0" \
74 "u-boot=virtlab2/u-image.bin\0" \
75 "load=tftp 200000 ${u-boot}\0" \
76 "update=prot off 40000000 +${filesize};" \
77 "era 40000000 +${filesize};" \
78 "cp.b 200000 40000000 ${filesize};" \
79 "sete filesize;save\0" \
Wolfgang Denk8cba0902006-05-12 16:15:46 +020080 ""
81#define CONFIG_BOOTCOMMAND "run flash_self"
82
83#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
84#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
85
86#undef CONFIG_WATCHDOG /* watchdog disabled */
87
88#if defined(CONFIG_LCD)
89# undef CONFIG_STATUS_LED /* disturbs display */
90#else
91# define CONFIG_STATUS_LED 1 /* Status LED enabled */
92#endif /* CONFIG_LCD */
93
94#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
95
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050096/*
97 * BOOTP options
98 */
99#define CONFIG_BOOTP_SUBNETMASK
100#define CONFIG_BOOTP_GATEWAY
101#define CONFIG_BOOTP_HOSTNAME
102#define CONFIG_BOOTP_BOOTPATH
103#define CONFIG_BOOTP_BOOTFILESIZE
104
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200105
106#define CONFIG_MAC_PARTITION
107#define CONFIG_DOS_PARTITION
108
109#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
110
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500111
112/*
113 * Command line configuration.
114 */
115#include <config_cmd_default.h>
116
117#define CONFIG_CMD_ASKENV
118#define CONFIG_CMD_DATE
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200121#define CONFIG_CMD_JFFS2
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500122#define CONFIG_CMD_NFS
123#define CONFIG_CMD_SNTP
124
125#if defined(CONFIG_SPLASH_SCREEN)
126 #define CONFIG_CMD_BMP
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200127#endif
128
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200129
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200130#define CONFIG_NETCONSOLE
131
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200132/*
133 * Miscellaneous configurable options
134 */
135#define CFG_LONGHELP /* undef to save memory */
136#define CFG_PROMPT "=> " /* Monitor Command Prompt */
137
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200138#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200139#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200140#ifdef CFG_HUSH_PARSER
141#define CFG_PROMPT_HUSH_PS2 "> "
142#endif
143
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500144#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200145#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
146#else
147#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
148#endif
149#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
150#define CFG_MAXARGS 16 /* max number of command args */
151#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
152
153#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
154#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
155
156#define CFG_LOAD_ADDR 0x100000 /* default load address */
157
158#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
159
160#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
161
162/*
163 * Low Level Configuration Settings
164 * (address mappings, register initial values, etc.)
165 * You should know what you are doing if you make changes here.
166 */
167/*-----------------------------------------------------------------------
168 * Internal Memory Mapped Register
169 */
170#define CFG_IMMR 0xFFF00000
171
172/*-----------------------------------------------------------------------
173 * Definitions for initial stack pointer and data area (in DPRAM)
174 */
175#define CFG_INIT_RAM_ADDR CFG_IMMR
176#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
177#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
178#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
179#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
180
181/*-----------------------------------------------------------------------
182 * Start addresses for the final memory configuration
183 * (Set up by the startup code)
184 * Please note that CFG_SDRAM_BASE _must_ start at 0
185 */
186#define CFG_SDRAM_BASE 0x00000000
187#define CFG_FLASH_BASE 0x40000000
188#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
189#define CFG_MONITOR_BASE CFG_FLASH_BASE
190#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
191
192/*
193 * For booting Linux, the board info and command line data
194 * have to be in the first 8 MB of memory, since this is
195 * the maximum mapped by the Linux kernel during initialization.
196 */
197#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
198
199/*-----------------------------------------------------------------------
200 * FLASH organization
201 */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200202
Martin Krausee318d9e2007-09-27 11:10:08 +0200203/* use CFI flash driver */
204#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200205#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200206#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
Martin Krausee318d9e2007-09-27 11:10:08 +0200207#define CFG_FLASH_EMPTY_INFO
208#define CFG_FLASH_USE_BUFFER_WRITE 1
209#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
210#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200211
212#define CFG_ENV_IS_IN_FLASH 1
213#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
214#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
215
216/* Address and size of Redundant Environment Sector */
217#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
218#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
219
Wolfgang Denk67c31032007-09-16 17:10:04 +0200220#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
221
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200222/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200223 * Dynamic MTD partition support
224 */
225#define CONFIG_JFFS2_CMDLINE
226#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
227
228#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
229 "128k(dtb)," \
230 "1664k(kernel)," \
231 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200232 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200233
234/*-----------------------------------------------------------------------
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200235 * Hardware Information Block
236 */
237#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
238#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
239#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
240
241/*-----------------------------------------------------------------------
242 * Cache Configuration
243 */
244#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500245#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200246#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
247#endif
248
249/*-----------------------------------------------------------------------
250 * SYPCR - System Protection Control 11-9
251 * SYPCR can only be written once after reset!
252 *-----------------------------------------------------------------------
253 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
254 */
255#if defined(CONFIG_WATCHDOG)
256#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
257 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
258#else
259#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
260#endif
261
262/*-----------------------------------------------------------------------
263 * SIUMCR - SIU Module Configuration 11-6
264 *-----------------------------------------------------------------------
265 * PCMCIA config., multi-function pin tri-state
266 */
267#ifndef CONFIG_CAN_DRIVER
268#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
269#else /* we must activate GPL5 in the SIUMCR for CAN */
270#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
271#endif /* CONFIG_CAN_DRIVER */
272
273/*-----------------------------------------------------------------------
274 * TBSCR - Time Base Status and Control 11-26
275 *-----------------------------------------------------------------------
276 * Clear Reference Interrupt Status, Timebase freezing enabled
277 */
278#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
279
280/*-----------------------------------------------------------------------
281 * RTCSC - Real-Time Clock Status and Control Register 11-27
282 *-----------------------------------------------------------------------
283 */
284#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
285
286/*-----------------------------------------------------------------------
287 * PISCR - Periodic Interrupt Status and Control 11-31
288 *-----------------------------------------------------------------------
289 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
290 */
291#define CFG_PISCR (PISCR_PS | PISCR_PITF)
292
293/*-----------------------------------------------------------------------
294 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
295 *-----------------------------------------------------------------------
296 * Reset PLL lock status sticky bit, timer expired status bit and timer
297 * interrupt status bit
298 */
299#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
300
301/*-----------------------------------------------------------------------
302 * SCCR - System Clock and reset Control Register 15-27
303 *-----------------------------------------------------------------------
304 * Set clock output, timebase and RTC source and divider,
305 * power management and some other internal clocks
306 */
307#define SCCR_MASK SCCR_EBDF11
308#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
309 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
310 SCCR_DFALCD00)
311
312/*-----------------------------------------------------------------------
313 * PCMCIA stuff
314 *-----------------------------------------------------------------------
315 *
316 */
317#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
318#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
319#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
320#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
321#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
322#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
323#define CFG_PCMCIA_IO_ADDR (0xEC000000)
324#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
325
326/*-----------------------------------------------------------------------
327 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
328 *-----------------------------------------------------------------------
329 */
330
331#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
332
333#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
334#undef CONFIG_IDE_LED /* LED for ide not supported */
335#undef CONFIG_IDE_RESET /* reset for ide not supported */
336
337#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
338#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
339
340#define CFG_ATA_IDE0_OFFSET 0x0000
341
342#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
343
344/* Offset for data I/O */
345#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
346
347/* Offset for normal register accesses */
348#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
349
350/* Offset for alternate registers */
351#define CFG_ATA_ALT_OFFSET 0x0100
352
353/*-----------------------------------------------------------------------
354 *
355 *-----------------------------------------------------------------------
356 *
357 */
358#define CFG_DER 0
359
360/*
361 * Init Memory Controller:
362 *
363 * BR0/1 and OR0/1 (FLASH)
364 */
365
366#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
367#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
368
369/* used to re-map FLASH both when starting from SRAM or FLASH:
370 * restrict access enough to keep SRAM working (if any)
371 * but not too much to meddle with FLASH accesses
372 */
373#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
374#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
375
376/*
377 * FLASH timing:
378 */
379#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
380 OR_SCY_3_CLK | OR_EHTR | OR_BI)
381
382#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
383#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
384#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
385
386#define CFG_OR1_REMAP CFG_OR0_REMAP
387#define CFG_OR1_PRELIM CFG_OR0_PRELIM
388#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
389
390/*
391 * BR2/3 and OR2/3 (SDRAM)
392 *
393 */
394#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
395#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
396#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
397
398/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
399#define CFG_OR_TIMING_SDRAM 0x00000A00
400
401#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
402#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
403
404#ifndef CONFIG_CAN_DRIVER
405#define CFG_OR3_PRELIM CFG_OR2_PRELIM
406#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
407#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
408#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
409#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
410#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
411#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
412 BR_PS_8 | BR_MS_UPMB | BR_V )
413#endif /* CONFIG_CAN_DRIVER */
414
415/*
416 * Memory Periodic Timer Prescaler
417 *
418 * The Divider for PTA (refresh timer) configuration is based on an
419 * example SDRAM configuration (64 MBit, one bank). The adjustment to
420 * the number of chip selects (NCS) and the actually needed refresh
421 * rate is done by setting MPTPR.
422 *
423 * PTA is calculated from
424 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
425 *
426 * gclk CPU clock (not bus clock!)
427 * Trefresh Refresh cycle * 4 (four word bursts used)
428 *
429 * 4096 Rows from SDRAM example configuration
430 * 1000 factor s -> ms
431 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
432 * 4 Number of refresh cycles per period
433 * 64 Refresh cycle in ms per number of rows
434 * --------------------------------------------
435 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
436 *
437 * 50 MHz => 50.000.000 / Divider = 98
438 * 66 Mhz => 66.000.000 / Divider = 129
439 * 80 Mhz => 80.000.000 / Divider = 156
440 */
441
442#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
443#define CFG_MAMR_PTA 98
444
445/*
446 * For 16 MBit, refresh rates could be 31.3 us
447 * (= 64 ms / 2K = 125 / quad bursts).
448 * For a simpler initialization, 15.6 us is used instead.
449 *
450 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
451 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
452 */
453#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
454#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
455
456/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
457#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
458#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
459
460/*
461 * MAMR settings for SDRAM
462 */
463
464/* 8 column SDRAM */
465#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
466 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
467 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
468/* 9 column SDRAM */
469#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
470 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
472
473
474/*
475 * Internal Definitions
476 *
477 * Boot Flags
478 */
479#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
480#define BOOTFLAG_WARM 0x02 /* Software reboot */
481
482/* Map peripheral control registers on CS4 */
483#define CFG_PERIPHERAL_BASE 0xA0000000
484#define CFG_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
485#define CFG_OR4_PRELIM (CFG_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
486 OR_SCY_2_CLK)
487#define CFG_BR4_PRELIM ((CFG_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
488#define PCMCIA_CTRL (CFG_PERIPHERAL_BASE + 0xB00)
489#endif /* __CONFIG_H */