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Wolfgang Grandegger1ca56202011-11-11 14:03:36 +01001/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +01006 */
7
8#include <common.h>
9#include <usb.h>
10#include <errno.h>
11#include <linux/compiler.h>
12#include <usb/ehci-fsl.h>
13#include <asm/io.h>
14#include <asm/arch/imx-regs.h>
15#include <asm/arch/clock.h>
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010016
17#include "ehci.h"
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010018
19#define MX5_USBOTHER_REGS_OFFSET 0x800
20
21
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +000022#define MXC_OTG_OFFSET 0
23#define MXC_H1_OFFSET 0x200
24#define MXC_H2_OFFSET 0x400
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +000025#define MXC_H3_OFFSET 0x600
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010026
27#define MXC_USBCTRL_OFFSET 0
28#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
29#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
30#define MXC_USB_CTRL_1_OFFSET 0x10
31#define MXC_USBH2CTRL_OFFSET 0x14
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +000032#define MXC_USBH3CTRL_OFFSET 0x18
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010033
34/* USB_CTRL */
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +000035/* OTG wakeup intr enable */
36#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
37/* OTG power mask */
38#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000039/* OTG power pin polarity */
40#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +000041/* Host1 ULPI interrupt enable */
42#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
43/* HOST1 wakeup intr enable */
44#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
45/* HOST1 power mask */
46#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000047/* HOST1 power pin polarity */
48#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010049
50/* USB_PHY_CTRL_FUNC */
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000051/* OTG Polarity of Overcurrent */
52#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +000053/* OTG Disable Overcurrent Event */
54#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000055/* UH1 Polarity of Overcurrent */
56#define MXC_H1_OC_POL_BIT (1 << 6)
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +000057/* UH1 Disable Overcurrent Event */
58#define MXC_H1_OC_DIS_BIT (1 << 5)
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000059/* OTG Power Pin Polarity */
60#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010061
62/* USBH2CTRL */
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000063#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +000064#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +000065#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
66#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
67#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000068#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010069
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +000070/* USBH3CTRL */
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000071#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +000072#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
73#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
74#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000075#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +000076
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010077/* USB_CTRL_1 */
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +000078#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010079
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010080int mxc_set_usbcontrol(int port, unsigned int flags)
81{
82 unsigned int v;
83 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
84 void __iomem *usbother_base;
85 int ret = 0;
86
87 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
88
89 switch (port) {
90 case 0: /* OTG port */
91 if (flags & MXC_EHCI_INTERNAL_PHY) {
92 v = __raw_readl(usbother_base +
93 MXC_USB_PHY_CTR_FUNC_OFFSET);
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +000094 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
95 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
96 else
97 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010098 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +010099 /* OC/USBPWR is used */
100 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
Benoît Thébaudeau7d424322012-11-13 09:56:30 +0000101 else
102 /* OC/USBPWR is not used */
103 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000104#ifdef CONFIG_MX51
105 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
106 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
107 else
108 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
109#endif
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100110 __raw_writel(v, usbother_base +
111 MXC_USB_PHY_CTR_FUNC_OFFSET);
112
113 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
Benoît Thébaudeau661052f2012-11-13 09:56:59 +0000114#ifdef CONFIG_MX51
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100115 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100116 v &= ~MXC_OTG_UCTRL_OPM_BIT;
Benoît Thébaudeau394c00d2012-11-13 09:56:44 +0000117 else
118 v |= MXC_OTG_UCTRL_OPM_BIT;
Benoît Thébaudeau661052f2012-11-13 09:56:59 +0000119#endif
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000120#ifdef CONFIG_MX53
121 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
122 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
123 else
124 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
125#endif
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100126 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
127 }
128 break;
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +0000129 case 1: /* Host 1 ULPI */
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100130#ifdef CONFIG_MX51
131 /* The clock for the USBH1 ULPI port will come externally
132 from the PHY. */
133 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
134 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
135 MXC_USB_CTRL_1_OFFSET);
136#endif
137
138 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
Benoît Thébaudeau661052f2012-11-13 09:56:59 +0000139#ifdef CONFIG_MX51
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100140 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +0000141 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100142 else
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +0000143 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
Benoît Thébaudeau661052f2012-11-13 09:56:59 +0000144#endif
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000145#ifdef CONFIG_MX53
146 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
147 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
148 else
149 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
150#endif
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100151 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
152
153 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000154 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
155 v |= MXC_H1_OC_POL_BIT;
156 else
157 v &= ~MXC_H1_OC_POL_BIT;
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100158 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
159 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
160 else
161 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
162 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
163
164 break;
165 case 2: /* Host 2 ULPI */
166 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
Benoît Thébaudeau661052f2012-11-13 09:56:59 +0000167#ifdef CONFIG_MX51
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100168 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +0000169 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100170 else
Benoît Thébaudeaubdc52022012-11-13 09:56:15 +0000171 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
Benoît Thébaudeau661052f2012-11-13 09:56:59 +0000172#endif
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +0000173#ifdef CONFIG_MX53
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000174 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
175 v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
176 else
177 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +0000178 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
179 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
180 else
181 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000182 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
183 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
184 else
185 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +0000186#endif
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100187 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
188 break;
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +0000189#ifdef CONFIG_MX53
190 case 3: /* Host 3 ULPI */
191 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000192 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
193 v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
194 else
195 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +0000196 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
197 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
198 else
199 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
Benoît Thébaudeau31ac2d02012-11-13 09:57:27 +0000200 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
201 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
202 else
203 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
Benoît Thébaudeau2cfe0b82012-11-13 09:57:14 +0000204 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
205 break;
206#endif
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100207 }
208
209 return ret;
210}
211
Benoît Thébaudeauf22e4fa2012-11-13 09:58:35 +0000212int __weak board_ehci_hcd_init(int port)
Marek Vasut1b80f272011-11-24 05:14:00 +0100213{
Benoît Thébaudeauf22e4fa2012-11-13 09:58:35 +0000214 return 0;
Marek Vasut1b80f272011-11-24 05:14:00 +0100215}
216
Benoît Thébaudeauf22e4fa2012-11-13 09:58:35 +0000217void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
218{
219}
Marek Vasut1b80f272011-11-24 05:14:00 +0100220
Simon Glassdeb85082015-03-25 12:22:27 -0600221__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
222 uint32_t *reg)
223{
224 mdelay(50);
225}
226
227static const struct ehci_ops mx5_ehci_ops = {
228 .powerup_fixup = mx5_ehci_powerup_fixup,
229};
230
Troy Kisky127efc42013-10-10 15:27:57 -0700231int ehci_hcd_init(int index, enum usb_init_type init,
232 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100233{
234 struct usb_ehci *ehci;
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100235
Simon Glassdeb85082015-03-25 12:22:27 -0600236 /* The only user for this is efikamx-usb */
237 ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100238 set_usboh3_clk();
Fabio Estevam76b6b192013-07-26 13:54:28 -0300239 enable_usboh3_clk(true);
Benoît Thébaudeau414e1662012-09-28 07:09:03 +0000240 set_usb_phy_clk();
Fabio Estevam76b6b192013-07-26 13:54:28 -0300241 enable_usb_phy1_clk(true);
242 enable_usb_phy2_clk(true);
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100243 mdelay(1);
244
Marek Vasut1b80f272011-11-24 05:14:00 +0100245 /* Do board specific initialization */
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100246 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
247
248 ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
249 (0x200 * CONFIG_MXC_USB_PORT));
Lucas Stach676ae062012-09-26 00:14:35 +0200250 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
251 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
252 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100253 setbits_le32(&ehci->usbmode, CM_HOST);
254
255 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
256 setbits_le32(&ehci->portsc, USB_EN);
257
258 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100259 mdelay(10);
260
Marek Vasut1b80f272011-11-24 05:14:00 +0100261 /* Do board specific post-initialization */
262 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
263
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100264 return 0;
265}
266
Lucas Stach676ae062012-09-26 00:14:35 +0200267int ehci_hcd_stop(int index)
Wolfgang Grandegger1ca56202011-11-11 14:03:36 +0100268{
269 return 0;
270}